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/*
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 *  MIPS emulation micro-operations for qemu.
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 * 
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 *  Copyright (c) 2004-2005 Jocelyn Mayer
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 *  Copyright (c) 2006 Marius Groeger (FPU operations)
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "config.h"
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#include "exec.h"
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#ifndef CALL_FROM_TB0
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#define CALL_FROM_TB0(func) func();
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#endif
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#ifndef CALL_FROM_TB1
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#define CALL_FROM_TB1(func, arg0) func(arg0);
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#endif
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#ifndef CALL_FROM_TB1_CONST16
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#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
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#endif
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#ifndef CALL_FROM_TB2
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#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
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#endif
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#ifndef CALL_FROM_TB2_CONST16
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#define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
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CALL_FROM_TB2(func, arg0, arg1);
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#endif
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#ifndef CALL_FROM_TB3
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#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
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#endif
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#ifndef CALL_FROM_TB4
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#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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        func(arg0, arg1, arg2, arg3);
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#endif
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#define REG 1
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#include "op_template.c"
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#undef REG
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#define REG 2
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#include "op_template.c"
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#undef REG
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#define REG 3
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#include "op_template.c"
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#undef REG
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#define REG 4
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#include "op_template.c"
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#undef REG
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#define REG 5
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#include "op_template.c"
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#undef REG
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#define REG 6
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#include "op_template.c"
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#undef REG
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#define REG 7
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#include "op_template.c"
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#undef REG
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#define REG 8
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#include "op_template.c"
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#undef REG
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#define REG 9
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#include "op_template.c"
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#undef REG
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#define REG 10
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#include "op_template.c"
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#undef REG
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#define REG 11
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#include "op_template.c"
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#undef REG
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#define REG 12
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#include "op_template.c"
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#undef REG
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#define REG 13
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#include "op_template.c"
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#undef REG
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#define REG 14
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#include "op_template.c"
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#undef REG
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#define REG 15
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#include "op_template.c"
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#undef REG
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#define REG 16
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#include "op_template.c"
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#undef REG
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#define REG 17
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#include "op_template.c"
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#undef REG
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#define REG 18
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#include "op_template.c"
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#undef REG
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#define REG 19
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#include "op_template.c"
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#undef REG
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#define REG 20
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#include "op_template.c"
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#undef REG
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#define REG 21
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#include "op_template.c"
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#undef REG
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#define REG 22
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#include "op_template.c"
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#undef REG
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#define REG 23
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#include "op_template.c"
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#undef REG
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#define REG 24
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#include "op_template.c"
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#undef REG
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#define REG 25
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#include "op_template.c"
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#undef REG
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#define REG 26
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#include "op_template.c"
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#undef REG
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#define REG 27
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#include "op_template.c"
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#undef REG
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#define REG 28
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#include "op_template.c"
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#undef REG
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#define REG 29
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#include "op_template.c"
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#undef REG
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#define REG 30
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#include "op_template.c"
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#undef REG
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#define REG 31
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#include "op_template.c"
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#undef REG
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#define TN
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#include "op_template.c"
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#undef TN
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#ifdef MIPS_USES_FPU
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#define SFREG 0
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#define DFREG 0
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 1
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 2
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#define DFREG 2
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 3
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 4
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#define DFREG 4
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 5
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 6
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#define DFREG 6
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 7
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 8
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#define DFREG 8
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 9
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 10
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#define DFREG 10
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 11
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 12
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#define DFREG 12
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 13
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 14
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#define DFREG 14
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 15
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 16
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#define DFREG 16
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 17
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 18
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#define DFREG 18
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 19
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 20
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#define DFREG 20
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 21
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 22
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#define DFREG 22
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 23
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 24
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#define DFREG 24
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 25
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 26
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#define DFREG 26
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 27
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 28
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#define DFREG 28
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 29
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 30
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#define DFREG 30
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 31
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#include "fop_template.c"
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#undef SFREG
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#define FTN
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#include "fop_template.c"
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#undef FTN
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#endif
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void op_dup_T0 (void)
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{
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    T2 = T0;
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    RETURN();
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}
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void op_load_HI (void)
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{
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    T0 = env->HI;
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    RETURN();
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}
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void op_store_HI (void)
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{
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    env->HI = T0;
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    RETURN();
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}
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void op_load_LO (void)
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{
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    T0 = env->LO;
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    RETURN();
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}
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void op_store_LO (void)
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{
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    env->LO = T0;
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    RETURN();
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}
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/* Load and store */
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#define MEMSUFFIX _raw
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#include "op_mem.c"
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_mem.c"
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_mem.c"
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#undef MEMSUFFIX
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#endif
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/* Arithmetic */
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void op_add (void)
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{
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    T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
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    RETURN();
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}
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void op_addo (void)
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{
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    target_ulong tmp;
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    tmp = (int32_t)T0;
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    T0 = (int32_t)T0 + (int32_t)T1;
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    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
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        /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
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    }
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    T0 = (int32_t)T0;
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    RETURN();
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}
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void op_sub (void)
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{
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    T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
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    RETURN();
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}
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void op_subo (void)
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{
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    target_ulong tmp;
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    tmp = (int32_t)T0;
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    T0 = (int32_t)T0 - (int32_t)T1;
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    if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
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        /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
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    }
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    T0 = (int32_t)T0;
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    RETURN();
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}
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void op_mul (void)
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{
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    T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
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    RETURN();
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}
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void op_div (void)
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{
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    if (T1 != 0) {
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        env->LO = (int32_t)((int32_t)T0 / (int32_t)T1);
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        env->HI = (int32_t)((int32_t)T0 % (int32_t)T1);
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    }
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    RETURN();
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}
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void op_divu (void)
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{
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    if (T1 != 0) {
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        env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1);
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        env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1);
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    }
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    RETURN();
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}
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#ifdef MIPS_HAS_MIPS64
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/* Arithmetic */
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void op_dadd (void)
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{
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    T0 += T1;
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    RETURN();
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}
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void op_daddo (void)
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{
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    target_long tmp;
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    tmp = T0;
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    T0 += T1;
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    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
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        /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
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    }
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    RETURN();
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}
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void op_dsub (void)
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{
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    T0 -= T1;
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    RETURN();
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}
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void op_dsubo (void)
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{
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    target_long tmp;
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    tmp = T0;
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    T0 = (int64_t)T0 - (int64_t)T1;
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    if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
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        /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
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    }
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    RETURN();
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}
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void op_dmul (void)
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{
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    T0 = (int64_t)T0 * (int64_t)T1;
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    RETURN();
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}
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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/* Those might call libgcc functions.  */
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void op_ddiv (void)
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{
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    do_ddiv();
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    RETURN();
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}
446 c570fd16 ths
447 c570fd16 ths
void op_ddivu (void)
448 c570fd16 ths
{
449 c570fd16 ths
    do_ddivu();
450 c570fd16 ths
    RETURN();
451 c570fd16 ths
}
452 c570fd16 ths
#else
453 c570fd16 ths
void op_ddiv (void)
454 c570fd16 ths
{
455 c570fd16 ths
    if (T1 != 0) {
456 c570fd16 ths
        env->LO = (int64_t)T0 / (int64_t)T1;
457 c570fd16 ths
        env->HI = (int64_t)T0 % (int64_t)T1;
458 c570fd16 ths
    }
459 c570fd16 ths
    RETURN();
460 c570fd16 ths
}
461 c570fd16 ths
462 c570fd16 ths
void op_ddivu (void)
463 c570fd16 ths
{
464 c570fd16 ths
    if (T1 != 0) {
465 6af0bf9c bellard
        env->LO = T0 / T1;
466 6af0bf9c bellard
        env->HI = T0 % T1;
467 6af0bf9c bellard
    }
468 6af0bf9c bellard
    RETURN();
469 6af0bf9c bellard
}
470 c570fd16 ths
#endif
471 c570fd16 ths
#endif /* MIPS_HAS_MIPS64 */
472 6af0bf9c bellard
473 6af0bf9c bellard
/* Logical */
474 6af0bf9c bellard
void op_and (void)
475 6af0bf9c bellard
{
476 6af0bf9c bellard
    T0 &= T1;
477 6af0bf9c bellard
    RETURN();
478 6af0bf9c bellard
}
479 6af0bf9c bellard
480 6af0bf9c bellard
void op_nor (void)
481 6af0bf9c bellard
{
482 6af0bf9c bellard
    T0 = ~(T0 | T1);
483 6af0bf9c bellard
    RETURN();
484 6af0bf9c bellard
}
485 6af0bf9c bellard
486 6af0bf9c bellard
void op_or (void)
487 6af0bf9c bellard
{
488 6af0bf9c bellard
    T0 |= T1;
489 6af0bf9c bellard
    RETURN();
490 6af0bf9c bellard
}
491 6af0bf9c bellard
492 6af0bf9c bellard
void op_xor (void)
493 6af0bf9c bellard
{
494 6af0bf9c bellard
    T0 ^= T1;
495 6af0bf9c bellard
    RETURN();
496 6af0bf9c bellard
}
497 6af0bf9c bellard
498 6af0bf9c bellard
void op_sll (void)
499 6af0bf9c bellard
{
500 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T0 << (uint32_t)T1);
501 6af0bf9c bellard
    RETURN();
502 6af0bf9c bellard
}
503 6af0bf9c bellard
504 6af0bf9c bellard
void op_sra (void)
505 6af0bf9c bellard
{
506 5dc4b744 ths
    T0 = (int32_t)((int32_t)T0 >> (uint32_t)T1);
507 6af0bf9c bellard
    RETURN();
508 6af0bf9c bellard
}
509 6af0bf9c bellard
510 6af0bf9c bellard
void op_srl (void)
511 6af0bf9c bellard
{
512 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1);
513 6af0bf9c bellard
    RETURN();
514 6af0bf9c bellard
}
515 6af0bf9c bellard
516 7a387fff ths
void op_rotr (void)
517 7a387fff ths
{
518 7a387fff ths
    target_ulong tmp;
519 7a387fff ths
520 7a387fff ths
    if (T1) {
521 5dc4b744 ths
       tmp = (int32_t)((uint32_t)T0 << (0x20 - (uint32_t)T1));
522 5dc4b744 ths
       T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1) | tmp;
523 7a387fff ths
    } else
524 7a387fff ths
       T0 = T1;
525 7a387fff ths
    RETURN();
526 7a387fff ths
}
527 7a387fff ths
528 6af0bf9c bellard
void op_sllv (void)
529 6af0bf9c bellard
{
530 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
531 6af0bf9c bellard
    RETURN();
532 6af0bf9c bellard
}
533 6af0bf9c bellard
534 6af0bf9c bellard
void op_srav (void)
535 6af0bf9c bellard
{
536 5dc4b744 ths
    T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
537 6af0bf9c bellard
    RETURN();
538 6af0bf9c bellard
}
539 6af0bf9c bellard
540 6af0bf9c bellard
void op_srlv (void)
541 6af0bf9c bellard
{
542 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
543 6af0bf9c bellard
    RETURN();
544 6af0bf9c bellard
}
545 6af0bf9c bellard
546 7a387fff ths
void op_rotrv (void)
547 7a387fff ths
{
548 7a387fff ths
    target_ulong tmp;
549 7a387fff ths
550 7a387fff ths
    T0 &= 0x1F;
551 7a387fff ths
    if (T0) {
552 5dc4b744 ths
       tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
553 5dc4b744 ths
       T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
554 7a387fff ths
    } else
555 7a387fff ths
       T0 = T1;
556 7a387fff ths
    RETURN();
557 7a387fff ths
}
558 7a387fff ths
559 6af0bf9c bellard
void op_clo (void)
560 6af0bf9c bellard
{
561 6af0bf9c bellard
    int n;
562 6af0bf9c bellard
563 c570fd16 ths
    if (T0 == ~((target_ulong)0)) {
564 6af0bf9c bellard
        T0 = 32;
565 6af0bf9c bellard
    } else {
566 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
567 6af0bf9c bellard
            if (!(T0 & (1 << 31)))
568 6af0bf9c bellard
                break;
569 6af0bf9c bellard
            T0 = T0 << 1;
570 6af0bf9c bellard
        }
571 6af0bf9c bellard
        T0 = n;
572 6af0bf9c bellard
    }
573 6af0bf9c bellard
    RETURN();
574 6af0bf9c bellard
}
575 6af0bf9c bellard
576 6af0bf9c bellard
void op_clz (void)
577 6af0bf9c bellard
{
578 6af0bf9c bellard
    int n;
579 6af0bf9c bellard
580 6af0bf9c bellard
    if (T0 == 0) {
581 6af0bf9c bellard
        T0 = 32;
582 6af0bf9c bellard
    } else {
583 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
584 6af0bf9c bellard
            if (T0 & (1 << 31))
585 6af0bf9c bellard
                break;
586 6af0bf9c bellard
            T0 = T0 << 1;
587 6af0bf9c bellard
        }
588 6af0bf9c bellard
        T0 = n;
589 6af0bf9c bellard
    }
590 6af0bf9c bellard
    RETURN();
591 6af0bf9c bellard
}
592 6af0bf9c bellard
593 c570fd16 ths
#ifdef MIPS_HAS_MIPS64
594 c570fd16 ths
595 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
596 c570fd16 ths
/* Those might call libgcc functions.  */
597 c570fd16 ths
void op_dsll (void)
598 6af0bf9c bellard
{
599 c570fd16 ths
    CALL_FROM_TB0(do_dsll);
600 c570fd16 ths
    RETURN();
601 6af0bf9c bellard
}
602 6af0bf9c bellard
603 c570fd16 ths
void op_dsll32 (void)
604 6af0bf9c bellard
{
605 c570fd16 ths
    CALL_FROM_TB0(do_dsll32);
606 c570fd16 ths
    RETURN();
607 6af0bf9c bellard
}
608 6af0bf9c bellard
609 c570fd16 ths
void op_dsra (void)
610 6af0bf9c bellard
{
611 c570fd16 ths
    CALL_FROM_TB0(do_dsra);
612 6af0bf9c bellard
    RETURN();
613 6af0bf9c bellard
}
614 6af0bf9c bellard
615 c570fd16 ths
void op_dsra32 (void)
616 6af0bf9c bellard
{
617 c570fd16 ths
    CALL_FROM_TB0(do_dsra32);
618 6af0bf9c bellard
    RETURN();
619 6af0bf9c bellard
}
620 6af0bf9c bellard
621 c570fd16 ths
void op_dsrl (void)
622 6af0bf9c bellard
{
623 c570fd16 ths
    CALL_FROM_TB0(do_dsrl);
624 c570fd16 ths
    RETURN();
625 c570fd16 ths
}
626 6af0bf9c bellard
627 c570fd16 ths
void op_dsrl32 (void)
628 c570fd16 ths
{
629 c570fd16 ths
    CALL_FROM_TB0(do_dsrl32);
630 6af0bf9c bellard
    RETURN();
631 6af0bf9c bellard
}
632 6af0bf9c bellard
633 c570fd16 ths
void op_drotr (void)
634 6af0bf9c bellard
{
635 c570fd16 ths
    CALL_FROM_TB0(do_drotr);
636 c570fd16 ths
    RETURN();
637 c570fd16 ths
}
638 6af0bf9c bellard
639 c570fd16 ths
void op_drotr32 (void)
640 c570fd16 ths
{
641 c570fd16 ths
    CALL_FROM_TB0(do_drotr32);
642 6af0bf9c bellard
    RETURN();
643 6af0bf9c bellard
}
644 6af0bf9c bellard
645 c570fd16 ths
void op_dsllv (void)
646 6af0bf9c bellard
{
647 c570fd16 ths
    CALL_FROM_TB0(do_dsllv);
648 c570fd16 ths
    RETURN();
649 c570fd16 ths
}
650 6af0bf9c bellard
651 c570fd16 ths
void op_dsrav (void)
652 c570fd16 ths
{
653 c570fd16 ths
    CALL_FROM_TB0(do_dsrav);
654 6af0bf9c bellard
    RETURN();
655 6af0bf9c bellard
}
656 6af0bf9c bellard
657 c570fd16 ths
void op_dsrlv (void)
658 6af0bf9c bellard
{
659 c570fd16 ths
    CALL_FROM_TB0(do_dsrlv);
660 c570fd16 ths
    RETURN();
661 c570fd16 ths
}
662 6af0bf9c bellard
663 c570fd16 ths
void op_drotrv (void)
664 c570fd16 ths
{
665 c570fd16 ths
    CALL_FROM_TB0(do_drotrv);
666 6af0bf9c bellard
    RETURN();
667 6af0bf9c bellard
}
668 c570fd16 ths
669 c570fd16 ths
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
670 c570fd16 ths
671 c570fd16 ths
void op_dsll (void)
672 c570fd16 ths
{
673 c570fd16 ths
    T0 = T0 << T1;
674 c570fd16 ths
    RETURN();
675 c570fd16 ths
}
676 c570fd16 ths
677 c570fd16 ths
void op_dsll32 (void)
678 c570fd16 ths
{
679 c570fd16 ths
    T0 = T0 << (T1 + 32);
680 c570fd16 ths
    RETURN();
681 c570fd16 ths
}
682 c570fd16 ths
683 c570fd16 ths
void op_dsra (void)
684 c570fd16 ths
{
685 c570fd16 ths
    T0 = (int64_t)T0 >> T1;
686 c570fd16 ths
    RETURN();
687 c570fd16 ths
}
688 c570fd16 ths
689 c570fd16 ths
void op_dsra32 (void)
690 c570fd16 ths
{
691 c570fd16 ths
    T0 = (int64_t)T0 >> (T1 + 32);
692 c570fd16 ths
    RETURN();
693 c570fd16 ths
}
694 c570fd16 ths
695 c570fd16 ths
void op_dsrl (void)
696 c570fd16 ths
{
697 c570fd16 ths
    T0 = T0 >> T1;
698 c570fd16 ths
    RETURN();
699 c570fd16 ths
}
700 c570fd16 ths
701 c570fd16 ths
void op_dsrl32 (void)
702 c570fd16 ths
{
703 c570fd16 ths
    T0 = T0 >> (T1 + 32);
704 c570fd16 ths
    RETURN();
705 c570fd16 ths
}
706 c570fd16 ths
707 c570fd16 ths
void op_drotr (void)
708 c570fd16 ths
{
709 c570fd16 ths
    target_ulong tmp;
710 c570fd16 ths
711 c570fd16 ths
    if (T1) {
712 c570fd16 ths
       tmp = T0 << (0x40 - T1);
713 c570fd16 ths
       T0 = (T0 >> T1) | tmp;
714 c570fd16 ths
    } else
715 c570fd16 ths
       T0 = T1;
716 c570fd16 ths
    RETURN();
717 c570fd16 ths
}
718 c570fd16 ths
719 c570fd16 ths
void op_drotr32 (void)
720 c570fd16 ths
{
721 c570fd16 ths
    target_ulong tmp;
722 c570fd16 ths
723 c570fd16 ths
    if (T1) {
724 c570fd16 ths
       tmp = T0 << (0x40 - (32 + T1));
725 c570fd16 ths
       T0 = (T0 >> (32 + T1)) | tmp;
726 c570fd16 ths
    } else
727 c570fd16 ths
       T0 = T1;
728 c570fd16 ths
    RETURN();
729 c570fd16 ths
}
730 c570fd16 ths
731 c570fd16 ths
void op_dsllv (void)
732 c570fd16 ths
{
733 c570fd16 ths
    T0 = T1 << (T0 & 0x3F);
734 c570fd16 ths
    RETURN();
735 c570fd16 ths
}
736 c570fd16 ths
737 c570fd16 ths
void op_dsrav (void)
738 c570fd16 ths
{
739 c570fd16 ths
    T0 = (int64_t)T1 >> (T0 & 0x3F);
740 c570fd16 ths
    RETURN();
741 c570fd16 ths
}
742 c570fd16 ths
743 c570fd16 ths
void op_dsrlv (void)
744 c570fd16 ths
{
745 c570fd16 ths
    T0 = T1 >> (T0 & 0x3F);
746 c570fd16 ths
    RETURN();
747 c570fd16 ths
}
748 c570fd16 ths
749 c570fd16 ths
void op_drotrv (void)
750 c570fd16 ths
{
751 c570fd16 ths
    target_ulong tmp;
752 c570fd16 ths
753 c570fd16 ths
    T0 &= 0x3F;
754 c570fd16 ths
    if (T0) {
755 c570fd16 ths
       tmp = T1 << (0x40 - T0);
756 c570fd16 ths
       T0 = (T1 >> T0) | tmp;
757 c570fd16 ths
    } else
758 c570fd16 ths
       T0 = T1;
759 c570fd16 ths
    RETURN();
760 c570fd16 ths
}
761 c570fd16 ths
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
762 c570fd16 ths
763 c570fd16 ths
void op_dclo (void)
764 c570fd16 ths
{
765 c570fd16 ths
    int n;
766 c570fd16 ths
767 c570fd16 ths
    if (T0 == ~((target_ulong)0)) {
768 c570fd16 ths
        T0 = 64;
769 c570fd16 ths
    } else {
770 c570fd16 ths
        for (n = 0; n < 64; n++) {
771 c570fd16 ths
            if (!(T0 & (1ULL << 63)))
772 c570fd16 ths
                break;
773 c570fd16 ths
            T0 = T0 << 1;
774 c570fd16 ths
        }
775 c570fd16 ths
        T0 = n;
776 c570fd16 ths
    }
777 c570fd16 ths
    RETURN();
778 c570fd16 ths
}
779 c570fd16 ths
780 c570fd16 ths
void op_dclz (void)
781 c570fd16 ths
{
782 c570fd16 ths
    int n;
783 c570fd16 ths
784 c570fd16 ths
    if (T0 == 0) {
785 c570fd16 ths
        T0 = 64;
786 c570fd16 ths
    } else {
787 c570fd16 ths
        for (n = 0; n < 64; n++) {
788 c570fd16 ths
            if (T0 & (1ULL << 63))
789 c570fd16 ths
                break;
790 c570fd16 ths
            T0 = T0 << 1;
791 c570fd16 ths
        }
792 c570fd16 ths
        T0 = n;
793 c570fd16 ths
    }
794 c570fd16 ths
    RETURN();
795 c570fd16 ths
}
796 c570fd16 ths
#endif
797 c570fd16 ths
798 c570fd16 ths
/* 64 bits arithmetic */
799 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
800 6af0bf9c bellard
void op_mult (void)
801 6af0bf9c bellard
{
802 6af0bf9c bellard
    CALL_FROM_TB0(do_mult);
803 6af0bf9c bellard
    RETURN();
804 6af0bf9c bellard
}
805 6af0bf9c bellard
806 6af0bf9c bellard
void op_multu (void)
807 6af0bf9c bellard
{
808 6af0bf9c bellard
    CALL_FROM_TB0(do_multu);
809 6af0bf9c bellard
    RETURN();
810 6af0bf9c bellard
}
811 6af0bf9c bellard
812 6af0bf9c bellard
void op_madd (void)
813 6af0bf9c bellard
{
814 6af0bf9c bellard
    CALL_FROM_TB0(do_madd);
815 6af0bf9c bellard
    RETURN();
816 6af0bf9c bellard
}
817 6af0bf9c bellard
818 6af0bf9c bellard
void op_maddu (void)
819 6af0bf9c bellard
{
820 6af0bf9c bellard
    CALL_FROM_TB0(do_maddu);
821 6af0bf9c bellard
    RETURN();
822 6af0bf9c bellard
}
823 6af0bf9c bellard
824 6af0bf9c bellard
void op_msub (void)
825 6af0bf9c bellard
{
826 6af0bf9c bellard
    CALL_FROM_TB0(do_msub);
827 6af0bf9c bellard
    RETURN();
828 6af0bf9c bellard
}
829 6af0bf9c bellard
830 6af0bf9c bellard
void op_msubu (void)
831 6af0bf9c bellard
{
832 6af0bf9c bellard
    CALL_FROM_TB0(do_msubu);
833 6af0bf9c bellard
    RETURN();
834 6af0bf9c bellard
}
835 c570fd16 ths
836 c570fd16 ths
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
837 c570fd16 ths
838 c570fd16 ths
static inline uint64_t get_HILO (void)
839 c570fd16 ths
{
840 c570fd16 ths
    return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO);
841 c570fd16 ths
}
842 c570fd16 ths
843 c570fd16 ths
static inline void set_HILO (uint64_t HILO)
844 c570fd16 ths
{
845 5dc4b744 ths
    env->LO = (int32_t)(HILO & 0xFFFFFFFF);
846 5dc4b744 ths
    env->HI = (int32_t)(HILO >> 32);
847 c570fd16 ths
}
848 c570fd16 ths
849 c570fd16 ths
void op_mult (void)
850 c570fd16 ths
{
851 c570fd16 ths
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
852 c570fd16 ths
    RETURN();
853 c570fd16 ths
}
854 c570fd16 ths
855 c570fd16 ths
void op_multu (void)
856 c570fd16 ths
{
857 c570fd16 ths
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
858 c570fd16 ths
    RETURN();
859 c570fd16 ths
}
860 c570fd16 ths
861 c570fd16 ths
void op_madd (void)
862 c570fd16 ths
{
863 c570fd16 ths
    int64_t tmp;
864 c570fd16 ths
865 c570fd16 ths
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
866 c570fd16 ths
    set_HILO((int64_t)get_HILO() + tmp);
867 c570fd16 ths
    RETURN();
868 c570fd16 ths
}
869 c570fd16 ths
870 c570fd16 ths
void op_maddu (void)
871 c570fd16 ths
{
872 c570fd16 ths
    uint64_t tmp;
873 c570fd16 ths
874 c570fd16 ths
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
875 c570fd16 ths
    set_HILO(get_HILO() + tmp);
876 c570fd16 ths
    RETURN();
877 c570fd16 ths
}
878 c570fd16 ths
879 c570fd16 ths
void op_msub (void)
880 c570fd16 ths
{
881 c570fd16 ths
    int64_t tmp;
882 c570fd16 ths
883 c570fd16 ths
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
884 c570fd16 ths
    set_HILO((int64_t)get_HILO() - tmp);
885 c570fd16 ths
    RETURN();
886 c570fd16 ths
}
887 c570fd16 ths
888 c570fd16 ths
void op_msubu (void)
889 c570fd16 ths
{
890 c570fd16 ths
    uint64_t tmp;
891 c570fd16 ths
892 c570fd16 ths
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
893 c570fd16 ths
    set_HILO(get_HILO() - tmp);
894 c570fd16 ths
    RETURN();
895 c570fd16 ths
}
896 c570fd16 ths
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
897 c570fd16 ths
898 c570fd16 ths
#ifdef MIPS_HAS_MIPS64
899 c570fd16 ths
void op_dmult (void)
900 c570fd16 ths
{
901 c570fd16 ths
    CALL_FROM_TB0(do_dmult);
902 c570fd16 ths
    RETURN();
903 c570fd16 ths
}
904 c570fd16 ths
905 c570fd16 ths
void op_dmultu (void)
906 c570fd16 ths
{
907 c570fd16 ths
    CALL_FROM_TB0(do_dmultu);
908 c570fd16 ths
    RETURN();
909 c570fd16 ths
}
910 6af0bf9c bellard
#endif
911 6af0bf9c bellard
912 6af0bf9c bellard
/* Conditional moves */
913 6af0bf9c bellard
void op_movn (void)
914 6af0bf9c bellard
{
915 6af0bf9c bellard
    if (T1 != 0)
916 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
917 6af0bf9c bellard
    RETURN();
918 6af0bf9c bellard
}
919 6af0bf9c bellard
920 6af0bf9c bellard
void op_movz (void)
921 6af0bf9c bellard
{
922 6af0bf9c bellard
    if (T1 == 0)
923 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
924 6af0bf9c bellard
    RETURN();
925 6af0bf9c bellard
}
926 6af0bf9c bellard
927 71fb7241 ths
#ifdef MIPS_USES_FPU
928 7a387fff ths
void op_movf (void)
929 7a387fff ths
{
930 7a387fff ths
    if (!(env->fcr31 & PARAM1))
931 7a387fff ths
        env->gpr[PARAM2] = env->gpr[PARAM3];
932 7a387fff ths
    RETURN();
933 7a387fff ths
}
934 7a387fff ths
935 7a387fff ths
void op_movt (void)
936 7a387fff ths
{
937 7a387fff ths
    if (env->fcr31 & PARAM1)
938 7a387fff ths
        env->gpr[PARAM2] = env->gpr[PARAM3];
939 7a387fff ths
    RETURN();
940 7a387fff ths
}
941 71fb7241 ths
#endif
942 7a387fff ths
943 6af0bf9c bellard
/* Tests */
944 6af0bf9c bellard
#define OP_COND(name, cond) \
945 6af0bf9c bellard
void glue(op_, name) (void) \
946 6af0bf9c bellard
{                           \
947 6af0bf9c bellard
    if (cond) {             \
948 6af0bf9c bellard
        T0 = 1;             \
949 6af0bf9c bellard
    } else {                \
950 6af0bf9c bellard
        T0 = 0;             \
951 6af0bf9c bellard
    }                       \
952 6af0bf9c bellard
    RETURN();               \
953 6af0bf9c bellard
}
954 6af0bf9c bellard
955 6af0bf9c bellard
OP_COND(eq, T0 == T1);
956 6af0bf9c bellard
OP_COND(ne, T0 != T1);
957 6af0bf9c bellard
OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
958 6af0bf9c bellard
OP_COND(geu, T0 >= T1);
959 6af0bf9c bellard
OP_COND(lt, (int32_t)T0 < (int32_t)T1);
960 6af0bf9c bellard
OP_COND(ltu, T0 < T1);
961 6af0bf9c bellard
OP_COND(gez, (int32_t)T0 >= 0);
962 6af0bf9c bellard
OP_COND(gtz, (int32_t)T0 > 0);
963 6af0bf9c bellard
OP_COND(lez, (int32_t)T0 <= 0);
964 6af0bf9c bellard
OP_COND(ltz, (int32_t)T0 < 0);
965 6af0bf9c bellard
966 7a387fff ths
/* Branches */
967 6af0bf9c bellard
//#undef USE_DIRECT_JUMP
968 c53be334 bellard
969 c53be334 bellard
void OPPROTO op_goto_tb0(void)
970 c53be334 bellard
{
971 c53be334 bellard
    GOTO_TB(op_goto_tb0, PARAM1, 0);
972 7a387fff ths
    RETURN();
973 c53be334 bellard
}
974 c53be334 bellard
975 c53be334 bellard
void OPPROTO op_goto_tb1(void)
976 c53be334 bellard
{
977 c53be334 bellard
    GOTO_TB(op_goto_tb1, PARAM1, 1);
978 7a387fff ths
    RETURN();
979 c53be334 bellard
}
980 6af0bf9c bellard
981 6af0bf9c bellard
/* Branch to register */
982 6af0bf9c bellard
void op_save_breg_target (void)
983 6af0bf9c bellard
{
984 6af0bf9c bellard
    env->btarget = T2;
985 7a387fff ths
    RETURN();
986 6af0bf9c bellard
}
987 6af0bf9c bellard
988 6af0bf9c bellard
void op_restore_breg_target (void)
989 6af0bf9c bellard
{
990 6af0bf9c bellard
    T2 = env->btarget;
991 7a387fff ths
    RETURN();
992 6af0bf9c bellard
}
993 6af0bf9c bellard
994 6af0bf9c bellard
void op_breg (void)
995 6af0bf9c bellard
{
996 6af0bf9c bellard
    env->PC = T2;
997 6af0bf9c bellard
    RETURN();
998 6af0bf9c bellard
}
999 6af0bf9c bellard
1000 6af0bf9c bellard
void op_save_btarget (void)
1001 6af0bf9c bellard
{
1002 6af0bf9c bellard
    env->btarget = PARAM1;
1003 6af0bf9c bellard
    RETURN();
1004 6af0bf9c bellard
}
1005 6af0bf9c bellard
1006 6af0bf9c bellard
/* Conditional branch */
1007 6af0bf9c bellard
void op_set_bcond (void)
1008 6af0bf9c bellard
{
1009 6af0bf9c bellard
    T2 = T0;
1010 6af0bf9c bellard
    RETURN();
1011 6af0bf9c bellard
}
1012 6af0bf9c bellard
1013 6af0bf9c bellard
void op_save_bcond (void)
1014 6af0bf9c bellard
{
1015 6af0bf9c bellard
    env->bcond = T2;
1016 6af0bf9c bellard
    RETURN();
1017 6af0bf9c bellard
}
1018 6af0bf9c bellard
1019 6af0bf9c bellard
void op_restore_bcond (void)
1020 6af0bf9c bellard
{
1021 6af0bf9c bellard
    T2 = env->bcond;
1022 6af0bf9c bellard
    RETURN();
1023 6af0bf9c bellard
}
1024 6af0bf9c bellard
1025 c53be334 bellard
void op_jnz_T2 (void)
1026 6af0bf9c bellard
{
1027 c53be334 bellard
    if (T2)
1028 c53be334 bellard
        GOTO_LABEL_PARAM(1);
1029 6af0bf9c bellard
    RETURN();
1030 6af0bf9c bellard
}
1031 6af0bf9c bellard
1032 6af0bf9c bellard
/* CP0 functions */
1033 873eb012 ths
void op_mfc0_index (void)
1034 6af0bf9c bellard
{
1035 9c2149c8 ths
    T0 = env->CP0_Index;
1036 873eb012 ths
    RETURN();
1037 873eb012 ths
}
1038 873eb012 ths
1039 873eb012 ths
void op_mfc0_random (void)
1040 873eb012 ths
{
1041 873eb012 ths
    CALL_FROM_TB0(do_mfc0_random);
1042 873eb012 ths
    RETURN();
1043 873eb012 ths
}
1044 873eb012 ths
1045 873eb012 ths
void op_mfc0_entrylo0 (void)
1046 873eb012 ths
{
1047 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryLo0;
1048 873eb012 ths
    RETURN();
1049 873eb012 ths
}
1050 873eb012 ths
1051 873eb012 ths
void op_mfc0_entrylo1 (void)
1052 873eb012 ths
{
1053 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryLo1;
1054 873eb012 ths
    RETURN();
1055 873eb012 ths
}
1056 873eb012 ths
1057 873eb012 ths
void op_mfc0_context (void)
1058 873eb012 ths
{
1059 9c2149c8 ths
    T0 = (int32_t)env->CP0_Context;
1060 873eb012 ths
    RETURN();
1061 873eb012 ths
}
1062 873eb012 ths
1063 873eb012 ths
void op_mfc0_pagemask (void)
1064 873eb012 ths
{
1065 9c2149c8 ths
    T0 = env->CP0_PageMask;
1066 873eb012 ths
    RETURN();
1067 873eb012 ths
}
1068 873eb012 ths
1069 7a387fff ths
void op_mfc0_pagegrain (void)
1070 7a387fff ths
{
1071 9c2149c8 ths
    T0 = env->CP0_PageGrain;
1072 7a387fff ths
    RETURN();
1073 7a387fff ths
}
1074 7a387fff ths
1075 873eb012 ths
void op_mfc0_wired (void)
1076 873eb012 ths
{
1077 9c2149c8 ths
    T0 = env->CP0_Wired;
1078 873eb012 ths
    RETURN();
1079 873eb012 ths
}
1080 873eb012 ths
1081 7a387fff ths
void op_mfc0_hwrena (void)
1082 7a387fff ths
{
1083 9c2149c8 ths
    T0 = env->CP0_HWREna;
1084 7a387fff ths
    RETURN();
1085 7a387fff ths
}
1086 7a387fff ths
1087 873eb012 ths
void op_mfc0_badvaddr (void)
1088 873eb012 ths
{
1089 9c2149c8 ths
    T0 = (int32_t)env->CP0_BadVAddr;
1090 873eb012 ths
    RETURN();
1091 873eb012 ths
}
1092 873eb012 ths
1093 873eb012 ths
void op_mfc0_count (void)
1094 873eb012 ths
{
1095 873eb012 ths
    CALL_FROM_TB0(do_mfc0_count);
1096 873eb012 ths
    RETURN();
1097 873eb012 ths
}
1098 873eb012 ths
1099 873eb012 ths
void op_mfc0_entryhi (void)
1100 873eb012 ths
{
1101 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryHi;
1102 873eb012 ths
    RETURN();
1103 873eb012 ths
}
1104 873eb012 ths
1105 873eb012 ths
void op_mfc0_compare (void)
1106 873eb012 ths
{
1107 9c2149c8 ths
    T0 = env->CP0_Compare;
1108 873eb012 ths
    RETURN();
1109 873eb012 ths
}
1110 873eb012 ths
1111 873eb012 ths
void op_mfc0_status (void)
1112 873eb012 ths
{
1113 9c2149c8 ths
    T0 = env->CP0_Status;
1114 873eb012 ths
    if (env->hflags & MIPS_HFLAG_UM)
1115 873eb012 ths
        T0 |= (1 << CP0St_UM);
1116 873eb012 ths
    if (env->hflags & MIPS_HFLAG_ERL)
1117 873eb012 ths
        T0 |= (1 << CP0St_ERL);
1118 873eb012 ths
    if (env->hflags & MIPS_HFLAG_EXL)
1119 873eb012 ths
        T0 |= (1 << CP0St_EXL);
1120 873eb012 ths
    RETURN();
1121 873eb012 ths
}
1122 873eb012 ths
1123 7a387fff ths
void op_mfc0_intctl (void)
1124 7a387fff ths
{
1125 9c2149c8 ths
    T0 = env->CP0_IntCtl;
1126 7a387fff ths
    RETURN();
1127 7a387fff ths
}
1128 7a387fff ths
1129 7a387fff ths
void op_mfc0_srsctl (void)
1130 7a387fff ths
{
1131 9c2149c8 ths
    T0 = env->CP0_SRSCtl;
1132 9c2149c8 ths
    RETURN();
1133 9c2149c8 ths
}
1134 9c2149c8 ths
1135 9c2149c8 ths
void op_mfc0_srsmap (void)
1136 9c2149c8 ths
{
1137 9c2149c8 ths
    T0 = env->CP0_SRSMap;
1138 7a387fff ths
    RETURN();
1139 7a387fff ths
}
1140 7a387fff ths
1141 873eb012 ths
void op_mfc0_cause (void)
1142 873eb012 ths
{
1143 9c2149c8 ths
    T0 = env->CP0_Cause;
1144 873eb012 ths
    RETURN();
1145 873eb012 ths
}
1146 873eb012 ths
1147 873eb012 ths
void op_mfc0_epc (void)
1148 873eb012 ths
{
1149 9c2149c8 ths
    T0 = (int32_t)env->CP0_EPC;
1150 873eb012 ths
    RETURN();
1151 873eb012 ths
}
1152 873eb012 ths
1153 873eb012 ths
void op_mfc0_prid (void)
1154 873eb012 ths
{
1155 9c2149c8 ths
    T0 = env->CP0_PRid;
1156 873eb012 ths
    RETURN();
1157 873eb012 ths
}
1158 873eb012 ths
1159 7a387fff ths
void op_mfc0_ebase (void)
1160 7a387fff ths
{
1161 b29a0341 ths
    T0 = env->CP0_EBase;
1162 7a387fff ths
    RETURN();
1163 7a387fff ths
}
1164 7a387fff ths
1165 873eb012 ths
void op_mfc0_config0 (void)
1166 873eb012 ths
{
1167 9c2149c8 ths
    T0 = env->CP0_Config0;
1168 873eb012 ths
    RETURN();
1169 873eb012 ths
}
1170 873eb012 ths
1171 873eb012 ths
void op_mfc0_config1 (void)
1172 873eb012 ths
{
1173 9c2149c8 ths
    T0 = env->CP0_Config1;
1174 873eb012 ths
    RETURN();
1175 873eb012 ths
}
1176 873eb012 ths
1177 7a387fff ths
void op_mfc0_config2 (void)
1178 7a387fff ths
{
1179 9c2149c8 ths
    T0 = env->CP0_Config2;
1180 7a387fff ths
    RETURN();
1181 7a387fff ths
}
1182 7a387fff ths
1183 7a387fff ths
void op_mfc0_config3 (void)
1184 7a387fff ths
{
1185 9c2149c8 ths
    T0 = env->CP0_Config3;
1186 7a387fff ths
    RETURN();
1187 7a387fff ths
}
1188 7a387fff ths
1189 873eb012 ths
void op_mfc0_lladdr (void)
1190 873eb012 ths
{
1191 9c2149c8 ths
    T0 = (int32_t)env->CP0_LLAddr >> 4;
1192 873eb012 ths
    RETURN();
1193 873eb012 ths
}
1194 873eb012 ths
1195 7a387fff ths
void op_mfc0_watchlo0 (void)
1196 873eb012 ths
{
1197 5dc4b744 ths
    T0 = (int32_t)env->CP0_WatchLo;
1198 873eb012 ths
    RETURN();
1199 873eb012 ths
}
1200 873eb012 ths
1201 7a387fff ths
void op_mfc0_watchhi0 (void)
1202 873eb012 ths
{
1203 9c2149c8 ths
    T0 = env->CP0_WatchHi;
1204 873eb012 ths
    RETURN();
1205 873eb012 ths
}
1206 873eb012 ths
1207 7a387fff ths
void op_mfc0_xcontext (void)
1208 7a387fff ths
{
1209 9c2149c8 ths
    T0 = (int32_t)env->CP0_XContext;
1210 7a387fff ths
    RETURN();
1211 7a387fff ths
}
1212 7a387fff ths
1213 7a387fff ths
void op_mfc0_framemask (void)
1214 7a387fff ths
{
1215 7a387fff ths
    T0 = env->CP0_Framemask;
1216 7a387fff ths
    RETURN();
1217 7a387fff ths
}
1218 7a387fff ths
1219 873eb012 ths
void op_mfc0_debug (void)
1220 873eb012 ths
{
1221 9c2149c8 ths
    T0 = env->CP0_Debug;
1222 873eb012 ths
    if (env->hflags & MIPS_HFLAG_DM)
1223 873eb012 ths
        T0 |= 1 << CP0DB_DM;
1224 873eb012 ths
    RETURN();
1225 873eb012 ths
}
1226 873eb012 ths
1227 873eb012 ths
void op_mfc0_depc (void)
1228 873eb012 ths
{
1229 9c2149c8 ths
    T0 = (int32_t)env->CP0_DEPC;
1230 873eb012 ths
    RETURN();
1231 873eb012 ths
}
1232 873eb012 ths
1233 7a387fff ths
void op_mfc0_performance0 (void)
1234 7a387fff ths
{
1235 9c2149c8 ths
    T0 = env->CP0_Performance0;
1236 7a387fff ths
    RETURN();
1237 7a387fff ths
}
1238 7a387fff ths
1239 873eb012 ths
void op_mfc0_taglo (void)
1240 873eb012 ths
{
1241 9c2149c8 ths
    T0 = env->CP0_TagLo;
1242 873eb012 ths
    RETURN();
1243 873eb012 ths
}
1244 873eb012 ths
1245 873eb012 ths
void op_mfc0_datalo (void)
1246 873eb012 ths
{
1247 9c2149c8 ths
    T0 = env->CP0_DataLo;
1248 873eb012 ths
    RETURN();
1249 873eb012 ths
}
1250 873eb012 ths
1251 7a387fff ths
void op_mfc0_taghi (void)
1252 7a387fff ths
{
1253 9c2149c8 ths
    T0 = env->CP0_TagHi;
1254 7a387fff ths
    RETURN();
1255 7a387fff ths
}
1256 7a387fff ths
1257 7a387fff ths
void op_mfc0_datahi (void)
1258 7a387fff ths
{
1259 9c2149c8 ths
    T0 = env->CP0_DataHi;
1260 7a387fff ths
    RETURN();
1261 7a387fff ths
}
1262 7a387fff ths
1263 873eb012 ths
void op_mfc0_errorepc (void)
1264 873eb012 ths
{
1265 9c2149c8 ths
    T0 = (int32_t)env->CP0_ErrorEPC;
1266 873eb012 ths
    RETURN();
1267 873eb012 ths
}
1268 873eb012 ths
1269 873eb012 ths
void op_mfc0_desave (void)
1270 873eb012 ths
{
1271 9c2149c8 ths
    T0 = env->CP0_DESAVE;
1272 6af0bf9c bellard
    RETURN();
1273 6af0bf9c bellard
}
1274 6af0bf9c bellard
1275 8c0fdd85 ths
void op_mtc0_index (void)
1276 6af0bf9c bellard
{
1277 9c2149c8 ths
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
1278 8c0fdd85 ths
    RETURN();
1279 8c0fdd85 ths
}
1280 8c0fdd85 ths
1281 8c0fdd85 ths
void op_mtc0_entrylo0 (void)
1282 8c0fdd85 ths
{
1283 7a387fff ths
    /* Large physaddr not implemented */
1284 7a387fff ths
    /* 1k pages not implemented */
1285 9c2149c8 ths
    env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
1286 8c0fdd85 ths
    RETURN();
1287 8c0fdd85 ths
}
1288 8c0fdd85 ths
1289 8c0fdd85 ths
void op_mtc0_entrylo1 (void)
1290 8c0fdd85 ths
{
1291 7a387fff ths
    /* Large physaddr not implemented */
1292 7a387fff ths
    /* 1k pages not implemented */
1293 9c2149c8 ths
    env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
1294 8c0fdd85 ths
    RETURN();
1295 8c0fdd85 ths
}
1296 8c0fdd85 ths
1297 8c0fdd85 ths
void op_mtc0_context (void)
1298 8c0fdd85 ths
{
1299 7a387fff ths
    env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
1300 8c0fdd85 ths
    RETURN();
1301 8c0fdd85 ths
}
1302 8c0fdd85 ths
1303 8c0fdd85 ths
void op_mtc0_pagemask (void)
1304 8c0fdd85 ths
{
1305 7a387fff ths
    /* 1k pages not implemented */
1306 7a387fff ths
    env->CP0_PageMask = T0 & 0x1FFFE000;
1307 7a387fff ths
    RETURN();
1308 7a387fff ths
}
1309 7a387fff ths
1310 7a387fff ths
void op_mtc0_pagegrain (void)
1311 7a387fff ths
{
1312 7a387fff ths
    /* SmartMIPS not implemented */
1313 7a387fff ths
    /* Large physaddr not implemented */
1314 7a387fff ths
    /* 1k pages not implemented */
1315 7a387fff ths
    env->CP0_PageGrain = 0;
1316 8c0fdd85 ths
    RETURN();
1317 8c0fdd85 ths
}
1318 8c0fdd85 ths
1319 8c0fdd85 ths
void op_mtc0_wired (void)
1320 8c0fdd85 ths
{
1321 7a387fff ths
    env->CP0_Wired = T0 & (MIPS_TLB_NB - 1);
1322 7a387fff ths
    RETURN();
1323 7a387fff ths
}
1324 7a387fff ths
1325 7a387fff ths
void op_mtc0_hwrena (void)
1326 7a387fff ths
{
1327 7a387fff ths
    env->CP0_HWREna = T0 & 0x0000000F;
1328 8c0fdd85 ths
    RETURN();
1329 8c0fdd85 ths
}
1330 8c0fdd85 ths
1331 8c0fdd85 ths
void op_mtc0_count (void)
1332 8c0fdd85 ths
{
1333 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1334 8c0fdd85 ths
    RETURN();
1335 8c0fdd85 ths
}
1336 8c0fdd85 ths
1337 8c0fdd85 ths
void op_mtc0_entryhi (void)
1338 8c0fdd85 ths
{
1339 0feef828 ths
    target_ulong old, val;
1340 8c0fdd85 ths
1341 7a387fff ths
    /* 1k pages not implemented */
1342 7a387fff ths
    /* Ignore MIPS64 TLB for now */
1343 9c2149c8 ths
    val = (int32_t)T0 & 0xFFFFE0FF;
1344 8c0fdd85 ths
    old = env->CP0_EntryHi;
1345 8c0fdd85 ths
    env->CP0_EntryHi = val;
1346 8c0fdd85 ths
    /* If the ASID changes, flush qemu's TLB.  */
1347 8c0fdd85 ths
    if ((old & 0xFF) != (val & 0xFF))
1348 8c0fdd85 ths
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1349 8c0fdd85 ths
    RETURN();
1350 8c0fdd85 ths
}
1351 8c0fdd85 ths
1352 8c0fdd85 ths
void op_mtc0_compare (void)
1353 8c0fdd85 ths
{
1354 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1355 8c0fdd85 ths
    RETURN();
1356 8c0fdd85 ths
}
1357 8c0fdd85 ths
1358 8c0fdd85 ths
void op_mtc0_status (void)
1359 8c0fdd85 ths
{
1360 4de9b249 ths
    uint32_t val, old;
1361 8c0fdd85 ths
1362 9c2149c8 ths
    val = (int32_t)T0 & 0xFA78FF01;
1363 8c0fdd85 ths
    old = env->CP0_Status;
1364 8c0fdd85 ths
    if (T0 & (1 << CP0St_UM))
1365 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_UM;
1366 8c0fdd85 ths
    else
1367 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_UM;
1368 8c0fdd85 ths
    if (T0 & (1 << CP0St_ERL))
1369 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_ERL;
1370 8c0fdd85 ths
    else
1371 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_ERL;
1372 8c0fdd85 ths
    if (T0 & (1 << CP0St_EXL))
1373 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_EXL;
1374 8c0fdd85 ths
    else
1375 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_EXL;
1376 8c0fdd85 ths
    env->CP0_Status = val;
1377 8c0fdd85 ths
    if (loglevel & CPU_LOG_TB_IN_ASM)
1378 8c0fdd85 ths
       CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1379 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
1380 8c0fdd85 ths
    RETURN();
1381 8c0fdd85 ths
}
1382 8c0fdd85 ths
1383 7a387fff ths
void op_mtc0_intctl (void)
1384 7a387fff ths
{
1385 7a387fff ths
    /* vectored interrupts not implemented */
1386 7a387fff ths
    env->CP0_IntCtl = 0;
1387 7a387fff ths
    RETURN();
1388 7a387fff ths
}
1389 7a387fff ths
1390 7a387fff ths
void op_mtc0_srsctl (void)
1391 7a387fff ths
{
1392 7a387fff ths
    /* shadow registers not implemented */
1393 7a387fff ths
    env->CP0_SRSCtl = 0;
1394 7a387fff ths
    RETURN();
1395 7a387fff ths
}
1396 7a387fff ths
1397 9c2149c8 ths
void op_mtc0_srsmap (void)
1398 9c2149c8 ths
{
1399 9c2149c8 ths
    /* shadow registers not implemented */
1400 9c2149c8 ths
    env->CP0_SRSMap = 0;
1401 9c2149c8 ths
    RETURN();
1402 9c2149c8 ths
}
1403 9c2149c8 ths
1404 8c0fdd85 ths
void op_mtc0_cause (void)
1405 8c0fdd85 ths
{
1406 4de9b249 ths
    env->CP0_Cause = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x00C00300);
1407 8c0fdd85 ths
1408 4de9b249 ths
    /* Handle the software interrupt as an hardware one, as they
1409 4de9b249 ths
       are very similar */
1410 4de9b249 ths
    if (T0 & CP0Ca_IP_mask) {
1411 4de9b249 ths
        CALL_FROM_TB1(cpu_mips_update_irq, env);
1412 8c0fdd85 ths
    }
1413 8c0fdd85 ths
    RETURN();
1414 8c0fdd85 ths
}
1415 8c0fdd85 ths
1416 8c0fdd85 ths
void op_mtc0_epc (void)
1417 8c0fdd85 ths
{
1418 9c2149c8 ths
    env->CP0_EPC = (int32_t)T0;
1419 8c0fdd85 ths
    RETURN();
1420 8c0fdd85 ths
}
1421 8c0fdd85 ths
1422 7a387fff ths
void op_mtc0_ebase (void)
1423 7a387fff ths
{
1424 7a387fff ths
    /* vectored interrupts not implemented */
1425 7a387fff ths
    /* Multi-CPU not implemented */
1426 b29a0341 ths
    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1427 7a387fff ths
    RETURN();
1428 7a387fff ths
}
1429 7a387fff ths
1430 8c0fdd85 ths
void op_mtc0_config0 (void)
1431 8c0fdd85 ths
{
1432 8c0fdd85 ths
#if defined(MIPS_USES_R4K_TLB)
1433 7a387fff ths
     /* Fixed mapping MMU not implemented */
1434 7a387fff ths
    env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001);
1435 8c0fdd85 ths
#else
1436 7a387fff ths
    env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
1437 8c0fdd85 ths
#endif
1438 8c0fdd85 ths
    RETURN();
1439 8c0fdd85 ths
}
1440 8c0fdd85 ths
1441 7a387fff ths
void op_mtc0_config2 (void)
1442 7a387fff ths
{
1443 7a387fff ths
    /* tertiary/secondary caches not implemented */
1444 7a387fff ths
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1445 7a387fff ths
    RETURN();
1446 7a387fff ths
}
1447 7a387fff ths
1448 7a387fff ths
void op_mtc0_watchlo0 (void)
1449 8c0fdd85 ths
{
1450 9c2149c8 ths
    env->CP0_WatchLo = (int32_t)T0;
1451 8c0fdd85 ths
    RETURN();
1452 8c0fdd85 ths
}
1453 8c0fdd85 ths
1454 7a387fff ths
void op_mtc0_watchhi0 (void)
1455 8c0fdd85 ths
{
1456 8c0fdd85 ths
    env->CP0_WatchHi = T0 & 0x40FF0FF8;
1457 8c0fdd85 ths
    RETURN();
1458 8c0fdd85 ths
}
1459 8c0fdd85 ths
1460 7a387fff ths
void op_mtc0_xcontext (void)
1461 7a387fff ths
{
1462 9c2149c8 ths
    env->CP0_XContext = (int32_t)T0; /* XXX */
1463 7a387fff ths
    RETURN();
1464 7a387fff ths
}
1465 7a387fff ths
1466 7a387fff ths
void op_mtc0_framemask (void)
1467 7a387fff ths
{
1468 7a387fff ths
    env->CP0_Framemask = T0; /* XXX */
1469 7a387fff ths
    RETURN();
1470 7a387fff ths
}
1471 7a387fff ths
1472 8c0fdd85 ths
void op_mtc0_debug (void)
1473 8c0fdd85 ths
{
1474 8c0fdd85 ths
    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1475 8c0fdd85 ths
    if (T0 & (1 << CP0DB_DM))
1476 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_DM;
1477 8c0fdd85 ths
    else
1478 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_DM;
1479 8c0fdd85 ths
    RETURN();
1480 8c0fdd85 ths
}
1481 8c0fdd85 ths
1482 8c0fdd85 ths
void op_mtc0_depc (void)
1483 8c0fdd85 ths
{
1484 9c2149c8 ths
    env->CP0_DEPC = (int32_t)T0;
1485 8c0fdd85 ths
    RETURN();
1486 8c0fdd85 ths
}
1487 8c0fdd85 ths
1488 7a387fff ths
void op_mtc0_performance0 (void)
1489 7a387fff ths
{
1490 7a387fff ths
    env->CP0_Performance0 = T0; /* XXX */
1491 7a387fff ths
    RETURN();
1492 7a387fff ths
}
1493 7a387fff ths
1494 8c0fdd85 ths
void op_mtc0_taglo (void)
1495 8c0fdd85 ths
{
1496 9c2149c8 ths
    env->CP0_TagLo = T0 & 0xFFFFFCF6;
1497 8c0fdd85 ths
    RETURN();
1498 8c0fdd85 ths
}
1499 8c0fdd85 ths
1500 7a387fff ths
void op_mtc0_datalo (void)
1501 7a387fff ths
{
1502 7a387fff ths
    env->CP0_DataLo = T0; /* XXX */
1503 7a387fff ths
    RETURN();
1504 7a387fff ths
}
1505 7a387fff ths
1506 7a387fff ths
void op_mtc0_taghi (void)
1507 7a387fff ths
{
1508 7a387fff ths
    env->CP0_TagHi = T0; /* XXX */
1509 7a387fff ths
    RETURN();
1510 7a387fff ths
}
1511 7a387fff ths
1512 7a387fff ths
void op_mtc0_datahi (void)
1513 7a387fff ths
{
1514 7a387fff ths
    env->CP0_DataHi = T0; /* XXX */
1515 7a387fff ths
    RETURN();
1516 7a387fff ths
}
1517 7a387fff ths
1518 8c0fdd85 ths
void op_mtc0_errorepc (void)
1519 8c0fdd85 ths
{
1520 9c2149c8 ths
    env->CP0_ErrorEPC = (int32_t)T0;
1521 8c0fdd85 ths
    RETURN();
1522 8c0fdd85 ths
}
1523 8c0fdd85 ths
1524 8c0fdd85 ths
void op_mtc0_desave (void)
1525 8c0fdd85 ths
{
1526 8c0fdd85 ths
    env->CP0_DESAVE = T0;
1527 6af0bf9c bellard
    RETURN();
1528 6af0bf9c bellard
}
1529 6af0bf9c bellard
1530 9c2149c8 ths
void op_dmfc0_entrylo0 (void)
1531 9c2149c8 ths
{
1532 9c2149c8 ths
    T0 = env->CP0_EntryLo0;
1533 9c2149c8 ths
    RETURN();
1534 9c2149c8 ths
}
1535 9c2149c8 ths
1536 9c2149c8 ths
void op_dmfc0_entrylo1 (void)
1537 9c2149c8 ths
{
1538 9c2149c8 ths
    T0 = env->CP0_EntryLo1;
1539 9c2149c8 ths
    RETURN();
1540 9c2149c8 ths
}
1541 9c2149c8 ths
1542 9c2149c8 ths
void op_dmfc0_context (void)
1543 9c2149c8 ths
{
1544 9c2149c8 ths
    T0 = env->CP0_Context;
1545 9c2149c8 ths
    RETURN();
1546 9c2149c8 ths
}
1547 9c2149c8 ths
1548 9c2149c8 ths
void op_dmfc0_badvaddr (void)
1549 9c2149c8 ths
{
1550 9c2149c8 ths
    T0 = env->CP0_BadVAddr;
1551 9c2149c8 ths
    RETURN();
1552 9c2149c8 ths
}
1553 9c2149c8 ths
1554 9c2149c8 ths
void op_dmfc0_entryhi (void)
1555 9c2149c8 ths
{
1556 9c2149c8 ths
    T0 = env->CP0_EntryHi;
1557 9c2149c8 ths
    RETURN();
1558 9c2149c8 ths
}
1559 9c2149c8 ths
1560 9c2149c8 ths
void op_dmfc0_epc (void)
1561 9c2149c8 ths
{
1562 9c2149c8 ths
    T0 = env->CP0_EPC;
1563 9c2149c8 ths
    RETURN();
1564 9c2149c8 ths
}
1565 9c2149c8 ths
1566 9c2149c8 ths
void op_dmfc0_lladdr (void)
1567 9c2149c8 ths
{
1568 9c2149c8 ths
    T0 = env->CP0_LLAddr >> 4;
1569 9c2149c8 ths
    RETURN();
1570 9c2149c8 ths
}
1571 9c2149c8 ths
1572 9c2149c8 ths
void op_dmfc0_watchlo0 (void)
1573 9c2149c8 ths
{
1574 9c2149c8 ths
    T0 = env->CP0_WatchLo;
1575 9c2149c8 ths
    RETURN();
1576 9c2149c8 ths
}
1577 9c2149c8 ths
1578 9c2149c8 ths
void op_dmfc0_xcontext (void)
1579 9c2149c8 ths
{
1580 9c2149c8 ths
    T0 = env->CP0_XContext;
1581 9c2149c8 ths
    RETURN();
1582 9c2149c8 ths
}
1583 9c2149c8 ths
1584 9c2149c8 ths
void op_dmfc0_depc (void)
1585 9c2149c8 ths
{
1586 9c2149c8 ths
    T0 = env->CP0_DEPC;
1587 9c2149c8 ths
    RETURN();
1588 9c2149c8 ths
}
1589 9c2149c8 ths
1590 9c2149c8 ths
void op_dmfc0_errorepc (void)
1591 9c2149c8 ths
{
1592 9c2149c8 ths
    T0 = env->CP0_ErrorEPC;
1593 9c2149c8 ths
    RETURN();
1594 9c2149c8 ths
}
1595 9c2149c8 ths
1596 9c2149c8 ths
void op_dmtc0_entrylo0 (void)
1597 9c2149c8 ths
{
1598 9c2149c8 ths
    /* Large physaddr not implemented */
1599 9c2149c8 ths
    /* 1k pages not implemented */
1600 9c2149c8 ths
    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1601 9c2149c8 ths
    RETURN();
1602 9c2149c8 ths
}
1603 9c2149c8 ths
1604 9c2149c8 ths
void op_dmtc0_entrylo1 (void)
1605 9c2149c8 ths
{
1606 9c2149c8 ths
    /* Large physaddr not implemented */
1607 9c2149c8 ths
    /* 1k pages not implemented */
1608 9c2149c8 ths
    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1609 9c2149c8 ths
    RETURN();
1610 9c2149c8 ths
}
1611 9c2149c8 ths
1612 9c2149c8 ths
void op_dmtc0_context (void)
1613 9c2149c8 ths
{
1614 9c2149c8 ths
    env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
1615 9c2149c8 ths
    RETURN();
1616 9c2149c8 ths
}
1617 9c2149c8 ths
1618 9c2149c8 ths
void op_dmtc0_epc (void)
1619 9c2149c8 ths
{
1620 9c2149c8 ths
    env->CP0_EPC = T0;
1621 9c2149c8 ths
    RETURN();
1622 9c2149c8 ths
}
1623 9c2149c8 ths
1624 9c2149c8 ths
void op_dmtc0_watchlo0 (void)
1625 9c2149c8 ths
{
1626 9c2149c8 ths
    env->CP0_WatchLo = T0;
1627 9c2149c8 ths
    RETURN();
1628 9c2149c8 ths
}
1629 9c2149c8 ths
1630 9c2149c8 ths
void op_dmtc0_xcontext (void)
1631 9c2149c8 ths
{
1632 9c2149c8 ths
    env->CP0_XContext = T0; /* XXX */
1633 9c2149c8 ths
    RETURN();
1634 9c2149c8 ths
}
1635 9c2149c8 ths
1636 9c2149c8 ths
void op_dmtc0_depc (void)
1637 9c2149c8 ths
{
1638 9c2149c8 ths
    env->CP0_DEPC = T0;
1639 9c2149c8 ths
    RETURN();
1640 9c2149c8 ths
}
1641 9c2149c8 ths
1642 9c2149c8 ths
void op_dmtc0_errorepc (void)
1643 9c2149c8 ths
{
1644 9c2149c8 ths
    env->CP0_ErrorEPC = T0;
1645 9c2149c8 ths
    RETURN();
1646 9c2149c8 ths
}
1647 9c2149c8 ths
1648 6ea83fed bellard
#ifdef MIPS_USES_FPU
1649 6ea83fed bellard
1650 6ea83fed bellard
#if 0
1651 6ea83fed bellard
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1652 6ea83fed bellard
#else
1653 6ea83fed bellard
# define DEBUG_FPU_STATE() do { } while(0)
1654 6ea83fed bellard
#endif
1655 6ea83fed bellard
1656 6ea83fed bellard
void op_cp1_enabled(void)
1657 6ea83fed bellard
{
1658 6ea83fed bellard
    if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1659 6ea83fed bellard
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
1660 6ea83fed bellard
    }
1661 6ea83fed bellard
    RETURN();
1662 6ea83fed bellard
}
1663 6ea83fed bellard
1664 6ea83fed bellard
/* CP1 functions */
1665 6ea83fed bellard
void op_cfc1 (void)
1666 6ea83fed bellard
{
1667 6ea83fed bellard
    if (T1 == 0) {
1668 6ea83fed bellard
        T0 = env->fcr0;
1669 6ea83fed bellard
    }
1670 6ea83fed bellard
    else {
1671 6ea83fed bellard
        /* fetch fcr31, masking unused bits */
1672 6ea83fed bellard
        T0 = env->fcr31 & 0x0183FFFF;
1673 6ea83fed bellard
    }
1674 6ea83fed bellard
    DEBUG_FPU_STATE();
1675 6ea83fed bellard
    RETURN();
1676 6ea83fed bellard
}
1677 6ea83fed bellard
1678 6ea83fed bellard
/* convert MIPS rounding mode in FCR31 to IEEE library */
1679 6ea83fed bellard
unsigned int ieee_rm[] = { 
1680 6ea83fed bellard
    float_round_nearest_even,
1681 6ea83fed bellard
    float_round_to_zero,
1682 6ea83fed bellard
    float_round_up,
1683 6ea83fed bellard
    float_round_down
1684 6ea83fed bellard
};
1685 6ea83fed bellard
1686 6ea83fed bellard
#define RESTORE_ROUNDING_MODE \
1687 6ea83fed bellard
    set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
1688 6ea83fed bellard
1689 6ea83fed bellard
void op_ctc1 (void)
1690 6ea83fed bellard
{
1691 6ea83fed bellard
    if (T1 == 0) {
1692 6ea83fed bellard
        /* XXX should this throw an exception?
1693 6ea83fed bellard
         * don't write to FCR0.
1694 6ea83fed bellard
         * env->fcr0 = T0; 
1695 6ea83fed bellard
         */
1696 6ea83fed bellard
    }
1697 6ea83fed bellard
    else {
1698 6ea83fed bellard
        /* store new fcr31, masking unused bits */  
1699 6ea83fed bellard
        env->fcr31 = T0 & 0x0183FFFF;
1700 6ea83fed bellard
1701 6ea83fed bellard
        /* set rounding mode */
1702 6ea83fed bellard
        RESTORE_ROUNDING_MODE;
1703 6ea83fed bellard
1704 6ea83fed bellard
#ifndef CONFIG_SOFTFLOAT
1705 6ea83fed bellard
        /* no floating point exception for native float */
1706 6ea83fed bellard
        SET_FP_ENABLE(env->fcr31, 0);
1707 6ea83fed bellard
#endif
1708 6ea83fed bellard
    }
1709 6ea83fed bellard
    DEBUG_FPU_STATE();
1710 6ea83fed bellard
    RETURN();
1711 6ea83fed bellard
}
1712 6ea83fed bellard
1713 6ea83fed bellard
void op_mfc1 (void)
1714 6ea83fed bellard
{
1715 6ea83fed bellard
    T0 = WT0;
1716 6ea83fed bellard
    DEBUG_FPU_STATE();
1717 6ea83fed bellard
    RETURN();
1718 6ea83fed bellard
}
1719 6ea83fed bellard
1720 6ea83fed bellard
void op_mtc1 (void)
1721 6ea83fed bellard
{
1722 6ea83fed bellard
    WT0 = T0;
1723 6ea83fed bellard
    DEBUG_FPU_STATE();
1724 6ea83fed bellard
    RETURN();
1725 6ea83fed bellard
}
1726 6ea83fed bellard
1727 6ea83fed bellard
/* Float support.
1728 6ea83fed bellard
   Single precition routines have a "s" suffix, double precision a
1729 6ea83fed bellard
   "d" suffix.  */
1730 6ea83fed bellard
1731 6ea83fed bellard
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1732 6ea83fed bellard
1733 dd016883 bellard
FLOAT_OP(cvtd, s)
1734 dd016883 bellard
{
1735 dd016883 bellard
    FDT2 = float32_to_float64(WT0, &env->fp_status);
1736 dd016883 bellard
    DEBUG_FPU_STATE();
1737 dd016883 bellard
    RETURN();
1738 dd016883 bellard
}
1739 6ea83fed bellard
FLOAT_OP(cvtd, w)
1740 6ea83fed bellard
{
1741 6ea83fed bellard
    FDT2 = int32_to_float64(WT0, &env->fp_status);
1742 6ea83fed bellard
    DEBUG_FPU_STATE();
1743 6ea83fed bellard
    RETURN();
1744 6ea83fed bellard
}
1745 dd016883 bellard
FLOAT_OP(cvts, d)
1746 dd016883 bellard
{
1747 417f38f0 pbrook
    FST2 = float64_to_float32(FDT0, &env->fp_status);
1748 dd016883 bellard
    DEBUG_FPU_STATE();
1749 dd016883 bellard
    RETURN();
1750 dd016883 bellard
}
1751 6ea83fed bellard
FLOAT_OP(cvts, w)
1752 6ea83fed bellard
{
1753 6ea83fed bellard
    FST2 = int32_to_float32(WT0, &env->fp_status);
1754 6ea83fed bellard
    DEBUG_FPU_STATE();
1755 6ea83fed bellard
    RETURN();
1756 6ea83fed bellard
}
1757 6ea83fed bellard
FLOAT_OP(cvtw, s)
1758 6ea83fed bellard
{
1759 6ea83fed bellard
    WT2 = float32_to_int32(FST0, &env->fp_status);
1760 6ea83fed bellard
    DEBUG_FPU_STATE();
1761 6ea83fed bellard
    RETURN();
1762 6ea83fed bellard
}
1763 6ea83fed bellard
FLOAT_OP(cvtw, d)
1764 6ea83fed bellard
{
1765 6ea83fed bellard
    WT2 = float64_to_int32(FDT0, &env->fp_status);
1766 6ea83fed bellard
    DEBUG_FPU_STATE();
1767 6ea83fed bellard
    RETURN();
1768 6ea83fed bellard
}
1769 6ea83fed bellard
1770 6ea83fed bellard
FLOAT_OP(roundw, d)
1771 6ea83fed bellard
{
1772 6ea83fed bellard
    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1773 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1774 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1775 6ea83fed bellard
1776 6ea83fed bellard
    DEBUG_FPU_STATE();
1777 6ea83fed bellard
    RETURN();
1778 6ea83fed bellard
}
1779 6ea83fed bellard
FLOAT_OP(roundw, s)
1780 6ea83fed bellard
{
1781 6ea83fed bellard
    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1782 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1783 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1784 6ea83fed bellard
    DEBUG_FPU_STATE();
1785 6ea83fed bellard
    RETURN();
1786 6ea83fed bellard
}
1787 6ea83fed bellard
1788 6ea83fed bellard
FLOAT_OP(truncw, d)
1789 6ea83fed bellard
{
1790 6ea83fed bellard
    WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status);
1791 6ea83fed bellard
    DEBUG_FPU_STATE();
1792 6ea83fed bellard
    RETURN();
1793 6ea83fed bellard
}
1794 6ea83fed bellard
FLOAT_OP(truncw, s)
1795 6ea83fed bellard
{
1796 6ea83fed bellard
    WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status);
1797 6ea83fed bellard
    DEBUG_FPU_STATE();
1798 6ea83fed bellard
    RETURN();
1799 6ea83fed bellard
}
1800 6ea83fed bellard
1801 6ea83fed bellard
FLOAT_OP(ceilw, d)
1802 6ea83fed bellard
{
1803 6ea83fed bellard
    set_float_rounding_mode(float_round_up, &env->fp_status);
1804 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1805 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1806 6ea83fed bellard
1807 6ea83fed bellard
    DEBUG_FPU_STATE();
1808 6ea83fed bellard
    RETURN();
1809 6ea83fed bellard
}
1810 6ea83fed bellard
FLOAT_OP(ceilw, s)
1811 6ea83fed bellard
{
1812 6ea83fed bellard
    set_float_rounding_mode(float_round_up, &env->fp_status);
1813 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1814 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1815 6ea83fed bellard
    DEBUG_FPU_STATE();
1816 6ea83fed bellard
    RETURN();
1817 6ea83fed bellard
}
1818 6ea83fed bellard
1819 6ea83fed bellard
FLOAT_OP(floorw, d)
1820 6ea83fed bellard
{
1821 6ea83fed bellard
    set_float_rounding_mode(float_round_down, &env->fp_status);
1822 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1823 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1824 6ea83fed bellard
1825 6ea83fed bellard
    DEBUG_FPU_STATE();
1826 6ea83fed bellard
    RETURN();
1827 6ea83fed bellard
}
1828 6ea83fed bellard
FLOAT_OP(floorw, s)
1829 6ea83fed bellard
{
1830 6ea83fed bellard
    set_float_rounding_mode(float_round_down, &env->fp_status);
1831 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1832 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1833 6ea83fed bellard
    DEBUG_FPU_STATE();
1834 6ea83fed bellard
    RETURN();
1835 6ea83fed bellard
}
1836 6ea83fed bellard
1837 6ea83fed bellard
/* binary operations */
1838 6ea83fed bellard
#define FLOAT_BINOP(name) \
1839 6ea83fed bellard
FLOAT_OP(name, d)         \
1840 6ea83fed bellard
{                         \
1841 6ea83fed bellard
    FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status);    \
1842 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1843 6ea83fed bellard
}                         \
1844 6ea83fed bellard
FLOAT_OP(name, s)         \
1845 6ea83fed bellard
{                         \
1846 6ea83fed bellard
    FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
1847 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1848 6ea83fed bellard
}
1849 6ea83fed bellard
FLOAT_BINOP(add)
1850 6ea83fed bellard
FLOAT_BINOP(sub)
1851 6ea83fed bellard
FLOAT_BINOP(mul)
1852 6ea83fed bellard
FLOAT_BINOP(div)
1853 6ea83fed bellard
#undef FLOAT_BINOP
1854 6ea83fed bellard
1855 6ea83fed bellard
/* unary operations, modifying fp status  */
1856 6ea83fed bellard
#define FLOAT_UNOP(name)  \
1857 6ea83fed bellard
FLOAT_OP(name, d)         \
1858 6ea83fed bellard
{                         \
1859 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0, &env->fp_status);   \
1860 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1861 6ea83fed bellard
}                         \
1862 6ea83fed bellard
FLOAT_OP(name, s)         \
1863 6ea83fed bellard
{                         \
1864 6ea83fed bellard
    FST2 = float32_ ## name(FST0, &env->fp_status);   \
1865 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1866 6ea83fed bellard
}
1867 6ea83fed bellard
FLOAT_UNOP(sqrt)
1868 6ea83fed bellard
#undef FLOAT_UNOP
1869 6ea83fed bellard
1870 6ea83fed bellard
/* unary operations, not modifying fp status  */
1871 6ea83fed bellard
#define FLOAT_UNOP(name)  \
1872 6ea83fed bellard
FLOAT_OP(name, d)         \
1873 6ea83fed bellard
{                         \
1874 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0);   \
1875 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1876 6ea83fed bellard
}                         \
1877 6ea83fed bellard
FLOAT_OP(name, s)         \
1878 6ea83fed bellard
{                         \
1879 6ea83fed bellard
    FST2 = float32_ ## name(FST0);   \
1880 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1881 6ea83fed bellard
}
1882 6ea83fed bellard
FLOAT_UNOP(abs)
1883 6ea83fed bellard
FLOAT_UNOP(chs)
1884 6ea83fed bellard
#undef FLOAT_UNOP
1885 6ea83fed bellard
1886 6ea83fed bellard
FLOAT_OP(mov, d)
1887 6ea83fed bellard
{
1888 6ea83fed bellard
    FDT2 = FDT0;
1889 6ea83fed bellard
    DEBUG_FPU_STATE();
1890 6ea83fed bellard
    RETURN();
1891 6ea83fed bellard
}
1892 6ea83fed bellard
FLOAT_OP(mov, s)
1893 6ea83fed bellard
{
1894 6ea83fed bellard
    FST2 = FST0;
1895 6ea83fed bellard
    DEBUG_FPU_STATE();
1896 6ea83fed bellard
    RETURN();
1897 6ea83fed bellard
}
1898 6ea83fed bellard
1899 6ea83fed bellard
#ifdef CONFIG_SOFTFLOAT
1900 6ea83fed bellard
#define clear_invalid() do {                                \
1901 6ea83fed bellard
    int flags = get_float_exception_flags(&env->fp_status); \
1902 6ea83fed bellard
    flags &= ~float_flag_invalid;                           \
1903 6ea83fed bellard
    set_float_exception_flags(flags, &env->fp_status);      \
1904 6ea83fed bellard
} while(0)
1905 6ea83fed bellard
#else
1906 6ea83fed bellard
#define clear_invalid() do { } while(0)
1907 6ea83fed bellard
#endif
1908 6ea83fed bellard
1909 6ea83fed bellard
extern void dump_fpu_s(CPUState *env);
1910 6ea83fed bellard
1911 6ea83fed bellard
#define FOP_COND(fmt, op, sig, cond)           \
1912 6ea83fed bellard
void op_cmp_ ## fmt ## _ ## op (void)          \
1913 6ea83fed bellard
{                                              \
1914 6ea83fed bellard
    if (cond)                                  \
1915 6ea83fed bellard
        SET_FP_COND(env->fcr31);               \
1916 6ea83fed bellard
    else                                       \
1917 6ea83fed bellard
        CLEAR_FP_COND(env->fcr31);             \
1918 6ea83fed bellard
    if (!sig)                                  \
1919 6ea83fed bellard
        clear_invalid();                       \
1920 6ea83fed bellard
    /*CALL_FROM_TB1(dump_fpu_s, env);*/ \
1921 6ea83fed bellard
    DEBUG_FPU_STATE();                         \
1922 6ea83fed bellard
    RETURN();                                  \
1923 6ea83fed bellard
}
1924 6ea83fed bellard
1925 569f5d66 bellard
int float64_is_unordered(float64 a, float64 b STATUS_PARAM)
1926 6ea83fed bellard
{
1927 6ea83fed bellard
    if (float64_is_nan(a) || float64_is_nan(b)) {
1928 6ea83fed bellard
        float_raise(float_flag_invalid, status);
1929 6ea83fed bellard
        return 1;
1930 6ea83fed bellard
    }
1931 6ea83fed bellard
    else {
1932 6ea83fed bellard
        return 0;
1933 6ea83fed bellard
    }
1934 6ea83fed bellard
}
1935 6ea83fed bellard
1936 6ea83fed bellard
FOP_COND(d, f,   0,                                                      0) 
1937 6ea83fed bellard
FOP_COND(d, un,  0, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1938 6ea83fed bellard
FOP_COND(d, eq,  0,                                                      float64_eq(FDT0, FDT1, &env->fp_status))
1939 6ea83fed bellard
FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1940 6ea83fed bellard
FOP_COND(d, olt, 0,                                                      float64_lt(FDT0, FDT1, &env->fp_status))
1941 6ea83fed bellard
FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1942 6ea83fed bellard
FOP_COND(d, ole, 0,                                                      float64_le(FDT0, FDT1, &env->fp_status))
1943 6ea83fed bellard
FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1944 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1945 6ea83fed bellard
 * but float*_is_unordered() is still called
1946 6ea83fed bellard
 */
1947 6ea83fed bellard
FOP_COND(d, sf,  1,                                                      (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0))
1948 6ea83fed bellard
FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1949 6ea83fed bellard
FOP_COND(d, seq, 1,                                                      float64_eq(FDT0, FDT1, &env->fp_status))
1950 6ea83fed bellard
FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1951 6ea83fed bellard
FOP_COND(d, lt,  1,                                                      float64_lt(FDT0, FDT1, &env->fp_status))
1952 6ea83fed bellard
FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1953 6ea83fed bellard
FOP_COND(d, le,  1,                                                      float64_le(FDT0, FDT1, &env->fp_status))
1954 6ea83fed bellard
FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1955 6ea83fed bellard
1956 6ea83fed bellard
flag float32_is_unordered(float32 a, float32 b STATUS_PARAM)
1957 6ea83fed bellard
{
1958 6ea83fed bellard
    extern flag float32_is_nan( float32 a );
1959 6ea83fed bellard
    if (float32_is_nan(a) || float32_is_nan(b)) {
1960 6ea83fed bellard
        float_raise(float_flag_invalid, status);
1961 6ea83fed bellard
        return 1;
1962 6ea83fed bellard
    }
1963 6ea83fed bellard
    else {
1964 6ea83fed bellard
        return 0;
1965 6ea83fed bellard
    }
1966 6ea83fed bellard
}
1967 6ea83fed bellard
1968 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1969 6ea83fed bellard
 * but float*_is_unordered() is still called
1970 6ea83fed bellard
 */
1971 6ea83fed bellard
FOP_COND(s, f,   0,                                                      0) 
1972 6ea83fed bellard
FOP_COND(s, un,  0, float32_is_unordered(FST1, FST0, &env->fp_status))
1973 6ea83fed bellard
FOP_COND(s, eq,  0,                                                      float32_eq(FST0, FST1, &env->fp_status))
1974 6ea83fed bellard
FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1975 6ea83fed bellard
FOP_COND(s, olt, 0,                                                      float32_lt(FST0, FST1, &env->fp_status))
1976 6ea83fed bellard
FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1977 6ea83fed bellard
FOP_COND(s, ole, 0,                                                      float32_le(FST0, FST1, &env->fp_status))
1978 6ea83fed bellard
FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1979 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1980 6ea83fed bellard
 * but float*_is_unordered() is still called
1981 6ea83fed bellard
 */
1982 6ea83fed bellard
FOP_COND(s, sf,  1,                                                      (float32_is_unordered(FST0, FST1, &env->fp_status), 0))
1983 6ea83fed bellard
FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status))
1984 6ea83fed bellard
FOP_COND(s, seq, 1,                                                      float32_eq(FST0, FST1, &env->fp_status))
1985 6ea83fed bellard
FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1986 6ea83fed bellard
FOP_COND(s, lt,  1,                                                      float32_lt(FST0, FST1, &env->fp_status))
1987 6ea83fed bellard
FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1988 6ea83fed bellard
FOP_COND(s, le,  1,                                                      float32_le(FST0, FST1, &env->fp_status))
1989 6ea83fed bellard
FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1990 6ea83fed bellard
1991 6ea83fed bellard
void op_bc1f (void)
1992 6ea83fed bellard
{
1993 6ea83fed bellard
    T0 = ! IS_FP_COND_SET(env->fcr31);
1994 6ea83fed bellard
    DEBUG_FPU_STATE();
1995 6ea83fed bellard
    RETURN();
1996 6ea83fed bellard
}
1997 6ea83fed bellard
1998 6ea83fed bellard
void op_bc1t (void)
1999 6ea83fed bellard
{
2000 6ea83fed bellard
    T0 = IS_FP_COND_SET(env->fcr31);
2001 6ea83fed bellard
    DEBUG_FPU_STATE();
2002 6ea83fed bellard
    RETURN();
2003 6ea83fed bellard
}
2004 6ea83fed bellard
#endif /* MIPS_USES_FPU */
2005 6ea83fed bellard
2006 6af0bf9c bellard
#if defined(MIPS_USES_R4K_TLB)
2007 6af0bf9c bellard
void op_tlbwi (void)
2008 6af0bf9c bellard
{
2009 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbwi);
2010 6af0bf9c bellard
    RETURN();
2011 6af0bf9c bellard
}
2012 6af0bf9c bellard
2013 6af0bf9c bellard
void op_tlbwr (void)
2014 6af0bf9c bellard
{
2015 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbwr);
2016 6af0bf9c bellard
    RETURN();
2017 6af0bf9c bellard
}
2018 6af0bf9c bellard
2019 6af0bf9c bellard
void op_tlbp (void)
2020 6af0bf9c bellard
{
2021 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbp);
2022 6af0bf9c bellard
    RETURN();
2023 6af0bf9c bellard
}
2024 6af0bf9c bellard
2025 6af0bf9c bellard
void op_tlbr (void)
2026 6af0bf9c bellard
{
2027 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbr);
2028 6af0bf9c bellard
    RETURN();
2029 6af0bf9c bellard
}
2030 6af0bf9c bellard
#endif
2031 6af0bf9c bellard
2032 6af0bf9c bellard
/* Specials */
2033 6af0bf9c bellard
void op_pmon (void)
2034 6af0bf9c bellard
{
2035 6af0bf9c bellard
    CALL_FROM_TB1(do_pmon, PARAM1);
2036 7a387fff ths
    RETURN();
2037 7a387fff ths
}
2038 7a387fff ths
2039 7a387fff ths
void op_di (void)
2040 7a387fff ths
{
2041 7a387fff ths
    T0 = env->CP0_Status;
2042 4de9b249 ths
    env->CP0_Status = T0 & ~(1 << CP0St_IE);
2043 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2044 7a387fff ths
    RETURN();
2045 7a387fff ths
}
2046 7a387fff ths
2047 7a387fff ths
void op_ei (void)
2048 7a387fff ths
{
2049 7a387fff ths
    T0 = env->CP0_Status;
2050 4de9b249 ths
    env->CP0_Status = T0 | (1 << CP0St_IE);
2051 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2052 7a387fff ths
    RETURN();
2053 6af0bf9c bellard
}
2054 6af0bf9c bellard
2055 6af0bf9c bellard
void op_trap (void)
2056 6af0bf9c bellard
{
2057 6af0bf9c bellard
    if (T0) {
2058 4ad40f36 bellard
        CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP);
2059 6af0bf9c bellard
    }
2060 6af0bf9c bellard
    RETURN();
2061 6af0bf9c bellard
}
2062 6af0bf9c bellard
2063 4ad40f36 bellard
void op_debug (void)
2064 4ad40f36 bellard
{
2065 7a387fff ths
    CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2066 7a387fff ths
    RETURN();
2067 4ad40f36 bellard
}
2068 4ad40f36 bellard
2069 6af0bf9c bellard
void op_set_lladdr (void)
2070 6af0bf9c bellard
{
2071 6af0bf9c bellard
    env->CP0_LLAddr = T2;
2072 7a387fff ths
    RETURN();
2073 6af0bf9c bellard
}
2074 6af0bf9c bellard
2075 6af0bf9c bellard
void debug_eret (void);
2076 6af0bf9c bellard
void op_eret (void)
2077 6af0bf9c bellard
{
2078 6af0bf9c bellard
    CALL_FROM_TB0(debug_eret);
2079 51e11d9e bellard
    if (env->hflags & MIPS_HFLAG_ERL) {
2080 6af0bf9c bellard
        env->PC = env->CP0_ErrorEPC;
2081 51e11d9e bellard
        env->hflags &= ~MIPS_HFLAG_ERL;
2082 3e382bc8 bellard
        env->CP0_Status &= ~(1 << CP0St_ERL);
2083 51e11d9e bellard
    } else {
2084 6af0bf9c bellard
        env->PC = env->CP0_EPC;
2085 51e11d9e bellard
        env->hflags &= ~MIPS_HFLAG_EXL;
2086 3e382bc8 bellard
        env->CP0_Status &= ~(1 << CP0St_EXL);
2087 51e11d9e bellard
    }
2088 6af0bf9c bellard
    env->CP0_LLAddr = 1;
2089 7a387fff ths
    RETURN();
2090 6af0bf9c bellard
}
2091 6af0bf9c bellard
2092 6af0bf9c bellard
void op_deret (void)
2093 6af0bf9c bellard
{
2094 6af0bf9c bellard
    CALL_FROM_TB0(debug_eret);
2095 6af0bf9c bellard
    env->PC = env->CP0_DEPC;
2096 7a387fff ths
    RETURN();
2097 7a387fff ths
}
2098 7a387fff ths
2099 7a387fff ths
void op_rdhwr_cpunum(void)
2100 7a387fff ths
{
2101 7a387fff ths
    if (env->CP0_HWREna & (1 << 0))
2102 7a387fff ths
       T0 = env->CP0_EBase & 0x2ff;
2103 7a387fff ths
    else
2104 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2105 7a387fff ths
    RETURN();
2106 7a387fff ths
}
2107 7a387fff ths
2108 7a387fff ths
void op_rdhwr_synci_step(void)
2109 7a387fff ths
{
2110 7a387fff ths
    if (env->CP0_HWREna & (1 << 1))
2111 7a387fff ths
       T0 = env->SYNCI_Step;
2112 7a387fff ths
    else
2113 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2114 7a387fff ths
    RETURN();
2115 7a387fff ths
}
2116 7a387fff ths
2117 7a387fff ths
void op_rdhwr_cc(void)
2118 7a387fff ths
{
2119 7a387fff ths
    if (env->CP0_HWREna & (1 << 2))
2120 7a387fff ths
       T0 = env->CP0_Count;
2121 7a387fff ths
    else
2122 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2123 7a387fff ths
    RETURN();
2124 7a387fff ths
}
2125 7a387fff ths
2126 7a387fff ths
void op_rdhwr_ccres(void)
2127 7a387fff ths
{
2128 7a387fff ths
    if (env->CP0_HWREna & (1 << 3))
2129 7a387fff ths
       T0 = env->CCRes;
2130 7a387fff ths
    else
2131 7a387fff ths
       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2132 7a387fff ths
    RETURN();
2133 6af0bf9c bellard
}
2134 6af0bf9c bellard
2135 6af0bf9c bellard
void op_save_state (void)
2136 6af0bf9c bellard
{
2137 6af0bf9c bellard
    env->hflags = PARAM1;
2138 6af0bf9c bellard
    RETURN();
2139 6af0bf9c bellard
}
2140 6af0bf9c bellard
2141 6af0bf9c bellard
void op_save_pc (void)
2142 6af0bf9c bellard
{
2143 6af0bf9c bellard
    env->PC = PARAM1;
2144 6af0bf9c bellard
    RETURN();
2145 6af0bf9c bellard
}
2146 6af0bf9c bellard
2147 6af0bf9c bellard
void op_raise_exception (void)
2148 6af0bf9c bellard
{
2149 6af0bf9c bellard
    CALL_FROM_TB1(do_raise_exception, PARAM1);
2150 6af0bf9c bellard
    RETURN();
2151 6af0bf9c bellard
}
2152 6af0bf9c bellard
2153 6af0bf9c bellard
void op_raise_exception_err (void)
2154 6af0bf9c bellard
{
2155 6af0bf9c bellard
    CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
2156 6af0bf9c bellard
    RETURN();
2157 6af0bf9c bellard
}
2158 6af0bf9c bellard
2159 6af0bf9c bellard
void op_exit_tb (void)
2160 6af0bf9c bellard
{
2161 6af0bf9c bellard
    EXIT_TB();
2162 7a387fff ths
    RETURN();
2163 6af0bf9c bellard
}
2164 6af0bf9c bellard
2165 4ad40f36 bellard
void op_wait (void)
2166 4ad40f36 bellard
{
2167 4ad40f36 bellard
    env->halted = 1;
2168 4ad40f36 bellard
    CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
2169 7a387fff ths
    RETURN();
2170 7a387fff ths
}
2171 7a387fff ths
2172 7a387fff ths
/* Bitfield operations. */
2173 7a387fff ths
void op_ext(void)
2174 7a387fff ths
{
2175 7a387fff ths
    unsigned int pos = PARAM1;
2176 7a387fff ths
    unsigned int size = PARAM2;
2177 7a387fff ths
2178 c570fd16 ths
    T0 = ((uint32_t)T1 >> pos) & ((1 << size) - 1);
2179 7a387fff ths
    RETURN();
2180 7a387fff ths
}
2181 7a387fff ths
2182 7a387fff ths
void op_ins(void)
2183 7a387fff ths
{
2184 7a387fff ths
    unsigned int pos = PARAM1;
2185 7a387fff ths
    unsigned int size = PARAM2;
2186 7a387fff ths
    target_ulong mask = ((1 << size) - 1) << pos;
2187 7a387fff ths
2188 c570fd16 ths
    T0 = (T2 & ~mask) | (((uint32_t)T1 << pos) & mask);
2189 7a387fff ths
    RETURN();
2190 7a387fff ths
}
2191 7a387fff ths
2192 7a387fff ths
void op_wsbh(void)
2193 7a387fff ths
{
2194 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
2195 7a387fff ths
    RETURN();
2196 7a387fff ths
}
2197 7a387fff ths
2198 c570fd16 ths
#ifdef MIPS_HAS_MIPS64
2199 c570fd16 ths
void op_dext(void)
2200 c570fd16 ths
{
2201 c570fd16 ths
    unsigned int pos = PARAM1;
2202 c570fd16 ths
    unsigned int size = PARAM2;
2203 c570fd16 ths
2204 c570fd16 ths
    T0 = (T1 >> pos) & ((1 << size) - 1);
2205 c570fd16 ths
    RETURN();
2206 c570fd16 ths
}
2207 c570fd16 ths
2208 c570fd16 ths
void op_dins(void)
2209 c570fd16 ths
{
2210 c570fd16 ths
    unsigned int pos = PARAM1;
2211 c570fd16 ths
    unsigned int size = PARAM2;
2212 c570fd16 ths
    target_ulong mask = ((1 << size) - 1) << pos;
2213 c570fd16 ths
2214 c570fd16 ths
    T0 = (T2 & ~mask) | ((T1 << pos) & mask);
2215 c570fd16 ths
    RETURN();
2216 c570fd16 ths
}
2217 c570fd16 ths
2218 7a387fff ths
void op_dsbh(void)
2219 7a387fff ths
{
2220 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
2221 7a387fff ths
    RETURN();
2222 7a387fff ths
}
2223 7a387fff ths
2224 7a387fff ths
void op_dshd(void)
2225 7a387fff ths
{
2226 7a387fff ths
    T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
2227 7a387fff ths
    RETURN();
2228 7a387fff ths
}
2229 c570fd16 ths
#endif
2230 7a387fff ths
2231 7a387fff ths
void op_seb(void)
2232 7a387fff ths
{
2233 7a387fff ths
    T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
2234 7a387fff ths
    RETURN();
2235 7a387fff ths
}
2236 7a387fff ths
2237 7a387fff ths
void op_seh(void)
2238 7a387fff ths
{
2239 7a387fff ths
    T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
2240 7a387fff ths
    RETURN();
2241 4ad40f36 bellard
}