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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 emulation
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3 | fdf9b3e8 | bellard | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #ifndef _CPU_SH4_H
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21 | fdf9b3e8 | bellard | #define _CPU_SH4_H
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22 | fdf9b3e8 | bellard | |
23 | fdf9b3e8 | bellard | #include "config.h" |
24 | fdf9b3e8 | bellard | |
25 | fdf9b3e8 | bellard | #define TARGET_LONG_BITS 32 |
26 | fdf9b3e8 | bellard | #define TARGET_HAS_ICE 1 |
27 | fdf9b3e8 | bellard | |
28 | 9042c0e2 | ths | #define ELF_MACHINE EM_SH
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29 | 9042c0e2 | ths | |
30 | fdf9b3e8 | bellard | #include "cpu-defs.h" |
31 | fdf9b3e8 | bellard | |
32 | eda9b09b | bellard | #include "softfloat.h" |
33 | eda9b09b | bellard | |
34 | fdf9b3e8 | bellard | #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ |
35 | fdf9b3e8 | bellard | |
36 | fdf9b3e8 | bellard | #define SR_MD (1 << 30) |
37 | fdf9b3e8 | bellard | #define SR_RB (1 << 29) |
38 | fdf9b3e8 | bellard | #define SR_BL (1 << 28) |
39 | fdf9b3e8 | bellard | #define SR_FD (1 << 15) |
40 | fdf9b3e8 | bellard | #define SR_M (1 << 9) |
41 | fdf9b3e8 | bellard | #define SR_Q (1 << 8) |
42 | fdf9b3e8 | bellard | #define SR_S (1 << 1) |
43 | fdf9b3e8 | bellard | #define SR_T (1 << 0) |
44 | fdf9b3e8 | bellard | |
45 | fdf9b3e8 | bellard | #define FPSCR_FR (1 << 21) |
46 | fdf9b3e8 | bellard | #define FPSCR_SZ (1 << 20) |
47 | fdf9b3e8 | bellard | #define FPSCR_PR (1 << 19) |
48 | fdf9b3e8 | bellard | #define FPSCR_DN (1 << 18) |
49 | fdf9b3e8 | bellard | |
50 | 9c2a9ea1 | pbrook | #define DELAY_SLOT (1 << 0) /* Must be the same as SR_T. */ |
51 | 9c2a9ea1 | pbrook | /* This flag is set if the next insn is a delay slot for a conditional jump.
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52 | 9c2a9ea1 | pbrook | The dynamic value of the DELAY_SLOT determines whether the jup is taken. */
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53 | fdf9b3e8 | bellard | #define DELAY_SLOT_CONDITIONAL (1 << 1) |
54 | fdf9b3e8 | bellard | /* Those are used in contexts only */
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55 | fdf9b3e8 | bellard | #define BRANCH (1 << 2) |
56 | fdf9b3e8 | bellard | #define BRANCH_CONDITIONAL (1 << 3) |
57 | fdf9b3e8 | bellard | #define MODE_CHANGE (1 << 4) /* Potential MD|RB change */ |
58 | fdf9b3e8 | bellard | #define BRANCH_EXCEPTION (1 << 5) /* Branch after exception */ |
59 | fdf9b3e8 | bellard | |
60 | fdf9b3e8 | bellard | /* XXXXX The structure could be made more compact */
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61 | fdf9b3e8 | bellard | typedef struct tlb_t { |
62 | fdf9b3e8 | bellard | uint8_t asid; /* address space identifier */
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63 | fdf9b3e8 | bellard | uint32_t vpn; /* virtual page number */
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64 | fdf9b3e8 | bellard | uint8_t v; /* validity */
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65 | fdf9b3e8 | bellard | uint32_t ppn; /* physical page number */
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66 | fdf9b3e8 | bellard | uint8_t sz; /* page size */
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67 | fdf9b3e8 | bellard | uint32_t size; /* cached page size in bytes */
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68 | fdf9b3e8 | bellard | uint8_t sh; /* share status */
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69 | fdf9b3e8 | bellard | uint8_t c; /* cacheability */
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70 | fdf9b3e8 | bellard | uint8_t pr; /* protection key */
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71 | fdf9b3e8 | bellard | uint8_t d; /* dirty */
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72 | fdf9b3e8 | bellard | uint8_t wt; /* write through */
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73 | fdf9b3e8 | bellard | uint8_t sa; /* space attribute (PCMCIA) */
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74 | fdf9b3e8 | bellard | uint8_t tc; /* timing control */
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75 | fdf9b3e8 | bellard | } tlb_t; |
76 | fdf9b3e8 | bellard | |
77 | fdf9b3e8 | bellard | #define UTLB_SIZE 64 |
78 | fdf9b3e8 | bellard | #define ITLB_SIZE 4 |
79 | fdf9b3e8 | bellard | |
80 | fdf9b3e8 | bellard | typedef struct CPUSH4State { |
81 | fdf9b3e8 | bellard | uint32_t flags; /* general execution flags */
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82 | fdf9b3e8 | bellard | uint32_t gregs[24]; /* general registers */ |
83 | fdf9b3e8 | bellard | uint32_t fregs[32]; /* floating point registers */ |
84 | fdf9b3e8 | bellard | uint32_t sr; /* status register */
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85 | fdf9b3e8 | bellard | uint32_t ssr; /* saved status register */
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86 | fdf9b3e8 | bellard | uint32_t spc; /* saved program counter */
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87 | fdf9b3e8 | bellard | uint32_t gbr; /* global base register */
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88 | fdf9b3e8 | bellard | uint32_t vbr; /* vector base register */
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89 | fdf9b3e8 | bellard | uint32_t sgr; /* saved global register 15 */
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90 | fdf9b3e8 | bellard | uint32_t dbr; /* debug base register */
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91 | fdf9b3e8 | bellard | uint32_t pc; /* program counter */
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92 | fdf9b3e8 | bellard | uint32_t delayed_pc; /* target of delayed jump */
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93 | fdf9b3e8 | bellard | uint32_t mach; /* multiply and accumulate high */
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94 | fdf9b3e8 | bellard | uint32_t macl; /* multiply and accumulate low */
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95 | fdf9b3e8 | bellard | uint32_t pr; /* procedure register */
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96 | fdf9b3e8 | bellard | uint32_t fpscr; /* floating point status/control register */
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97 | fdf9b3e8 | bellard | uint32_t fpul; /* floating point communication register */
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98 | fdf9b3e8 | bellard | |
99 | eda9b09b | bellard | /* temporary float registers */
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100 | eda9b09b | bellard | float32 ft0, ft1; |
101 | eda9b09b | bellard | float64 dt0, dt1; |
102 | eda9b09b | bellard | |
103 | fdf9b3e8 | bellard | /* Those belong to the specific unit (SH7750) but are handled here */
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104 | fdf9b3e8 | bellard | uint32_t mmucr; /* MMU control register */
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105 | fdf9b3e8 | bellard | uint32_t pteh; /* page table entry high register */
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106 | fdf9b3e8 | bellard | uint32_t ptel; /* page table entry low register */
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107 | fdf9b3e8 | bellard | uint32_t ptea; /* page table entry assistance register */
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108 | fdf9b3e8 | bellard | uint32_t ttb; /* tranlation table base register */
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109 | fdf9b3e8 | bellard | uint32_t tea; /* TLB exception address register */
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110 | fdf9b3e8 | bellard | uint32_t tra; /* TRAPA exception register */
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111 | fdf9b3e8 | bellard | uint32_t expevt; /* exception event register */
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112 | fdf9b3e8 | bellard | uint32_t intevt; /* interrupt event register */
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113 | fdf9b3e8 | bellard | |
114 | fdf9b3e8 | bellard | jmp_buf jmp_env; |
115 | fdf9b3e8 | bellard | int user_mode_only;
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116 | fdf9b3e8 | bellard | int interrupt_request;
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117 | fdf9b3e8 | bellard | int exception_index;
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118 | fdf9b3e8 | bellard | CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
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119 | fdf9b3e8 | bellard | tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
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120 | fdf9b3e8 | bellard | } CPUSH4State; |
121 | fdf9b3e8 | bellard | |
122 | fdf9b3e8 | bellard | CPUSH4State *cpu_sh4_init(void);
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123 | fdf9b3e8 | bellard | int cpu_sh4_exec(CPUSH4State * s);
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124 | 5a7b542b | ths | int cpu_sh4_signal_handler(int host_signum, void *pinfo, |
125 | 5a7b542b | ths | void *puc);
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126 | fdf9b3e8 | bellard | |
127 | fdf9b3e8 | bellard | #include "softfloat.h" |
128 | fdf9b3e8 | bellard | |
129 | fdf9b3e8 | bellard | #include "cpu-all.h" |
130 | fdf9b3e8 | bellard | |
131 | fdf9b3e8 | bellard | /* Memory access type */
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132 | fdf9b3e8 | bellard | enum {
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133 | fdf9b3e8 | bellard | /* Privilege */
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134 | fdf9b3e8 | bellard | ACCESS_PRIV = 0x01,
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135 | fdf9b3e8 | bellard | /* Direction */
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136 | fdf9b3e8 | bellard | ACCESS_WRITE = 0x02,
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137 | fdf9b3e8 | bellard | /* Type of instruction */
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138 | fdf9b3e8 | bellard | ACCESS_CODE = 0x10,
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139 | fdf9b3e8 | bellard | ACCESS_INT = 0x20
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140 | fdf9b3e8 | bellard | }; |
141 | fdf9b3e8 | bellard | |
142 | fdf9b3e8 | bellard | /* MMU control register */
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143 | fdf9b3e8 | bellard | #define MMUCR 0x1F000010 |
144 | fdf9b3e8 | bellard | #define MMUCR_AT (1<<0) |
145 | fdf9b3e8 | bellard | #define MMUCR_SV (1<<8) |
146 | fdf9b3e8 | bellard | |
147 | fdf9b3e8 | bellard | #endif /* _CPU_SH4_H */ |