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1 | 7a3f1944 | bellard | #ifndef CPU_SPARC_H
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2 | 7a3f1944 | bellard | #define CPU_SPARC_H
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3 | 7a3f1944 | bellard | |
4 | af7bf89b | bellard | #include "config.h" |
5 | af7bf89b | bellard | |
6 | af7bf89b | bellard | #if !defined(TARGET_SPARC64)
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7 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
8 | af7bf89b | bellard | #define TARGET_FPREGS 32 |
9 | 83469015 | bellard | #define TARGET_PAGE_BITS 12 /* 4k */ |
10 | af7bf89b | bellard | #else
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11 | af7bf89b | bellard | #define TARGET_LONG_BITS 64 |
12 | af7bf89b | bellard | #define TARGET_FPREGS 64 |
13 | 83469015 | bellard | #define TARGET_PAGE_BITS 12 /* XXX */ |
14 | af7bf89b | bellard | #endif
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15 | 3cf1e035 | bellard | |
16 | 7a3f1944 | bellard | #include "cpu-defs.h" |
17 | 7a3f1944 | bellard | |
18 | 7a0e1f41 | bellard | #include "softfloat.h" |
19 | 7a0e1f41 | bellard | |
20 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
21 | 1fddef4b | bellard | |
22 | 9042c0e2 | ths | #if !defined(TARGET_SPARC64)
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23 | 9042c0e2 | ths | #define ELF_MACHINE EM_SPARC
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24 | 9042c0e2 | ths | #else
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25 | 9042c0e2 | ths | #define ELF_MACHINE EM_SPARCV9
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26 | 9042c0e2 | ths | #endif
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27 | 9042c0e2 | ths | |
28 | 7a3f1944 | bellard | /*#define EXCP_INTERRUPT 0x100*/
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29 | 7a3f1944 | bellard | |
30 | cf495bcf | bellard | /* trap definitions */
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31 | 3475187d | bellard | #ifndef TARGET_SPARC64
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32 | 878d3096 | bellard | #define TT_TFAULT 0x01 |
33 | cf495bcf | bellard | #define TT_ILL_INSN 0x02 |
34 | e8af50a3 | bellard | #define TT_PRIV_INSN 0x03 |
35 | e80cfcfc | bellard | #define TT_NFPU_INSN 0x04 |
36 | cf495bcf | bellard | #define TT_WIN_OVF 0x05 |
37 | cf495bcf | bellard | #define TT_WIN_UNF 0x06 |
38 | e8af50a3 | bellard | #define TT_FP_EXCP 0x08 |
39 | 878d3096 | bellard | #define TT_DFAULT 0x09 |
40 | 878d3096 | bellard | #define TT_EXTINT 0x10 |
41 | cf495bcf | bellard | #define TT_DIV_ZERO 0x2a |
42 | cf495bcf | bellard | #define TT_TRAP 0x80 |
43 | 3475187d | bellard | #else
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44 | 3475187d | bellard | #define TT_TFAULT 0x08 |
45 | 83469015 | bellard | #define TT_TMISS 0x09 |
46 | 3475187d | bellard | #define TT_ILL_INSN 0x10 |
47 | 3475187d | bellard | #define TT_PRIV_INSN 0x11 |
48 | 3475187d | bellard | #define TT_NFPU_INSN 0x20 |
49 | 3475187d | bellard | #define TT_FP_EXCP 0x21 |
50 | 3475187d | bellard | #define TT_CLRWIN 0x24 |
51 | 3475187d | bellard | #define TT_DIV_ZERO 0x28 |
52 | 3475187d | bellard | #define TT_DFAULT 0x30 |
53 | 83469015 | bellard | #define TT_DMISS 0x31 |
54 | 83469015 | bellard | #define TT_DPROT 0x32 |
55 | 83469015 | bellard | #define TT_PRIV_ACT 0x37 |
56 | 3475187d | bellard | #define TT_EXTINT 0x40 |
57 | 3475187d | bellard | #define TT_SPILL 0x80 |
58 | 3475187d | bellard | #define TT_FILL 0xc0 |
59 | 3475187d | bellard | #define TT_WOTHER 0x10 |
60 | 3475187d | bellard | #define TT_TRAP 0x100 |
61 | 3475187d | bellard | #endif
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62 | 7a3f1944 | bellard | |
63 | 7a3f1944 | bellard | #define PSR_NEG (1<<23) |
64 | 7a3f1944 | bellard | #define PSR_ZERO (1<<22) |
65 | 7a3f1944 | bellard | #define PSR_OVF (1<<21) |
66 | 7a3f1944 | bellard | #define PSR_CARRY (1<<20) |
67 | e8af50a3 | bellard | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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68 | e80cfcfc | bellard | #define PSR_EF (1<<12) |
69 | e80cfcfc | bellard | #define PSR_PIL 0xf00 |
70 | e8af50a3 | bellard | #define PSR_S (1<<7) |
71 | e8af50a3 | bellard | #define PSR_PS (1<<6) |
72 | e8af50a3 | bellard | #define PSR_ET (1<<5) |
73 | e8af50a3 | bellard | #define PSR_CWP 0x1f |
74 | e8af50a3 | bellard | |
75 | e8af50a3 | bellard | /* Trap base register */
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76 | e8af50a3 | bellard | #define TBR_BASE_MASK 0xfffff000 |
77 | e8af50a3 | bellard | |
78 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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79 | 83469015 | bellard | #define PS_IG (1<<11) |
80 | 83469015 | bellard | #define PS_MG (1<<10) |
81 | 83469015 | bellard | #define PS_RED (1<<5) |
82 | 3475187d | bellard | #define PS_PEF (1<<4) |
83 | 3475187d | bellard | #define PS_AM (1<<3) |
84 | 3475187d | bellard | #define PS_PRIV (1<<2) |
85 | 3475187d | bellard | #define PS_IE (1<<1) |
86 | 83469015 | bellard | #define PS_AG (1<<0) |
87 | a80dde08 | bellard | |
88 | a80dde08 | bellard | #define FPRS_FEF (1<<2) |
89 | 3475187d | bellard | #endif
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90 | 3475187d | bellard | |
91 | e8af50a3 | bellard | /* Fcc */
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92 | e8af50a3 | bellard | #define FSR_RD1 (1<<31) |
93 | e8af50a3 | bellard | #define FSR_RD0 (1<<30) |
94 | e8af50a3 | bellard | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
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95 | e8af50a3 | bellard | #define FSR_RD_NEAREST 0 |
96 | e8af50a3 | bellard | #define FSR_RD_ZERO FSR_RD0
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97 | e8af50a3 | bellard | #define FSR_RD_POS FSR_RD1
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98 | e8af50a3 | bellard | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
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99 | e8af50a3 | bellard | |
100 | e8af50a3 | bellard | #define FSR_NVM (1<<27) |
101 | e8af50a3 | bellard | #define FSR_OFM (1<<26) |
102 | e8af50a3 | bellard | #define FSR_UFM (1<<25) |
103 | e8af50a3 | bellard | #define FSR_DZM (1<<24) |
104 | e8af50a3 | bellard | #define FSR_NXM (1<<23) |
105 | e8af50a3 | bellard | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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106 | e8af50a3 | bellard | |
107 | e8af50a3 | bellard | #define FSR_NVA (1<<9) |
108 | e8af50a3 | bellard | #define FSR_OFA (1<<8) |
109 | e8af50a3 | bellard | #define FSR_UFA (1<<7) |
110 | e8af50a3 | bellard | #define FSR_DZA (1<<6) |
111 | e8af50a3 | bellard | #define FSR_NXA (1<<5) |
112 | e8af50a3 | bellard | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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113 | e8af50a3 | bellard | |
114 | e8af50a3 | bellard | #define FSR_NVC (1<<4) |
115 | e8af50a3 | bellard | #define FSR_OFC (1<<3) |
116 | e8af50a3 | bellard | #define FSR_UFC (1<<2) |
117 | e8af50a3 | bellard | #define FSR_DZC (1<<1) |
118 | e8af50a3 | bellard | #define FSR_NXC (1<<0) |
119 | e8af50a3 | bellard | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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120 | e8af50a3 | bellard | |
121 | e8af50a3 | bellard | #define FSR_FTT2 (1<<16) |
122 | e8af50a3 | bellard | #define FSR_FTT1 (1<<15) |
123 | e8af50a3 | bellard | #define FSR_FTT0 (1<<14) |
124 | e8af50a3 | bellard | #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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125 | e80cfcfc | bellard | #define FSR_FTT_IEEE_EXCP (1 << 14) |
126 | e80cfcfc | bellard | #define FSR_FTT_UNIMPFPOP (3 << 14) |
127 | e80cfcfc | bellard | #define FSR_FTT_INVAL_FPR (6 << 14) |
128 | e8af50a3 | bellard | |
129 | e8af50a3 | bellard | #define FSR_FCC1 (1<<11) |
130 | e8af50a3 | bellard | #define FSR_FCC0 (1<<10) |
131 | e8af50a3 | bellard | |
132 | e8af50a3 | bellard | /* MMU */
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133 | e8af50a3 | bellard | #define MMU_E (1<<0) |
134 | e8af50a3 | bellard | #define MMU_NF (1<<1) |
135 | e8af50a3 | bellard | |
136 | e8af50a3 | bellard | #define PTE_ENTRYTYPE_MASK 3 |
137 | e8af50a3 | bellard | #define PTE_ACCESS_MASK 0x1c |
138 | e8af50a3 | bellard | #define PTE_ACCESS_SHIFT 2 |
139 | 8d5f07fa | bellard | #define PTE_PPN_SHIFT 7 |
140 | e8af50a3 | bellard | #define PTE_ADDR_MASK 0xffffff00 |
141 | e8af50a3 | bellard | |
142 | e8af50a3 | bellard | #define PG_ACCESSED_BIT 5 |
143 | e8af50a3 | bellard | #define PG_MODIFIED_BIT 6 |
144 | e8af50a3 | bellard | #define PG_CACHE_BIT 7 |
145 | e8af50a3 | bellard | |
146 | e8af50a3 | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
147 | e8af50a3 | bellard | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
148 | e8af50a3 | bellard | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
149 | e8af50a3 | bellard | |
150 | 1d6e34fd | bellard | /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
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151 | 1d6e34fd | bellard | #define NWINDOWS 8 |
152 | cf495bcf | bellard | |
153 | 7a3f1944 | bellard | typedef struct CPUSPARCState { |
154 | af7bf89b | bellard | target_ulong gregs[8]; /* general registers */ |
155 | af7bf89b | bellard | target_ulong *regwptr; /* pointer to current register window */
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156 | 65ce8c2f | bellard | float32 fpr[TARGET_FPREGS]; /* floating point registers */
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157 | af7bf89b | bellard | target_ulong pc; /* program counter */
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158 | af7bf89b | bellard | target_ulong npc; /* next program counter */
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159 | af7bf89b | bellard | target_ulong y; /* multiply/divide register */
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160 | cf495bcf | bellard | uint32_t psr; /* processor state register */
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161 | 3475187d | bellard | target_ulong fsr; /* FPU state register */
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162 | cf495bcf | bellard | uint32_t cwp; /* index of current register window (extracted
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163 | cf495bcf | bellard | from PSR) */
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164 | cf495bcf | bellard | uint32_t wim; /* window invalid mask */
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165 | 3475187d | bellard | target_ulong tbr; /* trap base register */
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166 | e8af50a3 | bellard | int psrs; /* supervisor mode (extracted from PSR) */ |
167 | e8af50a3 | bellard | int psrps; /* previous supervisor mode */ |
168 | e8af50a3 | bellard | int psret; /* enable traps */ |
169 | 3475187d | bellard | uint32_t psrpil; /* interrupt level */
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170 | e80cfcfc | bellard | int psref; /* enable fpu */ |
171 | cf495bcf | bellard | jmp_buf jmp_env; |
172 | cf495bcf | bellard | int user_mode_only;
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173 | cf495bcf | bellard | int exception_index;
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174 | cf495bcf | bellard | int interrupt_index;
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175 | cf495bcf | bellard | int interrupt_request;
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176 | ba3c64fb | bellard | int halted;
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177 | cf495bcf | bellard | /* NOTE: we allow 8 more registers to handle wrapping */
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178 | af7bf89b | bellard | target_ulong regbase[NWINDOWS * 16 + 8]; |
179 | d720b93d | bellard | |
180 | a316d335 | bellard | CPU_COMMON |
181 | a316d335 | bellard | |
182 | e8af50a3 | bellard | /* MMU regs */
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183 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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184 | 3475187d | bellard | uint64_t lsu; |
185 | 3475187d | bellard | #define DMMU_E 0x8 |
186 | 3475187d | bellard | #define IMMU_E 0x4 |
187 | 3475187d | bellard | uint64_t immuregs[16];
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188 | 3475187d | bellard | uint64_t dmmuregs[16];
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189 | 3475187d | bellard | uint64_t itlb_tag[64];
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190 | 3475187d | bellard | uint64_t itlb_tte[64];
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191 | 3475187d | bellard | uint64_t dtlb_tag[64];
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192 | 3475187d | bellard | uint64_t dtlb_tte[64];
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193 | 3475187d | bellard | #else
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194 | e8af50a3 | bellard | uint32_t mmuregs[16];
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195 | 3475187d | bellard | #endif
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196 | e8af50a3 | bellard | /* temporary float registers */
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197 | 65ce8c2f | bellard | float32 ft0, ft1; |
198 | 65ce8c2f | bellard | float64 dt0, dt1; |
199 | 7a0e1f41 | bellard | float_status fp_status; |
200 | af7bf89b | bellard | #if defined(TARGET_SPARC64)
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201 | 3475187d | bellard | #define MAXTL 4 |
202 | 3475187d | bellard | uint64_t t0, t1, t2; |
203 | 3475187d | bellard | uint64_t tpc[MAXTL]; |
204 | 3475187d | bellard | uint64_t tnpc[MAXTL]; |
205 | 3475187d | bellard | uint64_t tstate[MAXTL]; |
206 | 3475187d | bellard | uint32_t tt[MAXTL]; |
207 | 3475187d | bellard | uint32_t xcc; /* Extended integer condition codes */
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208 | 3475187d | bellard | uint32_t asi; |
209 | 3475187d | bellard | uint32_t pstate; |
210 | 3475187d | bellard | uint32_t tl; |
211 | 3475187d | bellard | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; |
212 | 83469015 | bellard | uint64_t agregs[8]; /* alternate general registers */ |
213 | 83469015 | bellard | uint64_t bgregs[8]; /* backup for normal global registers */ |
214 | 83469015 | bellard | uint64_t igregs[8]; /* interrupt general registers */ |
215 | 83469015 | bellard | uint64_t mgregs[8]; /* mmu general registers */ |
216 | 3475187d | bellard | uint64_t version; |
217 | 3475187d | bellard | uint64_t fprs; |
218 | 83469015 | bellard | uint64_t tick_cmpr, stick_cmpr; |
219 | 725cb90b | bellard | uint64_t gsr; |
220 | 3475187d | bellard | #endif
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221 | 3475187d | bellard | #if !defined(TARGET_SPARC64) && !defined(reg_T2)
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222 | 3475187d | bellard | target_ulong t2; |
223 | af7bf89b | bellard | #endif
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224 | 7a3f1944 | bellard | } CPUSPARCState; |
225 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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226 | 3475187d | bellard | #define GET_FSR32(env) (env->fsr & 0xcfc1ffff) |
227 | 3475187d | bellard | #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ |
228 | 3475187d | bellard | env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \ |
229 | 3475187d | bellard | } while (0) |
230 | 3475187d | bellard | #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL) |
231 | 3475187d | bellard | #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \ |
232 | 3475187d | bellard | env->fsr = _tmp & 0x3fcfc1c3ffULL; \
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233 | 3475187d | bellard | } while (0) |
234 | 3475187d | bellard | // Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
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235 | 3475187d | bellard | #define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) | \ |
236 | 3475187d | bellard | (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1)) |
237 | 3475187d | bellard | #else
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238 | 3475187d | bellard | #define GET_FSR32(env) (env->fsr)
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239 | 3475187d | bellard | #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ |
240 | 3475187d | bellard | env->fsr = _tmp & 0xcfc1ffff; \
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241 | 3475187d | bellard | } while (0) |
242 | 3475187d | bellard | #endif
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243 | 7a3f1944 | bellard | |
244 | 7a3f1944 | bellard | CPUSPARCState *cpu_sparc_init(void);
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245 | 7a3f1944 | bellard | int cpu_sparc_exec(CPUSPARCState *s);
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246 | 7a3f1944 | bellard | int cpu_sparc_close(CPUSPARCState *s);
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247 | 7a3f1944 | bellard | |
248 | b4ff5987 | bellard | /* Fake impl 0, version 4 */
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249 | af7bf89b | bellard | #define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \ |
250 | b4ff5987 | bellard | (env->psref? PSR_EF : 0) | \
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251 | b4ff5987 | bellard | (env->psrpil << 8) | \
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252 | b4ff5987 | bellard | (env->psrs? PSR_S : 0) | \
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253 | afc7df11 | bellard | (env->psrps? PSR_PS : 0) | \
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254 | b4ff5987 | bellard | (env->psret? PSR_ET : 0) | env->cwp)
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255 | b4ff5987 | bellard | |
256 | b4ff5987 | bellard | #ifndef NO_CPU_IO_DEFS
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257 | b4ff5987 | bellard | void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); |
258 | b4ff5987 | bellard | #endif
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259 | b4ff5987 | bellard | |
260 | b4ff5987 | bellard | #define PUT_PSR(env, val) do { int _tmp = val; \ |
261 | af7bf89b | bellard | env->psr = _tmp & PSR_ICC; \ |
262 | b4ff5987 | bellard | env->psref = (_tmp & PSR_EF)? 1 : 0; \ |
263 | b4ff5987 | bellard | env->psrpil = (_tmp & PSR_PIL) >> 8; \
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264 | b4ff5987 | bellard | env->psrs = (_tmp & PSR_S)? 1 : 0; \ |
265 | b4ff5987 | bellard | env->psrps = (_tmp & PSR_PS)? 1 : 0; \ |
266 | b4ff5987 | bellard | env->psret = (_tmp & PSR_ET)? 1 : 0; \ |
267 | b4ff5987 | bellard | cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
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268 | b4ff5987 | bellard | } while (0) |
269 | b4ff5987 | bellard | |
270 | 3475187d | bellard | #ifdef TARGET_SPARC64
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271 | 3475187d | bellard | #define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC)) |
272 | 3475187d | bellard | #define PUT_CCR(env, val) do { int _tmp = val; \ |
273 | 3475187d | bellard | env->xcc = _tmp >> 4; \
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274 | 3475187d | bellard | env->psr = (_tmp & 0xf) << 20; \ |
275 | 3475187d | bellard | } while (0) |
276 | 3475187d | bellard | #endif
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277 | 3475187d | bellard | |
278 | 5a7b542b | ths | int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
279 | 7a3f1944 | bellard | |
280 | 7a3f1944 | bellard | #include "cpu-all.h" |
281 | 7a3f1944 | bellard | |
282 | 7a3f1944 | bellard | #endif |