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/*
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 * QEMU System Emulator header
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 * 
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 * Copyright (c) 2003 Fabrice Bellard
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern int vm_running;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd, 
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                         IOCanRWHandler *fd_read_poll, 
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                         IOHandler *fd_read, 
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                         IOHandler *fd_write, 
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read, 
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s, 
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                           IOCanRWHandler *fd_can_read, 
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds);
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void console_select(unsigned int index);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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/* VLANs support */
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typedef struct VLANClientState VLANClientState;
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struct VLANClientState {
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    IOReadHandler *fd_read;
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    /* Packets may still be sent if this returns zero.  It's used to
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       rate-limit the slirp code.  */
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    IOCanRWHandler *fd_can_read;
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    void *opaque;
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    struct VLANClientState *next;
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    struct VLANState *vlan;
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    char info_str[256];
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};
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typedef struct VLANState {
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    int id;
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    VLANClientState *first_client;
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    struct VLANState *next;
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} VLANState;
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VLANState *qemu_find_vlan(int id);
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VLANClientState *qemu_new_vlan_client(VLANState *vlan,
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                                      IOReadHandler *fd_read,
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                                      IOCanRWHandler *fd_can_read,
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                                      void *opaque);
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int qemu_can_send_packet(VLANClientState *vc);
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void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
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void qemu_handler_true(void *opaque);
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void do_info_network(void);
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/* TAP win32 */
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int tap_win32_init(VLANState *vlan, const char *ifname);
386 7fb843f8 bellard
387 7c9d8e07 bellard
/* NIC info */
388 c4b1fcc0 bellard
389 c4b1fcc0 bellard
#define MAX_NICS 8
390 c4b1fcc0 bellard
391 7c9d8e07 bellard
typedef struct NICInfo {
392 c4b1fcc0 bellard
    uint8_t macaddr[6];
393 a41b2ff2 pbrook
    const char *model;
394 7c9d8e07 bellard
    VLANState *vlan;
395 7c9d8e07 bellard
} NICInfo;
396 c4b1fcc0 bellard
397 c4b1fcc0 bellard
extern int nb_nics;
398 7c9d8e07 bellard
extern NICInfo nd_table[MAX_NICS];
399 8a7ddc38 bellard
400 8a7ddc38 bellard
/* timers */
401 8a7ddc38 bellard
402 8a7ddc38 bellard
typedef struct QEMUClock QEMUClock;
403 8a7ddc38 bellard
typedef struct QEMUTimer QEMUTimer;
404 8a7ddc38 bellard
typedef void QEMUTimerCB(void *opaque);
405 8a7ddc38 bellard
406 8a7ddc38 bellard
/* The real time clock should be used only for stuff which does not
407 8a7ddc38 bellard
   change the virtual machine state, as it is run even if the virtual
408 69b91039 bellard
   machine is stopped. The real time clock has a frequency of 1000
409 8a7ddc38 bellard
   Hz. */
410 8a7ddc38 bellard
extern QEMUClock *rt_clock;
411 8a7ddc38 bellard
412 e80cfcfc bellard
/* The virtual clock is only run during the emulation. It is stopped
413 8a7ddc38 bellard
   when the virtual machine is stopped. Virtual timers use a high
414 8a7ddc38 bellard
   precision clock, usually cpu cycles (use ticks_per_sec). */
415 8a7ddc38 bellard
extern QEMUClock *vm_clock;
416 8a7ddc38 bellard
417 8a7ddc38 bellard
int64_t qemu_get_clock(QEMUClock *clock);
418 8a7ddc38 bellard
419 8a7ddc38 bellard
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
420 8a7ddc38 bellard
void qemu_free_timer(QEMUTimer *ts);
421 8a7ddc38 bellard
void qemu_del_timer(QEMUTimer *ts);
422 8a7ddc38 bellard
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
423 8a7ddc38 bellard
int qemu_timer_pending(QEMUTimer *ts);
424 8a7ddc38 bellard
425 8a7ddc38 bellard
extern int64_t ticks_per_sec;
426 8a7ddc38 bellard
extern int pit_min_timer_count;
427 8a7ddc38 bellard
428 1dce7c3c bellard
int64_t cpu_get_ticks(void);
429 8a7ddc38 bellard
void cpu_enable_ticks(void);
430 8a7ddc38 bellard
void cpu_disable_ticks(void);
431 8a7ddc38 bellard
432 8a7ddc38 bellard
/* VM Load/Save */
433 8a7ddc38 bellard
434 faea38e7 bellard
typedef struct QEMUFile QEMUFile;
435 8a7ddc38 bellard
436 faea38e7 bellard
QEMUFile *qemu_fopen(const char *filename, const char *mode);
437 faea38e7 bellard
void qemu_fflush(QEMUFile *f);
438 faea38e7 bellard
void qemu_fclose(QEMUFile *f);
439 8a7ddc38 bellard
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
440 8a7ddc38 bellard
void qemu_put_byte(QEMUFile *f, int v);
441 8a7ddc38 bellard
void qemu_put_be16(QEMUFile *f, unsigned int v);
442 8a7ddc38 bellard
void qemu_put_be32(QEMUFile *f, unsigned int v);
443 8a7ddc38 bellard
void qemu_put_be64(QEMUFile *f, uint64_t v);
444 8a7ddc38 bellard
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
445 8a7ddc38 bellard
int qemu_get_byte(QEMUFile *f);
446 8a7ddc38 bellard
unsigned int qemu_get_be16(QEMUFile *f);
447 8a7ddc38 bellard
unsigned int qemu_get_be32(QEMUFile *f);
448 8a7ddc38 bellard
uint64_t qemu_get_be64(QEMUFile *f);
449 8a7ddc38 bellard
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static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
451 8a7ddc38 bellard
{
452 8a7ddc38 bellard
    qemu_put_be64(f, *pv);
453 8a7ddc38 bellard
}
454 8a7ddc38 bellard
455 8a7ddc38 bellard
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
456 8a7ddc38 bellard
{
457 8a7ddc38 bellard
    qemu_put_be32(f, *pv);
458 8a7ddc38 bellard
}
459 8a7ddc38 bellard
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static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
461 8a7ddc38 bellard
{
462 8a7ddc38 bellard
    qemu_put_be16(f, *pv);
463 8a7ddc38 bellard
}
464 8a7ddc38 bellard
465 8a7ddc38 bellard
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
466 8a7ddc38 bellard
{
467 8a7ddc38 bellard
    qemu_put_byte(f, *pv);
468 8a7ddc38 bellard
}
469 8a7ddc38 bellard
470 8a7ddc38 bellard
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
471 8a7ddc38 bellard
{
472 8a7ddc38 bellard
    *pv = qemu_get_be64(f);
473 8a7ddc38 bellard
}
474 8a7ddc38 bellard
475 8a7ddc38 bellard
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
476 8a7ddc38 bellard
{
477 8a7ddc38 bellard
    *pv = qemu_get_be32(f);
478 8a7ddc38 bellard
}
479 8a7ddc38 bellard
480 8a7ddc38 bellard
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
481 8a7ddc38 bellard
{
482 8a7ddc38 bellard
    *pv = qemu_get_be16(f);
483 8a7ddc38 bellard
}
484 8a7ddc38 bellard
485 8a7ddc38 bellard
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
486 8a7ddc38 bellard
{
487 8a7ddc38 bellard
    *pv = qemu_get_byte(f);
488 8a7ddc38 bellard
}
489 8a7ddc38 bellard
490 c27004ec bellard
#if TARGET_LONG_BITS == 64
491 c27004ec bellard
#define qemu_put_betl qemu_put_be64
492 c27004ec bellard
#define qemu_get_betl qemu_get_be64
493 c27004ec bellard
#define qemu_put_betls qemu_put_be64s
494 c27004ec bellard
#define qemu_get_betls qemu_get_be64s
495 c27004ec bellard
#else
496 c27004ec bellard
#define qemu_put_betl qemu_put_be32
497 c27004ec bellard
#define qemu_get_betl qemu_get_be32
498 c27004ec bellard
#define qemu_put_betls qemu_put_be32s
499 c27004ec bellard
#define qemu_get_betls qemu_get_be32s
500 c27004ec bellard
#endif
501 c27004ec bellard
502 8a7ddc38 bellard
int64_t qemu_ftell(QEMUFile *f);
503 8a7ddc38 bellard
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
504 8a7ddc38 bellard
505 8a7ddc38 bellard
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
506 8a7ddc38 bellard
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
507 8a7ddc38 bellard
508 8a7ddc38 bellard
int register_savevm(const char *idstr, 
509 8a7ddc38 bellard
                    int instance_id, 
510 8a7ddc38 bellard
                    int version_id,
511 8a7ddc38 bellard
                    SaveStateHandler *save_state,
512 8a7ddc38 bellard
                    LoadStateHandler *load_state,
513 8a7ddc38 bellard
                    void *opaque);
514 8a7ddc38 bellard
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
515 8a7ddc38 bellard
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
516 c4b1fcc0 bellard
517 6a00d601 bellard
void cpu_save(QEMUFile *f, void *opaque);
518 6a00d601 bellard
int cpu_load(QEMUFile *f, void *opaque, int version_id);
519 6a00d601 bellard
520 faea38e7 bellard
void do_savevm(const char *name);
521 faea38e7 bellard
void do_loadvm(const char *name);
522 faea38e7 bellard
void do_delvm(const char *name);
523 faea38e7 bellard
void do_info_snapshots(void);
524 faea38e7 bellard
525 83f64091 bellard
/* bottom halves */
526 83f64091 bellard
typedef void QEMUBHFunc(void *opaque);
527 83f64091 bellard
528 83f64091 bellard
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
529 83f64091 bellard
void qemu_bh_schedule(QEMUBH *bh);
530 83f64091 bellard
void qemu_bh_cancel(QEMUBH *bh);
531 83f64091 bellard
void qemu_bh_delete(QEMUBH *bh);
532 6eb5733a bellard
int qemu_bh_poll(void);
533 83f64091 bellard
534 fc01f7e7 bellard
/* block.c */
535 fc01f7e7 bellard
typedef struct BlockDriverState BlockDriverState;
536 ea2384d3 bellard
typedef struct BlockDriver BlockDriver;
537 ea2384d3 bellard
538 ea2384d3 bellard
extern BlockDriver bdrv_raw;
539 19cb3738 bellard
extern BlockDriver bdrv_host_device;
540 ea2384d3 bellard
extern BlockDriver bdrv_cow;
541 ea2384d3 bellard
extern BlockDriver bdrv_qcow;
542 ea2384d3 bellard
extern BlockDriver bdrv_vmdk;
543 3c56521b bellard
extern BlockDriver bdrv_cloop;
544 585d0ed9 bellard
extern BlockDriver bdrv_dmg;
545 a8753c34 bellard
extern BlockDriver bdrv_bochs;
546 6a0f9e82 bellard
extern BlockDriver bdrv_vpc;
547 de167e41 bellard
extern BlockDriver bdrv_vvfat;
548 faea38e7 bellard
extern BlockDriver bdrv_qcow2;
549 faea38e7 bellard
550 faea38e7 bellard
typedef struct BlockDriverInfo {
551 faea38e7 bellard
    /* in bytes, 0 if irrelevant */
552 faea38e7 bellard
    int cluster_size; 
553 faea38e7 bellard
    /* offset at which the VM state can be saved (0 if not possible) */
554 faea38e7 bellard
    int64_t vm_state_offset; 
555 faea38e7 bellard
} BlockDriverInfo;
556 faea38e7 bellard
557 faea38e7 bellard
typedef struct QEMUSnapshotInfo {
558 faea38e7 bellard
    char id_str[128]; /* unique snapshot id */
559 faea38e7 bellard
    /* the following fields are informative. They are not needed for
560 faea38e7 bellard
       the consistency of the snapshot */
561 faea38e7 bellard
    char name[256]; /* user choosen name */
562 faea38e7 bellard
    uint32_t vm_state_size; /* VM state info size */
563 faea38e7 bellard
    uint32_t date_sec; /* UTC date of the snapshot */
564 faea38e7 bellard
    uint32_t date_nsec;
565 faea38e7 bellard
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
566 faea38e7 bellard
} QEMUSnapshotInfo;
567 ea2384d3 bellard
568 83f64091 bellard
#define BDRV_O_RDONLY      0x0000
569 83f64091 bellard
#define BDRV_O_RDWR        0x0002
570 83f64091 bellard
#define BDRV_O_ACCESS      0x0003
571 83f64091 bellard
#define BDRV_O_CREAT       0x0004 /* create an empty file */
572 83f64091 bellard
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
573 83f64091 bellard
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
574 83f64091 bellard
                                     use a disk image format on top of
575 83f64091 bellard
                                     it (default for
576 83f64091 bellard
                                     bdrv_file_open()) */
577 83f64091 bellard
578 ea2384d3 bellard
void bdrv_init(void);
579 ea2384d3 bellard
BlockDriver *bdrv_find_format(const char *format_name);
580 ea2384d3 bellard
int bdrv_create(BlockDriver *drv, 
581 ea2384d3 bellard
                const char *filename, int64_t size_in_sectors,
582 ea2384d3 bellard
                const char *backing_file, int flags);
583 c4b1fcc0 bellard
BlockDriverState *bdrv_new(const char *device_name);
584 c4b1fcc0 bellard
void bdrv_delete(BlockDriverState *bs);
585 83f64091 bellard
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
586 83f64091 bellard
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
587 83f64091 bellard
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
588 ea2384d3 bellard
               BlockDriver *drv);
589 fc01f7e7 bellard
void bdrv_close(BlockDriverState *bs);
590 fc01f7e7 bellard
int bdrv_read(BlockDriverState *bs, int64_t sector_num, 
591 fc01f7e7 bellard
              uint8_t *buf, int nb_sectors);
592 fc01f7e7 bellard
int bdrv_write(BlockDriverState *bs, int64_t sector_num, 
593 fc01f7e7 bellard
               const uint8_t *buf, int nb_sectors);
594 83f64091 bellard
int bdrv_pread(BlockDriverState *bs, int64_t offset, 
595 83f64091 bellard
               void *buf, int count);
596 83f64091 bellard
int bdrv_pwrite(BlockDriverState *bs, int64_t offset, 
597 83f64091 bellard
                const void *buf, int count);
598 83f64091 bellard
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
599 83f64091 bellard
int64_t bdrv_getlength(BlockDriverState *bs);
600 fc01f7e7 bellard
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
601 33e3963e bellard
int bdrv_commit(BlockDriverState *bs);
602 77fef8c1 bellard
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
603 83f64091 bellard
/* async block I/O */
604 83f64091 bellard
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
605 83f64091 bellard
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
606 83f64091 bellard
607 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
608 ce1a14dc pbrook
                                uint8_t *buf, int nb_sectors,
609 ce1a14dc pbrook
                                BlockDriverCompletionFunc *cb, void *opaque);
610 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
611 ce1a14dc pbrook
                                 const uint8_t *buf, int nb_sectors,
612 ce1a14dc pbrook
                                 BlockDriverCompletionFunc *cb, void *opaque);
613 83f64091 bellard
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
614 83f64091 bellard
615 83f64091 bellard
void qemu_aio_init(void);
616 83f64091 bellard
void qemu_aio_poll(void);
617 6192bc37 pbrook
void qemu_aio_flush(void);
618 83f64091 bellard
void qemu_aio_wait_start(void);
619 83f64091 bellard
void qemu_aio_wait(void);
620 83f64091 bellard
void qemu_aio_wait_end(void);
621 83f64091 bellard
622 7a6cba61 pbrook
/* Ensure contents are flushed to disk.  */
623 7a6cba61 pbrook
void bdrv_flush(BlockDriverState *bs);
624 33e3963e bellard
625 c4b1fcc0 bellard
#define BDRV_TYPE_HD     0
626 c4b1fcc0 bellard
#define BDRV_TYPE_CDROM  1
627 c4b1fcc0 bellard
#define BDRV_TYPE_FLOPPY 2
628 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_AUTO   0
629 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_NONE   1
630 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LBA    2
631 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LARGE  3
632 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_RECHS  4
633 c4b1fcc0 bellard
634 c4b1fcc0 bellard
void bdrv_set_geometry_hint(BlockDriverState *bs, 
635 c4b1fcc0 bellard
                            int cyls, int heads, int secs);
636 c4b1fcc0 bellard
void bdrv_set_type_hint(BlockDriverState *bs, int type);
637 46d4767d bellard
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
638 c4b1fcc0 bellard
void bdrv_get_geometry_hint(BlockDriverState *bs, 
639 c4b1fcc0 bellard
                            int *pcyls, int *pheads, int *psecs);
640 c4b1fcc0 bellard
int bdrv_get_type_hint(BlockDriverState *bs);
641 46d4767d bellard
int bdrv_get_translation_hint(BlockDriverState *bs);
642 c4b1fcc0 bellard
int bdrv_is_removable(BlockDriverState *bs);
643 c4b1fcc0 bellard
int bdrv_is_read_only(BlockDriverState *bs);
644 c4b1fcc0 bellard
int bdrv_is_inserted(BlockDriverState *bs);
645 19cb3738 bellard
int bdrv_media_changed(BlockDriverState *bs);
646 c4b1fcc0 bellard
int bdrv_is_locked(BlockDriverState *bs);
647 c4b1fcc0 bellard
void bdrv_set_locked(BlockDriverState *bs, int locked);
648 19cb3738 bellard
void bdrv_eject(BlockDriverState *bs, int eject_flag);
649 c4b1fcc0 bellard
void bdrv_set_change_cb(BlockDriverState *bs, 
650 c4b1fcc0 bellard
                        void (*change_cb)(void *opaque), void *opaque);
651 ea2384d3 bellard
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
652 c4b1fcc0 bellard
void bdrv_info(void);
653 c4b1fcc0 bellard
BlockDriverState *bdrv_find(const char *name);
654 82c643ff bellard
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
655 ea2384d3 bellard
int bdrv_is_encrypted(BlockDriverState *bs);
656 ea2384d3 bellard
int bdrv_set_key(BlockDriverState *bs, const char *key);
657 ea2384d3 bellard
void bdrv_iterate_format(void (*it)(void *opaque, const char *name), 
658 ea2384d3 bellard
                         void *opaque);
659 ea2384d3 bellard
const char *bdrv_get_device_name(BlockDriverState *bs);
660 faea38e7 bellard
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num, 
661 faea38e7 bellard
                          const uint8_t *buf, int nb_sectors);
662 faea38e7 bellard
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
663 c4b1fcc0 bellard
664 83f64091 bellard
void bdrv_get_backing_filename(BlockDriverState *bs, 
665 83f64091 bellard
                               char *filename, int filename_size);
666 faea38e7 bellard
int bdrv_snapshot_create(BlockDriverState *bs, 
667 faea38e7 bellard
                         QEMUSnapshotInfo *sn_info);
668 faea38e7 bellard
int bdrv_snapshot_goto(BlockDriverState *bs, 
669 faea38e7 bellard
                       const char *snapshot_id);
670 faea38e7 bellard
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
671 faea38e7 bellard
int bdrv_snapshot_list(BlockDriverState *bs, 
672 faea38e7 bellard
                       QEMUSnapshotInfo **psn_info);
673 faea38e7 bellard
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
674 faea38e7 bellard
675 faea38e7 bellard
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
676 83f64091 bellard
int path_is_absolute(const char *path);
677 83f64091 bellard
void path_combine(char *dest, int dest_size,
678 83f64091 bellard
                  const char *base_path,
679 83f64091 bellard
                  const char *filename);
680 ea2384d3 bellard
681 ea2384d3 bellard
#ifndef QEMU_TOOL
682 54fa5af5 bellard
683 54fa5af5 bellard
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, 
684 54fa5af5 bellard
                                 int boot_device,
685 54fa5af5 bellard
             DisplayState *ds, const char **fd_filename, int snapshot,
686 54fa5af5 bellard
             const char *kernel_filename, const char *kernel_cmdline,
687 54fa5af5 bellard
             const char *initrd_filename);
688 54fa5af5 bellard
689 54fa5af5 bellard
typedef struct QEMUMachine {
690 54fa5af5 bellard
    const char *name;
691 54fa5af5 bellard
    const char *desc;
692 54fa5af5 bellard
    QEMUMachineInitFunc *init;
693 54fa5af5 bellard
    struct QEMUMachine *next;
694 54fa5af5 bellard
} QEMUMachine;
695 54fa5af5 bellard
696 54fa5af5 bellard
int qemu_register_machine(QEMUMachine *m);
697 54fa5af5 bellard
698 54fa5af5 bellard
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
699 3de388f6 bellard
typedef void IRQRequestFunc(void *opaque, int level);
700 54fa5af5 bellard
701 26aa7d72 bellard
/* ISA bus */
702 26aa7d72 bellard
703 26aa7d72 bellard
extern target_phys_addr_t isa_mem_base;
704 26aa7d72 bellard
705 26aa7d72 bellard
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
706 26aa7d72 bellard
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
707 26aa7d72 bellard
708 26aa7d72 bellard
int register_ioport_read(int start, int length, int size, 
709 26aa7d72 bellard
                         IOPortReadFunc *func, void *opaque);
710 26aa7d72 bellard
int register_ioport_write(int start, int length, int size, 
711 26aa7d72 bellard
                          IOPortWriteFunc *func, void *opaque);
712 69b91039 bellard
void isa_unassign_ioport(int start, int length);
713 69b91039 bellard
714 aef445bd pbrook
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
715 aef445bd pbrook
716 69b91039 bellard
/* PCI bus */
717 69b91039 bellard
718 69b91039 bellard
extern target_phys_addr_t pci_mem_base;
719 69b91039 bellard
720 46e50e9d bellard
typedef struct PCIBus PCIBus;
721 69b91039 bellard
typedef struct PCIDevice PCIDevice;
722 69b91039 bellard
723 69b91039 bellard
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, 
724 69b91039 bellard
                                uint32_t address, uint32_t data, int len);
725 69b91039 bellard
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, 
726 69b91039 bellard
                                   uint32_t address, int len);
727 69b91039 bellard
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, 
728 69b91039 bellard
                                uint32_t addr, uint32_t size, int type);
729 69b91039 bellard
730 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM                0x00
731 69b91039 bellard
#define PCI_ADDRESS_SPACE_IO                0x01
732 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
733 69b91039 bellard
734 69b91039 bellard
typedef struct PCIIORegion {
735 5768f5ac bellard
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
736 69b91039 bellard
    uint32_t size;
737 69b91039 bellard
    uint8_t type;
738 69b91039 bellard
    PCIMapIORegionFunc *map_func;
739 69b91039 bellard
} PCIIORegion;
740 69b91039 bellard
741 8a8696a3 bellard
#define PCI_ROM_SLOT 6
742 8a8696a3 bellard
#define PCI_NUM_REGIONS 7
743 502a5395 pbrook
744 502a5395 pbrook
#define PCI_DEVICES_MAX 64
745 502a5395 pbrook
746 502a5395 pbrook
#define PCI_VENDOR_ID                0x00        /* 16 bits */
747 502a5395 pbrook
#define PCI_DEVICE_ID                0x02        /* 16 bits */
748 502a5395 pbrook
#define PCI_COMMAND                0x04        /* 16 bits */
749 502a5395 pbrook
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
750 502a5395 pbrook
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
751 502a5395 pbrook
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
752 502a5395 pbrook
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
753 502a5395 pbrook
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
754 502a5395 pbrook
#define PCI_MIN_GNT                0x3e        /* 8 bits */
755 502a5395 pbrook
#define PCI_MAX_LAT                0x3f        /* 8 bits */
756 502a5395 pbrook
757 69b91039 bellard
struct PCIDevice {
758 69b91039 bellard
    /* PCI config space */
759 69b91039 bellard
    uint8_t config[256];
760 69b91039 bellard
761 69b91039 bellard
    /* the following fields are read only */
762 46e50e9d bellard
    PCIBus *bus;
763 69b91039 bellard
    int devfn;
764 69b91039 bellard
    char name[64];
765 8a8696a3 bellard
    PCIIORegion io_regions[PCI_NUM_REGIONS];
766 69b91039 bellard
    
767 69b91039 bellard
    /* do not access the following fields */
768 69b91039 bellard
    PCIConfigReadFunc *config_read;
769 69b91039 bellard
    PCIConfigWriteFunc *config_write;
770 502a5395 pbrook
    /* ??? This is a PC-specific hack, and should be removed.  */
771 5768f5ac bellard
    int irq_index;
772 d2b59317 pbrook
773 d2b59317 pbrook
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
774 d2b59317 pbrook
    int irq_state[4];
775 69b91039 bellard
};
776 69b91039 bellard
777 46e50e9d bellard
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
778 46e50e9d bellard
                               int instance_size, int devfn,
779 69b91039 bellard
                               PCIConfigReadFunc *config_read, 
780 69b91039 bellard
                               PCIConfigWriteFunc *config_write);
781 69b91039 bellard
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void pci_register_io_region(PCIDevice *pci_dev, int region_num, 
783 69b91039 bellard
                            uint32_t size, int type, 
784 69b91039 bellard
                            PCIMapIORegionFunc *map_func);
785 69b91039 bellard
786 5768f5ac bellard
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level);
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uint32_t pci_default_read_config(PCIDevice *d, 
789 5768f5ac bellard
                                 uint32_t address, int len);
790 5768f5ac bellard
void pci_default_write_config(PCIDevice *d, 
791 5768f5ac bellard
                              uint32_t address, uint32_t val, int len);
792 89b6b508 bellard
void pci_device_save(PCIDevice *s, QEMUFile *f);
793 89b6b508 bellard
int pci_device_load(PCIDevice *s, QEMUFile *f);
794 5768f5ac bellard
795 d2b59317 pbrook
typedef void (*pci_set_irq_fn)(void *pic, int irq_num, int level);
796 d2b59317 pbrook
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
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PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
798 80b3ada7 pbrook
                         void *pic, int devfn_min, int nirq);
799 502a5395 pbrook
800 abcebc7e ths
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
801 502a5395 pbrook
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
802 502a5395 pbrook
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
803 502a5395 pbrook
int pci_bus_num(PCIBus *s);
804 80b3ada7 pbrook
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
805 9995c51f bellard
806 5768f5ac bellard
void pci_info(void);
807 80b3ada7 pbrook
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
808 80b3ada7 pbrook
                        pci_map_irq_fn map_irq, const char *name);
809 26aa7d72 bellard
810 502a5395 pbrook
/* prep_pci.c */
811 46e50e9d bellard
PCIBus *pci_prep_init(void);
812 77d4bc34 bellard
813 502a5395 pbrook
/* grackle_pci.c */
814 502a5395 pbrook
PCIBus *pci_grackle_init(uint32_t base, void *pic);
815 502a5395 pbrook
816 502a5395 pbrook
/* unin_pci.c */
817 502a5395 pbrook
PCIBus *pci_pmac_init(void *pic);
818 502a5395 pbrook
819 502a5395 pbrook
/* apb_pci.c */
820 502a5395 pbrook
PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
821 502a5395 pbrook
                     void *pic);
822 502a5395 pbrook
823 e69954b9 pbrook
PCIBus *pci_vpb_init(void *pic, int irq, int realview);
824 502a5395 pbrook
825 502a5395 pbrook
/* piix_pci.c */
826 f00fc47c bellard
PCIBus *i440fx_init(PCIDevice **pi440fx_state);
827 f00fc47c bellard
void i440fx_set_smm(PCIDevice *d, int val);
828 8f1c91d8 ths
int piix3_init(PCIBus *bus, int devfn);
829 f00fc47c bellard
void i440fx_init_memory_mappings(PCIDevice *d);
830 a41b2ff2 pbrook
831 5856de80 ths
int piix4_init(PCIBus *bus, int devfn);
832 5856de80 ths
833 28b9b5af bellard
/* openpic.c */
834 28b9b5af bellard
typedef struct openpic_t openpic_t;
835 54fa5af5 bellard
void openpic_set_irq(void *opaque, int n_IRQ, int level);
836 7668a27f bellard
openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
837 7668a27f bellard
                         CPUState **envp);
838 28b9b5af bellard
839 54fa5af5 bellard
/* heathrow_pic.c */
840 54fa5af5 bellard
typedef struct HeathrowPICS HeathrowPICS;
841 54fa5af5 bellard
void heathrow_pic_set_irq(void *opaque, int num, int level);
842 54fa5af5 bellard
HeathrowPICS *heathrow_pic_init(int *pmem_index);
843 54fa5af5 bellard
844 fde7d5bd ths
/* gt64xxx.c */
845 fde7d5bd ths
PCIBus *pci_gt64120_init(void *pic);
846 fde7d5bd ths
847 6a36d84e bellard
#ifdef HAS_AUDIO
848 6a36d84e bellard
struct soundhw {
849 6a36d84e bellard
    const char *name;
850 6a36d84e bellard
    const char *descr;
851 6a36d84e bellard
    int enabled;
852 6a36d84e bellard
    int isa;
853 6a36d84e bellard
    union {
854 6a36d84e bellard
        int (*init_isa) (AudioState *s);
855 6a36d84e bellard
        int (*init_pci) (PCIBus *bus, AudioState *s);
856 6a36d84e bellard
    } init;
857 6a36d84e bellard
};
858 6a36d84e bellard
859 6a36d84e bellard
extern struct soundhw soundhw[];
860 6a36d84e bellard
#endif
861 6a36d84e bellard
862 313aa567 bellard
/* vga.c */
863 313aa567 bellard
864 74a14f22 bellard
#define VGA_RAM_SIZE (8192 * 1024)
865 313aa567 bellard
866 82c643ff bellard
struct DisplayState {
867 313aa567 bellard
    uint8_t *data;
868 313aa567 bellard
    int linesize;
869 313aa567 bellard
    int depth;
870 d3079cd2 bellard
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
871 82c643ff bellard
    int width;
872 82c643ff bellard
    int height;
873 24236869 bellard
    void *opaque;
874 24236869 bellard
875 313aa567 bellard
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
876 313aa567 bellard
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
877 313aa567 bellard
    void (*dpy_refresh)(struct DisplayState *s);
878 24236869 bellard
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, int dst_x, int dst_y, int w, int h);
879 82c643ff bellard
};
880 313aa567 bellard
881 313aa567 bellard
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
882 313aa567 bellard
{
883 313aa567 bellard
    s->dpy_update(s, x, y, w, h);
884 313aa567 bellard
}
885 313aa567 bellard
886 313aa567 bellard
static inline void dpy_resize(DisplayState *s, int w, int h)
887 313aa567 bellard
{
888 313aa567 bellard
    s->dpy_resize(s, w, h);
889 313aa567 bellard
}
890 313aa567 bellard
891 89b6b508 bellard
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
892 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size);
893 89b6b508 bellard
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
894 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size,
895 89b6b508 bellard
                 unsigned long vga_bios_offset, int vga_bios_size);
896 313aa567 bellard
897 d6bfa22f bellard
/* cirrus_vga.c */
898 46e50e9d bellard
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base, 
899 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
900 d6bfa22f bellard
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base, 
901 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
902 d6bfa22f bellard
903 313aa567 bellard
/* sdl.c */
904 d63d307f bellard
void sdl_display_init(DisplayState *ds, int full_screen);
905 313aa567 bellard
906 da4dbf74 bellard
/* cocoa.m */
907 da4dbf74 bellard
void cocoa_display_init(DisplayState *ds, int full_screen);
908 da4dbf74 bellard
909 24236869 bellard
/* vnc.c */
910 73fc9742 ths
void vnc_display_init(DisplayState *ds, const char *display);
911 a9ce8590 bellard
void do_info_vnc(void);
912 24236869 bellard
913 6070dd07 ths
/* x_keymap.c */
914 6070dd07 ths
extern uint8_t _translate_keycode(const int key);
915 6070dd07 ths
916 5391d806 bellard
/* ide.c */
917 5391d806 bellard
#define MAX_DISKS 4
918 5391d806 bellard
919 faea38e7 bellard
extern BlockDriverState *bs_table[MAX_DISKS + 1];
920 5391d806 bellard
921 69b91039 bellard
void isa_ide_init(int iobase, int iobase2, int irq,
922 69b91039 bellard
                  BlockDriverState *hd0, BlockDriverState *hd1);
923 54fa5af5 bellard
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
924 54fa5af5 bellard
                         int secondary_ide_enabled);
925 502a5395 pbrook
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn);
926 28b9b5af bellard
int pmac_ide_init (BlockDriverState **hd_table,
927 54fa5af5 bellard
                   SetIRQFunc *set_irq, void *irq_opaque, int irq);
928 5391d806 bellard
929 2e5d83bb pbrook
/* cdrom.c */
930 2e5d83bb pbrook
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
931 2e5d83bb pbrook
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
932 2e5d83bb pbrook
933 1d14ffa9 bellard
/* es1370.c */
934 c0fe3827 bellard
int es1370_init (PCIBus *bus, AudioState *s);
935 1d14ffa9 bellard
936 fb065187 bellard
/* sb16.c */
937 c0fe3827 bellard
int SB16_init (AudioState *s);
938 fb065187 bellard
939 fb065187 bellard
/* adlib.c */
940 c0fe3827 bellard
int Adlib_init (AudioState *s);
941 fb065187 bellard
942 fb065187 bellard
/* gus.c */
943 c0fe3827 bellard
int GUS_init (AudioState *s);
944 27503323 bellard
945 27503323 bellard
/* dma.c */
946 85571bc7 bellard
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
947 27503323 bellard
int DMA_get_channel_mode (int nchan);
948 85571bc7 bellard
int DMA_read_memory (int nchan, void *buf, int pos, int size);
949 85571bc7 bellard
int DMA_write_memory (int nchan, void *buf, int pos, int size);
950 27503323 bellard
void DMA_hold_DREQ (int nchan);
951 27503323 bellard
void DMA_release_DREQ (int nchan);
952 16f62432 bellard
void DMA_schedule(int nchan);
953 27503323 bellard
void DMA_run (void);
954 28b9b5af bellard
void DMA_init (int high_page_enable);
955 27503323 bellard
void DMA_register_channel (int nchan,
956 85571bc7 bellard
                           DMA_transfer_handler transfer_handler,
957 85571bc7 bellard
                           void *opaque);
958 7138fcfb bellard
/* fdc.c */
959 7138fcfb bellard
#define MAX_FD 2
960 7138fcfb bellard
extern BlockDriverState *fd_table[MAX_FD];
961 7138fcfb bellard
962 baca51fa bellard
typedef struct fdctrl_t fdctrl_t;
963 baca51fa bellard
964 baca51fa bellard
fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped, 
965 baca51fa bellard
                       uint32_t io_base,
966 baca51fa bellard
                       BlockDriverState **fds);
967 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
968 7138fcfb bellard
969 80cabfad bellard
/* ne2000.c */
970 80cabfad bellard
971 7c9d8e07 bellard
void isa_ne2000_init(int base, int irq, NICInfo *nd);
972 abcebc7e ths
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
973 80cabfad bellard
974 a41b2ff2 pbrook
/* rtl8139.c */
975 a41b2ff2 pbrook
976 abcebc7e ths
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
977 a41b2ff2 pbrook
978 e3c2613f bellard
/* pcnet.c */
979 e3c2613f bellard
980 abcebc7e ths
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
981 67e999be bellard
void pcnet_h_reset(void *opaque);
982 67e999be bellard
void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque);
983 67e999be bellard
984 e3c2613f bellard
985 80cabfad bellard
/* pckbd.c */
986 80cabfad bellard
987 80cabfad bellard
void kbd_init(void);
988 80cabfad bellard
989 80cabfad bellard
/* mc146818rtc.c */
990 80cabfad bellard
991 8a7ddc38 bellard
typedef struct RTCState RTCState;
992 80cabfad bellard
993 8a7ddc38 bellard
RTCState *rtc_init(int base, int irq);
994 8a7ddc38 bellard
void rtc_set_memory(RTCState *s, int addr, int val);
995 8a7ddc38 bellard
void rtc_set_date(RTCState *s, const struct tm *tm);
996 80cabfad bellard
997 80cabfad bellard
/* serial.c */
998 80cabfad bellard
999 c4b1fcc0 bellard
typedef struct SerialState SerialState;
1000 e5d13e2f bellard
SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
1001 e5d13e2f bellard
                         int base, int irq, CharDriverState *chr);
1002 e5d13e2f bellard
SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
1003 e5d13e2f bellard
                             target_ulong base, int it_shift,
1004 e5d13e2f bellard
                             int irq, CharDriverState *chr);
1005 80cabfad bellard
1006 6508fe59 bellard
/* parallel.c */
1007 6508fe59 bellard
1008 6508fe59 bellard
typedef struct ParallelState ParallelState;
1009 6508fe59 bellard
ParallelState *parallel_init(int base, int irq, CharDriverState *chr);
1010 6508fe59 bellard
1011 80cabfad bellard
/* i8259.c */
1012 80cabfad bellard
1013 3de388f6 bellard
typedef struct PicState2 PicState2;
1014 3de388f6 bellard
extern PicState2 *isa_pic;
1015 80cabfad bellard
void pic_set_irq(int irq, int level);
1016 54fa5af5 bellard
void pic_set_irq_new(void *opaque, int irq, int level);
1017 3de388f6 bellard
PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque);
1018 d592d303 bellard
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1019 d592d303 bellard
                          void *alt_irq_opaque);
1020 3de388f6 bellard
int pic_read_irq(PicState2 *s);
1021 3de388f6 bellard
void pic_update_irq(PicState2 *s);
1022 3de388f6 bellard
uint32_t pic_intack_read(PicState2 *s);
1023 c20709aa bellard
void pic_info(void);
1024 4a0fb71e bellard
void irq_info(void);
1025 80cabfad bellard
1026 c27004ec bellard
/* APIC */
1027 d592d303 bellard
typedef struct IOAPICState IOAPICState;
1028 d592d303 bellard
1029 c27004ec bellard
int apic_init(CPUState *env);
1030 c27004ec bellard
int apic_get_interrupt(CPUState *env);
1031 d592d303 bellard
IOAPICState *ioapic_init(void);
1032 d592d303 bellard
void ioapic_set_irq(void *opaque, int vector, int level);
1033 c27004ec bellard
1034 80cabfad bellard
/* i8254.c */
1035 80cabfad bellard
1036 80cabfad bellard
#define PIT_FREQ 1193182
1037 80cabfad bellard
1038 ec844b96 bellard
typedef struct PITState PITState;
1039 ec844b96 bellard
1040 ec844b96 bellard
PITState *pit_init(int base, int irq);
1041 ec844b96 bellard
void pit_set_gate(PITState *pit, int channel, int val);
1042 ec844b96 bellard
int pit_get_gate(PITState *pit, int channel);
1043 fd06c375 bellard
int pit_get_initial_count(PITState *pit, int channel);
1044 fd06c375 bellard
int pit_get_mode(PITState *pit, int channel);
1045 ec844b96 bellard
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1046 80cabfad bellard
1047 fd06c375 bellard
/* pcspk.c */
1048 fd06c375 bellard
void pcspk_init(PITState *);
1049 fd06c375 bellard
int pcspk_audio_init(AudioState *);
1050 fd06c375 bellard
1051 3fffc223 ths
#include "hw/smbus.h"
1052 3fffc223 ths
1053 6515b203 bellard
/* acpi.c */
1054 6515b203 bellard
extern int acpi_enabled;
1055 502a5395 pbrook
void piix4_pm_init(PCIBus *bus, int devfn);
1056 3fffc223 ths
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1057 6515b203 bellard
void acpi_bios_init(void);
1058 6515b203 bellard
1059 3fffc223 ths
/* smbus_eeprom.c */
1060 3fffc223 ths
SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
1061 3fffc223 ths
1062 80cabfad bellard
/* pc.c */
1063 54fa5af5 bellard
extern QEMUMachine pc_machine;
1064 3dbbdc25 bellard
extern QEMUMachine isapc_machine;
1065 52ca8d6a bellard
extern int fd_bootchk;
1066 80cabfad bellard
1067 6a00d601 bellard
void ioport_set_a20(int enable);
1068 6a00d601 bellard
int ioport_get_a20(void);
1069 6a00d601 bellard
1070 26aa7d72 bellard
/* ppc.c */
1071 54fa5af5 bellard
extern QEMUMachine prep_machine;
1072 54fa5af5 bellard
extern QEMUMachine core99_machine;
1073 54fa5af5 bellard
extern QEMUMachine heathrow_machine;
1074 54fa5af5 bellard
1075 6af0bf9c bellard
/* mips_r4k.c */
1076 6af0bf9c bellard
extern QEMUMachine mips_machine;
1077 6af0bf9c bellard
1078 5856de80 ths
/* mips_malta.c */
1079 5856de80 ths
extern QEMUMachine mips_malta_machine;
1080 5856de80 ths
1081 4de9b249 ths
/* mips_int */
1082 4de9b249 ths
extern void cpu_mips_irq_request(void *opaque, int irq, int level);
1083 4de9b249 ths
1084 e16fe40c ths
/* mips_timer.c */
1085 e16fe40c ths
extern void cpu_mips_clock_init(CPUState *);
1086 e16fe40c ths
extern void cpu_mips_irqctrl_init (void);
1087 e16fe40c ths
1088 27c7ca7e bellard
/* shix.c */
1089 27c7ca7e bellard
extern QEMUMachine shix_machine;
1090 27c7ca7e bellard
1091 8cc43fef bellard
#ifdef TARGET_PPC
1092 8cc43fef bellard
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1093 8cc43fef bellard
#endif
1094 64201201 bellard
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1095 77d4bc34 bellard
1096 77d4bc34 bellard
extern CPUWriteMemoryFunc *PPC_io_write[];
1097 77d4bc34 bellard
extern CPUReadMemoryFunc *PPC_io_read[];
1098 54fa5af5 bellard
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1099 26aa7d72 bellard
1100 e95c8d51 bellard
/* sun4m.c */
1101 54fa5af5 bellard
extern QEMUMachine sun4m_machine;
1102 ba3c64fb bellard
void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
1103 e95c8d51 bellard
1104 e95c8d51 bellard
/* iommu.c */
1105 e80cfcfc bellard
void *iommu_init(uint32_t addr);
1106 67e999be bellard
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1107 a917d384 pbrook
                                 uint8_t *buf, int len, int is_write);
1108 67e999be bellard
static inline void sparc_iommu_memory_read(void *opaque,
1109 67e999be bellard
                                           target_phys_addr_t addr,
1110 67e999be bellard
                                           uint8_t *buf, int len)
1111 67e999be bellard
{
1112 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1113 67e999be bellard
}
1114 e95c8d51 bellard
1115 67e999be bellard
static inline void sparc_iommu_memory_write(void *opaque,
1116 67e999be bellard
                                            target_phys_addr_t addr,
1117 67e999be bellard
                                            uint8_t *buf, int len)
1118 67e999be bellard
{
1119 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1120 67e999be bellard
}
1121 e95c8d51 bellard
1122 e95c8d51 bellard
/* tcx.c */
1123 95219897 pbrook
void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
1124 6f7e9aec bellard
               unsigned long vram_offset, int vram_size, int width, int height);
1125 e80cfcfc bellard
1126 e80cfcfc bellard
/* slavio_intctl.c */
1127 e80cfcfc bellard
void *slavio_intctl_init();
1128 ba3c64fb bellard
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
1129 e80cfcfc bellard
void slavio_pic_info(void *opaque);
1130 e80cfcfc bellard
void slavio_irq_info(void *opaque);
1131 e80cfcfc bellard
void slavio_pic_set_irq(void *opaque, int irq, int level);
1132 ba3c64fb bellard
void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
1133 e95c8d51 bellard
1134 5fe141fd bellard
/* loader.c */
1135 5fe141fd bellard
int get_image_size(const char *filename);
1136 5fe141fd bellard
int load_image(const char *filename, uint8_t *addr);
1137 9ee3c029 bellard
int load_elf(const char *filename, int64_t virt_to_phys_addend, uint64_t *pentry);
1138 e80cfcfc bellard
int load_aout(const char *filename, uint8_t *addr);
1139 e80cfcfc bellard
1140 e80cfcfc bellard
/* slavio_timer.c */
1141 ba3c64fb bellard
void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu);
1142 8d5f07fa bellard
1143 e80cfcfc bellard
/* slavio_serial.c */
1144 e80cfcfc bellard
SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2);
1145 e80cfcfc bellard
void slavio_serial_ms_kbd_init(int base, int irq);
1146 e95c8d51 bellard
1147 3475187d bellard
/* slavio_misc.c */
1148 3475187d bellard
void *slavio_misc_init(uint32_t base, int irq);
1149 3475187d bellard
void slavio_set_power_fail(void *opaque, int power_failing);
1150 3475187d bellard
1151 6f7e9aec bellard
/* esp.c */
1152 fa1fb14c ths
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1153 67e999be bellard
void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
1154 67e999be bellard
void esp_reset(void *opaque);
1155 67e999be bellard
1156 67e999be bellard
/* sparc32_dma.c */
1157 67e999be bellard
void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu,
1158 67e999be bellard
                       void *intctl);
1159 67e999be bellard
void ledma_set_irq(void *opaque, int isr);
1160 9b94dc32 bellard
void ledma_memory_read(void *opaque, target_phys_addr_t addr, 
1161 9b94dc32 bellard
                       uint8_t *buf, int len, int do_bswap);
1162 9b94dc32 bellard
void ledma_memory_write(void *opaque, target_phys_addr_t addr, 
1163 9b94dc32 bellard
                        uint8_t *buf, int len, int do_bswap);
1164 67e999be bellard
void espdma_raise_irq(void *opaque);
1165 67e999be bellard
void espdma_clear_irq(void *opaque);
1166 67e999be bellard
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1167 67e999be bellard
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1168 67e999be bellard
void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1169 67e999be bellard
                                void *lance_opaque);
1170 6f7e9aec bellard
1171 b8174937 bellard
/* cs4231.c */
1172 b8174937 bellard
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1173 b8174937 bellard
1174 3475187d bellard
/* sun4u.c */
1175 3475187d bellard
extern QEMUMachine sun4u_machine;
1176 3475187d bellard
1177 64201201 bellard
/* NVRAM helpers */
1178 64201201 bellard
#include "hw/m48t59.h"
1179 64201201 bellard
1180 64201201 bellard
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1181 64201201 bellard
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1182 64201201 bellard
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1183 64201201 bellard
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1184 64201201 bellard
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1185 64201201 bellard
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1186 64201201 bellard
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1187 64201201 bellard
                       const unsigned char *str, uint32_t max);
1188 64201201 bellard
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1189 64201201 bellard
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1190 64201201 bellard
                    uint32_t start, uint32_t count);
1191 64201201 bellard
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1192 64201201 bellard
                          const unsigned char *arch,
1193 64201201 bellard
                          uint32_t RAM_size, int boot_device,
1194 64201201 bellard
                          uint32_t kernel_image, uint32_t kernel_size,
1195 28b9b5af bellard
                          const char *cmdline,
1196 64201201 bellard
                          uint32_t initrd_image, uint32_t initrd_size,
1197 28b9b5af bellard
                          uint32_t NVRAM_image,
1198 28b9b5af bellard
                          int width, int height, int depth);
1199 64201201 bellard
1200 63066f4f bellard
/* adb.c */
1201 63066f4f bellard
1202 63066f4f bellard
#define MAX_ADB_DEVICES 16
1203 63066f4f bellard
1204 e2733d20 bellard
#define ADB_MAX_OUT_LEN 16
1205 63066f4f bellard
1206 e2733d20 bellard
typedef struct ADBDevice ADBDevice;
1207 63066f4f bellard
1208 e2733d20 bellard
/* buf = NULL means polling */
1209 e2733d20 bellard
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1210 e2733d20 bellard
                              const uint8_t *buf, int len);
1211 12c28fed bellard
typedef int ADBDeviceReset(ADBDevice *d);
1212 12c28fed bellard
1213 63066f4f bellard
struct ADBDevice {
1214 63066f4f bellard
    struct ADBBusState *bus;
1215 63066f4f bellard
    int devaddr;
1216 63066f4f bellard
    int handler;
1217 e2733d20 bellard
    ADBDeviceRequest *devreq;
1218 12c28fed bellard
    ADBDeviceReset *devreset;
1219 63066f4f bellard
    void *opaque;
1220 63066f4f bellard
};
1221 63066f4f bellard
1222 63066f4f bellard
typedef struct ADBBusState {
1223 63066f4f bellard
    ADBDevice devices[MAX_ADB_DEVICES];
1224 63066f4f bellard
    int nb_devices;
1225 e2733d20 bellard
    int poll_index;
1226 63066f4f bellard
} ADBBusState;
1227 63066f4f bellard
1228 e2733d20 bellard
int adb_request(ADBBusState *s, uint8_t *buf_out,
1229 e2733d20 bellard
                const uint8_t *buf, int len);
1230 e2733d20 bellard
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1231 63066f4f bellard
1232 63066f4f bellard
ADBDevice *adb_register_device(ADBBusState *s, int devaddr, 
1233 e2733d20 bellard
                               ADBDeviceRequest *devreq, 
1234 12c28fed bellard
                               ADBDeviceReset *devreset, 
1235 63066f4f bellard
                               void *opaque);
1236 63066f4f bellard
void adb_kbd_init(ADBBusState *bus);
1237 63066f4f bellard
void adb_mouse_init(ADBBusState *bus);
1238 63066f4f bellard
1239 63066f4f bellard
/* cuda.c */
1240 63066f4f bellard
1241 63066f4f bellard
extern ADBBusState adb_bus;
1242 54fa5af5 bellard
int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq);
1243 63066f4f bellard
1244 bb36d470 bellard
#include "hw/usb.h"
1245 bb36d470 bellard
1246 a594cfbf bellard
/* usb ports of the VM */
1247 a594cfbf bellard
1248 0d92ed30 pbrook
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1249 0d92ed30 pbrook
                            usb_attachfn attach);
1250 a594cfbf bellard
1251 0d92ed30 pbrook
#define VM_USB_HUB_SIZE 8
1252 a594cfbf bellard
1253 a594cfbf bellard
void do_usb_add(const char *devname);
1254 a594cfbf bellard
void do_usb_del(const char *devname);
1255 a594cfbf bellard
void usb_info(void);
1256 a594cfbf bellard
1257 2e5d83bb pbrook
/* scsi-disk.c */
1258 4d611c9a pbrook
enum scsi_reason {
1259 4d611c9a pbrook
    SCSI_REASON_DONE, /* Command complete.  */
1260 4d611c9a pbrook
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1261 4d611c9a pbrook
};
1262 4d611c9a pbrook
1263 2e5d83bb pbrook
typedef struct SCSIDevice SCSIDevice;
1264 a917d384 pbrook
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1265 a917d384 pbrook
                                  uint32_t arg);
1266 2e5d83bb pbrook
1267 2e5d83bb pbrook
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1268 a917d384 pbrook
                           int tcq,
1269 2e5d83bb pbrook
                           scsi_completionfn completion,
1270 2e5d83bb pbrook
                           void *opaque);
1271 2e5d83bb pbrook
void scsi_disk_destroy(SCSIDevice *s);
1272 2e5d83bb pbrook
1273 0fc5c15a pbrook
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1274 4d611c9a pbrook
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1275 4d611c9a pbrook
   layer the completion routine may be called directly by
1276 4d611c9a pbrook
   scsi_{read,write}_data.  */
1277 a917d384 pbrook
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1278 a917d384 pbrook
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1279 a917d384 pbrook
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1280 a917d384 pbrook
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1281 2e5d83bb pbrook
1282 7d8406be pbrook
/* lsi53c895a.c */
1283 7d8406be pbrook
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1284 7d8406be pbrook
void *lsi_scsi_init(PCIBus *bus, int devfn);
1285 7d8406be pbrook
1286 b5ff1b31 bellard
/* integratorcp.c */
1287 40f137e1 pbrook
extern QEMUMachine integratorcp926_machine;
1288 40f137e1 pbrook
extern QEMUMachine integratorcp1026_machine;
1289 b5ff1b31 bellard
1290 cdbdb648 pbrook
/* versatilepb.c */
1291 cdbdb648 pbrook
extern QEMUMachine versatilepb_machine;
1292 16406950 pbrook
extern QEMUMachine versatileab_machine;
1293 cdbdb648 pbrook
1294 e69954b9 pbrook
/* realview.c */
1295 e69954b9 pbrook
extern QEMUMachine realview_machine;
1296 e69954b9 pbrook
1297 daa57963 bellard
/* ps2.c */
1298 daa57963 bellard
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1299 daa57963 bellard
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1300 daa57963 bellard
void ps2_write_mouse(void *, int val);
1301 daa57963 bellard
void ps2_write_keyboard(void *, int val);
1302 daa57963 bellard
uint32_t ps2_read_data(void *);
1303 daa57963 bellard
void ps2_queue(void *, int b);
1304 f94f5d71 pbrook
void ps2_keyboard_set_translation(void *opaque, int mode);
1305 daa57963 bellard
1306 80337b66 bellard
/* smc91c111.c */
1307 80337b66 bellard
void smc91c111_init(NICInfo *, uint32_t, void *, int);
1308 80337b66 bellard
1309 bdd5003a pbrook
/* pl110.c */
1310 95219897 pbrook
void *pl110_init(DisplayState *ds, uint32_t base, void *pic, int irq, int);
1311 bdd5003a pbrook
1312 cdbdb648 pbrook
/* pl011.c */
1313 cdbdb648 pbrook
void pl011_init(uint32_t base, void *pic, int irq, CharDriverState *chr);
1314 cdbdb648 pbrook
1315 cdbdb648 pbrook
/* pl050.c */
1316 cdbdb648 pbrook
void pl050_init(uint32_t base, void *pic, int irq, int is_mouse);
1317 cdbdb648 pbrook
1318 cdbdb648 pbrook
/* pl080.c */
1319 e69954b9 pbrook
void *pl080_init(uint32_t base, void *pic, int irq, int nchannels);
1320 cdbdb648 pbrook
1321 cdbdb648 pbrook
/* pl190.c */
1322 cdbdb648 pbrook
void *pl190_init(uint32_t base, void *parent, int irq, int fiq);
1323 cdbdb648 pbrook
1324 cdbdb648 pbrook
/* arm-timer.c */
1325 cdbdb648 pbrook
void sp804_init(uint32_t base, void *pic, int irq);
1326 cdbdb648 pbrook
void icp_pit_init(uint32_t base, void *pic, int irq);
1327 cdbdb648 pbrook
1328 e69954b9 pbrook
/* arm_sysctl.c */
1329 e69954b9 pbrook
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1330 e69954b9 pbrook
1331 e69954b9 pbrook
/* arm_gic.c */
1332 e69954b9 pbrook
void *arm_gic_init(uint32_t base, void *parent, int parent_irq);
1333 e69954b9 pbrook
1334 16406950 pbrook
/* arm_boot.c */
1335 16406950 pbrook
1336 daf90626 pbrook
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1337 16406950 pbrook
                     const char *kernel_cmdline, const char *initrd_filename,
1338 16406950 pbrook
                     int board_id);
1339 16406950 pbrook
1340 27c7ca7e bellard
/* sh7750.c */
1341 27c7ca7e bellard
struct SH7750State;
1342 27c7ca7e bellard
1343 008a8818 pbrook
struct SH7750State *sh7750_init(CPUState * cpu);
1344 27c7ca7e bellard
1345 27c7ca7e bellard
typedef struct {
1346 27c7ca7e bellard
    /* The callback will be triggered if any of the designated lines change */
1347 27c7ca7e bellard
    uint16_t portamask_trigger;
1348 27c7ca7e bellard
    uint16_t portbmask_trigger;
1349 27c7ca7e bellard
    /* Return 0 if no action was taken */
1350 27c7ca7e bellard
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1351 27c7ca7e bellard
                           uint16_t * periph_pdtra,
1352 27c7ca7e bellard
                           uint16_t * periph_portdira,
1353 27c7ca7e bellard
                           uint16_t * periph_pdtrb,
1354 27c7ca7e bellard
                           uint16_t * periph_portdirb);
1355 27c7ca7e bellard
} sh7750_io_device;
1356 27c7ca7e bellard
1357 27c7ca7e bellard
int sh7750_register_io_device(struct SH7750State *s,
1358 27c7ca7e bellard
                              sh7750_io_device * device);
1359 27c7ca7e bellard
/* tc58128.c */
1360 27c7ca7e bellard
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1361 27c7ca7e bellard
1362 29133e9a bellard
/* NOR flash devices */
1363 29133e9a bellard
typedef struct pflash_t pflash_t;
1364 29133e9a bellard
1365 29133e9a bellard
pflash_t *pflash_register (target_ulong base, ram_addr_t off,
1366 29133e9a bellard
                           BlockDriverState *bs,
1367 29133e9a bellard
                           target_ulong sector_len, int nb_blocs, int width,
1368 29133e9a bellard
                           uint16_t id0, uint16_t id1, 
1369 29133e9a bellard
                           uint16_t id2, uint16_t id3);
1370 29133e9a bellard
1371 4046d913 pbrook
#include "gdbstub.h"
1372 4046d913 pbrook
1373 ea2384d3 bellard
#endif /* defined(QEMU_TOOL) */
1374 ea2384d3 bellard
1375 c4b1fcc0 bellard
/* monitor.c */
1376 82c643ff bellard
void monitor_init(CharDriverState *hd, int show_banner);
1377 ea2384d3 bellard
void term_puts(const char *str);
1378 ea2384d3 bellard
void term_vprintf(const char *fmt, va_list ap);
1379 40c3bac3 bellard
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1380 fef30743 ths
void term_print_filename(const char *filename);
1381 c4b1fcc0 bellard
void term_flush(void);
1382 c4b1fcc0 bellard
void term_print_help(void);
1383 ea2384d3 bellard
void monitor_readline(const char *prompt, int is_password,
1384 ea2384d3 bellard
                      char *buf, int buf_size);
1385 ea2384d3 bellard
1386 ea2384d3 bellard
/* readline.c */
1387 ea2384d3 bellard
typedef void ReadLineFunc(void *opaque, const char *str);
1388 ea2384d3 bellard
1389 ea2384d3 bellard
extern int completion_index;
1390 ea2384d3 bellard
void add_completion(const char *str);
1391 ea2384d3 bellard
void readline_handle_byte(int ch);
1392 ea2384d3 bellard
void readline_find_completion(const char *cmdline);
1393 ea2384d3 bellard
const char *readline_get_history(unsigned int index);
1394 ea2384d3 bellard
void readline_start(const char *prompt, int is_password,
1395 ea2384d3 bellard
                    ReadLineFunc *readline_func, void *opaque);
1396 c4b1fcc0 bellard
1397 5e6ad6f9 bellard
void kqemu_record_dump(void);
1398 5e6ad6f9 bellard
1399 fc01f7e7 bellard
#endif /* VL_H */