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/*
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* QEMU GT64120 PCI host
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*
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* Copyright (c) 2006,2007 Aurelien Jarno
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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typedef target_phys_addr_t pci_addr_t;
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#include "pci_host.h" |
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|
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#define GT_REGS (0x1000 >> 2) |
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|
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/* CPU Configuration */
|
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#define GT_CPU (0x000 >> 2) |
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#define GT_MULTI (0x120 >> 2) |
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|
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/* CPU Address Decode */
|
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#define GT_SCS10LD (0x008 >> 2) |
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#define GT_SCS10HD (0x010 >> 2) |
| 38 |
#define GT_SCS32LD (0x018 >> 2) |
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#define GT_SCS32HD (0x020 >> 2) |
| 40 |
#define GT_CS20LD (0x028 >> 2) |
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#define GT_CS20HD (0x030 >> 2) |
| 42 |
#define GT_CS3BOOTLD (0x038 >> 2) |
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#define GT_CS3BOOTHD (0x040 >> 2) |
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#define GT_PCI0IOLD (0x048 >> 2) |
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#define GT_PCI0IOHD (0x050 >> 2) |
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#define GT_PCI0M0LD (0x058 >> 2) |
| 47 |
#define GT_PCI0M0HD (0x060 >> 2) |
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#define GT_ISD (0x068 >> 2) |
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|
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#define GT_PCI0M1LD (0x080 >> 2) |
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#define GT_PCI0M1HD (0x088 >> 2) |
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#define GT_PCI1IOLD (0x090 >> 2) |
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#define GT_PCI1IOHD (0x098 >> 2) |
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#define GT_PCI1M0LD (0x0a0 >> 2) |
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#define GT_PCI1M0HD (0x0a8 >> 2) |
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#define GT_PCI1M1LD (0x0b0 >> 2) |
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#define GT_PCI1M1HD (0x0b8 >> 2) |
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#define GT_PCI1M1LD (0x0b0 >> 2) |
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#define GT_PCI1M1HD (0x0b8 >> 2) |
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|
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#define GT_SCS10AR (0x0d0 >> 2) |
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#define GT_SCS32AR (0x0d8 >> 2) |
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#define GT_CS20R (0x0e0 >> 2) |
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#define GT_CS3BOOTR (0x0e8 >> 2) |
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|
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#define GT_PCI0IOREMAP (0x0f0 >> 2) |
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#define GT_PCI0M0REMAP (0x0f8 >> 2) |
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#define GT_PCI0M1REMAP (0x100 >> 2) |
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#define GT_PCI1IOREMAP (0x108 >> 2) |
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#define GT_PCI1M0REMAP (0x110 >> 2) |
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#define GT_PCI1M1REMAP (0x118 >> 2) |
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|
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/* CPU Error Report */
|
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#define GT_CPUERR_ADDRLO (0x070 >> 2) |
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#define GT_CPUERR_ADDRHI (0x078 >> 2) |
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#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ |
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#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ |
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#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ |
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|
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/* CPU Sync Barrier */
|
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#define GT_PCI0SYNC (0x0c0 >> 2) |
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#define GT_PCI1SYNC (0x0c8 >> 2) |
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|
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/* SDRAM and Device Address Decode */
|
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#define GT_SCS0LD (0x400 >> 2) |
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#define GT_SCS0HD (0x404 >> 2) |
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#define GT_SCS1LD (0x408 >> 2) |
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#define GT_SCS1HD (0x40c >> 2) |
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#define GT_SCS2LD (0x410 >> 2) |
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#define GT_SCS2HD (0x414 >> 2) |
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#define GT_SCS3LD (0x418 >> 2) |
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#define GT_SCS3HD (0x41c >> 2) |
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#define GT_CS0LD (0x420 >> 2) |
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#define GT_CS0HD (0x424 >> 2) |
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#define GT_CS1LD (0x428 >> 2) |
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#define GT_CS1HD (0x42c >> 2) |
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#define GT_CS2LD (0x430 >> 2) |
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#define GT_CS2HD (0x434 >> 2) |
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#define GT_CS3LD (0x438 >> 2) |
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#define GT_CS3HD (0x43c >> 2) |
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#define GT_BOOTLD (0x440 >> 2) |
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#define GT_BOOTHD (0x444 >> 2) |
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#define GT_ADERR (0x470 >> 2) |
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|
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/* SDRAM Configuration */
|
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#define GT_SDRAM_CFG (0x448 >> 2) |
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#define GT_SDRAM_OPMODE (0x474 >> 2) |
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#define GT_SDRAM_BM (0x478 >> 2) |
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#define GT_SDRAM_ADDRDECODE (0x47c >> 2) |
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|
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/* SDRAM Parameters */
|
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#define GT_SDRAM_B0 (0x44c >> 2) |
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#define GT_SDRAM_B1 (0x450 >> 2) |
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#define GT_SDRAM_B2 (0x454 >> 2) |
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#define GT_SDRAM_B3 (0x458 >> 2) |
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|
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/* Device Parameters */
|
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#define GT_DEV_B0 (0x45c >> 2) |
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#define GT_DEV_B1 (0x460 >> 2) |
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#define GT_DEV_B2 (0x464 >> 2) |
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#define GT_DEV_B3 (0x468 >> 2) |
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#define GT_DEV_BOOT (0x46c >> 2) |
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|
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/* ECC */
|
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#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ |
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#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ |
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#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ |
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#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ |
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#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ |
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|
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/* DMA Record */
|
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#define GT_DMA0_CNT (0x800 >> 2) |
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#define GT_DMA1_CNT (0x804 >> 2) |
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#define GT_DMA2_CNT (0x808 >> 2) |
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#define GT_DMA3_CNT (0x80c >> 2) |
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#define GT_DMA0_SA (0x810 >> 2) |
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#define GT_DMA1_SA (0x814 >> 2) |
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#define GT_DMA2_SA (0x818 >> 2) |
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#define GT_DMA3_SA (0x81c >> 2) |
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#define GT_DMA0_DA (0x820 >> 2) |
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#define GT_DMA1_DA (0x824 >> 2) |
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#define GT_DMA2_DA (0x828 >> 2) |
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#define GT_DMA3_DA (0x82c >> 2) |
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#define GT_DMA0_NEXT (0x830 >> 2) |
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#define GT_DMA1_NEXT (0x834 >> 2) |
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#define GT_DMA2_NEXT (0x838 >> 2) |
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#define GT_DMA3_NEXT (0x83c >> 2) |
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#define GT_DMA0_CUR (0x870 >> 2) |
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#define GT_DMA1_CUR (0x874 >> 2) |
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#define GT_DMA2_CUR (0x878 >> 2) |
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#define GT_DMA3_CUR (0x87c >> 2) |
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|
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/* DMA Channel Control */
|
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#define GT_DMA0_CTRL (0x840 >> 2) |
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#define GT_DMA1_CTRL (0x844 >> 2) |
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#define GT_DMA2_CTRL (0x848 >> 2) |
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#define GT_DMA3_CTRL (0x84c >> 2) |
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|
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/* DMA Arbiter */
|
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#define GT_DMA_ARB (0x860 >> 2) |
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|
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/* Timer/Counter */
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#define GT_TC0 (0x850 >> 2) |
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#define GT_TC1 (0x854 >> 2) |
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#define GT_TC2 (0x858 >> 2) |
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#define GT_TC3 (0x85c >> 2) |
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#define GT_TC_CONTROL (0x864 >> 2) |
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|
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/* PCI Internal */
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#define GT_PCI0_CMD (0xc00 >> 2) |
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#define GT_PCI0_TOR (0xc04 >> 2) |
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#define GT_PCI0_BS_SCS10 (0xc08 >> 2) |
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#define GT_PCI0_BS_SCS32 (0xc0c >> 2) |
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#define GT_PCI0_BS_CS20 (0xc10 >> 2) |
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#define GT_PCI0_BS_CS3BT (0xc14 >> 2) |
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#define GT_PCI1_IACK (0xc30 >> 2) |
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#define GT_PCI0_IACK (0xc34 >> 2) |
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#define GT_PCI0_BARE (0xc3c >> 2) |
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#define GT_PCI0_PREFMBR (0xc40 >> 2) |
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#define GT_PCI0_SCS10_BAR (0xc48 >> 2) |
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#define GT_PCI0_SCS32_BAR (0xc4c >> 2) |
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#define GT_PCI0_CS20_BAR (0xc50 >> 2) |
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#define GT_PCI0_CS3BT_BAR (0xc54 >> 2) |
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#define GT_PCI0_SSCS10_BAR (0xc58 >> 2) |
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#define GT_PCI0_SSCS32_BAR (0xc5c >> 2) |
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#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) |
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#define GT_PCI1_CMD (0xc80 >> 2) |
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#define GT_PCI1_TOR (0xc84 >> 2) |
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#define GT_PCI1_BS_SCS10 (0xc88 >> 2) |
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#define GT_PCI1_BS_SCS32 (0xc8c >> 2) |
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#define GT_PCI1_BS_CS20 (0xc90 >> 2) |
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#define GT_PCI1_BS_CS3BT (0xc94 >> 2) |
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#define GT_PCI1_BARE (0xcbc >> 2) |
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#define GT_PCI1_PREFMBR (0xcc0 >> 2) |
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#define GT_PCI1_SCS10_BAR (0xcc8 >> 2) |
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#define GT_PCI1_SCS32_BAR (0xccc >> 2) |
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#define GT_PCI1_CS20_BAR (0xcd0 >> 2) |
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#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) |
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#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) |
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#define GT_PCI1_SSCS32_BAR (0xcdc >> 2) |
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#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) |
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#define GT_PCI1_CFGADDR (0xcf0 >> 2) |
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#define GT_PCI1_CFGDATA (0xcf4 >> 2) |
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#define GT_PCI0_CFGADDR (0xcf8 >> 2) |
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#define GT_PCI0_CFGDATA (0xcfc >> 2) |
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|
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/* Interrupts */
|
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#define GT_INTRCAUSE (0xc18 >> 2) |
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#define GT_INTRMASK (0xc1c >> 2) |
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#define GT_PCI0_ICMASK (0xc24 >> 2) |
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#define GT_PCI0_SERR0MASK (0xc28 >> 2) |
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#define GT_CPU_INTSEL (0xc70 >> 2) |
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#define GT_PCI0_INTSEL (0xc74 >> 2) |
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#define GT_HINTRCAUSE (0xc98 >> 2) |
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#define GT_HINTRMASK (0xc9c >> 2) |
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#define GT_PCI0_HICMASK (0xca4 >> 2) |
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#define GT_PCI1_SERR1MASK (0xca8 >> 2) |
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|
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|
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typedef PCIHostState GT64120PCIState;
|
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|
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typedef struct GT64120State { |
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GT64120PCIState *pci; |
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uint32_t regs[GT_REGS]; |
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} GT64120State; |
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|
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static void gt64120_pci_mapping(GT64120State *s) |
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{
|
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target_phys_addr_t start, length; |
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|
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/* Update IO mapping */
|
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if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) |
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{
|
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start = s->regs[GT_PCI0IOLD] << 21;
|
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length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; |
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isa_mmio_init(start, length); |
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} |
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} |
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|
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static void gt64120_writel (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{
|
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GT64120State *s = opaque; |
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uint32_t saddr; |
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|
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#ifdef TARGET_WORDS_BIGENDIAN
|
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val = bswap32(val); |
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#endif
|
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|
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saddr = (addr & 0xfff) >> 2; |
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switch (saddr) {
|
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|
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/* CPU Configuration */
|
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case GT_CPU:
|
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s->regs[GT_CPU] = val; |
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break;
|
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case GT_MULTI:
|
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/* Read-only register as only one GT64xxx is present on the CPU bus */
|
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break;
|
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|
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/* CPU Address Decode */
|
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case GT_PCI0IOLD:
|
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s->regs[GT_PCI0IOLD] = val & 0x00007fff;
|
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s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
|
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gt64120_pci_mapping(s); |
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break;
|
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case GT_PCI0M0LD:
|
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s->regs[GT_PCI0M0LD] = val & 0x00007fff;
|
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s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
|
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gt64120_pci_mapping(s); |
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break;
|
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case GT_PCI0M1LD:
|
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s->regs[GT_PCI0M1LD] = val & 0x00007fff;
|
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s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
|
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gt64120_pci_mapping(s); |
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break;
|
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case GT_PCI1IOLD:
|
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s->regs[GT_PCI1IOLD] = val & 0x00007fff;
|
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s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
|
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gt64120_pci_mapping(s); |
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break;
|
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case GT_PCI1M0LD:
|
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s->regs[GT_PCI1M0LD] = val & 0x00007fff;
|
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s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
|
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gt64120_pci_mapping(s); |
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break;
|
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case GT_PCI1M1LD:
|
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s->regs[GT_PCI1M1LD] = val & 0x00007fff;
|
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s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
|
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gt64120_pci_mapping(s); |
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break;
|
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case GT_PCI0IOHD:
|
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case GT_PCI0M0HD:
|
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case GT_PCI0M1HD:
|
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case GT_PCI1IOHD:
|
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case GT_PCI1M0HD:
|
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case GT_PCI1M1HD:
|
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s->regs[saddr] = val & 0x0000007f;
|
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gt64120_pci_mapping(s); |
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break;
|
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case GT_PCI0IOREMAP:
|
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case GT_PCI0M0REMAP:
|
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case GT_PCI0M1REMAP:
|
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case GT_PCI1IOREMAP:
|
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case GT_PCI1M0REMAP:
|
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case GT_PCI1M1REMAP:
|
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s->regs[saddr] = val & 0x000007ff;
|
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gt64120_pci_mapping(s); |
| 309 |
break;
|
| 310 |
|
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/* CPU Error Report */
|
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case GT_CPUERR_ADDRLO:
|
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case GT_CPUERR_ADDRHI:
|
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case GT_CPUERR_DATALO:
|
| 315 |
case GT_CPUERR_DATAHI:
|
| 316 |
case GT_CPUERR_PARITY:
|
| 317 |
/* Read-only registers, do nothing */
|
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break;
|
| 319 |
|
| 320 |
/* CPU Sync Barrier */
|
| 321 |
case GT_PCI0SYNC:
|
| 322 |
case GT_PCI1SYNC:
|
| 323 |
/* Read-only registers, do nothing */
|
| 324 |
break;
|
| 325 |
|
| 326 |
/* ECC */
|
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case GT_ECC_ERRDATALO:
|
| 328 |
case GT_ECC_ERRDATAHI:
|
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case GT_ECC_MEM:
|
| 330 |
case GT_ECC_CALC:
|
| 331 |
case GT_ECC_ERRADDR:
|
| 332 |
/* Read-only registers, do nothing */
|
| 333 |
break;
|
| 334 |
|
| 335 |
/* PCI Internal */
|
| 336 |
case GT_PCI0_CMD:
|
| 337 |
case GT_PCI1_CMD:
|
| 338 |
s->regs[saddr] = val & 0x0401fc0f;
|
| 339 |
break;
|
| 340 |
case GT_PCI0_CFGADDR:
|
| 341 |
s->pci->config_reg = val & 0x80fffffc;
|
| 342 |
break;
|
| 343 |
case GT_PCI0_CFGDATA:
|
| 344 |
pci_host_data_writel(s->pci, 0, val);
|
| 345 |
break;
|
| 346 |
|
| 347 |
/* SDRAM Parameters */
|
| 348 |
case GT_SDRAM_B0:
|
| 349 |
case GT_SDRAM_B1:
|
| 350 |
case GT_SDRAM_B2:
|
| 351 |
case GT_SDRAM_B3:
|
| 352 |
/* We don't simulate electrical parameters of the SDRAM.
|
| 353 |
Accept, but ignore the values. */
|
| 354 |
s->regs[saddr] = val; |
| 355 |
break;
|
| 356 |
|
| 357 |
default:
|
| 358 |
#if 0
|
| 359 |
printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
|
| 360 |
#endif
|
| 361 |
break;
|
| 362 |
} |
| 363 |
} |
| 364 |
|
| 365 |
static uint32_t gt64120_readl (void *opaque, |
| 366 |
target_phys_addr_t addr) |
| 367 |
{
|
| 368 |
GT64120State *s = opaque; |
| 369 |
uint32_t val; |
| 370 |
uint32_t saddr; |
| 371 |
|
| 372 |
val = 0;
|
| 373 |
saddr = (addr & 0xfff) >> 2; |
| 374 |
|
| 375 |
switch (saddr) {
|
| 376 |
|
| 377 |
/* CPU Configuration */
|
| 378 |
case GT_MULTI:
|
| 379 |
/* Only one GT64xxx is present on the CPU bus, return
|
| 380 |
the initial value */
|
| 381 |
val = s->regs[saddr]; |
| 382 |
break;
|
| 383 |
|
| 384 |
/* CPU Error Report */
|
| 385 |
case GT_CPUERR_ADDRLO:
|
| 386 |
case GT_CPUERR_ADDRHI:
|
| 387 |
case GT_CPUERR_DATALO:
|
| 388 |
case GT_CPUERR_DATAHI:
|
| 389 |
case GT_CPUERR_PARITY:
|
| 390 |
/* Emulated memory has no error, always return the initial
|
| 391 |
values */
|
| 392 |
val = s->regs[saddr]; |
| 393 |
break;
|
| 394 |
|
| 395 |
/* CPU Sync Barrier */
|
| 396 |
case GT_PCI0SYNC:
|
| 397 |
case GT_PCI1SYNC:
|
| 398 |
/* Reading those register should empty all FIFO on the PCI
|
| 399 |
bus, which are not emulated. The return value should be
|
| 400 |
a random value that should be ignored. */
|
| 401 |
val = 0xc000ffee;
|
| 402 |
break;
|
| 403 |
|
| 404 |
/* ECC */
|
| 405 |
case GT_ECC_ERRDATALO:
|
| 406 |
case GT_ECC_ERRDATAHI:
|
| 407 |
case GT_ECC_MEM:
|
| 408 |
case GT_ECC_CALC:
|
| 409 |
case GT_ECC_ERRADDR:
|
| 410 |
/* Emulated memory has no error, always return the initial
|
| 411 |
values */
|
| 412 |
val = s->regs[saddr]; |
| 413 |
break;
|
| 414 |
|
| 415 |
case GT_CPU:
|
| 416 |
case GT_PCI0IOLD:
|
| 417 |
case GT_PCI0M0LD:
|
| 418 |
case GT_PCI0M1LD:
|
| 419 |
case GT_PCI1IOLD:
|
| 420 |
case GT_PCI1M0LD:
|
| 421 |
case GT_PCI1M1LD:
|
| 422 |
case GT_PCI0IOHD:
|
| 423 |
case GT_PCI0M0HD:
|
| 424 |
case GT_PCI0M1HD:
|
| 425 |
case GT_PCI1IOHD:
|
| 426 |
case GT_PCI1M0HD:
|
| 427 |
case GT_PCI1M1HD:
|
| 428 |
case GT_PCI0_CMD:
|
| 429 |
case GT_PCI1_CMD:
|
| 430 |
case GT_PCI0IOREMAP:
|
| 431 |
case GT_PCI0M0REMAP:
|
| 432 |
case GT_PCI0M1REMAP:
|
| 433 |
case GT_PCI1IOREMAP:
|
| 434 |
case GT_PCI1M0REMAP:
|
| 435 |
case GT_PCI1M1REMAP:
|
| 436 |
val = s->regs[saddr]; |
| 437 |
break;
|
| 438 |
case GT_PCI0_IACK:
|
| 439 |
/* Read the IRQ number */
|
| 440 |
val = pic_read_irq(isa_pic); |
| 441 |
break;
|
| 442 |
|
| 443 |
/* SDRAM Parameters */
|
| 444 |
case GT_SDRAM_B0:
|
| 445 |
case GT_SDRAM_B1:
|
| 446 |
case GT_SDRAM_B2:
|
| 447 |
case GT_SDRAM_B3:
|
| 448 |
/* We don't simulate electrical parameters of the SDRAM.
|
| 449 |
Just return the last written value. */
|
| 450 |
val = s->regs[saddr]; |
| 451 |
break;
|
| 452 |
|
| 453 |
/* PCI Internal */
|
| 454 |
case GT_PCI0_CFGADDR:
|
| 455 |
val = s->pci->config_reg; |
| 456 |
break;
|
| 457 |
case GT_PCI0_CFGDATA:
|
| 458 |
val = pci_host_data_readl(s->pci, 0);
|
| 459 |
break;
|
| 460 |
|
| 461 |
default:
|
| 462 |
val = s->regs[saddr]; |
| 463 |
#if 0
|
| 464 |
printf ("gt64120_readl: Bad register offset 0x%x\n", (int)addr);
|
| 465 |
#endif
|
| 466 |
break;
|
| 467 |
} |
| 468 |
|
| 469 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 470 |
return bswap32(val);
|
| 471 |
#else
|
| 472 |
return val;
|
| 473 |
#endif
|
| 474 |
} |
| 475 |
|
| 476 |
static CPUWriteMemoryFunc *gt64120_write[] = {
|
| 477 |
>64120_writel, |
| 478 |
>64120_writel, |
| 479 |
>64120_writel, |
| 480 |
}; |
| 481 |
|
| 482 |
static CPUReadMemoryFunc *gt64120_read[] = {
|
| 483 |
>64120_readl, |
| 484 |
>64120_readl, |
| 485 |
>64120_readl, |
| 486 |
}; |
| 487 |
|
| 488 |
static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num) |
| 489 |
{
|
| 490 |
int slot;
|
| 491 |
|
| 492 |
slot = (pci_dev->devfn >> 3);
|
| 493 |
|
| 494 |
switch (slot) {
|
| 495 |
/* PIIX4 USB */
|
| 496 |
case 10: |
| 497 |
return 3; |
| 498 |
/* AMD 79C973 Ethernet */
|
| 499 |
case 11: |
| 500 |
return 0; |
| 501 |
/* Crystal 4281 Sound */
|
| 502 |
case 12: |
| 503 |
return 0; |
| 504 |
/* PCI slot 1 to 4 */
|
| 505 |
case 18 ... 21: |
| 506 |
return ((slot - 18) + irq_num) & 0x03; |
| 507 |
/* Unknown device, don't do any translation */
|
| 508 |
default:
|
| 509 |
return irq_num;
|
| 510 |
} |
| 511 |
} |
| 512 |
|
| 513 |
extern PCIDevice *piix4_dev;
|
| 514 |
static int pci_irq_levels[4]; |
| 515 |
|
| 516 |
static void pci_gt64120_set_irq(void *pic, int irq_num, int level) |
| 517 |
{
|
| 518 |
int i, pic_irq, pic_level;
|
| 519 |
|
| 520 |
pci_irq_levels[irq_num] = level; |
| 521 |
|
| 522 |
/* now we change the pic irq level according to the piix irq mappings */
|
| 523 |
/* XXX: optimize */
|
| 524 |
pic_irq = piix4_dev->config[0x60 + irq_num];
|
| 525 |
if (pic_irq < 16) { |
| 526 |
/* The pic level is the logical OR of all the PCI irqs mapped
|
| 527 |
to it */
|
| 528 |
pic_level = 0;
|
| 529 |
for (i = 0; i < 4; i++) { |
| 530 |
if (pic_irq == piix4_dev->config[0x60 + i]) |
| 531 |
pic_level |= pci_irq_levels[i]; |
| 532 |
} |
| 533 |
pic_set_irq(pic_irq, pic_level); |
| 534 |
} |
| 535 |
} |
| 536 |
|
| 537 |
|
| 538 |
void gt64120_reset(void *opaque) |
| 539 |
{
|
| 540 |
GT64120State *s = opaque; |
| 541 |
|
| 542 |
/* CPU Configuration */
|
| 543 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 544 |
s->regs[GT_CPU] = 0x00000000;
|
| 545 |
#else
|
| 546 |
s->regs[GT_CPU] = 0x00000800;
|
| 547 |
#endif
|
| 548 |
s->regs[GT_MULTI] = 0x00000000;
|
| 549 |
|
| 550 |
/* CPU Address decode FIXME: not complete*/
|
| 551 |
s->regs[GT_PCI0IOLD] = 0x00000080;
|
| 552 |
s->regs[GT_PCI0IOHD] = 0x0000000f;
|
| 553 |
s->regs[GT_PCI0M0LD] = 0x00000090;
|
| 554 |
s->regs[GT_PCI0M0HD] = 0x0000001f;
|
| 555 |
s->regs[GT_PCI0M1LD] = 0x00000790;
|
| 556 |
s->regs[GT_PCI0M1HD] = 0x0000001f;
|
| 557 |
s->regs[GT_PCI1IOLD] = 0x00000100;
|
| 558 |
s->regs[GT_PCI1IOHD] = 0x0000000f;
|
| 559 |
s->regs[GT_PCI1M0LD] = 0x00000110;
|
| 560 |
s->regs[GT_PCI1M0HD] = 0x0000001f;
|
| 561 |
s->regs[GT_PCI1M1LD] = 0x00000120;
|
| 562 |
s->regs[GT_PCI1M1HD] = 0x0000002f;
|
| 563 |
s->regs[GT_PCI0IOREMAP] = 0x00000080;
|
| 564 |
s->regs[GT_PCI0M0REMAP] = 0x00000090;
|
| 565 |
s->regs[GT_PCI0M1REMAP] = 0x00000790;
|
| 566 |
s->regs[GT_PCI1IOREMAP] = 0x00000100;
|
| 567 |
s->regs[GT_PCI1M0REMAP] = 0x00000110;
|
| 568 |
s->regs[GT_PCI1M1REMAP] = 0x00000120;
|
| 569 |
|
| 570 |
/* CPU Error Report */
|
| 571 |
s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
|
| 572 |
s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
|
| 573 |
s->regs[GT_CPUERR_DATALO] = 0xffffffff;
|
| 574 |
s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
|
| 575 |
s->regs[GT_CPUERR_PARITY] = 0x000000ff;
|
| 576 |
|
| 577 |
/* ECC */
|
| 578 |
s->regs[GT_ECC_ERRDATALO] = 0x00000000;
|
| 579 |
s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
|
| 580 |
s->regs[GT_ECC_MEM] = 0x00000000;
|
| 581 |
s->regs[GT_ECC_CALC] = 0x00000000;
|
| 582 |
s->regs[GT_ECC_ERRADDR] = 0x00000000;
|
| 583 |
|
| 584 |
/* SDRAM Parameters */
|
| 585 |
s->regs[GT_SDRAM_B0] = 0x00000005;
|
| 586 |
s->regs[GT_SDRAM_B1] = 0x00000005;
|
| 587 |
s->regs[GT_SDRAM_B2] = 0x00000005;
|
| 588 |
s->regs[GT_SDRAM_B3] = 0x00000005;
|
| 589 |
|
| 590 |
/* PCI Internal FIXME: not complete*/
|
| 591 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 592 |
s->regs[GT_PCI0_CMD] = 0x00000000;
|
| 593 |
s->regs[GT_PCI1_CMD] = 0x00000000;
|
| 594 |
#else
|
| 595 |
s->regs[GT_PCI0_CMD] = 0x00010001;
|
| 596 |
s->regs[GT_PCI1_CMD] = 0x00010001;
|
| 597 |
#endif
|
| 598 |
s->regs[GT_PCI0_IACK] = 0x00000000;
|
| 599 |
s->regs[GT_PCI1_IACK] = 0x00000000;
|
| 600 |
|
| 601 |
gt64120_pci_mapping(s); |
| 602 |
} |
| 603 |
|
| 604 |
PCIBus *pci_gt64120_init(void *pic)
|
| 605 |
{
|
| 606 |
GT64120State *s; |
| 607 |
PCIDevice *d; |
| 608 |
int gt64120;
|
| 609 |
|
| 610 |
s = qemu_mallocz(sizeof(GT64120State));
|
| 611 |
s->pci = qemu_mallocz(sizeof(GT64120PCIState));
|
| 612 |
gt64120_reset(s); |
| 613 |
|
| 614 |
s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq, |
| 615 |
pic, 144, 4); |
| 616 |
|
| 617 |
gt64120 = cpu_register_io_memory(0, gt64120_read,
|
| 618 |
gt64120_write, s); |
| 619 |
cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120); |
| 620 |
|
| 621 |
d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice), |
| 622 |
0, NULL, NULL); |
| 623 |
|
| 624 |
d->config[0x00] = 0xab; // vendor_id |
| 625 |
d->config[0x01] = 0x11; |
| 626 |
d->config[0x02] = 0x46; // device_id |
| 627 |
d->config[0x03] = 0x20; |
| 628 |
d->config[0x04] = 0x06; |
| 629 |
d->config[0x05] = 0x00; |
| 630 |
d->config[0x06] = 0x80; |
| 631 |
d->config[0x07] = 0xa2; |
| 632 |
d->config[0x08] = 0x10; |
| 633 |
d->config[0x09] = 0x00; |
| 634 |
d->config[0x0A] = 0x80; |
| 635 |
d->config[0x0B] = 0x05; |
| 636 |
d->config[0x0C] = 0x08; |
| 637 |
d->config[0x0D] = 0x40; |
| 638 |
d->config[0x0E] = 0x00; |
| 639 |
d->config[0x0F] = 0x00; |
| 640 |
d->config[0x17] = 0x08; |
| 641 |
d->config[0x1B] = 0x1c; |
| 642 |
d->config[0x1F] = 0x1f; |
| 643 |
d->config[0x23] = 0x14; |
| 644 |
d->config[0x27] = 0x14; |
| 645 |
d->config[0x3D] = 0x01; |
| 646 |
|
| 647 |
return s->pci->bus;
|
| 648 |
} |