Revision eae6bcbf
| b/hw/piix_pci.c | ||
|---|---|---|
| 272 | 272 |
memset(pci_irq_levels, 0, sizeof(pci_irq_levels)); |
| 273 | 273 |
} |
| 274 | 274 |
|
| 275 |
static void piix4_reset(PCIDevice *d)
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|
| 275 |
static void piix4_reset(void *opaque)
|
|
| 276 | 276 |
{
|
| 277 |
PCIDevice *d = opaque; |
|
| 277 | 278 |
uint8_t *pci_conf = d->config; |
| 278 | 279 |
|
| 279 | 280 |
pci_conf[0x04] = 0x07; // master, memory and I/O |
| ... | ... | |
| 307 | 308 |
pci_conf[0xab] = 0x00; |
| 308 | 309 |
pci_conf[0xac] = 0x00; |
| 309 | 310 |
pci_conf[0xae] = 0x00; |
| 311 |
|
|
| 312 |
memset(pci_irq_levels, 0, sizeof(pci_irq_levels)); |
|
| 310 | 313 |
} |
| 311 | 314 |
|
| 312 | 315 |
static void piix_save(QEMUFile* f, void *opaque) |
| ... | ... | |
| 366 | 369 |
|
| 367 | 370 |
|
| 368 | 371 |
piix4_reset(d); |
| 372 |
qemu_register_reset(piix4_reset, 0, d); |
|
| 369 | 373 |
return d->devfn; |
| 370 | 374 |
} |
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