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/*
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* QEMU generic PPC hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#include "m48t59.h" |
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extern FILE *logfile;
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extern int loglevel; |
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/*****************************************************************************/
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/* PowerPC internal fake IRQ controller
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* used to manage multiple sources hardware events
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*/
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/* XXX: should be protected */
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void ppc_set_irq (void *opaque, int n_IRQ, int level) |
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{ |
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CPUState *env; |
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env = opaque; |
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if (level) {
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env->pending_interrupts |= 1 << n_IRQ;
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} else {
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env->pending_interrupts &= ~(1 << n_IRQ);
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if (env->pending_interrupts == 0) |
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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#if 0
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printf("%s: %p n_IRQ %d level %d => pending %08x req %08x\n", __func__,
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env, n_IRQ, level, env->pending_interrupts, env->interrupt_request);
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#endif
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} |
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/* External IRQ callback from OpenPIC IRQ controller */
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void ppc_openpic_irq (void *opaque, int n_IRQ, int level) |
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{ |
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switch (n_IRQ) {
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case OPENPIC_EVT_INT:
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n_IRQ = PPC_INTERRUPT_EXT; |
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break;
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case OPENPIC_EVT_CINT:
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/* On PowerPC BookE, critical input use vector 0 */
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n_IRQ = PPC_INTERRUPT_RESET; |
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break;
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case OPENPIC_EVT_MCK:
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n_IRQ = PPC_INTERRUPT_MCK; |
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break;
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case OPENPIC_EVT_DEBUG:
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n_IRQ = PPC_INTERRUPT_DEBUG; |
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break;
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case OPENPIC_EVT_RESET:
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qemu_system_reset_request(); |
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return;
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} |
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ppc_set_irq(opaque, n_IRQ, level); |
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} |
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/*****************************************************************************/
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/* PPC time base and decrementer emulation */
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//#define DEBUG_TB
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struct ppc_tb_t {
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/* Time base management */
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int64_t tb_offset; /* Compensation */
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uint32_t tb_freq; /* TB frequency */
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/* Decrementer management */
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uint64_t decr_next; /* Tick for next decr interrupt */
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struct QEMUTimer *decr_timer;
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void *opaque;
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}; |
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static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env) |
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{ |
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/* TB time in tb periods */
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return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
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tb_env->tb_freq, ticks_per_sec); |
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} |
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uint32_t cpu_ppc_load_tbl (CPUState *env) |
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{ |
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ppc_tb_t *tb_env = env->tb_env; |
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uint64_t tb; |
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tb = cpu_ppc_get_tb(tb_env); |
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#ifdef DEBUG_TB
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{ |
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static int last_time; |
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int now;
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now = time(NULL);
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if (last_time != now) {
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last_time = now; |
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printf("%s: tb=0x%016lx %d %08lx\n",
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__func__, tb, now, tb_env->tb_offset); |
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} |
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} |
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#endif
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return tb & 0xFFFFFFFF; |
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} |
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uint32_t cpu_ppc_load_tbu (CPUState *env) |
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{ |
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ppc_tb_t *tb_env = env->tb_env; |
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uint64_t tb; |
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tb = cpu_ppc_get_tb(tb_env); |
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#ifdef DEBUG_TB
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printf("%s: tb=0x%016lx\n", __func__, tb);
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#endif
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return tb >> 32; |
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} |
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static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value) |
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{ |
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tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq) |
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- qemu_get_clock(vm_clock); |
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#ifdef DEBUG_TB
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printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
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#endif
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} |
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void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
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{ |
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ppc_tb_t *tb_env = env->tb_env; |
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cpu_ppc_store_tb(tb_env, |
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((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
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} |
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void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
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{ |
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ppc_tb_t *tb_env = env->tb_env; |
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cpu_ppc_store_tb(tb_env, |
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((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
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} |
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uint32_t cpu_ppc_load_decr (CPUState *env) |
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{ |
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ppc_tb_t *tb_env = env->tb_env; |
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uint32_t decr; |
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int64_t diff; |
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diff = tb_env->decr_next - qemu_get_clock(vm_clock); |
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if (diff >= 0) |
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decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec); |
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else
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decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec); |
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#if defined(DEBUG_TB)
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printf("%s: 0x%08x\n", __func__, decr);
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#endif
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return decr;
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} |
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/* When decrementer expires,
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* all we need to do is generate or queue a CPU exception
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*/
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static inline void cpu_ppc_decr_excp (CPUState *env) |
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{ |
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/* Raise it */
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#ifdef DEBUG_TB
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printf("raise decrementer exception\n");
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
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} |
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static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
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uint32_t value, int is_excp)
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{ |
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ppc_tb_t *tb_env = env->tb_env; |
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uint64_t now, next; |
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#ifdef DEBUG_TB
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printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
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#endif
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now = qemu_get_clock(vm_clock); |
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next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq); |
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if (is_excp)
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next += tb_env->decr_next - now; |
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if (next == now)
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next++; |
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tb_env->decr_next = next; |
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/* Adjust timer */
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qemu_mod_timer(tb_env->decr_timer, next); |
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/* If we set a negative value and the decrementer was positive,
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* raise an exception.
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*/
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if ((value & 0x80000000) && !(decr & 0x80000000)) |
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cpu_ppc_decr_excp(env); |
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} |
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void cpu_ppc_store_decr (CPUState *env, uint32_t value)
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{ |
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_cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
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} |
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static void cpu_ppc_decr_cb (void *opaque) |
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{ |
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_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
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} |
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/* Set up (once) timebase frequency (in Hz) */
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ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
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{ |
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ppc_tb_t *tb_env; |
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tb_env = qemu_mallocz(sizeof(ppc_tb_t));
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if (tb_env == NULL) |
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return NULL; |
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env->tb_env = tb_env; |
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if (tb_env->tb_freq == 0 || 1) { |
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tb_env->tb_freq = freq; |
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/* Create new timer */
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tb_env->decr_timer = |
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qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); |
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/* There is a bug in Linux 2.4 kernels:
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* if a decrementer exception is pending when it enables msr_ee,
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* it's not ready to handle it...
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*/
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_cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
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} |
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return tb_env;
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} |
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/* Specific helpers for POWER & PowerPC 601 RTC */
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ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env) |
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{ |
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return cpu_ppc_tb_init(env, 7812500); |
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} |
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void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
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__attribute__ (( alias ("cpu_ppc_store_tbu") ));
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uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
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__attribute__ (( alias ("cpu_ppc_load_tbu") ));
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void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
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{ |
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cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
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} |
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uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
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{ |
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return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
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} |
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/*****************************************************************************/
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/* Embedded PowerPC timers */
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/* PIT, FIT & WDT */
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typedef struct ppcemb_timer_t ppcemb_timer_t; |
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struct ppcemb_timer_t {
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uint64_t pit_reload; /* PIT auto-reload value */
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uint64_t fit_next; /* Tick for next FIT interrupt */
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struct QEMUTimer *fit_timer;
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uint64_t wdt_next; /* Tick for next WDT interrupt */
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struct QEMUTimer *wdt_timer;
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}; |
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/* Fixed interval timer */
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static void cpu_4xx_fit_cb (void *opaque) |
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{ |
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CPUState *env; |
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ppc_tb_t *tb_env; |
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ppcemb_timer_t *ppcemb_timer; |
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uint64_t now, next; |
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env = opaque; |
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tb_env = env->tb_env; |
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ppcemb_timer = tb_env->opaque; |
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now = qemu_get_clock(vm_clock); |
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switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
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case 0: |
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next = 1 << 9; |
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break;
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case 1: |
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next = 1 << 13; |
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break;
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case 2: |
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next = 1 << 17; |
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break;
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case 3: |
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next = 1 << 21; |
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break;
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default:
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/* Cannot occur, but makes gcc happy */
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return;
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} |
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next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
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if (next == now)
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next++; |
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qemu_mod_timer(ppcemb_timer->fit_timer, next); |
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tb_env->decr_next = next; |
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env->spr[SPR_40x_TSR] |= 1 << 26; |
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if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
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ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
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if (loglevel) {
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fprintf(logfile, "%s: ir %d TCR %08x TSR %08x\n", __func__,
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(env->spr[SPR_40x_TCR] >> 23) & 0x1, |
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
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} |
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} |
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/* Programmable interval timer */
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static void cpu_4xx_pit_cb (void *opaque) |
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{ |
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CPUState *env; |
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ppc_tb_t *tb_env; |
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ppcemb_timer_t *ppcemb_timer; |
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uint64_t now, next; |
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env = opaque; |
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tb_env = env->tb_env; |
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ppcemb_timer = tb_env->opaque; |
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now = qemu_get_clock(vm_clock); |
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if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) { |
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/* Auto reload */
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next = now + muldiv64(ppcemb_timer->pit_reload, |
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ticks_per_sec, tb_env->tb_freq); |
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if (next == now)
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next++; |
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qemu_mod_timer(tb_env->decr_timer, next); |
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tb_env->decr_next = next; |
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} |
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env->spr[SPR_40x_TSR] |= 1 << 27; |
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if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
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ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
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if (loglevel) {
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fprintf(logfile, "%s: ar %d ir %d TCR %08x TSR %08x %08lx\n", __func__,
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(env->spr[SPR_40x_TCR] >> 22) & 0x1, |
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(env->spr[SPR_40x_TCR] >> 26) & 0x1, |
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
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ppcemb_timer->pit_reload); |
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} |
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} |
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|
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/* Watchdog timer */
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static void cpu_4xx_wdt_cb (void *opaque) |
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{ |
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CPUState *env; |
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ppc_tb_t *tb_env; |
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ppcemb_timer_t *ppcemb_timer; |
366 |
uint64_t now, next; |
367 |
|
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env = opaque; |
369 |
tb_env = env->tb_env; |
370 |
ppcemb_timer = tb_env->opaque; |
371 |
now = qemu_get_clock(vm_clock); |
372 |
switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
373 |
case 0: |
374 |
next = 1 << 17; |
375 |
break;
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376 |
case 1: |
377 |
next = 1 << 21; |
378 |
break;
|
379 |
case 2: |
380 |
next = 1 << 25; |
381 |
break;
|
382 |
case 3: |
383 |
next = 1 << 29; |
384 |
break;
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385 |
default:
|
386 |
/* Cannot occur, but makes gcc happy */
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return;
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388 |
} |
389 |
next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
390 |
if (next == now)
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next++; |
392 |
if (loglevel) {
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fprintf(logfile, "%s: TCR %08x TSR %08x\n", __func__,
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
395 |
} |
396 |
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
397 |
case 0x0: |
398 |
case 0x1: |
399 |
qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
400 |
ppcemb_timer->wdt_next = next; |
401 |
env->spr[SPR_40x_TSR] |= 1 << 31; |
402 |
break;
|
403 |
case 0x2: |
404 |
qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
405 |
ppcemb_timer->wdt_next = next; |
406 |
env->spr[SPR_40x_TSR] |= 1 << 30; |
407 |
if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) |
408 |
ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
|
409 |
break;
|
410 |
case 0x3: |
411 |
env->spr[SPR_40x_TSR] &= ~0x30000000;
|
412 |
env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
|
413 |
switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
414 |
case 0x0: |
415 |
/* No reset */
|
416 |
break;
|
417 |
case 0x1: /* Core reset */ |
418 |
case 0x2: /* Chip reset */ |
419 |
case 0x3: /* System reset */ |
420 |
qemu_system_reset_request(); |
421 |
return;
|
422 |
} |
423 |
} |
424 |
} |
425 |
|
426 |
void store_40x_pit (CPUState *env, target_ulong val)
|
427 |
{ |
428 |
ppc_tb_t *tb_env; |
429 |
ppcemb_timer_t *ppcemb_timer; |
430 |
uint64_t now, next; |
431 |
|
432 |
tb_env = env->tb_env; |
433 |
ppcemb_timer = tb_env->opaque; |
434 |
if (loglevel)
|
435 |
fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
|
436 |
ppcemb_timer->pit_reload = val; |
437 |
if (val == 0) { |
438 |
/* Stop PIT */
|
439 |
if (loglevel)
|
440 |
fprintf(logfile, "%s: stop PIT\n", __func__);
|
441 |
qemu_del_timer(tb_env->decr_timer); |
442 |
} else {
|
443 |
if (loglevel)
|
444 |
fprintf(logfile, "%s: start PIT 0x%08x\n", __func__, val);
|
445 |
now = qemu_get_clock(vm_clock); |
446 |
next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq); |
447 |
if (next == now)
|
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next++; |
449 |
qemu_mod_timer(tb_env->decr_timer, next); |
450 |
tb_env->decr_next = next; |
451 |
} |
452 |
} |
453 |
|
454 |
target_ulong load_40x_pit (CPUState *env) |
455 |
{ |
456 |
return cpu_ppc_load_decr(env);
|
457 |
} |
458 |
|
459 |
void store_booke_tsr (CPUState *env, target_ulong val)
|
460 |
{ |
461 |
env->spr[SPR_40x_TSR] = val & 0xFC000000;
|
462 |
} |
463 |
|
464 |
void store_booke_tcr (CPUState *env, target_ulong val)
|
465 |
{ |
466 |
/* We don't update timers now. Maybe we should... */
|
467 |
env->spr[SPR_40x_TCR] = val & 0xFF800000;
|
468 |
} |
469 |
|
470 |
void ppc_emb_timers_init (CPUState *env)
|
471 |
{ |
472 |
ppc_tb_t *tb_env; |
473 |
ppcemb_timer_t *ppcemb_timer; |
474 |
|
475 |
tb_env = env->tb_env; |
476 |
ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
|
477 |
tb_env->opaque = ppcemb_timer; |
478 |
if (loglevel)
|
479 |
fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
|
480 |
if (ppcemb_timer != NULL) { |
481 |
/* We use decr timer for PIT */
|
482 |
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); |
483 |
ppcemb_timer->fit_timer = |
484 |
qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); |
485 |
ppcemb_timer->wdt_timer = |
486 |
qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); |
487 |
} |
488 |
} |
489 |
|
490 |
#if 0
|
491 |
/*****************************************************************************/
|
492 |
/* Handle system reset (for now, just stop emulation) */
|
493 |
void cpu_ppc_reset (CPUState *env)
|
494 |
{
|
495 |
printf("Reset asked... Stop emulation\n");
|
496 |
abort();
|
497 |
}
|
498 |
#endif
|
499 |
|
500 |
/*****************************************************************************/
|
501 |
/* Debug port */
|
502 |
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
503 |
{ |
504 |
addr &= 0xF;
|
505 |
switch (addr) {
|
506 |
case 0: |
507 |
printf("%c", val);
|
508 |
break;
|
509 |
case 1: |
510 |
printf("\n");
|
511 |
fflush(stdout); |
512 |
break;
|
513 |
case 2: |
514 |
printf("Set loglevel to %04x\n", val);
|
515 |
cpu_set_log(val | 0x100);
|
516 |
break;
|
517 |
} |
518 |
} |
519 |
|
520 |
/*****************************************************************************/
|
521 |
/* NVRAM helpers */
|
522 |
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
|
523 |
{ |
524 |
m48t59_write(nvram, addr, value); |
525 |
} |
526 |
|
527 |
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) |
528 |
{ |
529 |
return m48t59_read(nvram, addr);
|
530 |
} |
531 |
|
532 |
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
|
533 |
{ |
534 |
m48t59_write(nvram, addr, value >> 8);
|
535 |
m48t59_write(nvram, addr + 1, value & 0xFF); |
536 |
} |
537 |
|
538 |
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) |
539 |
{ |
540 |
uint16_t tmp; |
541 |
|
542 |
tmp = m48t59_read(nvram, addr) << 8;
|
543 |
tmp |= m48t59_read(nvram, addr + 1);
|
544 |
return tmp;
|
545 |
} |
546 |
|
547 |
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
|
548 |
{ |
549 |
m48t59_write(nvram, addr, value >> 24);
|
550 |
m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF); |
551 |
m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF); |
552 |
m48t59_write(nvram, addr + 3, value & 0xFF); |
553 |
} |
554 |
|
555 |
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) |
556 |
{ |
557 |
uint32_t tmp; |
558 |
|
559 |
tmp = m48t59_read(nvram, addr) << 24;
|
560 |
tmp |= m48t59_read(nvram, addr + 1) << 16; |
561 |
tmp |= m48t59_read(nvram, addr + 2) << 8; |
562 |
tmp |= m48t59_read(nvram, addr + 3);
|
563 |
|
564 |
return tmp;
|
565 |
} |
566 |
|
567 |
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
568 |
const unsigned char *str, uint32_t max) |
569 |
{ |
570 |
int i;
|
571 |
|
572 |
for (i = 0; i < max && str[i] != '\0'; i++) { |
573 |
m48t59_write(nvram, addr + i, str[i]); |
574 |
} |
575 |
m48t59_write(nvram, addr + max - 1, '\0'); |
576 |
} |
577 |
|
578 |
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) |
579 |
{ |
580 |
int i;
|
581 |
|
582 |
memset(dst, 0, max);
|
583 |
for (i = 0; i < max; i++) { |
584 |
dst[i] = NVRAM_get_byte(nvram, addr + i); |
585 |
if (dst[i] == '\0') |
586 |
break;
|
587 |
} |
588 |
|
589 |
return i;
|
590 |
} |
591 |
|
592 |
static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
593 |
{ |
594 |
uint16_t tmp; |
595 |
uint16_t pd, pd1, pd2; |
596 |
|
597 |
tmp = prev >> 8;
|
598 |
pd = prev ^ value; |
599 |
pd1 = pd & 0x000F;
|
600 |
pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
601 |
tmp ^= (pd1 << 3) | (pd1 << 8); |
602 |
tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
603 |
|
604 |
return tmp;
|
605 |
} |
606 |
|
607 |
uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) |
608 |
{ |
609 |
uint32_t i; |
610 |
uint16_t crc = 0xFFFF;
|
611 |
int odd;
|
612 |
|
613 |
odd = count & 1;
|
614 |
count &= ~1;
|
615 |
for (i = 0; i != count; i++) { |
616 |
crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
617 |
} |
618 |
if (odd) {
|
619 |
crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
620 |
} |
621 |
|
622 |
return crc;
|
623 |
} |
624 |
|
625 |
#define CMDLINE_ADDR 0x017ff000 |
626 |
|
627 |
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
628 |
const unsigned char *arch, |
629 |
uint32_t RAM_size, int boot_device,
|
630 |
uint32_t kernel_image, uint32_t kernel_size, |
631 |
const char *cmdline, |
632 |
uint32_t initrd_image, uint32_t initrd_size, |
633 |
uint32_t NVRAM_image, |
634 |
int width, int height, int depth) |
635 |
{ |
636 |
uint16_t crc; |
637 |
|
638 |
/* Set parameters for Open Hack'Ware BIOS */
|
639 |
NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
640 |
NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
641 |
NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
642 |
NVRAM_set_string(nvram, 0x20, arch, 16); |
643 |
NVRAM_set_lword(nvram, 0x30, RAM_size);
|
644 |
NVRAM_set_byte(nvram, 0x34, boot_device);
|
645 |
NVRAM_set_lword(nvram, 0x38, kernel_image);
|
646 |
NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
647 |
if (cmdline) {
|
648 |
/* XXX: put the cmdline in NVRAM too ? */
|
649 |
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
650 |
NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
651 |
NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
652 |
} else {
|
653 |
NVRAM_set_lword(nvram, 0x40, 0); |
654 |
NVRAM_set_lword(nvram, 0x44, 0); |
655 |
} |
656 |
NVRAM_set_lword(nvram, 0x48, initrd_image);
|
657 |
NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
658 |
NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
659 |
|
660 |
NVRAM_set_word(nvram, 0x54, width);
|
661 |
NVRAM_set_word(nvram, 0x56, height);
|
662 |
NVRAM_set_word(nvram, 0x58, depth);
|
663 |
crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
664 |
NVRAM_set_word(nvram, 0xFC, crc);
|
665 |
|
666 |
return 0; |
667 |
} |