/ - Diff - qemu - Greek Research and Technology Network's projects

Revision eb23b556

     #define UC32_EXCP_TRAP          (ASR_MODE_TRAP)
     /* Return the current ASR value.  */
     target_ulong cpu_asr_read(CPUState *env1);
     target_ulong cpu_asr_read(CPUUniCore32State *env1);
     /* Set the ASR.  Note that some bits of mask must be all-set or all-clear.  */
     void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask);
     void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask);
     /* UniCore-F64 system registers.  */
     #define UC32_UCF64_FPSCR                (31)
-...
     #define cpu_signal_handler              uc32_cpu_signal_handler
     #define cpu_handle_mmu_fault            uc32_cpu_handle_mmu_fault
     CPUState *uc32_cpu_init(const char *cpu_model);
     int uc32_cpu_exec(CPUState *s);
     CPUUniCore32State *uc32_cpu_init(const char *cpu_model);
     int uc32_cpu_exec(CPUUniCore32State *s);
     int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
     int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
     int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
                                   int mmu_idx);
     #define CPU_SAVE_VERSION 2
-...
     #define MMU_MODE0_SUFFIX _kernel
     #define MMU_MODE1_SUFFIX _user
     #define MMU_USER_IDX 1
     static inline int cpu_mmu_index(CPUState *env)
     static inline int cpu_mmu_index(CPUUniCore32State *env)
+    {
         return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
+    }
     static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
     static inline void cpu_clone_regs(CPUUniCore32State *env, target_ulong newsp)
+    {
         if (newsp) {
             env->regs[29] = newsp;
-...
         env->regs[0] = 0;
+    }
     static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
     static inline void cpu_set_tls(CPUUniCore32State *env, target_ulong newtls)
+    {
         env->regs[16] = newtls;
+    }
-...
     #include "cpu-all.h"
     #include "exec-all.h"
     static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
     static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlock *tb)
+    {
         env->regs[31] = tb->pc;
+    }
     static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
     static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
                                             target_ulong *cs_base, int *flags)
+    {
         *pc = env->regs[31];
-...
+    }
     void uc32_translate_init(void);
     void do_interrupt(CPUState *);
     void do_interrupt(CPUUniCore32State *);
     void switch_mode(CPUUniCore32State *, int);
     static inline bool cpu_has_work(CPUState *env)
     static inline bool cpu_has_work(CPUUniCore32State *env)
+    {
         return env->interrupt_request &
             (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);

b/target-unicore32/helper.c
11	11	#include "helper.h"
12	12	#include "host-utils.h"
13	13
14		static inline void set_feature(CPUState *env, int feature)
	14	static inline void set_feature(CPUUniCore32State *env, int feature)
15	15	{
16	16	env->features \|= feature;
17	17	}
...	...
43	43	return id;
44	44	}
45	45
46		CPUState uc32_cpu_init(const char cpu_model)
	46	CPUUniCore32State uc32_cpu_init(const char cpu_model)
47	47	{
48		CPUState *env;
	48	CPUUniCore32State *env;
49	49	uint32_t id;
50	50	static int inited = 1;
51	51
52		env = g_malloc0(sizeof(CPUState));
	52	env = g_malloc0(sizeof(CPUUniCore32State));
53	53	cpu_exec_init(env);
54	54
55	55	id = uc32_cpu_find_by_name(cpu_model);
...	...
94	94	return clz32(x);
95	95	}
96	96
97		void do_interrupt(CPUState *env)
	97	void do_interrupt(CPUUniCore32State *env)
98	98	{
99	99	env->exception_index = -1;
100	100	}
101	101
102		int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
	102	int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
103	103	int mmu_idx)
104	104	{
105	105	env->exception_index = UC32_EXCP_TRAP;
...	...
108	108	}
109	109
110	110	/* These should probably raise undefined insn exceptions. */
111		void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
	111	void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
112	112	{
113	113	int op1 = (insn >> 8) & 0xf;
114	114	cpu_abort(env, "cp%i insn %08x\n", op1, insn);
115	115	return;
116	116	}
117	117
118		uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
	118	uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t insn)
119	119	{
120	120	int op1 = (insn >> 8) & 0xf;
121	121	cpu_abort(env, "cp%i insn %08x\n", op1, insn);
122	122	return 0;
123	123	}
124	124
125		void HELPER(set_cp0)(CPUState *env, uint32_t insn, uint32_t val)
	125	void HELPER(set_cp0)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
126	126	{
127	127	cpu_abort(env, "cp0 insn %08x\n", insn);
128	128	}
129	129
130		uint32_t HELPER(get_cp0)(CPUState *env, uint32_t insn)
	130	uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn)
131	131	{
132	132	cpu_abort(env, "cp0 insn %08x\n", insn);
133	133	return 0;
134	134	}
135	135
136		void switch_mode(CPUState *env, int mode)
	136	void switch_mode(CPUUniCore32State *env, int mode)
137	137	{
138	138	if (mode != ASR_MODE_USER) {
139	139	cpu_abort(env, "Tried to switch out of user mode\n");
140	140	}
141	141	}
142	142
143		void HELPER(set_r29_banked)(CPUState *env, uint32_t mode, uint32_t val)
	143	void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val)
144	144	{
145	145	cpu_abort(env, "banked r29 write\n");
146	146	}
147	147
148		uint32_t HELPER(get_r29_banked)(CPUState *env, uint32_t mode)
	148	uint32_t HELPER(get_r29_banked)(CPUUniCore32State *env, uint32_t mode)
149	149	{
150	150	cpu_abort(env, "banked r29 read\n");
151	151	return 0;
...	...
178	178	return target_bits;
179	179	}
180	180
181		uint32_t HELPER(ucf64_get_fpscr)(CPUState *env)
	181	uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
182	182	{
183	183	int i;
184	184	uint32_t fpscr;
...	...
212	212	return host_bits;
213	213	}
214	214
215		void HELPER(ucf64_set_fpscr)(CPUState *env, uint32_t val)
	215	void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
216	216	{
217	217	int i;
218	218	uint32_t changed;
...	...
246	246	set_float_exception_flags(i, &env->ucf64.fp_status);
247	247	}
248	248
249		float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUState *env)
	249	float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
250	250	{
251	251	return float32_add(a, b, &env->ucf64.fp_status);
252	252	}
253	253
254		float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUState *env)
	254	float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
255	255	{
256	256	return float64_add(a, b, &env->ucf64.fp_status);
257	257	}
258	258
259		float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUState *env)
	259	float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
260	260	{
261	261	return float32_sub(a, b, &env->ucf64.fp_status);
262	262	}
263	263
264		float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUState *env)
	264	float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
265	265	{
266	266	return float64_sub(a, b, &env->ucf64.fp_status);
267	267	}
268	268
269		float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUState *env)
	269	float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
270	270	{
271	271	return float32_mul(a, b, &env->ucf64.fp_status);
272	272	}
273	273
274		float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUState *env)
	274	float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
275	275	{
276	276	return float64_mul(a, b, &env->ucf64.fp_status);
277	277	}
278	278
279		float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUState *env)
	279	float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
280	280	{
281	281	return float32_div(a, b, &env->ucf64.fp_status);
282	282	}
283	283
284		float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUState *env)
	284	float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
285	285	{
286	286	return float64_div(a, b, &env->ucf64.fp_status);
287	287	}
...	...
307	307	}
308	308
309	309	/* XXX: check quiet/signaling case */
310		void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUState *env)
	310	void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUUniCore32State *env)
311	311	{
312	312	int flag;
313	313	flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
...	...
355	355	\| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
356	356	}
357	357
358		void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUState *env)
	358	void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUUniCore32State *env)
359	359	{
360	360	int flag;
361	361	flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
...	...
449	449	}
450	450
451	451	/* Integer to float conversion. */
452		float32 HELPER(ucf64_si2sf)(float32 x, CPUState *env)
	452	float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
453	453	{
454	454	return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
455	455	}
456	456
457		float64 HELPER(ucf64_si2df)(float32 x, CPUState *env)
	457	float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
458	458	{
459	459	return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
460	460	}
461	461
462	462	/* Float to integer conversion. */
463		float32 HELPER(ucf64_sf2si)(float32 x, CPUState *env)
	463	float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
464	464	{
465	465	return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
466	466	}
467	467
468		float32 HELPER(ucf64_df2si)(float64 x, CPUState *env)
	468	float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
469	469	{
470	470	return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
471	471	}
472	472
473	473	/* floating point conversion */
474		float64 HELPER(ucf64_sf2df)(float32 x, CPUState *env)
	474	float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
475	475	{
476	476	return float32_to_float64(x, &env->ucf64.fp_status);
477	477	}
478	478
479		float32 HELPER(ucf64_df2sf)(float64 x, CPUState *env)
	479	float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
480	480	{
481	481	return float64_to_float32(x, &env->ucf64.fp_status);
482	482	}

b/target-unicore32/op_helper.c
28	28	(env->CF << 29) \| ((env->VF & 0x80000000) >> 3);
29	29	}
30	30
31		target_ulong cpu_asr_read(CPUState *env1)
	31	target_ulong cpu_asr_read(CPUUniCore32State *env1)
32	32	{
33		CPUState *saved_env;
	33	CPUUniCore32State *saved_env;
34	34	target_ulong ret;
35	35
36	36	saved_env = env;
...	...
61	61	env->uncached_asr = (env->uncached_asr & ~mask) \| (val & mask);
62	62	}
63	63
64		void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask)
	64	void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask)
65	65	{
66		CPUState *saved_env;
	66	CPUUniCore32State *saved_env;
67	67
68	68	saved_env = env;
69	69	env = env1;

b/target-unicore32/translate.c
64	64
65	65	for (i = 0; i < 32; i++) {
66	66	cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
67		offsetof(CPUState, regs[i]), regnames[i]);
	67	offsetof(CPUUniCore32State, regs[i]), regnames[i]);
68	68	}
69	69
70	70	#define GEN_HELPER 2
...	...
94	94	return tmp;
95	95	}
96	96
97		#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
	97	#define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
98	98
99	99	static inline void store_cpu_offset(TCGv var, int offset)
100	100	{
...	...
103	103	}
104	104
105	105	#define store_cpu_field(var, name) \
106		store_cpu_offset(var, offsetof(CPUState, name))
	106	store_cpu_offset(var, offsetof(CPUUniCore32State, name))
107	107
108	108	/* Set a variable to the value of a CPU register. */
109	109	static void load_reg_var(DisasContext *s, TCGv var, int reg)
...	...
223	223	return tmp1;
224	224	}
225	225
226		#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
	226	#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
227	227
228	228	/* Set CF to the top bit of var. */
229	229	static void gen_set_CF_bit31(TCGv var)
...	...
237	237	/* Set N and Z flags from var. */
238	238	static inline void gen_logic_CC(TCGv var)
239	239	{
240		tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
241		tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
	240	tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, NF));
	241	tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, ZF));
242	242	}
243	243
244	244	/* dest = T0 + T1 + CF. */
...	...
634	634	static inline long ucf64_reg_offset(int reg)
635	635	{
636	636	if (reg & 1) {
637		return offsetof(CPUState, ucf64.regs[reg >> 1])
	637	return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
638	638	+ offsetof(CPU_DoubleU, l.upper);
639	639	} else {
640		return offsetof(CPUState, ucf64.regs[reg >> 1])
	640	return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
641	641	+ offsetof(CPU_DoubleU, l.lower);
642	642	}
643	643	}
...	...
646	646	#define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))
647	647
648	648	/* UniCore-F64 single load/store I_offset */
649		static void do_ucf64_ldst_i(CPUState env, DisasContext s, uint32_t insn)
	649	static void do_ucf64_ldst_i(CPUUniCore32State env, DisasContext s, uint32_t insn)
650	650	{
651	651	int offset;
652	652	TCGv tmp;
...	...
692	692	}
693	693
694	694	/* UniCore-F64 load/store multiple words */
695		static void do_ucf64_ldst_m(CPUState env, DisasContext s, uint32_t insn)
	695	static void do_ucf64_ldst_m(CPUUniCore32State env, DisasContext s, uint32_t insn)
696	696	{
697	697	unsigned int i;
698	698	int j, n, freg;
...	...
777	777	}
778	778
779	779	/* UniCore-F64 mrc/mcr */
780		static void do_ucf64_trans(CPUState env, DisasContext s, uint32_t insn)
	780	static void do_ucf64_trans(CPUUniCore32State env, DisasContext s, uint32_t insn)
781	781	{
782	782	TCGv tmp;
783	783
...	...
841	841	}
842	842
843	843	/* UniCore-F64 convert instructions */
844		static void do_ucf64_fcvt(CPUState env, DisasContext s, uint32_t insn)
	844	static void do_ucf64_fcvt(CPUUniCore32State env, DisasContext s, uint32_t insn)
845	845	{
846	846	if (UCOP_UCF64_FMT == 3) {
847	847	ILLEGAL;
...	...
907	907	}
908	908
909	909	/* UniCore-F64 compare instructions */
910		static void do_ucf64_fcmp(CPUState env, DisasContext s, uint32_t insn)
	910	static void do_ucf64_fcmp(CPUUniCore32State env, DisasContext s, uint32_t insn)
911	911	{
912	912	if (UCOP_SET(25)) {
913	913	ILLEGAL;
...	...
985	985	} while (0)
986	986
987	987	/* UniCore-F64 data processing */
988		static void do_ucf64_datap(CPUState env, DisasContext s, uint32_t insn)
	988	static void do_ucf64_datap(CPUUniCore32State env, DisasContext s, uint32_t insn)
989	989	{
990	990	if (UCOP_UCF64_FMT == 3) {
991	991	ILLEGAL;
...	...
1018	1018	}
1019	1019
1020	1020	/* Disassemble an F64 instruction */
1021		static void disas_ucf64_insn(CPUState env, DisasContext s, uint32_t insn)
	1021	static void disas_ucf64_insn(CPUUniCore32State env, DisasContext s, uint32_t insn)
1022	1022	{
1023	1023	if (!UCOP_SET(29)) {
1024	1024	if (UCOP_SET(26)) {
...	...
1123	1123	s->is_jmp = DISAS_UPDATE;
1124	1124	}
1125	1125
1126		static void disas_coproc_insn(CPUState env, DisasContext s, uint32_t insn)
	1126	static void disas_coproc_insn(CPUUniCore32State env, DisasContext s, uint32_t insn)
1127	1127	{
1128	1128	switch (UCOP_CPNUM) {
1129	1129	case 2:
...	...
1168	1168	}
1169	1169
1170	1170	/* data processing instructions */
1171		static void do_datap(CPUState env, DisasContext s, uint32_t insn)
	1171	static void do_datap(CPUUniCore32State env, DisasContext s, uint32_t insn)
1172	1172	{
1173	1173	TCGv tmp;
1174	1174	TCGv tmp2;
...	...
1359	1359	}
1360	1360
1361	1361	/* multiply */
1362		static void do_mult(CPUState env, DisasContext s, uint32_t insn)
	1362	static void do_mult(CPUUniCore32State env, DisasContext s, uint32_t insn)
1363	1363	{
1364	1364	TCGv tmp;
1365	1365	TCGv tmp2;
...	...
1399	1399	}
1400	1400
1401	1401	/* miscellaneous instructions */
1402		static void do_misc(CPUState env, DisasContext s, uint32_t insn)
	1402	static void do_misc(CPUUniCore32State env, DisasContext s, uint32_t insn)
1403	1403	{
1404	1404	unsigned int val;
1405	1405	TCGv tmp;
...	...
1475	1475	}
1476	1476
1477	1477	/* load/store I_offset and R_offset */
1478		static void do_ldst_ir(CPUState env, DisasContext s, uint32_t insn)
	1478	static void do_ldst_ir(CPUUniCore32State env, DisasContext s, uint32_t insn)
1479	1479	{
1480	1480	unsigned int i;
1481	1481	TCGv tmp;
...	...
1524	1524	}
1525	1525
1526	1526	/* SWP instruction */
1527		static void do_swap(CPUState env, DisasContext s, uint32_t insn)
	1527	static void do_swap(CPUUniCore32State env, DisasContext s, uint32_t insn)
1528	1528	{
1529	1529	TCGv addr;
1530	1530	TCGv tmp;
...	...
1551	1551	}
1552	1552
1553	1553	/* load/store hw/sb */
1554		static void do_ldst_hwsb(CPUState env, DisasContext s, uint32_t insn)
	1554	static void do_ldst_hwsb(CPUUniCore32State env, DisasContext s, uint32_t insn)
1555	1555	{
1556	1556	TCGv addr;
1557	1557	TCGv tmp;
...	...
1603	1603	}
1604	1604
1605	1605	/* load/store multiple words */
1606		static void do_ldst_m(CPUState env, DisasContext s, uint32_t insn)
	1606	static void do_ldst_m(CPUUniCore32State env, DisasContext s, uint32_t insn)
1607	1607	{
1608	1608	unsigned int val, i;
1609	1609	int j, n, reg, user, loaded_base;
...	...
1743	1743	}
1744	1744
1745	1745	/* branch (and link) */
1746		static void do_branch(CPUState env, DisasContext s, uint32_t insn)
	1746	static void do_branch(CPUUniCore32State env, DisasContext s, uint32_t insn)
1747	1747	{
1748	1748	unsigned int val;
1749	1749	int32_t offset;
...	...
1772	1772	gen_jmp(s, val);
1773	1773	}
1774	1774
1775		static void disas_uc32_insn(CPUState env, DisasContext s)
	1775	static void disas_uc32_insn(CPUUniCore32State env, DisasContext s)
1776	1776	{
1777	1777	unsigned int insn;
1778	1778
...	...
1850	1850	/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
1851	1851	basic block 'tb'. If search_pc is TRUE, also generate PC
1852	1852	information for each intermediate instruction. */
1853		static inline void gen_intermediate_code_internal(CPUState *env,
	1853	static inline void gen_intermediate_code_internal(CPUUniCore32State *env,
1854	1854	TranslationBlock *tb, int search_pc)
1855	1855	{
1856	1856	DisasContext dc1, *dc = &dc1;
...	...
2030	2030	}
2031	2031	}
2032	2032
2033		void gen_intermediate_code(CPUState env, TranslationBlock tb)
	2033	void gen_intermediate_code(CPUUniCore32State env, TranslationBlock tb)
2034	2034	{
2035	2035	gen_intermediate_code_internal(env, tb, 0);
2036	2036	}
2037	2037
2038		void gen_intermediate_code_pc(CPUState env, TranslationBlock tb)
	2038	void gen_intermediate_code_pc(CPUUniCore32State env, TranslationBlock tb)
2039	2039	{
2040	2040	gen_intermediate_code_internal(env, tb, 1);
2041	2041	}
...	...
2046	2046	};
2047	2047
2048	2048	#define UCF64_DUMP_STATE
2049		void cpu_dump_state(CPUState env, FILE f, fprintf_function cpu_fprintf,
	2049	void cpu_dump_state(CPUUniCore32State env, FILE f, fprintf_function cpu_fprintf,
2050	2050	int flags)
2051	2051	{
2052	2052	int i;
...	...
2097	2097	#endif
2098	2098	}
2099	2099
2100		void restore_state_to_opc(CPUState env, TranslationBlock tb, int pc_pos)
	2100	void restore_state_to_opc(CPUUniCore32State env, TranslationBlock tb, int pc_pos)
2101	2101	{
2102	2102	env->regs[31] = gen_opc_pc[pc_pos];
2103	2103	}

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Archipelago » qemu

Revision eb23b556