Revision eb23b556 target-unicore32/translate.c
| b/target-unicore32/translate.c | ||
|---|---|---|
| 64 | 64 |
|
| 65 | 65 |
for (i = 0; i < 32; i++) {
|
| 66 | 66 |
cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, |
| 67 |
offsetof(CPUState, regs[i]), regnames[i]); |
|
| 67 |
offsetof(CPUUniCore32State, regs[i]), regnames[i]);
|
|
| 68 | 68 |
} |
| 69 | 69 |
|
| 70 | 70 |
#define GEN_HELPER 2 |
| ... | ... | |
| 94 | 94 |
return tmp; |
| 95 | 95 |
} |
| 96 | 96 |
|
| 97 |
#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name)) |
|
| 97 |
#define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
|
|
| 98 | 98 |
|
| 99 | 99 |
static inline void store_cpu_offset(TCGv var, int offset) |
| 100 | 100 |
{
|
| ... | ... | |
| 103 | 103 |
} |
| 104 | 104 |
|
| 105 | 105 |
#define store_cpu_field(var, name) \ |
| 106 |
store_cpu_offset(var, offsetof(CPUState, name)) |
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| 106 |
store_cpu_offset(var, offsetof(CPUUniCore32State, name))
|
|
| 107 | 107 |
|
| 108 | 108 |
/* Set a variable to the value of a CPU register. */ |
| 109 | 109 |
static void load_reg_var(DisasContext *s, TCGv var, int reg) |
| ... | ... | |
| 223 | 223 |
return tmp1; |
| 224 | 224 |
} |
| 225 | 225 |
|
| 226 |
#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF)) |
|
| 226 |
#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
|
|
| 227 | 227 |
|
| 228 | 228 |
/* Set CF to the top bit of var. */ |
| 229 | 229 |
static void gen_set_CF_bit31(TCGv var) |
| ... | ... | |
| 237 | 237 |
/* Set N and Z flags from var. */ |
| 238 | 238 |
static inline void gen_logic_CC(TCGv var) |
| 239 | 239 |
{
|
| 240 |
tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF)); |
|
| 241 |
tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF)); |
|
| 240 |
tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, NF));
|
|
| 241 |
tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, ZF));
|
|
| 242 | 242 |
} |
| 243 | 243 |
|
| 244 | 244 |
/* dest = T0 + T1 + CF. */ |
| ... | ... | |
| 634 | 634 |
static inline long ucf64_reg_offset(int reg) |
| 635 | 635 |
{
|
| 636 | 636 |
if (reg & 1) {
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| 637 |
return offsetof(CPUState, ucf64.regs[reg >> 1]) |
|
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return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
|
|
| 638 | 638 |
+ offsetof(CPU_DoubleU, l.upper); |
| 639 | 639 |
} else {
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| 640 |
return offsetof(CPUState, ucf64.regs[reg >> 1]) |
|
| 640 |
return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
|
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| 641 | 641 |
+ offsetof(CPU_DoubleU, l.lower); |
| 642 | 642 |
} |
| 643 | 643 |
} |
| ... | ... | |
| 646 | 646 |
#define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg)) |
| 647 | 647 |
|
| 648 | 648 |
/* UniCore-F64 single load/store I_offset */ |
| 649 |
static void do_ucf64_ldst_i(CPUState *env, DisasContext *s, uint32_t insn) |
|
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static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 650 | 650 |
{
|
| 651 | 651 |
int offset; |
| 652 | 652 |
TCGv tmp; |
| ... | ... | |
| 692 | 692 |
} |
| 693 | 693 |
|
| 694 | 694 |
/* UniCore-F64 load/store multiple words */ |
| 695 |
static void do_ucf64_ldst_m(CPUState *env, DisasContext *s, uint32_t insn) |
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static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 696 | 696 |
{
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| 697 | 697 |
unsigned int i; |
| 698 | 698 |
int j, n, freg; |
| ... | ... | |
| 777 | 777 |
} |
| 778 | 778 |
|
| 779 | 779 |
/* UniCore-F64 mrc/mcr */ |
| 780 |
static void do_ucf64_trans(CPUState *env, DisasContext *s, uint32_t insn) |
|
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static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
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{
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TCGv tmp; |
| 783 | 783 |
|
| ... | ... | |
| 841 | 841 |
} |
| 842 | 842 |
|
| 843 | 843 |
/* UniCore-F64 convert instructions */ |
| 844 |
static void do_ucf64_fcvt(CPUState *env, DisasContext *s, uint32_t insn) |
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static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 845 | 845 |
{
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| 846 | 846 |
if (UCOP_UCF64_FMT == 3) {
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| 847 | 847 |
ILLEGAL; |
| ... | ... | |
| 907 | 907 |
} |
| 908 | 908 |
|
| 909 | 909 |
/* UniCore-F64 compare instructions */ |
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static void do_ucf64_fcmp(CPUState *env, DisasContext *s, uint32_t insn) |
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static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 911 | 911 |
{
|
| 912 | 912 |
if (UCOP_SET(25)) {
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| 913 | 913 |
ILLEGAL; |
| ... | ... | |
| 985 | 985 |
} while (0) |
| 986 | 986 |
|
| 987 | 987 |
/* UniCore-F64 data processing */ |
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static void do_ucf64_datap(CPUState *env, DisasContext *s, uint32_t insn) |
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static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
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{
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| 990 | 990 |
if (UCOP_UCF64_FMT == 3) {
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| 991 | 991 |
ILLEGAL; |
| ... | ... | |
| 1018 | 1018 |
} |
| 1019 | 1019 |
|
| 1020 | 1020 |
/* Disassemble an F64 instruction */ |
| 1021 |
static void disas_ucf64_insn(CPUState *env, DisasContext *s, uint32_t insn) |
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| 1021 |
static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 1022 | 1022 |
{
|
| 1023 | 1023 |
if (!UCOP_SET(29)) {
|
| 1024 | 1024 |
if (UCOP_SET(26)) {
|
| ... | ... | |
| 1123 | 1123 |
s->is_jmp = DISAS_UPDATE; |
| 1124 | 1124 |
} |
| 1125 | 1125 |
|
| 1126 |
static void disas_coproc_insn(CPUState *env, DisasContext *s, uint32_t insn) |
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static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
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{
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| 1128 | 1128 |
switch (UCOP_CPNUM) {
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| 1129 | 1129 |
case 2: |
| ... | ... | |
| 1168 | 1168 |
} |
| 1169 | 1169 |
|
| 1170 | 1170 |
/* data processing instructions */ |
| 1171 |
static void do_datap(CPUState *env, DisasContext *s, uint32_t insn) |
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static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
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{
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| 1173 | 1173 |
TCGv tmp; |
| 1174 | 1174 |
TCGv tmp2; |
| ... | ... | |
| 1359 | 1359 |
} |
| 1360 | 1360 |
|
| 1361 | 1361 |
/* multiply */ |
| 1362 |
static void do_mult(CPUState *env, DisasContext *s, uint32_t insn) |
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static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 1363 | 1363 |
{
|
| 1364 | 1364 |
TCGv tmp; |
| 1365 | 1365 |
TCGv tmp2; |
| ... | ... | |
| 1399 | 1399 |
} |
| 1400 | 1400 |
|
| 1401 | 1401 |
/* miscellaneous instructions */ |
| 1402 |
static void do_misc(CPUState *env, DisasContext *s, uint32_t insn) |
|
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static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 1403 | 1403 |
{
|
| 1404 | 1404 |
unsigned int val; |
| 1405 | 1405 |
TCGv tmp; |
| ... | ... | |
| 1475 | 1475 |
} |
| 1476 | 1476 |
|
| 1477 | 1477 |
/* load/store I_offset and R_offset */ |
| 1478 |
static void do_ldst_ir(CPUState *env, DisasContext *s, uint32_t insn) |
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| 1478 |
static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
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|
| 1479 | 1479 |
{
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| 1480 | 1480 |
unsigned int i; |
| 1481 | 1481 |
TCGv tmp; |
| ... | ... | |
| 1524 | 1524 |
} |
| 1525 | 1525 |
|
| 1526 | 1526 |
/* SWP instruction */ |
| 1527 |
static void do_swap(CPUState *env, DisasContext *s, uint32_t insn) |
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| 1527 |
static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 1528 | 1528 |
{
|
| 1529 | 1529 |
TCGv addr; |
| 1530 | 1530 |
TCGv tmp; |
| ... | ... | |
| 1551 | 1551 |
} |
| 1552 | 1552 |
|
| 1553 | 1553 |
/* load/store hw/sb */ |
| 1554 |
static void do_ldst_hwsb(CPUState *env, DisasContext *s, uint32_t insn) |
|
| 1554 |
static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 1555 | 1555 |
{
|
| 1556 | 1556 |
TCGv addr; |
| 1557 | 1557 |
TCGv tmp; |
| ... | ... | |
| 1603 | 1603 |
} |
| 1604 | 1604 |
|
| 1605 | 1605 |
/* load/store multiple words */ |
| 1606 |
static void do_ldst_m(CPUState *env, DisasContext *s, uint32_t insn) |
|
| 1606 |
static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 1607 | 1607 |
{
|
| 1608 | 1608 |
unsigned int val, i; |
| 1609 | 1609 |
int j, n, reg, user, loaded_base; |
| ... | ... | |
| 1743 | 1743 |
} |
| 1744 | 1744 |
|
| 1745 | 1745 |
/* branch (and link) */ |
| 1746 |
static void do_branch(CPUState *env, DisasContext *s, uint32_t insn) |
|
| 1746 |
static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
|
|
| 1747 | 1747 |
{
|
| 1748 | 1748 |
unsigned int val; |
| 1749 | 1749 |
int32_t offset; |
| ... | ... | |
| 1772 | 1772 |
gen_jmp(s, val); |
| 1773 | 1773 |
} |
| 1774 | 1774 |
|
| 1775 |
static void disas_uc32_insn(CPUState *env, DisasContext *s) |
|
| 1775 |
static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
|
|
| 1776 | 1776 |
{
|
| 1777 | 1777 |
unsigned int insn; |
| 1778 | 1778 |
|
| ... | ... | |
| 1850 | 1850 |
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for |
| 1851 | 1851 |
basic block 'tb'. If search_pc is TRUE, also generate PC |
| 1852 | 1852 |
information for each intermediate instruction. */ |
| 1853 |
static inline void gen_intermediate_code_internal(CPUState *env, |
|
| 1853 |
static inline void gen_intermediate_code_internal(CPUUniCore32State *env,
|
|
| 1854 | 1854 |
TranslationBlock *tb, int search_pc) |
| 1855 | 1855 |
{
|
| 1856 | 1856 |
DisasContext dc1, *dc = &dc1; |
| ... | ... | |
| 2030 | 2030 |
} |
| 2031 | 2031 |
} |
| 2032 | 2032 |
|
| 2033 |
void gen_intermediate_code(CPUState *env, TranslationBlock *tb) |
|
| 2033 |
void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
|
|
| 2034 | 2034 |
{
|
| 2035 | 2035 |
gen_intermediate_code_internal(env, tb, 0); |
| 2036 | 2036 |
} |
| 2037 | 2037 |
|
| 2038 |
void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) |
|
| 2038 |
void gen_intermediate_code_pc(CPUUniCore32State *env, TranslationBlock *tb)
|
|
| 2039 | 2039 |
{
|
| 2040 | 2040 |
gen_intermediate_code_internal(env, tb, 1); |
| 2041 | 2041 |
} |
| ... | ... | |
| 2046 | 2046 |
}; |
| 2047 | 2047 |
|
| 2048 | 2048 |
#define UCF64_DUMP_STATE |
| 2049 |
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, |
|
| 2049 |
void cpu_dump_state(CPUUniCore32State *env, FILE *f, fprintf_function cpu_fprintf,
|
|
| 2050 | 2050 |
int flags) |
| 2051 | 2051 |
{
|
| 2052 | 2052 |
int i; |
| ... | ... | |
| 2097 | 2097 |
#endif |
| 2098 | 2098 |
} |
| 2099 | 2099 |
|
| 2100 |
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) |
|
| 2100 |
void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, int pc_pos)
|
|
| 2101 | 2101 |
{
|
| 2102 | 2102 |
env->regs[31] = gen_opc_pc[pc_pos]; |
| 2103 | 2103 |
} |
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