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/*
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 * QEMU PC System Emulator
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 *
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 * Copyright (c) 2003-2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "pc.h"
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#include "fdc.h"
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#include "pci.h"
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#include "block.h"
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#include "sysemu.h"
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#include "audio/audio.h"
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#include "net.h"
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#include "smbus.h"
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#include "boards.h"
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#include "console.h"
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/* output Bochs bios info messages */
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//#define DEBUG_BIOS
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#define BIOS_FILENAME "bios.bin"
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#define VGABIOS_FILENAME "vgabios.bin"
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#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
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#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
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/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
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#define ACPI_DATA_SIZE       0x10000
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#define MAX_IDE_BUS 2
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static fdctrl_t *floppy_controller;
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static RTCState *rtc_state;
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static PITState *pit;
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static IOAPICState *ioapic;
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static PCIDevice *i440fx_state;
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
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{
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}
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
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/* XXX: add IGNNE support */
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void cpu_set_ferr(CPUX86State *s)
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{
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    qemu_irq_raise(ferr_irq);
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}
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static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
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{
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    qemu_irq_lower(ferr_irq);
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}
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env)
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{
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    /* Note: when using kqemu, it is more logical to return the host TSC
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       because kqemu does not trap the RDTSC instruction for
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       performance reasons */
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#ifdef USE_KQEMU
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    if (env->kqemu_enabled) {
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        return cpu_get_real_ticks();
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    } else
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#endif
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    {
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        return cpu_get_ticks();
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    }
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}
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/* SMM support */
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void cpu_smm_update(CPUState *env)
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{
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    if (i440fx_state && env == first_cpu)
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        i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
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}
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{
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    int intno;
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    intno = apic_get_interrupt(env);
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    if (intno >= 0) {
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        /* set irq request if a PIC irq is still pending */
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        /* XXX: improve that */
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        pic_update_irq(isa_pic);
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        return intno;
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    }
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    /* read the irq from the PIC */
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    if (!apic_accept_pic_intr(env))
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        return -1;
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    intno = pic_read_irq(isa_pic);
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    return intno;
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}
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static void pic_irq_request(void *opaque, int irq, int level)
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{
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    CPUState *env = first_cpu;
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    if (env->apic_state) {
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        while (env) {
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            if (apic_accept_pic_intr(env))
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                apic_deliver_pic_intr(env, level);
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            env = env->next_cpu;
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        }
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    } else {
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        if (level)
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            cpu_interrupt(env, CPU_INTERRUPT_HARD);
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        else
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            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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    }
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}
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE          0x14
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static int cmos_get_fd_drive_type(int fd0)
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{
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    int val;
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    switch (fd0) {
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    case 0:
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        /* 1.44 Mb 3"5 drive */
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        val = 4;
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        break;
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    case 1:
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        /* 2.88 Mb 3"5 drive */
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        val = 5;
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        break;
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    case 2:
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        /* 1.2 Mb 5"5 drive */
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        val = 2;
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        break;
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    default:
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        val = 0;
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        break;
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    }
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    return val;
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}
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static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
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{
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    RTCState *s = rtc_state;
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    int cylinders, heads, sectors;
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    bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
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    rtc_set_memory(s, type_ofs, 47);
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    rtc_set_memory(s, info_ofs, cylinders);
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    rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
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    rtc_set_memory(s, info_ofs + 2, heads);
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    rtc_set_memory(s, info_ofs + 3, 0xff);
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    rtc_set_memory(s, info_ofs + 4, 0xff);
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    rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
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    rtc_set_memory(s, info_ofs + 6, cylinders);
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    rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
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    rtc_set_memory(s, info_ofs + 8, sectors);
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}
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device)
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{
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    switch(boot_device) {
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    case 'a':
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    case 'b':
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        return 0x01; /* floppy boot */
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    case 'c':
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        return 0x02; /* hard drive boot */
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    case 'd':
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        return 0x03; /* CD-ROM boot */
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    case 'n':
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        return 0x04; /* Network boot */
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    }
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    return 0;
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}
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/* copy/pasted from cmos_init, should be made a general function
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 and used there as well */
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static int pc_boot_set(void *opaque, const char *boot_device)
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{
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#define PC_MAX_BOOT_DEVICES 3
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    RTCState *s = (RTCState *)opaque;
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    int nbds, bds[3] = { 0, };
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    int i;
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    nbds = strlen(boot_device);
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    if (nbds > PC_MAX_BOOT_DEVICES) {
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        term_printf("Too many boot devices for PC\n");
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        return(1);
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    }
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    for (i = 0; i < nbds; i++) {
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        bds[i] = boot_device2nibble(boot_device[i]);
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        if (bds[i] == 0) {
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            term_printf("Invalid boot device for PC: '%c'\n",
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                    boot_device[i]);
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            return(1);
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        }
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    }
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    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
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    rtc_set_memory(s, 0x38, (bds[2] << 4));
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    return(0);
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}
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/* hd_table must contain 4 block drivers */
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static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
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                      const char *boot_device, BlockDriverState **hd_table)
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{
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    RTCState *s = rtc_state;
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    int nbds, bds[3] = { 0, };
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    int val;
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    int fd0, fd1, nb;
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    int i;
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    /* various important CMOS locations needed by PC/Bochs bios */
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    /* memory size */
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    val = 640; /* base memory in K */
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    rtc_set_memory(s, 0x15, val);
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    rtc_set_memory(s, 0x16, val >> 8);
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    val = (ram_size / 1024) - 1024;
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    if (val > 65535)
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        val = 65535;
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    rtc_set_memory(s, 0x17, val);
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    rtc_set_memory(s, 0x18, val >> 8);
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    rtc_set_memory(s, 0x30, val);
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    rtc_set_memory(s, 0x31, val >> 8);
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    if (above_4g_mem_size) {
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        rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
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        rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
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        rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
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    }
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    if (ram_size > (16 * 1024 * 1024))
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        val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
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    else
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        val = 0;
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    if (val > 65535)
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        val = 65535;
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    rtc_set_memory(s, 0x34, val);
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    rtc_set_memory(s, 0x35, val >> 8);
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    /* set the number of CPU */
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    rtc_set_memory(s, 0x5f, smp_cpus - 1);
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    /* set boot devices, and disable floppy signature check if requested */
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#define PC_MAX_BOOT_DEVICES 3
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    nbds = strlen(boot_device);
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    if (nbds > PC_MAX_BOOT_DEVICES) {
271 28c5af54 j_mayer
        fprintf(stderr, "Too many boot devices for PC\n");
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        exit(1);
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    }
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    for (i = 0; i < nbds; i++) {
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        bds[i] = boot_device2nibble(boot_device[i]);
276 28c5af54 j_mayer
        if (bds[i] == 0) {
277 28c5af54 j_mayer
            fprintf(stderr, "Invalid boot device for PC: '%c'\n",
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                    boot_device[i]);
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            exit(1);
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        }
281 28c5af54 j_mayer
    }
282 28c5af54 j_mayer
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
283 28c5af54 j_mayer
    rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
284 80cabfad bellard
285 b41a2cd1 bellard
    /* floppy type */
286 b41a2cd1 bellard
287 baca51fa bellard
    fd0 = fdctrl_get_drive_type(floppy_controller, 0);
288 baca51fa bellard
    fd1 = fdctrl_get_drive_type(floppy_controller, 1);
289 80cabfad bellard
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    val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
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    rtc_set_memory(s, 0x10, val);
292 3b46e624 ths
293 b0a21b53 bellard
    val = 0;
294 b41a2cd1 bellard
    nb = 0;
295 80cabfad bellard
    if (fd0 < 3)
296 80cabfad bellard
        nb++;
297 80cabfad bellard
    if (fd1 < 3)
298 80cabfad bellard
        nb++;
299 80cabfad bellard
    switch (nb) {
300 80cabfad bellard
    case 0:
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        break;
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    case 1:
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        val |= 0x01; /* 1 drive, ready for boot */
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        break;
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    case 2:
306 b0a21b53 bellard
        val |= 0x41; /* 2 drives, ready for boot */
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        break;
308 80cabfad bellard
    }
309 b0a21b53 bellard
    val |= 0x02; /* FPU is there */
310 b0a21b53 bellard
    val |= 0x04; /* PS/2 mouse installed */
311 b0a21b53 bellard
    rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
312 b0a21b53 bellard
313 ba6c2377 bellard
    /* hard drives */
314 ba6c2377 bellard
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    rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
316 ba6c2377 bellard
    if (hd_table[0])
317 ba6c2377 bellard
        cmos_init_hd(0x19, 0x1b, hd_table[0]);
318 5fafdf24 ths
    if (hd_table[1])
319 ba6c2377 bellard
        cmos_init_hd(0x1a, 0x24, hd_table[1]);
320 ba6c2377 bellard
321 ba6c2377 bellard
    val = 0;
322 40b6ecc6 bellard
    for (i = 0; i < 4; i++) {
323 ba6c2377 bellard
        if (hd_table[i]) {
324 46d4767d bellard
            int cylinders, heads, sectors, translation;
325 46d4767d bellard
            /* NOTE: bdrv_get_geometry_hint() returns the physical
326 46d4767d bellard
                geometry.  It is always such that: 1 <= sects <= 63, 1
327 46d4767d bellard
                <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
328 46d4767d bellard
                geometry can be different if a translation is done. */
329 46d4767d bellard
            translation = bdrv_get_translation_hint(hd_table[i]);
330 46d4767d bellard
            if (translation == BIOS_ATA_TRANSLATION_AUTO) {
331 46d4767d bellard
                bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
332 46d4767d bellard
                if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
333 46d4767d bellard
                    /* No translation. */
334 46d4767d bellard
                    translation = 0;
335 46d4767d bellard
                } else {
336 46d4767d bellard
                    /* LBA translation. */
337 46d4767d bellard
                    translation = 1;
338 46d4767d bellard
                }
339 40b6ecc6 bellard
            } else {
340 46d4767d bellard
                translation--;
341 ba6c2377 bellard
            }
342 ba6c2377 bellard
            val |= translation << (i * 2);
343 ba6c2377 bellard
        }
344 40b6ecc6 bellard
    }
345 ba6c2377 bellard
    rtc_set_memory(s, 0x39, val);
346 80cabfad bellard
}
347 80cabfad bellard
348 59b8ad81 bellard
void ioport_set_a20(int enable)
349 59b8ad81 bellard
{
350 59b8ad81 bellard
    /* XXX: send to all CPUs ? */
351 59b8ad81 bellard
    cpu_x86_set_a20(first_cpu, enable);
352 59b8ad81 bellard
}
353 59b8ad81 bellard
354 59b8ad81 bellard
int ioport_get_a20(void)
355 59b8ad81 bellard
{
356 59b8ad81 bellard
    return ((first_cpu->a20_mask >> 20) & 1);
357 59b8ad81 bellard
}
358 59b8ad81 bellard
359 e1a23744 bellard
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
360 e1a23744 bellard
{
361 59b8ad81 bellard
    ioport_set_a20((val >> 1) & 1);
362 e1a23744 bellard
    /* XXX: bit 0 is fast reset */
363 e1a23744 bellard
}
364 e1a23744 bellard
365 e1a23744 bellard
static uint32_t ioport92_read(void *opaque, uint32_t addr)
366 e1a23744 bellard
{
367 59b8ad81 bellard
    return ioport_get_a20() << 1;
368 e1a23744 bellard
}
369 e1a23744 bellard
370 80cabfad bellard
/***********************************************************/
371 80cabfad bellard
/* Bochs BIOS debug ports */
372 80cabfad bellard
373 9596ebb7 pbrook
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
374 80cabfad bellard
{
375 a2f659ee bellard
    static const char shutdown_str[8] = "Shutdown";
376 a2f659ee bellard
    static int shutdown_index = 0;
377 3b46e624 ths
378 80cabfad bellard
    switch(addr) {
379 80cabfad bellard
        /* Bochs BIOS messages */
380 80cabfad bellard
    case 0x400:
381 80cabfad bellard
    case 0x401:
382 80cabfad bellard
        fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
383 80cabfad bellard
        exit(1);
384 80cabfad bellard
    case 0x402:
385 80cabfad bellard
    case 0x403:
386 80cabfad bellard
#ifdef DEBUG_BIOS
387 80cabfad bellard
        fprintf(stderr, "%c", val);
388 80cabfad bellard
#endif
389 80cabfad bellard
        break;
390 a2f659ee bellard
    case 0x8900:
391 a2f659ee bellard
        /* same as Bochs power off */
392 a2f659ee bellard
        if (val == shutdown_str[shutdown_index]) {
393 a2f659ee bellard
            shutdown_index++;
394 a2f659ee bellard
            if (shutdown_index == 8) {
395 a2f659ee bellard
                shutdown_index = 0;
396 a2f659ee bellard
                qemu_system_shutdown_request();
397 a2f659ee bellard
            }
398 a2f659ee bellard
        } else {
399 a2f659ee bellard
            shutdown_index = 0;
400 a2f659ee bellard
        }
401 a2f659ee bellard
        break;
402 80cabfad bellard
403 80cabfad bellard
        /* LGPL'ed VGA BIOS messages */
404 80cabfad bellard
    case 0x501:
405 80cabfad bellard
    case 0x502:
406 80cabfad bellard
        fprintf(stderr, "VGA BIOS panic, line %d\n", val);
407 80cabfad bellard
        exit(1);
408 80cabfad bellard
    case 0x500:
409 80cabfad bellard
    case 0x503:
410 80cabfad bellard
#ifdef DEBUG_BIOS
411 80cabfad bellard
        fprintf(stderr, "%c", val);
412 80cabfad bellard
#endif
413 80cabfad bellard
        break;
414 80cabfad bellard
    }
415 80cabfad bellard
}
416 80cabfad bellard
417 9596ebb7 pbrook
static void bochs_bios_init(void)
418 80cabfad bellard
{
419 b41a2cd1 bellard
    register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
420 b41a2cd1 bellard
    register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
421 b41a2cd1 bellard
    register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
422 b41a2cd1 bellard
    register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
423 a2f659ee bellard
    register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
424 b41a2cd1 bellard
425 b41a2cd1 bellard
    register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
426 b41a2cd1 bellard
    register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
427 b41a2cd1 bellard
    register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
428 b41a2cd1 bellard
    register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
429 80cabfad bellard
}
430 80cabfad bellard
431 642a4f96 ths
/* Generate an initial boot sector which sets state and jump to
432 642a4f96 ths
   a specified vector */
433 3f6c925f balrog
static void generate_bootsect(uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
434 642a4f96 ths
{
435 642a4f96 ths
    uint8_t bootsect[512], *p;
436 642a4f96 ths
    int i;
437 e4bcb14c ths
    int hda;
438 642a4f96 ths
439 e4bcb14c ths
    hda = drive_get_index(IF_IDE, 0, 0);
440 e4bcb14c ths
    if (hda == -1) {
441 642a4f96 ths
        fprintf(stderr, "A disk image must be given for 'hda' when booting "
442 f97572e5 aurel32
                "a Linux kernel\n(if you really don't want it, use /dev/zero)\n");
443 642a4f96 ths
        exit(1);
444 642a4f96 ths
    }
445 642a4f96 ths
446 642a4f96 ths
    memset(bootsect, 0, sizeof(bootsect));
447 642a4f96 ths
448 642a4f96 ths
    /* Copy the MSDOS partition table if possible */
449 e4bcb14c ths
    bdrv_read(drives_table[hda].bdrv, 0, bootsect, 1);
450 642a4f96 ths
451 642a4f96 ths
    /* Make sure we have a partition signature */
452 642a4f96 ths
    bootsect[510] = 0x55;
453 642a4f96 ths
    bootsect[511] = 0xaa;
454 642a4f96 ths
455 642a4f96 ths
    /* Actual code */
456 642a4f96 ths
    p = bootsect;
457 642a4f96 ths
    *p++ = 0xfa;                /* CLI */
458 642a4f96 ths
    *p++ = 0xfc;                /* CLD */
459 642a4f96 ths
460 642a4f96 ths
    for (i = 0; i < 6; i++) {
461 642a4f96 ths
        if (i == 1)                /* Skip CS */
462 642a4f96 ths
            continue;
463 642a4f96 ths
464 642a4f96 ths
        *p++ = 0xb8;                /* MOV AX,imm16 */
465 642a4f96 ths
        *p++ = segs[i];
466 642a4f96 ths
        *p++ = segs[i] >> 8;
467 642a4f96 ths
        *p++ = 0x8e;                /* MOV <seg>,AX */
468 642a4f96 ths
        *p++ = 0xc0 + (i << 3);
469 642a4f96 ths
    }
470 642a4f96 ths
471 642a4f96 ths
    for (i = 0; i < 8; i++) {
472 642a4f96 ths
        *p++ = 0x66;                /* 32-bit operand size */
473 642a4f96 ths
        *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
474 642a4f96 ths
        *p++ = gpr[i];
475 642a4f96 ths
        *p++ = gpr[i] >> 8;
476 642a4f96 ths
        *p++ = gpr[i] >> 16;
477 642a4f96 ths
        *p++ = gpr[i] >> 24;
478 642a4f96 ths
    }
479 642a4f96 ths
480 642a4f96 ths
    *p++ = 0xea;                /* JMP FAR */
481 642a4f96 ths
    *p++ = ip;                        /* IP */
482 642a4f96 ths
    *p++ = ip >> 8;
483 642a4f96 ths
    *p++ = segs[1];                /* CS */
484 642a4f96 ths
    *p++ = segs[1] >> 8;
485 642a4f96 ths
486 e4bcb14c ths
    bdrv_set_boot_sector(drives_table[hda].bdrv, bootsect, sizeof(bootsect));
487 642a4f96 ths
}
488 80cabfad bellard
489 642a4f96 ths
static long get_file_size(FILE *f)
490 642a4f96 ths
{
491 642a4f96 ths
    long where, size;
492 642a4f96 ths
493 642a4f96 ths
    /* XXX: on Unix systems, using fstat() probably makes more sense */
494 642a4f96 ths
495 642a4f96 ths
    where = ftell(f);
496 642a4f96 ths
    fseek(f, 0, SEEK_END);
497 642a4f96 ths
    size = ftell(f);
498 642a4f96 ths
    fseek(f, where, SEEK_SET);
499 642a4f96 ths
500 642a4f96 ths
    return size;
501 642a4f96 ths
}
502 642a4f96 ths
503 642a4f96 ths
static void load_linux(const char *kernel_filename,
504 642a4f96 ths
                       const char *initrd_filename,
505 642a4f96 ths
                       const char *kernel_cmdline)
506 642a4f96 ths
{
507 642a4f96 ths
    uint16_t protocol;
508 642a4f96 ths
    uint32_t gpr[8];
509 642a4f96 ths
    uint16_t seg[6];
510 642a4f96 ths
    uint16_t real_seg;
511 642a4f96 ths
    int setup_size, kernel_size, initrd_size, cmdline_size;
512 642a4f96 ths
    uint32_t initrd_max;
513 642a4f96 ths
    uint8_t header[1024];
514 a37af289 blueswir1
    target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr;
515 642a4f96 ths
    FILE *f, *fi;
516 642a4f96 ths
517 642a4f96 ths
    /* Align to 16 bytes as a paranoia measure */
518 642a4f96 ths
    cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
519 642a4f96 ths
520 642a4f96 ths
    /* load the kernel header */
521 642a4f96 ths
    f = fopen(kernel_filename, "rb");
522 642a4f96 ths
    if (!f || !(kernel_size = get_file_size(f)) ||
523 642a4f96 ths
        fread(header, 1, 1024, f) != 1024) {
524 642a4f96 ths
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
525 642a4f96 ths
                kernel_filename);
526 642a4f96 ths
        exit(1);
527 642a4f96 ths
    }
528 642a4f96 ths
529 642a4f96 ths
    /* kernel protocol version */
530 bc4edd79 bellard
#if 0
531 642a4f96 ths
    fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
532 bc4edd79 bellard
#endif
533 642a4f96 ths
    if (ldl_p(header+0x202) == 0x53726448)
534 642a4f96 ths
        protocol = lduw_p(header+0x206);
535 642a4f96 ths
    else
536 642a4f96 ths
        protocol = 0;
537 642a4f96 ths
538 642a4f96 ths
    if (protocol < 0x200 || !(header[0x211] & 0x01)) {
539 642a4f96 ths
        /* Low kernel */
540 a37af289 blueswir1
        real_addr    = 0x90000;
541 a37af289 blueswir1
        cmdline_addr = 0x9a000 - cmdline_size;
542 a37af289 blueswir1
        prot_addr    = 0x10000;
543 642a4f96 ths
    } else if (protocol < 0x202) {
544 642a4f96 ths
        /* High but ancient kernel */
545 a37af289 blueswir1
        real_addr    = 0x90000;
546 a37af289 blueswir1
        cmdline_addr = 0x9a000 - cmdline_size;
547 a37af289 blueswir1
        prot_addr    = 0x100000;
548 642a4f96 ths
    } else {
549 642a4f96 ths
        /* High and recent kernel */
550 a37af289 blueswir1
        real_addr    = 0x10000;
551 a37af289 blueswir1
        cmdline_addr = 0x20000;
552 a37af289 blueswir1
        prot_addr    = 0x100000;
553 642a4f96 ths
    }
554 642a4f96 ths
555 bc4edd79 bellard
#if 0
556 642a4f96 ths
    fprintf(stderr,
557 526ccb7a balrog
            "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
558 526ccb7a balrog
            "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
559 526ccb7a balrog
            "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
560 a37af289 blueswir1
            real_addr,
561 a37af289 blueswir1
            cmdline_addr,
562 a37af289 blueswir1
            prot_addr);
563 bc4edd79 bellard
#endif
564 642a4f96 ths
565 642a4f96 ths
    /* highest address for loading the initrd */
566 642a4f96 ths
    if (protocol >= 0x203)
567 642a4f96 ths
        initrd_max = ldl_p(header+0x22c);
568 642a4f96 ths
    else
569 642a4f96 ths
        initrd_max = 0x37ffffff;
570 642a4f96 ths
571 642a4f96 ths
    if (initrd_max >= ram_size-ACPI_DATA_SIZE)
572 642a4f96 ths
        initrd_max = ram_size-ACPI_DATA_SIZE-1;
573 642a4f96 ths
574 642a4f96 ths
    /* kernel command line */
575 a37af289 blueswir1
    pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
576 642a4f96 ths
577 642a4f96 ths
    if (protocol >= 0x202) {
578 a37af289 blueswir1
        stl_p(header+0x228, cmdline_addr);
579 642a4f96 ths
    } else {
580 642a4f96 ths
        stw_p(header+0x20, 0xA33F);
581 642a4f96 ths
        stw_p(header+0x22, cmdline_addr-real_addr);
582 642a4f96 ths
    }
583 642a4f96 ths
584 642a4f96 ths
    /* loader type */
585 642a4f96 ths
    /* High nybble = B reserved for Qemu; low nybble is revision number.
586 642a4f96 ths
       If this code is substantially changed, you may want to consider
587 642a4f96 ths
       incrementing the revision. */
588 642a4f96 ths
    if (protocol >= 0x200)
589 642a4f96 ths
        header[0x210] = 0xB0;
590 642a4f96 ths
591 642a4f96 ths
    /* heap */
592 642a4f96 ths
    if (protocol >= 0x201) {
593 642a4f96 ths
        header[0x211] |= 0x80;        /* CAN_USE_HEAP */
594 642a4f96 ths
        stw_p(header+0x224, cmdline_addr-real_addr-0x200);
595 642a4f96 ths
    }
596 642a4f96 ths
597 642a4f96 ths
    /* load initrd */
598 642a4f96 ths
    if (initrd_filename) {
599 642a4f96 ths
        if (protocol < 0x200) {
600 642a4f96 ths
            fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
601 642a4f96 ths
            exit(1);
602 642a4f96 ths
        }
603 642a4f96 ths
604 642a4f96 ths
        fi = fopen(initrd_filename, "rb");
605 642a4f96 ths
        if (!fi) {
606 642a4f96 ths
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
607 642a4f96 ths
                    initrd_filename);
608 642a4f96 ths
            exit(1);
609 642a4f96 ths
        }
610 642a4f96 ths
611 642a4f96 ths
        initrd_size = get_file_size(fi);
612 a37af289 blueswir1
        initrd_addr = (initrd_max-initrd_size) & ~4095;
613 642a4f96 ths
614 526ccb7a balrog
        fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx
615 526ccb7a balrog
                "\n", initrd_size, initrd_addr);
616 642a4f96 ths
617 a37af289 blueswir1
        if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
618 642a4f96 ths
            fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
619 642a4f96 ths
                    initrd_filename);
620 642a4f96 ths
            exit(1);
621 642a4f96 ths
        }
622 642a4f96 ths
        fclose(fi);
623 642a4f96 ths
624 a37af289 blueswir1
        stl_p(header+0x218, initrd_addr);
625 642a4f96 ths
        stl_p(header+0x21c, initrd_size);
626 642a4f96 ths
    }
627 642a4f96 ths
628 642a4f96 ths
    /* store the finalized header and load the rest of the kernel */
629 a37af289 blueswir1
    cpu_physical_memory_write(real_addr, header, 1024);
630 642a4f96 ths
631 642a4f96 ths
    setup_size = header[0x1f1];
632 642a4f96 ths
    if (setup_size == 0)
633 642a4f96 ths
        setup_size = 4;
634 642a4f96 ths
635 642a4f96 ths
    setup_size = (setup_size+1)*512;
636 642a4f96 ths
    kernel_size -= setup_size;        /* Size of protected-mode code */
637 642a4f96 ths
638 a37af289 blueswir1
    if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) ||
639 a37af289 blueswir1
        !fread_targphys_ok(prot_addr, kernel_size, f)) {
640 642a4f96 ths
        fprintf(stderr, "qemu: read error on kernel '%s'\n",
641 642a4f96 ths
                kernel_filename);
642 642a4f96 ths
        exit(1);
643 642a4f96 ths
    }
644 642a4f96 ths
    fclose(f);
645 642a4f96 ths
646 642a4f96 ths
    /* generate bootsector to set up the initial register state */
647 a37af289 blueswir1
    real_seg = real_addr >> 4;
648 642a4f96 ths
    seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
649 642a4f96 ths
    seg[1] = real_seg+0x20;        /* CS */
650 642a4f96 ths
    memset(gpr, 0, sizeof gpr);
651 642a4f96 ths
    gpr[4] = cmdline_addr-real_addr-16;        /* SP (-16 is paranoia) */
652 642a4f96 ths
653 642a4f96 ths
    generate_bootsect(gpr, seg, 0);
654 642a4f96 ths
}
655 642a4f96 ths
656 59b8ad81 bellard
static void main_cpu_reset(void *opaque)
657 59b8ad81 bellard
{
658 59b8ad81 bellard
    CPUState *env = opaque;
659 59b8ad81 bellard
    cpu_reset(env);
660 59b8ad81 bellard
}
661 59b8ad81 bellard
662 b41a2cd1 bellard
static const int ide_iobase[2] = { 0x1f0, 0x170 };
663 b41a2cd1 bellard
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
664 b41a2cd1 bellard
static const int ide_irq[2] = { 14, 15 };
665 b41a2cd1 bellard
666 b41a2cd1 bellard
#define NE2000_NB_MAX 6
667 b41a2cd1 bellard
668 8d11df9e bellard
static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
669 b41a2cd1 bellard
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
670 b41a2cd1 bellard
671 8d11df9e bellard
static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
672 8d11df9e bellard
static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
673 8d11df9e bellard
674 6508fe59 bellard
static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
675 6508fe59 bellard
static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
676 6508fe59 bellard
677 6a36d84e bellard
#ifdef HAS_AUDIO
678 d537cf6c pbrook
static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
679 6a36d84e bellard
{
680 6a36d84e bellard
    struct soundhw *c;
681 6a36d84e bellard
    int audio_enabled = 0;
682 6a36d84e bellard
683 6a36d84e bellard
    for (c = soundhw; !audio_enabled && c->name; ++c) {
684 6a36d84e bellard
        audio_enabled = c->enabled;
685 6a36d84e bellard
    }
686 6a36d84e bellard
687 6a36d84e bellard
    if (audio_enabled) {
688 6a36d84e bellard
        AudioState *s;
689 6a36d84e bellard
690 6a36d84e bellard
        s = AUD_init ();
691 6a36d84e bellard
        if (s) {
692 6a36d84e bellard
            for (c = soundhw; c->name; ++c) {
693 6a36d84e bellard
                if (c->enabled) {
694 6a36d84e bellard
                    if (c->isa) {
695 d537cf6c pbrook
                        c->init.init_isa (s, pic);
696 6a36d84e bellard
                    }
697 6a36d84e bellard
                    else {
698 6a36d84e bellard
                        if (pci_bus) {
699 6a36d84e bellard
                            c->init.init_pci (pci_bus, s);
700 6a36d84e bellard
                        }
701 6a36d84e bellard
                    }
702 6a36d84e bellard
                }
703 6a36d84e bellard
            }
704 6a36d84e bellard
        }
705 6a36d84e bellard
    }
706 6a36d84e bellard
}
707 6a36d84e bellard
#endif
708 6a36d84e bellard
709 d537cf6c pbrook
static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
710 a41b2ff2 pbrook
{
711 a41b2ff2 pbrook
    static int nb_ne2k = 0;
712 a41b2ff2 pbrook
713 a41b2ff2 pbrook
    if (nb_ne2k == NE2000_NB_MAX)
714 a41b2ff2 pbrook
        return;
715 d537cf6c pbrook
    isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
716 a41b2ff2 pbrook
    nb_ne2k++;
717 a41b2ff2 pbrook
}
718 a41b2ff2 pbrook
719 80cabfad bellard
/* PC hardware initialisation */
720 00f82b8a aurel32
static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
721 b881c2c6 blueswir1
                     const char *boot_device, DisplayState *ds,
722 b5ff2d6e bellard
                     const char *kernel_filename, const char *kernel_cmdline,
723 3dbbdc25 bellard
                     const char *initrd_filename,
724 a049de61 bellard
                     int pci_enabled, const char *cpu_model)
725 80cabfad bellard
{
726 80cabfad bellard
    char buf[1024];
727 642a4f96 ths
    int ret, linux_boot, i;
728 970ac5a3 bellard
    ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;
729 00f82b8a aurel32
    ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
730 970ac5a3 bellard
    int bios_size, isa_bios_size, vga_bios_size;
731 46e50e9d bellard
    PCIBus *pci_bus;
732 5c3ff3a7 pbrook
    int piix3_devfn = -1;
733 59b8ad81 bellard
    CPUState *env;
734 a41b2ff2 pbrook
    NICInfo *nd;
735 d537cf6c pbrook
    qemu_irq *cpu_irq;
736 d537cf6c pbrook
    qemu_irq *i8259;
737 e4bcb14c ths
    int index;
738 e4bcb14c ths
    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
739 e4bcb14c ths
    BlockDriverState *fd[MAX_FD];
740 d592d303 bellard
741 00f82b8a aurel32
    if (ram_size >= 0xe0000000 ) {
742 00f82b8a aurel32
        above_4g_mem_size = ram_size - 0xe0000000;
743 00f82b8a aurel32
        below_4g_mem_size = 0xe0000000;
744 00f82b8a aurel32
    } else {
745 00f82b8a aurel32
        below_4g_mem_size = ram_size;
746 00f82b8a aurel32
    }
747 00f82b8a aurel32
748 80cabfad bellard
    linux_boot = (kernel_filename != NULL);
749 80cabfad bellard
750 59b8ad81 bellard
    /* init CPUs */
751 a049de61 bellard
    if (cpu_model == NULL) {
752 a049de61 bellard
#ifdef TARGET_X86_64
753 a049de61 bellard
        cpu_model = "qemu64";
754 a049de61 bellard
#else
755 a049de61 bellard
        cpu_model = "qemu32";
756 a049de61 bellard
#endif
757 a049de61 bellard
    }
758 a049de61 bellard
    
759 59b8ad81 bellard
    for(i = 0; i < smp_cpus; i++) {
760 aaed909a bellard
        env = cpu_init(cpu_model);
761 aaed909a bellard
        if (!env) {
762 aaed909a bellard
            fprintf(stderr, "Unable to find x86 CPU definition\n");
763 aaed909a bellard
            exit(1);
764 aaed909a bellard
        }
765 59b8ad81 bellard
        if (i != 0)
766 ce5232c5 bellard
            env->halted = 1;
767 59b8ad81 bellard
        if (smp_cpus > 1) {
768 59b8ad81 bellard
            /* XXX: enable it in all cases */
769 59b8ad81 bellard
            env->cpuid_features |= CPUID_APIC;
770 59b8ad81 bellard
        }
771 59b8ad81 bellard
        qemu_register_reset(main_cpu_reset, env);
772 59b8ad81 bellard
        if (pci_enabled) {
773 59b8ad81 bellard
            apic_init(env);
774 59b8ad81 bellard
        }
775 59b8ad81 bellard
    }
776 59b8ad81 bellard
777 26fb5e48 aurel32
    vmport_init();
778 26fb5e48 aurel32
779 80cabfad bellard
    /* allocate RAM */
780 970ac5a3 bellard
    ram_addr = qemu_ram_alloc(ram_size);
781 00f82b8a aurel32
    cpu_register_physical_memory(0, below_4g_mem_size, ram_addr);
782 00f82b8a aurel32
783 00f82b8a aurel32
    /* above 4giga memory allocation */
784 00f82b8a aurel32
    if (above_4g_mem_size > 0) {
785 526ccb7a balrog
        cpu_register_physical_memory((target_phys_addr_t) 0x100000000ULL,
786 526ccb7a balrog
                                     above_4g_mem_size,
787 00f82b8a aurel32
                                     ram_addr + below_4g_mem_size);
788 00f82b8a aurel32
    }
789 80cabfad bellard
790 970ac5a3 bellard
    /* allocate VGA RAM */
791 970ac5a3 bellard
    vga_ram_addr = qemu_ram_alloc(vga_ram_size);
792 7587cf44 bellard
793 970ac5a3 bellard
    /* BIOS load */
794 1192dad8 j_mayer
    if (bios_name == NULL)
795 1192dad8 j_mayer
        bios_name = BIOS_FILENAME;
796 1192dad8 j_mayer
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
797 7587cf44 bellard
    bios_size = get_image_size(buf);
798 5fafdf24 ths
    if (bios_size <= 0 ||
799 970ac5a3 bellard
        (bios_size % 65536) != 0) {
800 7587cf44 bellard
        goto bios_error;
801 7587cf44 bellard
    }
802 970ac5a3 bellard
    bios_offset = qemu_ram_alloc(bios_size);
803 7587cf44 bellard
    ret = load_image(buf, phys_ram_base + bios_offset);
804 7587cf44 bellard
    if (ret != bios_size) {
805 7587cf44 bellard
    bios_error:
806 970ac5a3 bellard
        fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
807 80cabfad bellard
        exit(1);
808 80cabfad bellard
    }
809 7587cf44 bellard
810 80cabfad bellard
    /* VGA BIOS load */
811 de9258a8 bellard
    if (cirrus_vga_enabled) {
812 de9258a8 bellard
        snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME);
813 de9258a8 bellard
    } else {
814 de9258a8 bellard
        snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
815 de9258a8 bellard
    }
816 970ac5a3 bellard
    vga_bios_size = get_image_size(buf);
817 5fafdf24 ths
    if (vga_bios_size <= 0 || vga_bios_size > 65536)
818 970ac5a3 bellard
        goto vga_bios_error;
819 970ac5a3 bellard
    vga_bios_offset = qemu_ram_alloc(65536);
820 970ac5a3 bellard
821 7587cf44 bellard
    ret = load_image(buf, phys_ram_base + vga_bios_offset);
822 970ac5a3 bellard
    if (ret != vga_bios_size) {
823 970ac5a3 bellard
    vga_bios_error:
824 970ac5a3 bellard
        fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf);
825 970ac5a3 bellard
        exit(1);
826 970ac5a3 bellard
    }
827 970ac5a3 bellard
828 80cabfad bellard
    /* setup basic memory access */
829 5fafdf24 ths
    cpu_register_physical_memory(0xc0000, 0x10000,
830 7587cf44 bellard
                                 vga_bios_offset | IO_MEM_ROM);
831 7587cf44 bellard
832 7587cf44 bellard
    /* map the last 128KB of the BIOS in ISA space */
833 7587cf44 bellard
    isa_bios_size = bios_size;
834 7587cf44 bellard
    if (isa_bios_size > (128 * 1024))
835 7587cf44 bellard
        isa_bios_size = 128 * 1024;
836 5fafdf24 ths
    cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
837 7587cf44 bellard
                                 IO_MEM_UNASSIGNED);
838 5fafdf24 ths
    cpu_register_physical_memory(0x100000 - isa_bios_size,
839 5fafdf24 ths
                                 isa_bios_size,
840 7587cf44 bellard
                                 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
841 9ae02555 ths
842 970ac5a3 bellard
    {
843 970ac5a3 bellard
        ram_addr_t option_rom_offset;
844 970ac5a3 bellard
        int size, offset;
845 970ac5a3 bellard
846 970ac5a3 bellard
        offset = 0;
847 970ac5a3 bellard
        for (i = 0; i < nb_option_roms; i++) {
848 970ac5a3 bellard
            size = get_image_size(option_rom[i]);
849 970ac5a3 bellard
            if (size < 0) {
850 5fafdf24 ths
                fprintf(stderr, "Could not load option rom '%s'\n",
851 970ac5a3 bellard
                        option_rom[i]);
852 970ac5a3 bellard
                exit(1);
853 970ac5a3 bellard
            }
854 970ac5a3 bellard
            if (size > (0x10000 - offset))
855 970ac5a3 bellard
                goto option_rom_error;
856 970ac5a3 bellard
            option_rom_offset = qemu_ram_alloc(size);
857 970ac5a3 bellard
            ret = load_image(option_rom[i], phys_ram_base + option_rom_offset);
858 970ac5a3 bellard
            if (ret != size) {
859 970ac5a3 bellard
            option_rom_error:
860 970ac5a3 bellard
                fprintf(stderr, "Too many option ROMS\n");
861 970ac5a3 bellard
                exit(1);
862 970ac5a3 bellard
            }
863 970ac5a3 bellard
            size = (size + 4095) & ~4095;
864 970ac5a3 bellard
            cpu_register_physical_memory(0xd0000 + offset,
865 970ac5a3 bellard
                                         size, option_rom_offset | IO_MEM_ROM);
866 970ac5a3 bellard
            offset += size;
867 970ac5a3 bellard
        }
868 9ae02555 ths
    }
869 9ae02555 ths
870 7587cf44 bellard
    /* map all the bios at the top of memory */
871 5fafdf24 ths
    cpu_register_physical_memory((uint32_t)(-bios_size),
872 7587cf44 bellard
                                 bios_size, bios_offset | IO_MEM_ROM);
873 3b46e624 ths
874 80cabfad bellard
    bochs_bios_init();
875 80cabfad bellard
876 642a4f96 ths
    if (linux_boot)
877 642a4f96 ths
        load_linux(kernel_filename, initrd_filename, kernel_cmdline);
878 80cabfad bellard
879 a5b38b51 aurel32
    cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
880 d537cf6c pbrook
    i8259 = i8259_init(cpu_irq[0]);
881 d537cf6c pbrook
    ferr_irq = i8259[13];
882 d537cf6c pbrook
883 69b91039 bellard
    if (pci_enabled) {
884 d537cf6c pbrook
        pci_bus = i440fx_init(&i440fx_state, i8259);
885 8f1c91d8 ths
        piix3_devfn = piix3_init(pci_bus, -1);
886 46e50e9d bellard
    } else {
887 46e50e9d bellard
        pci_bus = NULL;
888 69b91039 bellard
    }
889 69b91039 bellard
890 80cabfad bellard
    /* init basic PC hardware */
891 b41a2cd1 bellard
    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
892 80cabfad bellard
893 f929aad6 bellard
    register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
894 f929aad6 bellard
895 1f04275e bellard
    if (cirrus_vga_enabled) {
896 1f04275e bellard
        if (pci_enabled) {
897 5fafdf24 ths
            pci_cirrus_vga_init(pci_bus,
898 5fafdf24 ths
                                ds, phys_ram_base + vga_ram_addr,
899 970ac5a3 bellard
                                vga_ram_addr, vga_ram_size);
900 1f04275e bellard
        } else {
901 5fafdf24 ths
            isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr,
902 970ac5a3 bellard
                                vga_ram_addr, vga_ram_size);
903 1f04275e bellard
        }
904 d34cab9f ths
    } else if (vmsvga_enabled) {
905 d34cab9f ths
        if (pci_enabled)
906 45e4522e balrog
            pci_vmsvga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
907 45e4522e balrog
                            vga_ram_addr, vga_ram_size);
908 d34cab9f ths
        else
909 d34cab9f ths
            fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
910 1f04275e bellard
    } else {
911 89b6b508 bellard
        if (pci_enabled) {
912 5fafdf24 ths
            pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
913 970ac5a3 bellard
                         vga_ram_addr, vga_ram_size, 0, 0);
914 89b6b508 bellard
        } else {
915 5fafdf24 ths
            isa_vga_init(ds, phys_ram_base + vga_ram_addr,
916 970ac5a3 bellard
                         vga_ram_addr, vga_ram_size);
917 89b6b508 bellard
        }
918 1f04275e bellard
    }
919 80cabfad bellard
920 d537cf6c pbrook
    rtc_state = rtc_init(0x70, i8259[8]);
921 80cabfad bellard
922 3b4366de blueswir1
    qemu_register_boot_set(pc_boot_set, rtc_state);
923 3b4366de blueswir1
924 e1a23744 bellard
    register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
925 e1a23744 bellard
    register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
926 e1a23744 bellard
927 d592d303 bellard
    if (pci_enabled) {
928 d592d303 bellard
        ioapic = ioapic_init();
929 d592d303 bellard
    }
930 d537cf6c pbrook
    pit = pit_init(0x40, i8259[0]);
931 fd06c375 bellard
    pcspk_init(pit);
932 d592d303 bellard
    if (pci_enabled) {
933 d592d303 bellard
        pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
934 d592d303 bellard
    }
935 b41a2cd1 bellard
936 8d11df9e bellard
    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
937 8d11df9e bellard
        if (serial_hds[i]) {
938 b6cd0ea1 aurel32
            serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
939 b6cd0ea1 aurel32
                        serial_hds[i]);
940 8d11df9e bellard
        }
941 8d11df9e bellard
    }
942 b41a2cd1 bellard
943 6508fe59 bellard
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
944 6508fe59 bellard
        if (parallel_hds[i]) {
945 d537cf6c pbrook
            parallel_init(parallel_io[i], i8259[parallel_irq[i]],
946 d537cf6c pbrook
                          parallel_hds[i]);
947 6508fe59 bellard
        }
948 6508fe59 bellard
    }
949 6508fe59 bellard
950 a41b2ff2 pbrook
    for(i = 0; i < nb_nics; i++) {
951 a41b2ff2 pbrook
        nd = &nd_table[i];
952 a41b2ff2 pbrook
        if (!nd->model) {
953 a41b2ff2 pbrook
            if (pci_enabled) {
954 a41b2ff2 pbrook
                nd->model = "ne2k_pci";
955 a41b2ff2 pbrook
            } else {
956 a41b2ff2 pbrook
                nd->model = "ne2k_isa";
957 a41b2ff2 pbrook
            }
958 69b91039 bellard
        }
959 a41b2ff2 pbrook
        if (strcmp(nd->model, "ne2k_isa") == 0) {
960 d537cf6c pbrook
            pc_init_ne2k_isa(nd, i8259);
961 a41b2ff2 pbrook
        } else if (pci_enabled) {
962 c4a7060c blueswir1
            if (strcmp(nd->model, "?") == 0)
963 c4a7060c blueswir1
                fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
964 abcebc7e ths
            pci_nic_init(pci_bus, nd, -1);
965 c4a7060c blueswir1
        } else if (strcmp(nd->model, "?") == 0) {
966 c4a7060c blueswir1
            fprintf(stderr, "qemu: Supported ISA NICs: ne2k_isa\n");
967 c4a7060c blueswir1
            exit(1);
968 a41b2ff2 pbrook
        } else {
969 a41b2ff2 pbrook
            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
970 a41b2ff2 pbrook
            exit(1);
971 69b91039 bellard
        }
972 a41b2ff2 pbrook
    }
973 b41a2cd1 bellard
974 e4bcb14c ths
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
975 e4bcb14c ths
        fprintf(stderr, "qemu: too many IDE bus\n");
976 e4bcb14c ths
        exit(1);
977 e4bcb14c ths
    }
978 e4bcb14c ths
979 e4bcb14c ths
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
980 e4bcb14c ths
        index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
981 e4bcb14c ths
        if (index != -1)
982 e4bcb14c ths
            hd[i] = drives_table[index].bdrv;
983 e4bcb14c ths
        else
984 e4bcb14c ths
            hd[i] = NULL;
985 e4bcb14c ths
    }
986 e4bcb14c ths
987 a41b2ff2 pbrook
    if (pci_enabled) {
988 e4bcb14c ths
        pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
989 a41b2ff2 pbrook
    } else {
990 e4bcb14c ths
        for(i = 0; i < MAX_IDE_BUS; i++) {
991 d537cf6c pbrook
            isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
992 e4bcb14c ths
                         hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
993 69b91039 bellard
        }
994 b41a2cd1 bellard
    }
995 69b91039 bellard
996 d537cf6c pbrook
    i8042_init(i8259[1], i8259[12], 0x60);
997 7c29d0c0 bellard
    DMA_init(0);
998 6a36d84e bellard
#ifdef HAS_AUDIO
999 d537cf6c pbrook
    audio_init(pci_enabled ? pci_bus : NULL, i8259);
1000 fb065187 bellard
#endif
1001 80cabfad bellard
1002 e4bcb14c ths
    for(i = 0; i < MAX_FD; i++) {
1003 e4bcb14c ths
        index = drive_get_index(IF_FLOPPY, 0, i);
1004 e4bcb14c ths
        if (index != -1)
1005 e4bcb14c ths
            fd[i] = drives_table[index].bdrv;
1006 e4bcb14c ths
        else
1007 e4bcb14c ths
            fd[i] = NULL;
1008 e4bcb14c ths
    }
1009 e4bcb14c ths
    floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1010 b41a2cd1 bellard
1011 00f82b8a aurel32
    cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1012 69b91039 bellard
1013 bb36d470 bellard
    if (pci_enabled && usb_enabled) {
1014 afcc3cdf ths
        usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1015 bb36d470 bellard
    }
1016 bb36d470 bellard
1017 6515b203 bellard
    if (pci_enabled && acpi_enabled) {
1018 3fffc223 ths
        uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1019 0ff596d0 pbrook
        i2c_bus *smbus;
1020 0ff596d0 pbrook
1021 0ff596d0 pbrook
        /* TODO: Populate SPD eeprom data.  */
1022 cf7a2fe2 aurel32
        smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1023 3fffc223 ths
        for (i = 0; i < 8; i++) {
1024 0ff596d0 pbrook
            smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
1025 3fffc223 ths
        }
1026 6515b203 bellard
    }
1027 3b46e624 ths
1028 a5954d5c bellard
    if (i440fx_state) {
1029 a5954d5c bellard
        i440fx_init_memory_mappings(i440fx_state);
1030 a5954d5c bellard
    }
1031 e4bcb14c ths
1032 7d8406be pbrook
    if (pci_enabled) {
1033 e4bcb14c ths
        int max_bus;
1034 e4bcb14c ths
        int bus, unit;
1035 7d8406be pbrook
        void *scsi;
1036 96d30e48 ths
1037 e4bcb14c ths
        max_bus = drive_get_max_bus(IF_SCSI);
1038 e4bcb14c ths
1039 e4bcb14c ths
        for (bus = 0; bus <= max_bus; bus++) {
1040 e4bcb14c ths
            scsi = lsi_scsi_init(pci_bus, -1);
1041 e4bcb14c ths
            for (unit = 0; unit < LSI_MAX_DEVS; unit++) {
1042 e4bcb14c ths
                index = drive_get_index(IF_SCSI, bus, unit);
1043 e4bcb14c ths
                if (index == -1)
1044 e4bcb14c ths
                    continue;
1045 e4bcb14c ths
                lsi_scsi_attach(scsi, drives_table[index].bdrv, unit);
1046 e4bcb14c ths
            }
1047 e4bcb14c ths
        }
1048 7d8406be pbrook
    }
1049 80cabfad bellard
}
1050 b5ff2d6e bellard
1051 00f82b8a aurel32
static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
1052 b881c2c6 blueswir1
                        const char *boot_device, DisplayState *ds,
1053 5fafdf24 ths
                        const char *kernel_filename,
1054 3dbbdc25 bellard
                        const char *kernel_cmdline,
1055 94fc95cd j_mayer
                        const char *initrd_filename,
1056 94fc95cd j_mayer
                        const char *cpu_model)
1057 3dbbdc25 bellard
{
1058 b881c2c6 blueswir1
    pc_init1(ram_size, vga_ram_size, boot_device, ds,
1059 3dbbdc25 bellard
             kernel_filename, kernel_cmdline,
1060 a049de61 bellard
             initrd_filename, 1, cpu_model);
1061 3dbbdc25 bellard
}
1062 3dbbdc25 bellard
1063 00f82b8a aurel32
static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
1064 b881c2c6 blueswir1
                        const char *boot_device, DisplayState *ds,
1065 5fafdf24 ths
                        const char *kernel_filename,
1066 3dbbdc25 bellard
                        const char *kernel_cmdline,
1067 94fc95cd j_mayer
                        const char *initrd_filename,
1068 94fc95cd j_mayer
                        const char *cpu_model)
1069 3dbbdc25 bellard
{
1070 b881c2c6 blueswir1
    pc_init1(ram_size, vga_ram_size, boot_device, ds,
1071 3dbbdc25 bellard
             kernel_filename, kernel_cmdline,
1072 a049de61 bellard
             initrd_filename, 0, cpu_model);
1073 3dbbdc25 bellard
}
1074 3dbbdc25 bellard
1075 b5ff2d6e bellard
QEMUMachine pc_machine = {
1076 a245f2e7 aurel32
    .name = "pc",
1077 a245f2e7 aurel32
    .desc = "Standard PC",
1078 a245f2e7 aurel32
    .init = pc_init_pci,
1079 a245f2e7 aurel32
    .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1080 3dbbdc25 bellard
};
1081 3dbbdc25 bellard
1082 3dbbdc25 bellard
QEMUMachine isapc_machine = {
1083 a245f2e7 aurel32
    .name = "isapc",
1084 a245f2e7 aurel32
    .desc = "ISA-only PC",
1085 a245f2e7 aurel32
    .init = pc_init_isa,
1086 a245f2e7 aurel32
    .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1087 b5ff2d6e bellard
};