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/**
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* QEMU RTL8139 emulation
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*
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* Copyright (c) 2006 Igor Kovalenko
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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* Modifications:
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* 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
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*
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* 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
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* HW revision ID changes for FreeBSD driver
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*
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* 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
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* Corrected packet transfer reassembly routine for 8139C+ mode
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* Rearranged debugging print statements
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* Implemented PCI timer interrupt (disabled by default)
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* Implemented Tally Counters, increased VM load/save version
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* Implemented IP/TCP/UDP checksum task offloading
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*
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* 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
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* Fixed MTU=1500 for produced ethernet frames
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*
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* 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
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* segmentation offloading
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* Removed slirp.h dependency
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* Added rx/tx buffer reset when enabling rx/tx operation
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*
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* 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
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* when strictly needed (required for for
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* Darwin)
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* 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
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*/
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/* For crc32 */
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#include <zlib.h> |
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#include "hw.h" |
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#include "pci.h" |
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#include "qemu-timer.h" |
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#include "net.h" |
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#include "loader.h" |
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#include "sysemu.h" |
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#include "iov.h" |
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/* debug RTL8139 card */
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//#define DEBUG_RTL8139 1
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#define PCI_FREQUENCY 33000000L |
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/* debug RTL8139 card C+ mode only */
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//#define DEBUG_RTL8139CP 1
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#define SET_MASKED(input, mask, curr) \
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( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) |
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/* arg % size for size which is a power of 2 */
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#define MOD2(input, size) \
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( ( input ) & ( size - 1 ) )
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#define ETHER_ADDR_LEN 6 |
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#define ETHER_TYPE_LEN 2 |
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#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN) |
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#define ETH_P_IP 0x0800 /* Internet Protocol packet */ |
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#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ |
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#define ETH_MTU 1500 |
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|
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#define VLAN_TCI_LEN 2 |
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#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
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#if defined (DEBUG_RTL8139)
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# define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) |
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#else
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static inline __attribute__ ((format (printf, 1, 2))) |
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int DPRINTF(const char *fmt, ...) |
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{
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return 0; |
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} |
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#endif
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/* Symbolic offsets to registers. */
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enum RTL8139_registers {
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MAC0 = 0, /* Ethernet hardware address. */ |
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MAR0 = 8, /* Multicast filter. */ |
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TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ |
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/* Dump Tally Conter control register(64bit). C+ mode only */
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TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ |
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RxBuf = 0x30,
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ChipCmd = 0x37,
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RxBufPtr = 0x38,
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RxBufAddr = 0x3A,
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IntrMask = 0x3C,
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IntrStatus = 0x3E,
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TxConfig = 0x40,
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RxConfig = 0x44,
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Timer = 0x48, /* A general-purpose counter. */ |
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RxMissed = 0x4C, /* 24 bits valid, write clears. */ |
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Cfg9346 = 0x50,
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Config0 = 0x51,
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Config1 = 0x52,
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FlashReg = 0x54,
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MediaStatus = 0x58,
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Config3 = 0x59,
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Config4 = 0x5A, /* absent on RTL-8139A */ |
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HltClk = 0x5B,
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MultiIntr = 0x5C,
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PCIRevisionID = 0x5E,
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TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ |
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BasicModeCtrl = 0x62,
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BasicModeStatus = 0x64,
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NWayAdvert = 0x66,
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NWayLPAR = 0x68,
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NWayExpansion = 0x6A,
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/* Undocumented registers, but required for proper operation. */
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FIFOTMS = 0x70, /* FIFO Control and test. */ |
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CSCR = 0x74, /* Chip Status and Configuration Register. */ |
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PARA78 = 0x78,
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PARA7c = 0x7c, /* Magic transceiver parameter register. */ |
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Config5 = 0xD8, /* absent on RTL-8139A */ |
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/* C+ mode */
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TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ |
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RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ |
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CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ |
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IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ |
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RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ |
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RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ |
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TxThresh = 0xEC, /* Early Tx threshold */ |
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}; |
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enum ClearBitMasks {
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MultiIntrClear = 0xF000,
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ChipCmdClear = 0xE2,
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Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), |
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}; |
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enum ChipCmdBits {
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CmdReset = 0x10,
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CmdRxEnb = 0x08,
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CmdTxEnb = 0x04,
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RxBufEmpty = 0x01,
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}; |
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/* C+ mode */
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enum CplusCmdBits {
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CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ |
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CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ |
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CPlusRxEnb = 0x0002,
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CPlusTxEnb = 0x0001,
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}; |
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/* Interrupt register bits, using my own meaningful names. */
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enum IntrStatusBits {
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PCIErr = 0x8000,
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PCSTimeout = 0x4000,
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RxFIFOOver = 0x40,
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RxUnderrun = 0x20,
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RxOverflow = 0x10,
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TxErr = 0x08,
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TxOK = 0x04,
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RxErr = 0x02,
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RxOK = 0x01,
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RxAckBits = RxFIFOOver | RxOverflow | RxOK, |
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}; |
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enum TxStatusBits {
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TxHostOwns = 0x2000,
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TxUnderrun = 0x4000,
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TxStatOK = 0x8000,
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TxOutOfWindow = 0x20000000,
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TxAborted = 0x40000000,
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TxCarrierLost = 0x80000000,
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}; |
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enum RxStatusBits {
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RxMulticast = 0x8000,
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RxPhysical = 0x4000,
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RxBroadcast = 0x2000,
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RxBadSymbol = 0x0020,
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RxRunt = 0x0010,
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RxTooLong = 0x0008,
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RxCRCErr = 0x0004,
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RxBadAlign = 0x0002,
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RxStatusOK = 0x0001,
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}; |
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/* Bits in RxConfig. */
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enum rx_mode_bits {
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AcceptErr = 0x20,
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AcceptRunt = 0x10,
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AcceptBroadcast = 0x08,
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AcceptMulticast = 0x04,
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AcceptMyPhys = 0x02,
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AcceptAllPhys = 0x01,
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}; |
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/* Bits in TxConfig. */
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enum tx_config_bits {
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/* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
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TxIFGShift = 24,
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TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ |
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TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ |
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TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ |
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TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ |
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TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ |
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TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ |
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TxClearAbt = (1 << 0), /* Clear abort (WO) */ |
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TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ |
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TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ |
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TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ |
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}; |
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/* Transmit Status of All Descriptors (TSAD) Register */
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enum TSAD_bits {
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TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 |
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TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 |
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TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 |
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TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 |
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TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 |
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TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 |
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TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 |
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TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 |
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TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 |
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TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 |
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TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 |
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TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 |
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TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 |
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TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 |
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TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 |
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TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 |
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}; |
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/* Bits in Config1 */
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enum Config1Bits {
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Cfg1_PM_Enable = 0x01,
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Cfg1_VPD_Enable = 0x02,
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Cfg1_PIO = 0x04,
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Cfg1_MMIO = 0x08,
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LWAKE = 0x10, /* not on 8139, 8139A */ |
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Cfg1_Driver_Load = 0x20,
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Cfg1_LED0 = 0x40,
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Cfg1_LED1 = 0x80,
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SLEEP = (1 << 1), /* only on 8139, 8139A */ |
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PWRDN = (1 << 0), /* only on 8139, 8139A */ |
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}; |
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/* Bits in Config3 */
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enum Config3Bits {
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Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ |
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Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ |
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Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ |
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Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ |
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Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ |
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Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ |
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Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ |
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Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ |
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}; |
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|
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/* Bits in Config4 */
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enum Config4Bits {
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LWPTN = (1 << 2), /* not on 8139, 8139A */ |
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}; |
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|
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/* Bits in Config5 */
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enum Config5Bits {
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Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ |
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Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ |
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Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ |
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Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ |
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Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ |
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Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ |
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Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ |
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}; |
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|
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enum RxConfigBits {
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/* rx fifo threshold */
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RxCfgFIFOShift = 13,
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RxCfgFIFONone = (7 << RxCfgFIFOShift),
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|
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/* Max DMA burst */
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RxCfgDMAShift = 8,
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RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
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|
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/* rx ring buffer length */
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RxCfgRcv8K = 0,
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RxCfgRcv16K = (1 << 11), |
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RxCfgRcv32K = (1 << 12), |
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RxCfgRcv64K = (1 << 11) | (1 << 12), |
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|
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/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
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RxNoWrap = (1 << 7), |
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}; |
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|
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/* Twister tuning parameters from RealTek.
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Completely undocumented, but required to tune bad links on some boards. */
|
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/*
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enum CSCRBits {
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CSCR_LinkOKBit = 0x0400,
|
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CSCR_LinkChangeBit = 0x0800,
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CSCR_LinkStatusBits = 0x0f000,
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CSCR_LinkDownOffCmd = 0x003c0,
|
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CSCR_LinkDownCmd = 0x0f3c0,
|
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*/
|
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enum CSCRBits {
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CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ |
| 327 |
CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ |
| 328 |
CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ |
| 329 |
CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ |
| 330 |
CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ |
| 331 |
CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ |
| 332 |
CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ |
| 333 |
CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ |
| 334 |
CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ |
| 335 |
}; |
| 336 |
|
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enum Cfg9346Bits {
|
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Cfg9346_Lock = 0x00,
|
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Cfg9346_Unlock = 0xC0,
|
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}; |
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|
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typedef enum { |
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CH_8139 = 0,
|
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CH_8139_K, |
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CH_8139A, |
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CH_8139A_G, |
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CH_8139B, |
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CH_8130, |
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CH_8139C, |
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CH_8100, |
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CH_8100B_8139D, |
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CH_8101, |
| 353 |
} chip_t; |
| 354 |
|
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enum chip_flags {
|
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HasHltClk = (1 << 0), |
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HasLWake = (1 << 1), |
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}; |
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|
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#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
|
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(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) |
| 362 |
#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) |
| 363 |
|
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#define RTL8139_PCI_REVID_8139 0x10 |
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#define RTL8139_PCI_REVID_8139CPLUS 0x20 |
| 366 |
|
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#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
|
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|
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/* Size is 64 * 16bit words */
|
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#define EEPROM_9346_ADDR_BITS 6 |
| 371 |
#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) |
| 372 |
#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) |
| 373 |
|
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enum Chip9346Operation
|
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{
|
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Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ |
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Chip9346_op_read = 0x80, /* 10 AAAAAA */ |
| 378 |
Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ |
| 379 |
Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ |
| 380 |
Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ |
| 381 |
Chip9346_op_write_all = 0x10, /* 00 01zzzz */ |
| 382 |
Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ |
| 383 |
}; |
| 384 |
|
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enum Chip9346Mode
|
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{
|
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Chip9346_none = 0,
|
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Chip9346_enter_command_mode, |
| 389 |
Chip9346_read_command, |
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Chip9346_data_read, /* from output register */
|
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Chip9346_data_write, /* to input register, then to contents at specified address */
|
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Chip9346_data_write_all, /* to input register, then filling contents */
|
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}; |
| 394 |
|
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typedef struct EEprom9346 |
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{
|
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uint16_t contents[EEPROM_9346_SIZE]; |
| 398 |
int mode;
|
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uint32_t tick; |
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uint8_t address; |
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uint16_t input; |
| 402 |
uint16_t output; |
| 403 |
|
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uint8_t eecs; |
| 405 |
uint8_t eesk; |
| 406 |
uint8_t eedi; |
| 407 |
uint8_t eedo; |
| 408 |
} EEprom9346; |
| 409 |
|
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typedef struct RTL8139TallyCounters |
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{
|
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/* Tally counters */
|
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uint64_t TxOk; |
| 414 |
uint64_t RxOk; |
| 415 |
uint64_t TxERR; |
| 416 |
uint32_t RxERR; |
| 417 |
uint16_t MissPkt; |
| 418 |
uint16_t FAE; |
| 419 |
uint32_t Tx1Col; |
| 420 |
uint32_t TxMCol; |
| 421 |
uint64_t RxOkPhy; |
| 422 |
uint64_t RxOkBrd; |
| 423 |
uint32_t RxOkMul; |
| 424 |
uint16_t TxAbt; |
| 425 |
uint16_t TxUndrn; |
| 426 |
} RTL8139TallyCounters; |
| 427 |
|
| 428 |
/* Clears all tally counters */
|
| 429 |
static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); |
| 430 |
|
| 431 |
/* Writes tally counters to specified physical memory address */
|
| 432 |
static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters); |
| 433 |
|
| 434 |
typedef struct RTL8139State { |
| 435 |
PCIDevice dev; |
| 436 |
uint8_t phys[8]; /* mac address */ |
| 437 |
uint8_t mult[8]; /* multicast mask array */ |
| 438 |
|
| 439 |
uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ |
| 440 |
uint32_t TxAddr[4]; /* TxAddr0 */ |
| 441 |
uint32_t RxBuf; /* Receive buffer */
|
| 442 |
uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
|
| 443 |
uint32_t RxBufPtr; |
| 444 |
uint32_t RxBufAddr; |
| 445 |
|
| 446 |
uint16_t IntrStatus; |
| 447 |
uint16_t IntrMask; |
| 448 |
|
| 449 |
uint32_t TxConfig; |
| 450 |
uint32_t RxConfig; |
| 451 |
uint32_t RxMissed; |
| 452 |
|
| 453 |
uint16_t CSCR; |
| 454 |
|
| 455 |
uint8_t Cfg9346; |
| 456 |
uint8_t Config0; |
| 457 |
uint8_t Config1; |
| 458 |
uint8_t Config3; |
| 459 |
uint8_t Config4; |
| 460 |
uint8_t Config5; |
| 461 |
|
| 462 |
uint8_t clock_enabled; |
| 463 |
uint8_t bChipCmdState; |
| 464 |
|
| 465 |
uint16_t MultiIntr; |
| 466 |
|
| 467 |
uint16_t BasicModeCtrl; |
| 468 |
uint16_t BasicModeStatus; |
| 469 |
uint16_t NWayAdvert; |
| 470 |
uint16_t NWayLPAR; |
| 471 |
uint16_t NWayExpansion; |
| 472 |
|
| 473 |
uint16_t CpCmd; |
| 474 |
uint8_t TxThresh; |
| 475 |
|
| 476 |
NICState *nic; |
| 477 |
NICConf conf; |
| 478 |
int rtl8139_mmio_io_addr;
|
| 479 |
|
| 480 |
/* C ring mode */
|
| 481 |
uint32_t currTxDesc; |
| 482 |
|
| 483 |
/* C+ mode */
|
| 484 |
uint32_t cplus_enabled; |
| 485 |
|
| 486 |
uint32_t currCPlusRxDesc; |
| 487 |
uint32_t currCPlusTxDesc; |
| 488 |
|
| 489 |
uint32_t RxRingAddrLO; |
| 490 |
uint32_t RxRingAddrHI; |
| 491 |
|
| 492 |
EEprom9346 eeprom; |
| 493 |
|
| 494 |
uint32_t TCTR; |
| 495 |
uint32_t TimerInt; |
| 496 |
int64_t TCTR_base; |
| 497 |
|
| 498 |
/* Tally counters */
|
| 499 |
RTL8139TallyCounters tally_counters; |
| 500 |
|
| 501 |
/* Non-persistent data */
|
| 502 |
uint8_t *cplus_txbuffer; |
| 503 |
int cplus_txbuffer_len;
|
| 504 |
int cplus_txbuffer_offset;
|
| 505 |
|
| 506 |
/* PCI interrupt timer */
|
| 507 |
QEMUTimer *timer; |
| 508 |
int64_t TimerExpire; |
| 509 |
|
| 510 |
/* Support migration to/from old versions */
|
| 511 |
int rtl8139_mmio_io_addr_dummy;
|
| 512 |
} RTL8139State; |
| 513 |
|
| 514 |
static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time); |
| 515 |
|
| 516 |
static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) |
| 517 |
{
|
| 518 |
DPRINTF("eeprom command 0x%02x\n", command);
|
| 519 |
|
| 520 |
switch (command & Chip9346_op_mask)
|
| 521 |
{
|
| 522 |
case Chip9346_op_read:
|
| 523 |
{
|
| 524 |
eeprom->address = command & EEPROM_9346_ADDR_MASK; |
| 525 |
eeprom->output = eeprom->contents[eeprom->address]; |
| 526 |
eeprom->eedo = 0;
|
| 527 |
eeprom->tick = 0;
|
| 528 |
eeprom->mode = Chip9346_data_read; |
| 529 |
DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
|
| 530 |
eeprom->address, eeprom->output); |
| 531 |
} |
| 532 |
break;
|
| 533 |
|
| 534 |
case Chip9346_op_write:
|
| 535 |
{
|
| 536 |
eeprom->address = command & EEPROM_9346_ADDR_MASK; |
| 537 |
eeprom->input = 0;
|
| 538 |
eeprom->tick = 0;
|
| 539 |
eeprom->mode = Chip9346_none; /* Chip9346_data_write */
|
| 540 |
DPRINTF("eeprom begin write to address 0x%02x\n",
|
| 541 |
eeprom->address); |
| 542 |
} |
| 543 |
break;
|
| 544 |
default:
|
| 545 |
eeprom->mode = Chip9346_none; |
| 546 |
switch (command & Chip9346_op_ext_mask)
|
| 547 |
{
|
| 548 |
case Chip9346_op_write_enable:
|
| 549 |
DPRINTF("eeprom write enabled\n");
|
| 550 |
break;
|
| 551 |
case Chip9346_op_write_all:
|
| 552 |
DPRINTF("eeprom begin write all\n");
|
| 553 |
break;
|
| 554 |
case Chip9346_op_write_disable:
|
| 555 |
DPRINTF("eeprom write disabled\n");
|
| 556 |
break;
|
| 557 |
} |
| 558 |
break;
|
| 559 |
} |
| 560 |
} |
| 561 |
|
| 562 |
static void prom9346_shift_clock(EEprom9346 *eeprom) |
| 563 |
{
|
| 564 |
int bit = eeprom->eedi?1:0; |
| 565 |
|
| 566 |
++ eeprom->tick; |
| 567 |
|
| 568 |
DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
|
| 569 |
eeprom->eedo); |
| 570 |
|
| 571 |
switch (eeprom->mode)
|
| 572 |
{
|
| 573 |
case Chip9346_enter_command_mode:
|
| 574 |
if (bit)
|
| 575 |
{
|
| 576 |
eeprom->mode = Chip9346_read_command; |
| 577 |
eeprom->tick = 0;
|
| 578 |
eeprom->input = 0;
|
| 579 |
DPRINTF("eeprom: +++ synchronized, begin command read\n");
|
| 580 |
} |
| 581 |
break;
|
| 582 |
|
| 583 |
case Chip9346_read_command:
|
| 584 |
eeprom->input = (eeprom->input << 1) | (bit & 1); |
| 585 |
if (eeprom->tick == 8) |
| 586 |
{
|
| 587 |
prom9346_decode_command(eeprom, eeprom->input & 0xff);
|
| 588 |
} |
| 589 |
break;
|
| 590 |
|
| 591 |
case Chip9346_data_read:
|
| 592 |
eeprom->eedo = (eeprom->output & 0x8000)?1:0; |
| 593 |
eeprom->output <<= 1;
|
| 594 |
if (eeprom->tick == 16) |
| 595 |
{
|
| 596 |
#if 1 |
| 597 |
// the FreeBSD drivers (rl and re) don't explicitly toggle
|
| 598 |
// CS between reads (or does setting Cfg9346 to 0 count too?),
|
| 599 |
// so we need to enter wait-for-command state here
|
| 600 |
eeprom->mode = Chip9346_enter_command_mode; |
| 601 |
eeprom->input = 0;
|
| 602 |
eeprom->tick = 0;
|
| 603 |
|
| 604 |
DPRINTF("eeprom: +++ end of read, awaiting next command\n");
|
| 605 |
#else
|
| 606 |
// original behaviour
|
| 607 |
++eeprom->address; |
| 608 |
eeprom->address &= EEPROM_9346_ADDR_MASK; |
| 609 |
eeprom->output = eeprom->contents[eeprom->address]; |
| 610 |
eeprom->tick = 0;
|
| 611 |
|
| 612 |
DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
|
| 613 |
eeprom->address, eeprom->output); |
| 614 |
#endif
|
| 615 |
} |
| 616 |
break;
|
| 617 |
|
| 618 |
case Chip9346_data_write:
|
| 619 |
eeprom->input = (eeprom->input << 1) | (bit & 1); |
| 620 |
if (eeprom->tick == 16) |
| 621 |
{
|
| 622 |
DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
|
| 623 |
eeprom->address, eeprom->input); |
| 624 |
|
| 625 |
eeprom->contents[eeprom->address] = eeprom->input; |
| 626 |
eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
|
| 627 |
eeprom->tick = 0;
|
| 628 |
eeprom->input = 0;
|
| 629 |
} |
| 630 |
break;
|
| 631 |
|
| 632 |
case Chip9346_data_write_all:
|
| 633 |
eeprom->input = (eeprom->input << 1) | (bit & 1); |
| 634 |
if (eeprom->tick == 16) |
| 635 |
{
|
| 636 |
int i;
|
| 637 |
for (i = 0; i < EEPROM_9346_SIZE; i++) |
| 638 |
{
|
| 639 |
eeprom->contents[i] = eeprom->input; |
| 640 |
} |
| 641 |
DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
|
| 642 |
|
| 643 |
eeprom->mode = Chip9346_enter_command_mode; |
| 644 |
eeprom->tick = 0;
|
| 645 |
eeprom->input = 0;
|
| 646 |
} |
| 647 |
break;
|
| 648 |
|
| 649 |
default:
|
| 650 |
break;
|
| 651 |
} |
| 652 |
} |
| 653 |
|
| 654 |
static int prom9346_get_wire(RTL8139State *s) |
| 655 |
{
|
| 656 |
EEprom9346 *eeprom = &s->eeprom; |
| 657 |
if (!eeprom->eecs)
|
| 658 |
return 0; |
| 659 |
|
| 660 |
return eeprom->eedo;
|
| 661 |
} |
| 662 |
|
| 663 |
/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
|
| 664 |
static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) |
| 665 |
{
|
| 666 |
EEprom9346 *eeprom = &s->eeprom; |
| 667 |
uint8_t old_eecs = eeprom->eecs; |
| 668 |
uint8_t old_eesk = eeprom->eesk; |
| 669 |
|
| 670 |
eeprom->eecs = eecs; |
| 671 |
eeprom->eesk = eesk; |
| 672 |
eeprom->eedi = eedi; |
| 673 |
|
| 674 |
DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
|
| 675 |
eeprom->eesk, eeprom->eedi, eeprom->eedo); |
| 676 |
|
| 677 |
if (!old_eecs && eecs)
|
| 678 |
{
|
| 679 |
/* Synchronize start */
|
| 680 |
eeprom->tick = 0;
|
| 681 |
eeprom->input = 0;
|
| 682 |
eeprom->output = 0;
|
| 683 |
eeprom->mode = Chip9346_enter_command_mode; |
| 684 |
|
| 685 |
DPRINTF("=== eeprom: begin access, enter command mode\n");
|
| 686 |
} |
| 687 |
|
| 688 |
if (!eecs)
|
| 689 |
{
|
| 690 |
DPRINTF("=== eeprom: end access\n");
|
| 691 |
return;
|
| 692 |
} |
| 693 |
|
| 694 |
if (!old_eesk && eesk)
|
| 695 |
{
|
| 696 |
/* SK front rules */
|
| 697 |
prom9346_shift_clock(eeprom); |
| 698 |
} |
| 699 |
} |
| 700 |
|
| 701 |
static void rtl8139_update_irq(RTL8139State *s) |
| 702 |
{
|
| 703 |
int isr;
|
| 704 |
isr = (s->IntrStatus & s->IntrMask) & 0xffff;
|
| 705 |
|
| 706 |
DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, |
| 707 |
s->IntrMask); |
| 708 |
|
| 709 |
qemu_set_irq(s->dev.irq[0], (isr != 0)); |
| 710 |
} |
| 711 |
|
| 712 |
#define POLYNOMIAL 0x04c11db6 |
| 713 |
|
| 714 |
/* From FreeBSD */
|
| 715 |
/* XXX: optimize */
|
| 716 |
static int compute_mcast_idx(const uint8_t *ep) |
| 717 |
{
|
| 718 |
uint32_t crc; |
| 719 |
int carry, i, j;
|
| 720 |
uint8_t b; |
| 721 |
|
| 722 |
crc = 0xffffffff;
|
| 723 |
for (i = 0; i < 6; i++) { |
| 724 |
b = *ep++; |
| 725 |
for (j = 0; j < 8; j++) { |
| 726 |
carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
| 727 |
crc <<= 1;
|
| 728 |
b >>= 1;
|
| 729 |
if (carry)
|
| 730 |
crc = ((crc ^ POLYNOMIAL) | carry); |
| 731 |
} |
| 732 |
} |
| 733 |
return (crc >> 26); |
| 734 |
} |
| 735 |
|
| 736 |
static int rtl8139_RxWrap(RTL8139State *s) |
| 737 |
{
|
| 738 |
/* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
|
| 739 |
return (s->RxConfig & (1 << 7)); |
| 740 |
} |
| 741 |
|
| 742 |
static int rtl8139_receiver_enabled(RTL8139State *s) |
| 743 |
{
|
| 744 |
return s->bChipCmdState & CmdRxEnb;
|
| 745 |
} |
| 746 |
|
| 747 |
static int rtl8139_transmitter_enabled(RTL8139State *s) |
| 748 |
{
|
| 749 |
return s->bChipCmdState & CmdTxEnb;
|
| 750 |
} |
| 751 |
|
| 752 |
static int rtl8139_cp_receiver_enabled(RTL8139State *s) |
| 753 |
{
|
| 754 |
return s->CpCmd & CPlusRxEnb;
|
| 755 |
} |
| 756 |
|
| 757 |
static int rtl8139_cp_transmitter_enabled(RTL8139State *s) |
| 758 |
{
|
| 759 |
return s->CpCmd & CPlusTxEnb;
|
| 760 |
} |
| 761 |
|
| 762 |
static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) |
| 763 |
{
|
| 764 |
if (s->RxBufAddr + size > s->RxBufferSize)
|
| 765 |
{
|
| 766 |
int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
|
| 767 |
|
| 768 |
/* write packet data */
|
| 769 |
if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) |
| 770 |
{
|
| 771 |
DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
|
| 772 |
|
| 773 |
if (size > wrapped)
|
| 774 |
{
|
| 775 |
cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, |
| 776 |
buf, size-wrapped ); |
| 777 |
} |
| 778 |
|
| 779 |
/* reset buffer pointer */
|
| 780 |
s->RxBufAddr = 0;
|
| 781 |
|
| 782 |
cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, |
| 783 |
buf + (size-wrapped), wrapped ); |
| 784 |
|
| 785 |
s->RxBufAddr = wrapped; |
| 786 |
|
| 787 |
return;
|
| 788 |
} |
| 789 |
} |
| 790 |
|
| 791 |
/* non-wrapping path or overwrapping enabled */
|
| 792 |
cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size ); |
| 793 |
|
| 794 |
s->RxBufAddr += size; |
| 795 |
} |
| 796 |
|
| 797 |
#define MIN_BUF_SIZE 60 |
| 798 |
static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high) |
| 799 |
{
|
| 800 |
#if TARGET_PHYS_ADDR_BITS > 32 |
| 801 |
return low | ((target_phys_addr_t)high << 32); |
| 802 |
#else
|
| 803 |
return low;
|
| 804 |
#endif
|
| 805 |
} |
| 806 |
|
| 807 |
static int rtl8139_can_receive(VLANClientState *nc) |
| 808 |
{
|
| 809 |
RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
| 810 |
int avail;
|
| 811 |
|
| 812 |
/* Receive (drop) packets if card is disabled. */
|
| 813 |
if (!s->clock_enabled)
|
| 814 |
return 1; |
| 815 |
if (!rtl8139_receiver_enabled(s))
|
| 816 |
return 1; |
| 817 |
|
| 818 |
if (rtl8139_cp_receiver_enabled(s)) {
|
| 819 |
/* ??? Flow control not implemented in c+ mode.
|
| 820 |
This is a hack to work around slirp deficiencies anyway. */
|
| 821 |
return 1; |
| 822 |
} else {
|
| 823 |
avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, |
| 824 |
s->RxBufferSize); |
| 825 |
return (avail == 0 || avail >= 1514); |
| 826 |
} |
| 827 |
} |
| 828 |
|
| 829 |
static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) |
| 830 |
{
|
| 831 |
RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
| 832 |
/* size is the length of the buffer passed to the driver */
|
| 833 |
int size = size_;
|
| 834 |
const uint8_t *dot1q_buf = NULL; |
| 835 |
|
| 836 |
uint32_t packet_header = 0;
|
| 837 |
|
| 838 |
uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; |
| 839 |
static const uint8_t broadcast_macaddr[6] = |
| 840 |
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
| 841 |
|
| 842 |
DPRINTF(">>> received len=%d\n", size);
|
| 843 |
|
| 844 |
/* test if board clock is stopped */
|
| 845 |
if (!s->clock_enabled)
|
| 846 |
{
|
| 847 |
DPRINTF("stopped ==========================\n");
|
| 848 |
return -1; |
| 849 |
} |
| 850 |
|
| 851 |
/* first check if receiver is enabled */
|
| 852 |
|
| 853 |
if (!rtl8139_receiver_enabled(s))
|
| 854 |
{
|
| 855 |
DPRINTF("receiver disabled ================\n");
|
| 856 |
return -1; |
| 857 |
} |
| 858 |
|
| 859 |
/* XXX: check this */
|
| 860 |
if (s->RxConfig & AcceptAllPhys) {
|
| 861 |
/* promiscuous: receive all */
|
| 862 |
DPRINTF(">>> packet received in promiscuous mode\n");
|
| 863 |
|
| 864 |
} else {
|
| 865 |
if (!memcmp(buf, broadcast_macaddr, 6)) { |
| 866 |
/* broadcast address */
|
| 867 |
if (!(s->RxConfig & AcceptBroadcast))
|
| 868 |
{
|
| 869 |
DPRINTF(">>> broadcast packet rejected\n");
|
| 870 |
|
| 871 |
/* update tally counter */
|
| 872 |
++s->tally_counters.RxERR; |
| 873 |
|
| 874 |
return size;
|
| 875 |
} |
| 876 |
|
| 877 |
packet_header |= RxBroadcast; |
| 878 |
|
| 879 |
DPRINTF(">>> broadcast packet received\n");
|
| 880 |
|
| 881 |
/* update tally counter */
|
| 882 |
++s->tally_counters.RxOkBrd; |
| 883 |
|
| 884 |
} else if (buf[0] & 0x01) { |
| 885 |
/* multicast */
|
| 886 |
if (!(s->RxConfig & AcceptMulticast))
|
| 887 |
{
|
| 888 |
DPRINTF(">>> multicast packet rejected\n");
|
| 889 |
|
| 890 |
/* update tally counter */
|
| 891 |
++s->tally_counters.RxERR; |
| 892 |
|
| 893 |
return size;
|
| 894 |
} |
| 895 |
|
| 896 |
int mcast_idx = compute_mcast_idx(buf);
|
| 897 |
|
| 898 |
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
| 899 |
{
|
| 900 |
DPRINTF(">>> multicast address mismatch\n");
|
| 901 |
|
| 902 |
/* update tally counter */
|
| 903 |
++s->tally_counters.RxERR; |
| 904 |
|
| 905 |
return size;
|
| 906 |
} |
| 907 |
|
| 908 |
packet_header |= RxMulticast; |
| 909 |
|
| 910 |
DPRINTF(">>> multicast packet received\n");
|
| 911 |
|
| 912 |
/* update tally counter */
|
| 913 |
++s->tally_counters.RxOkMul; |
| 914 |
|
| 915 |
} else if (s->phys[0] == buf[0] && |
| 916 |
s->phys[1] == buf[1] && |
| 917 |
s->phys[2] == buf[2] && |
| 918 |
s->phys[3] == buf[3] && |
| 919 |
s->phys[4] == buf[4] && |
| 920 |
s->phys[5] == buf[5]) { |
| 921 |
/* match */
|
| 922 |
if (!(s->RxConfig & AcceptMyPhys))
|
| 923 |
{
|
| 924 |
DPRINTF(">>> rejecting physical address matching packet\n");
|
| 925 |
|
| 926 |
/* update tally counter */
|
| 927 |
++s->tally_counters.RxERR; |
| 928 |
|
| 929 |
return size;
|
| 930 |
} |
| 931 |
|
| 932 |
packet_header |= RxPhysical; |
| 933 |
|
| 934 |
DPRINTF(">>> physical address matching packet received\n");
|
| 935 |
|
| 936 |
/* update tally counter */
|
| 937 |
++s->tally_counters.RxOkPhy; |
| 938 |
|
| 939 |
} else {
|
| 940 |
|
| 941 |
DPRINTF(">>> unknown packet\n");
|
| 942 |
|
| 943 |
/* update tally counter */
|
| 944 |
++s->tally_counters.RxERR; |
| 945 |
|
| 946 |
return size;
|
| 947 |
} |
| 948 |
} |
| 949 |
|
| 950 |
/* if too small buffer, then expand it
|
| 951 |
* Include some tailroom in case a vlan tag is later removed. */
|
| 952 |
if (size < MIN_BUF_SIZE + VLAN_HLEN) {
|
| 953 |
memcpy(buf1, buf, size); |
| 954 |
memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
|
| 955 |
buf = buf1; |
| 956 |
if (size < MIN_BUF_SIZE) {
|
| 957 |
size = MIN_BUF_SIZE; |
| 958 |
} |
| 959 |
} |
| 960 |
|
| 961 |
if (rtl8139_cp_receiver_enabled(s))
|
| 962 |
{
|
| 963 |
DPRINTF("in C+ Rx mode ================\n");
|
| 964 |
|
| 965 |
/* begin C+ receiver mode */
|
| 966 |
|
| 967 |
/* w0 ownership flag */
|
| 968 |
#define CP_RX_OWN (1<<31) |
| 969 |
/* w0 end of ring flag */
|
| 970 |
#define CP_RX_EOR (1<<30) |
| 971 |
/* w0 bits 0...12 : buffer size */
|
| 972 |
#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) |
| 973 |
/* w1 tag available flag */
|
| 974 |
#define CP_RX_TAVA (1<<16) |
| 975 |
/* w1 bits 0...15 : VLAN tag */
|
| 976 |
#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) |
| 977 |
/* w2 low 32bit of Rx buffer ptr */
|
| 978 |
/* w3 high 32bit of Rx buffer ptr */
|
| 979 |
|
| 980 |
int descriptor = s->currCPlusRxDesc;
|
| 981 |
target_phys_addr_t cplus_rx_ring_desc; |
| 982 |
|
| 983 |
cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); |
| 984 |
cplus_rx_ring_desc += 16 * descriptor;
|
| 985 |
|
| 986 |
DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
|
| 987 |
"%08x %08x = "TARGET_FMT_plx"\n", descriptor, s->RxRingAddrHI, |
| 988 |
s->RxRingAddrLO, cplus_rx_ring_desc); |
| 989 |
|
| 990 |
uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; |
| 991 |
|
| 992 |
cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
| 993 |
rxdw0 = le32_to_cpu(val); |
| 994 |
cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
| 995 |
rxdw1 = le32_to_cpu(val); |
| 996 |
cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4); |
| 997 |
rxbufLO = le32_to_cpu(val); |
| 998 |
cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4); |
| 999 |
rxbufHI = le32_to_cpu(val); |
| 1000 |
|
| 1001 |
DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
|
| 1002 |
descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); |
| 1003 |
|
| 1004 |
if (!(rxdw0 & CP_RX_OWN))
|
| 1005 |
{
|
| 1006 |
DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
|
| 1007 |
descriptor); |
| 1008 |
|
| 1009 |
s->IntrStatus |= RxOverflow; |
| 1010 |
++s->RxMissed; |
| 1011 |
|
| 1012 |
/* update tally counter */
|
| 1013 |
++s->tally_counters.RxERR; |
| 1014 |
++s->tally_counters.MissPkt; |
| 1015 |
|
| 1016 |
rtl8139_update_irq(s); |
| 1017 |
return size_;
|
| 1018 |
} |
| 1019 |
|
| 1020 |
uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; |
| 1021 |
|
| 1022 |
/* write VLAN info to descriptor variables. */
|
| 1023 |
if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
|
| 1024 |
&buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
|
| 1025 |
dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
|
| 1026 |
size -= VLAN_HLEN; |
| 1027 |
/* if too small buffer, use the tailroom added duing expansion */
|
| 1028 |
if (size < MIN_BUF_SIZE) {
|
| 1029 |
size = MIN_BUF_SIZE; |
| 1030 |
} |
| 1031 |
|
| 1032 |
rxdw1 &= ~CP_RX_VLAN_TAG_MASK; |
| 1033 |
/* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
|
| 1034 |
rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *) |
| 1035 |
&dot1q_buf[ETHER_TYPE_LEN]); |
| 1036 |
|
| 1037 |
DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", |
| 1038 |
be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN])); |
| 1039 |
} else {
|
| 1040 |
/* reset VLAN tag flag */
|
| 1041 |
rxdw1 &= ~CP_RX_TAVA; |
| 1042 |
} |
| 1043 |
|
| 1044 |
/* TODO: scatter the packet over available receive ring descriptors space */
|
| 1045 |
|
| 1046 |
if (size+4 > rx_space) |
| 1047 |
{
|
| 1048 |
DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
|
| 1049 |
descriptor, rx_space, size); |
| 1050 |
|
| 1051 |
s->IntrStatus |= RxOverflow; |
| 1052 |
++s->RxMissed; |
| 1053 |
|
| 1054 |
/* update tally counter */
|
| 1055 |
++s->tally_counters.RxERR; |
| 1056 |
++s->tally_counters.MissPkt; |
| 1057 |
|
| 1058 |
rtl8139_update_irq(s); |
| 1059 |
return size_;
|
| 1060 |
} |
| 1061 |
|
| 1062 |
target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); |
| 1063 |
|
| 1064 |
/* receive/copy to target memory */
|
| 1065 |
if (dot1q_buf) {
|
| 1066 |
cpu_physical_memory_write(rx_addr, buf, 2 * ETHER_ADDR_LEN);
|
| 1067 |
cpu_physical_memory_write(rx_addr + 2 * ETHER_ADDR_LEN,
|
| 1068 |
buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
|
| 1069 |
size - 2 * ETHER_ADDR_LEN);
|
| 1070 |
} else {
|
| 1071 |
cpu_physical_memory_write(rx_addr, buf, size); |
| 1072 |
} |
| 1073 |
|
| 1074 |
if (s->CpCmd & CPlusRxChkSum)
|
| 1075 |
{
|
| 1076 |
/* do some packet checksumming */
|
| 1077 |
} |
| 1078 |
|
| 1079 |
/* write checksum */
|
| 1080 |
val = cpu_to_le32(crc32(0, buf, size_));
|
| 1081 |
cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
|
| 1082 |
|
| 1083 |
/* first segment of received packet flag */
|
| 1084 |
#define CP_RX_STATUS_FS (1<<29) |
| 1085 |
/* last segment of received packet flag */
|
| 1086 |
#define CP_RX_STATUS_LS (1<<28) |
| 1087 |
/* multicast packet flag */
|
| 1088 |
#define CP_RX_STATUS_MAR (1<<26) |
| 1089 |
/* physical-matching packet flag */
|
| 1090 |
#define CP_RX_STATUS_PAM (1<<25) |
| 1091 |
/* broadcast packet flag */
|
| 1092 |
#define CP_RX_STATUS_BAR (1<<24) |
| 1093 |
/* runt packet flag */
|
| 1094 |
#define CP_RX_STATUS_RUNT (1<<19) |
| 1095 |
/* crc error flag */
|
| 1096 |
#define CP_RX_STATUS_CRC (1<<18) |
| 1097 |
/* IP checksum error flag */
|
| 1098 |
#define CP_RX_STATUS_IPF (1<<15) |
| 1099 |
/* UDP checksum error flag */
|
| 1100 |
#define CP_RX_STATUS_UDPF (1<<14) |
| 1101 |
/* TCP checksum error flag */
|
| 1102 |
#define CP_RX_STATUS_TCPF (1<<13) |
| 1103 |
|
| 1104 |
/* transfer ownership to target */
|
| 1105 |
rxdw0 &= ~CP_RX_OWN; |
| 1106 |
|
| 1107 |
/* set first segment bit */
|
| 1108 |
rxdw0 |= CP_RX_STATUS_FS; |
| 1109 |
|
| 1110 |
/* set last segment bit */
|
| 1111 |
rxdw0 |= CP_RX_STATUS_LS; |
| 1112 |
|
| 1113 |
/* set received packet type flags */
|
| 1114 |
if (packet_header & RxBroadcast)
|
| 1115 |
rxdw0 |= CP_RX_STATUS_BAR; |
| 1116 |
if (packet_header & RxMulticast)
|
| 1117 |
rxdw0 |= CP_RX_STATUS_MAR; |
| 1118 |
if (packet_header & RxPhysical)
|
| 1119 |
rxdw0 |= CP_RX_STATUS_PAM; |
| 1120 |
|
| 1121 |
/* set received size */
|
| 1122 |
rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; |
| 1123 |
rxdw0 |= (size+4);
|
| 1124 |
|
| 1125 |
/* update ring data */
|
| 1126 |
val = cpu_to_le32(rxdw0); |
| 1127 |
cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
| 1128 |
val = cpu_to_le32(rxdw1); |
| 1129 |
cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
| 1130 |
|
| 1131 |
/* update tally counter */
|
| 1132 |
++s->tally_counters.RxOk; |
| 1133 |
|
| 1134 |
/* seek to next Rx descriptor */
|
| 1135 |
if (rxdw0 & CP_RX_EOR)
|
| 1136 |
{
|
| 1137 |
s->currCPlusRxDesc = 0;
|
| 1138 |
} |
| 1139 |
else
|
| 1140 |
{
|
| 1141 |
++s->currCPlusRxDesc; |
| 1142 |
} |
| 1143 |
|
| 1144 |
DPRINTF("done C+ Rx mode ----------------\n");
|
| 1145 |
|
| 1146 |
} |
| 1147 |
else
|
| 1148 |
{
|
| 1149 |
DPRINTF("in ring Rx mode ================\n");
|
| 1150 |
|
| 1151 |
/* begin ring receiver mode */
|
| 1152 |
int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
|
| 1153 |
|
| 1154 |
/* if receiver buffer is empty then avail == 0 */
|
| 1155 |
|
| 1156 |
if (avail != 0 && size + 8 >= avail) |
| 1157 |
{
|
| 1158 |
DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
|
| 1159 |
"read 0x%04x === available 0x%04x need 0x%04x\n",
|
| 1160 |
s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
|
| 1161 |
|
| 1162 |
s->IntrStatus |= RxOverflow; |
| 1163 |
++s->RxMissed; |
| 1164 |
rtl8139_update_irq(s); |
| 1165 |
return size_;
|
| 1166 |
} |
| 1167 |
|
| 1168 |
packet_header |= RxStatusOK; |
| 1169 |
|
| 1170 |
packet_header |= (((size+4) << 16) & 0xffff0000); |
| 1171 |
|
| 1172 |
/* write header */
|
| 1173 |
uint32_t val = cpu_to_le32(packet_header); |
| 1174 |
|
| 1175 |
rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
| 1176 |
|
| 1177 |
rtl8139_write_buffer(s, buf, size); |
| 1178 |
|
| 1179 |
/* write checksum */
|
| 1180 |
val = cpu_to_le32(crc32(0, buf, size));
|
| 1181 |
rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
| 1182 |
|
| 1183 |
/* correct buffer write pointer */
|
| 1184 |
s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize); |
| 1185 |
|
| 1186 |
/* now we can signal we have received something */
|
| 1187 |
|
| 1188 |
DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
|
| 1189 |
s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); |
| 1190 |
} |
| 1191 |
|
| 1192 |
s->IntrStatus |= RxOK; |
| 1193 |
|
| 1194 |
if (do_interrupt)
|
| 1195 |
{
|
| 1196 |
rtl8139_update_irq(s); |
| 1197 |
} |
| 1198 |
|
| 1199 |
return size_;
|
| 1200 |
} |
| 1201 |
|
| 1202 |
static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size) |
| 1203 |
{
|
| 1204 |
return rtl8139_do_receive(nc, buf, size, 1); |
| 1205 |
} |
| 1206 |
|
| 1207 |
static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) |
| 1208 |
{
|
| 1209 |
s->RxBufferSize = bufferSize; |
| 1210 |
s->RxBufPtr = 0;
|
| 1211 |
s->RxBufAddr = 0;
|
| 1212 |
} |
| 1213 |
|
| 1214 |
static void rtl8139_reset(DeviceState *d) |
| 1215 |
{
|
| 1216 |
RTL8139State *s = container_of(d, RTL8139State, dev.qdev); |
| 1217 |
int i;
|
| 1218 |
|
| 1219 |
/* restore MAC address */
|
| 1220 |
memcpy(s->phys, s->conf.macaddr.a, 6);
|
| 1221 |
|
| 1222 |
/* reset interrupt mask */
|
| 1223 |
s->IntrStatus = 0;
|
| 1224 |
s->IntrMask = 0;
|
| 1225 |
|
| 1226 |
rtl8139_update_irq(s); |
| 1227 |
|
| 1228 |
/* mark all status registers as owned by host */
|
| 1229 |
for (i = 0; i < 4; ++i) |
| 1230 |
{
|
| 1231 |
s->TxStatus[i] = TxHostOwns; |
| 1232 |
} |
| 1233 |
|
| 1234 |
s->currTxDesc = 0;
|
| 1235 |
s->currCPlusRxDesc = 0;
|
| 1236 |
s->currCPlusTxDesc = 0;
|
| 1237 |
|
| 1238 |
s->RxRingAddrLO = 0;
|
| 1239 |
s->RxRingAddrHI = 0;
|
| 1240 |
|
| 1241 |
s->RxBuf = 0;
|
| 1242 |
|
| 1243 |
rtl8139_reset_rxring(s, 8192);
|
| 1244 |
|
| 1245 |
/* ACK the reset */
|
| 1246 |
s->TxConfig = 0;
|
| 1247 |
|
| 1248 |
#if 0
|
| 1249 |
// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
|
| 1250 |
s->clock_enabled = 0;
|
| 1251 |
#else
|
| 1252 |
s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake |
| 1253 |
s->clock_enabled = 1;
|
| 1254 |
#endif
|
| 1255 |
|
| 1256 |
s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
|
| 1257 |
|
| 1258 |
/* set initial state data */
|
| 1259 |
s->Config0 = 0x0; /* No boot ROM */ |
| 1260 |
s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ |
| 1261 |
s->Config3 = 0x1; /* fast back-to-back compatible */ |
| 1262 |
s->Config5 = 0x0;
|
| 1263 |
|
| 1264 |
s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; |
| 1265 |
|
| 1266 |
s->CpCmd = 0x0; /* reset C+ mode */ |
| 1267 |
s->cplus_enabled = 0;
|
| 1268 |
|
| 1269 |
|
| 1270 |
// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
|
| 1271 |
// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
|
| 1272 |
s->BasicModeCtrl = 0x1000; // autonegotiation |
| 1273 |
|
| 1274 |
s->BasicModeStatus = 0x7809;
|
| 1275 |
//s->BasicModeStatus |= 0x0040; /* UTP medium */
|
| 1276 |
s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ |
| 1277 |
s->BasicModeStatus |= 0x0004; /* link is up */ |
| 1278 |
|
| 1279 |
s->NWayAdvert = 0x05e1; /* all modes, full duplex */ |
| 1280 |
s->NWayLPAR = 0x05e1; /* all modes, full duplex */ |
| 1281 |
s->NWayExpansion = 0x0001; /* autonegotiation supported */ |
| 1282 |
|
| 1283 |
/* also reset timer and disable timer interrupt */
|
| 1284 |
s->TCTR = 0;
|
| 1285 |
s->TimerInt = 0;
|
| 1286 |
s->TCTR_base = 0;
|
| 1287 |
|
| 1288 |
/* reset tally counters */
|
| 1289 |
RTL8139TallyCounters_clear(&s->tally_counters); |
| 1290 |
} |
| 1291 |
|
| 1292 |
static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) |
| 1293 |
{
|
| 1294 |
counters->TxOk = 0;
|
| 1295 |
counters->RxOk = 0;
|
| 1296 |
counters->TxERR = 0;
|
| 1297 |
counters->RxERR = 0;
|
| 1298 |
counters->MissPkt = 0;
|
| 1299 |
counters->FAE = 0;
|
| 1300 |
counters->Tx1Col = 0;
|
| 1301 |
counters->TxMCol = 0;
|
| 1302 |
counters->RxOkPhy = 0;
|
| 1303 |
counters->RxOkBrd = 0;
|
| 1304 |
counters->RxOkMul = 0;
|
| 1305 |
counters->TxAbt = 0;
|
| 1306 |
counters->TxUndrn = 0;
|
| 1307 |
} |
| 1308 |
|
| 1309 |
static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters) |
| 1310 |
{
|
| 1311 |
uint16_t val16; |
| 1312 |
uint32_t val32; |
| 1313 |
uint64_t val64; |
| 1314 |
|
| 1315 |
val64 = cpu_to_le64(tally_counters->TxOk); |
| 1316 |
cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8); |
| 1317 |
|
| 1318 |
val64 = cpu_to_le64(tally_counters->RxOk); |
| 1319 |
cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8); |
| 1320 |
|
| 1321 |
val64 = cpu_to_le64(tally_counters->TxERR); |
| 1322 |
cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8); |
| 1323 |
|
| 1324 |
val32 = cpu_to_le32(tally_counters->RxERR); |
| 1325 |
cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4); |
| 1326 |
|
| 1327 |
val16 = cpu_to_le16(tally_counters->MissPkt); |
| 1328 |
cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2); |
| 1329 |
|
| 1330 |
val16 = cpu_to_le16(tally_counters->FAE); |
| 1331 |
cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2); |
| 1332 |
|
| 1333 |
val32 = cpu_to_le32(tally_counters->Tx1Col); |
| 1334 |
cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4); |
| 1335 |
|
| 1336 |
val32 = cpu_to_le32(tally_counters->TxMCol); |
| 1337 |
cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4); |
| 1338 |
|
| 1339 |
val64 = cpu_to_le64(tally_counters->RxOkPhy); |
| 1340 |
cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8); |
| 1341 |
|
| 1342 |
val64 = cpu_to_le64(tally_counters->RxOkBrd); |
| 1343 |
cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8); |
| 1344 |
|
| 1345 |
val32 = cpu_to_le32(tally_counters->RxOkMul); |
| 1346 |
cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4); |
| 1347 |
|
| 1348 |
val16 = cpu_to_le16(tally_counters->TxAbt); |
| 1349 |
cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2); |
| 1350 |
|
| 1351 |
val16 = cpu_to_le16(tally_counters->TxUndrn); |
| 1352 |
cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2); |
| 1353 |
} |
| 1354 |
|
| 1355 |
/* Loads values of tally counters from VM state file */
|
| 1356 |
|
| 1357 |
static const VMStateDescription vmstate_tally_counters = { |
| 1358 |
.name = "tally_counters",
|
| 1359 |
.version_id = 1,
|
| 1360 |
.minimum_version_id = 1,
|
| 1361 |
.minimum_version_id_old = 1,
|
| 1362 |
.fields = (VMStateField []) {
|
| 1363 |
VMSTATE_UINT64(TxOk, RTL8139TallyCounters), |
| 1364 |
VMSTATE_UINT64(RxOk, RTL8139TallyCounters), |
| 1365 |
VMSTATE_UINT64(TxERR, RTL8139TallyCounters), |
| 1366 |
VMSTATE_UINT32(RxERR, RTL8139TallyCounters), |
| 1367 |
VMSTATE_UINT16(MissPkt, RTL8139TallyCounters), |
| 1368 |
VMSTATE_UINT16(FAE, RTL8139TallyCounters), |
| 1369 |
VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters), |
| 1370 |
VMSTATE_UINT32(TxMCol, RTL8139TallyCounters), |
| 1371 |
VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters), |
| 1372 |
VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters), |
| 1373 |
VMSTATE_UINT16(TxAbt, RTL8139TallyCounters), |
| 1374 |
VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters), |
| 1375 |
VMSTATE_END_OF_LIST() |
| 1376 |
} |
| 1377 |
}; |
| 1378 |
|
| 1379 |
static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) |
| 1380 |
{
|
| 1381 |
val &= 0xff;
|
| 1382 |
|
| 1383 |
DPRINTF("ChipCmd write val=0x%08x\n", val);
|
| 1384 |
|
| 1385 |
if (val & CmdReset)
|
| 1386 |
{
|
| 1387 |
DPRINTF("ChipCmd reset\n");
|
| 1388 |
rtl8139_reset(&s->dev.qdev); |
| 1389 |
} |
| 1390 |
if (val & CmdRxEnb)
|
| 1391 |
{
|
| 1392 |
DPRINTF("ChipCmd enable receiver\n");
|
| 1393 |
|
| 1394 |
s->currCPlusRxDesc = 0;
|
| 1395 |
} |
| 1396 |
if (val & CmdTxEnb)
|
| 1397 |
{
|
| 1398 |
DPRINTF("ChipCmd enable transmitter\n");
|
| 1399 |
|
| 1400 |
s->currCPlusTxDesc = 0;
|
| 1401 |
} |
| 1402 |
|
| 1403 |
/* mask unwriteable bits */
|
| 1404 |
val = SET_MASKED(val, 0xe3, s->bChipCmdState);
|
| 1405 |
|
| 1406 |
/* Deassert reset pin before next read */
|
| 1407 |
val &= ~CmdReset; |
| 1408 |
|
| 1409 |
s->bChipCmdState = val; |
| 1410 |
} |
| 1411 |
|
| 1412 |
static int rtl8139_RxBufferEmpty(RTL8139State *s) |
| 1413 |
{
|
| 1414 |
int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
|
| 1415 |
|
| 1416 |
if (unread != 0) |
| 1417 |
{
|
| 1418 |
DPRINTF("receiver buffer data available 0x%04x\n", unread);
|
| 1419 |
return 0; |
| 1420 |
} |
| 1421 |
|
| 1422 |
DPRINTF("receiver buffer is empty\n");
|
| 1423 |
|
| 1424 |
return 1; |
| 1425 |
} |
| 1426 |
|
| 1427 |
static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
|
| 1428 |
{
|
| 1429 |
uint32_t ret = s->bChipCmdState; |
| 1430 |
|
| 1431 |
if (rtl8139_RxBufferEmpty(s))
|
| 1432 |
ret |= RxBufEmpty; |
| 1433 |
|
| 1434 |
DPRINTF("ChipCmd read val=0x%04x\n", ret);
|
| 1435 |
|
| 1436 |
return ret;
|
| 1437 |
} |
| 1438 |
|
| 1439 |
static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) |
| 1440 |
{
|
| 1441 |
val &= 0xffff;
|
| 1442 |
|
| 1443 |
DPRINTF("C+ command register write(w) val=0x%04x\n", val);
|
| 1444 |
|
| 1445 |
s->cplus_enabled = 1;
|
| 1446 |
|
| 1447 |
/* mask unwriteable bits */
|
| 1448 |
val = SET_MASKED(val, 0xff84, s->CpCmd);
|
| 1449 |
|
| 1450 |
s->CpCmd = val; |
| 1451 |
} |
| 1452 |
|
| 1453 |
static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
|
| 1454 |
{
|
| 1455 |
uint32_t ret = s->CpCmd; |
| 1456 |
|
| 1457 |
DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
|
| 1458 |
|
| 1459 |
return ret;
|
| 1460 |
} |
| 1461 |
|
| 1462 |
static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) |
| 1463 |
{
|
| 1464 |
DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
|
| 1465 |
} |
| 1466 |
|
| 1467 |
static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
|
| 1468 |
{
|
| 1469 |
uint32_t ret = 0;
|
| 1470 |
|
| 1471 |
DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
|
| 1472 |
|
| 1473 |
return ret;
|
| 1474 |
} |
| 1475 |
|
| 1476 |
static int rtl8139_config_writeable(RTL8139State *s) |
| 1477 |
{
|
| 1478 |
if (s->Cfg9346 & Cfg9346_Unlock)
|
| 1479 |
{
|
| 1480 |
return 1; |
| 1481 |
} |
| 1482 |
|
| 1483 |
DPRINTF("Configuration registers are write-protected\n");
|
| 1484 |
|
| 1485 |
return 0; |
| 1486 |
} |
| 1487 |
|
| 1488 |
static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) |
| 1489 |
{
|
| 1490 |
val &= 0xffff;
|
| 1491 |
|
| 1492 |
DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
|
| 1493 |
|
| 1494 |
/* mask unwriteable bits */
|
| 1495 |
uint32_t mask = 0x4cff;
|
| 1496 |
|
| 1497 |
if (1 || !rtl8139_config_writeable(s)) |
| 1498 |
{
|
| 1499 |
/* Speed setting and autonegotiation enable bits are read-only */
|
| 1500 |
mask |= 0x3000;
|
| 1501 |
/* Duplex mode setting is read-only */
|
| 1502 |
mask |= 0x0100;
|
| 1503 |
} |
| 1504 |
|
| 1505 |
val = SET_MASKED(val, mask, s->BasicModeCtrl); |
| 1506 |
|
| 1507 |
s->BasicModeCtrl = val; |
| 1508 |
} |
| 1509 |
|
| 1510 |
static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
|
| 1511 |
{
|
| 1512 |
uint32_t ret = s->BasicModeCtrl; |
| 1513 |
|
| 1514 |
DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
|
| 1515 |
|
| 1516 |
return ret;
|
| 1517 |
} |
| 1518 |
|
| 1519 |
static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) |
| 1520 |
{
|
| 1521 |
val &= 0xffff;
|
| 1522 |
|
| 1523 |
DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
|
| 1524 |
|
| 1525 |
/* mask unwriteable bits */
|
| 1526 |
val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
|
| 1527 |
|
| 1528 |
s->BasicModeStatus = val; |
| 1529 |
} |
| 1530 |
|
| 1531 |
static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
|
| 1532 |
{
|
| 1533 |
uint32_t ret = s->BasicModeStatus; |
| 1534 |
|
| 1535 |
DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
|
| 1536 |
|
| 1537 |
return ret;
|
| 1538 |
} |
| 1539 |
|
| 1540 |
static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) |
| 1541 |
{
|
| 1542 |
val &= 0xff;
|
| 1543 |
|
| 1544 |
DPRINTF("Cfg9346 write val=0x%02x\n", val);
|
| 1545 |
|
| 1546 |
/* mask unwriteable bits */
|
| 1547 |
val = SET_MASKED(val, 0x31, s->Cfg9346);
|
| 1548 |
|
| 1549 |
uint32_t opmode = val & 0xc0;
|
| 1550 |
uint32_t eeprom_val = val & 0xf;
|
| 1551 |
|
| 1552 |
if (opmode == 0x80) { |
| 1553 |
/* eeprom access */
|
| 1554 |
int eecs = (eeprom_val & 0x08)?1:0; |
| 1555 |
int eesk = (eeprom_val & 0x04)?1:0; |
| 1556 |
int eedi = (eeprom_val & 0x02)?1:0; |
| 1557 |
prom9346_set_wire(s, eecs, eesk, eedi); |
| 1558 |
} else if (opmode == 0x40) { |
| 1559 |
/* Reset. */
|
| 1560 |
val = 0;
|
| 1561 |
rtl8139_reset(&s->dev.qdev); |
| 1562 |
} |
| 1563 |
|
| 1564 |
s->Cfg9346 = val; |
| 1565 |
} |
| 1566 |
|
| 1567 |
static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
|
| 1568 |
{
|
| 1569 |
uint32_t ret = s->Cfg9346; |
| 1570 |
|
| 1571 |
uint32_t opmode = ret & 0xc0;
|
| 1572 |
|
| 1573 |
if (opmode == 0x80) |
| 1574 |
{
|
| 1575 |
/* eeprom access */
|
| 1576 |
int eedo = prom9346_get_wire(s);
|
| 1577 |
if (eedo)
|
| 1578 |
{
|
| 1579 |
ret |= 0x01;
|
| 1580 |
} |
| 1581 |
else
|
| 1582 |
{
|
| 1583 |
ret &= ~0x01;
|
| 1584 |
} |
| 1585 |
} |
| 1586 |
|
| 1587 |
DPRINTF("Cfg9346 read val=0x%02x\n", ret);
|
| 1588 |
|
| 1589 |
return ret;
|
| 1590 |
} |
| 1591 |
|
| 1592 |
static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) |
| 1593 |
{
|
| 1594 |
val &= 0xff;
|
| 1595 |
|
| 1596 |
DPRINTF("Config0 write val=0x%02x\n", val);
|
| 1597 |
|
| 1598 |
if (!rtl8139_config_writeable(s))
|
| 1599 |
return;
|
| 1600 |
|
| 1601 |
/* mask unwriteable bits */
|
| 1602 |
val = SET_MASKED(val, 0xf8, s->Config0);
|
| 1603 |
|
| 1604 |
s->Config0 = val; |
| 1605 |
} |
| 1606 |
|
| 1607 |
static uint32_t rtl8139_Config0_read(RTL8139State *s)
|
| 1608 |
{
|
| 1609 |
uint32_t ret = s->Config0; |
| 1610 |
|
| 1611 |
DPRINTF("Config0 read val=0x%02x\n", ret);
|
| 1612 |
|
| 1613 |
return ret;
|
| 1614 |
} |
| 1615 |
|
| 1616 |
static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) |
| 1617 |
{
|
| 1618 |
val &= 0xff;
|
| 1619 |
|
| 1620 |
DPRINTF("Config1 write val=0x%02x\n", val);
|
| 1621 |
|
| 1622 |
if (!rtl8139_config_writeable(s))
|
| 1623 |
return;
|
| 1624 |
|
| 1625 |
/* mask unwriteable bits */
|
| 1626 |
val = SET_MASKED(val, 0xC, s->Config1);
|
| 1627 |
|
| 1628 |
s->Config1 = val; |
| 1629 |
} |
| 1630 |
|
| 1631 |
static uint32_t rtl8139_Config1_read(RTL8139State *s)
|
| 1632 |
{
|
| 1633 |
uint32_t ret = s->Config1; |
| 1634 |
|
| 1635 |
DPRINTF("Config1 read val=0x%02x\n", ret);
|
| 1636 |
|
| 1637 |
return ret;
|
| 1638 |
} |
| 1639 |
|
| 1640 |
static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) |
| 1641 |
{
|
| 1642 |
val &= 0xff;
|
| 1643 |
|
| 1644 |
DPRINTF("Config3 write val=0x%02x\n", val);
|
| 1645 |
|
| 1646 |
if (!rtl8139_config_writeable(s))
|
| 1647 |
return;
|
| 1648 |
|
| 1649 |
/* mask unwriteable bits */
|
| 1650 |
val = SET_MASKED(val, 0x8F, s->Config3);
|
| 1651 |
|
| 1652 |
s->Config3 = val; |
| 1653 |
} |
| 1654 |
|
| 1655 |
static uint32_t rtl8139_Config3_read(RTL8139State *s)
|
| 1656 |
{
|
| 1657 |
uint32_t ret = s->Config3; |
| 1658 |
|
| 1659 |
DPRINTF("Config3 read val=0x%02x\n", ret);
|
| 1660 |
|
| 1661 |
return ret;
|
| 1662 |
} |
| 1663 |
|
| 1664 |
static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) |
| 1665 |
{
|
| 1666 |
val &= 0xff;
|
| 1667 |
|
| 1668 |
DPRINTF("Config4 write val=0x%02x\n", val);
|
| 1669 |
|
| 1670 |
if (!rtl8139_config_writeable(s))
|
| 1671 |
return;
|
| 1672 |
|
| 1673 |
/* mask unwriteable bits */
|
| 1674 |
val = SET_MASKED(val, 0x0a, s->Config4);
|
| 1675 |
|
| 1676 |
s->Config4 = val; |
| 1677 |
} |
| 1678 |
|
| 1679 |
static uint32_t rtl8139_Config4_read(RTL8139State *s)
|
| 1680 |
{
|
| 1681 |
uint32_t ret = s->Config4; |
| 1682 |
|
| 1683 |
DPRINTF("Config4 read val=0x%02x\n", ret);
|
| 1684 |
|
| 1685 |
return ret;
|
| 1686 |
} |
| 1687 |
|
| 1688 |
static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) |
| 1689 |
{
|
| 1690 |
val &= 0xff;
|
| 1691 |
|
| 1692 |
DPRINTF("Config5 write val=0x%02x\n", val);
|
| 1693 |
|
| 1694 |
/* mask unwriteable bits */
|
| 1695 |
val = SET_MASKED(val, 0x80, s->Config5);
|
| 1696 |
|
| 1697 |
s->Config5 = val; |
| 1698 |
} |
| 1699 |
|
| 1700 |
static uint32_t rtl8139_Config5_read(RTL8139State *s)
|
| 1701 |
{
|
| 1702 |
uint32_t ret = s->Config5; |
| 1703 |
|
| 1704 |
DPRINTF("Config5 read val=0x%02x\n", ret);
|
| 1705 |
|
| 1706 |
return ret;
|
| 1707 |
} |
| 1708 |
|
| 1709 |
static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) |
| 1710 |
{
|
| 1711 |
if (!rtl8139_transmitter_enabled(s))
|
| 1712 |
{
|
| 1713 |
DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
|
| 1714 |
return;
|
| 1715 |
} |
| 1716 |
|
| 1717 |
DPRINTF("TxConfig write val=0x%08x\n", val);
|
| 1718 |
|
| 1719 |
val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
|
| 1720 |
|
| 1721 |
s->TxConfig = val; |
| 1722 |
} |
| 1723 |
|
| 1724 |
static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) |
| 1725 |
{
|
| 1726 |
DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
|
| 1727 |
|
| 1728 |
uint32_t tc = s->TxConfig; |
| 1729 |
tc &= 0xFFFFFF00;
|
| 1730 |
tc |= (val & 0x000000FF);
|
| 1731 |
rtl8139_TxConfig_write(s, tc); |
| 1732 |
} |
| 1733 |
|
| 1734 |
static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
|
| 1735 |
{
|
| 1736 |
uint32_t ret = s->TxConfig; |
| 1737 |
|
| 1738 |
DPRINTF("TxConfig read val=0x%04x\n", ret);
|
| 1739 |
|
| 1740 |
return ret;
|
| 1741 |
} |
| 1742 |
|
| 1743 |
static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) |
| 1744 |
{
|
| 1745 |
DPRINTF("RxConfig write val=0x%08x\n", val);
|
| 1746 |
|
| 1747 |
/* mask unwriteable bits */
|
| 1748 |
val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
|
| 1749 |
|
| 1750 |
s->RxConfig = val; |
| 1751 |
|
| 1752 |
/* reset buffer size and read/write pointers */
|
| 1753 |
rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); |
| 1754 |
|
| 1755 |
DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
|
| 1756 |
} |
| 1757 |
|
| 1758 |
static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
|
| 1759 |
{
|
| 1760 |
uint32_t ret = s->RxConfig; |
| 1761 |
|
| 1762 |
DPRINTF("RxConfig read val=0x%08x\n", ret);
|
| 1763 |
|
| 1764 |
return ret;
|
| 1765 |
} |
| 1766 |
|
| 1767 |
static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, |
| 1768 |
int do_interrupt, const uint8_t *dot1q_buf) |
| 1769 |
{
|
| 1770 |
struct iovec *iov = NULL; |
| 1771 |
|
| 1772 |
if (!size)
|
| 1773 |
{
|
| 1774 |
DPRINTF("+++ empty ethernet frame\n");
|
| 1775 |
return;
|
| 1776 |
} |
| 1777 |
|
| 1778 |
if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) { |
| 1779 |
iov = (struct iovec[3]) { |
| 1780 |
{ .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
|
| 1781 |
{ .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
|
| 1782 |
{ .iov_base = buf + ETHER_ADDR_LEN * 2,
|
| 1783 |
.iov_len = size - ETHER_ADDR_LEN * 2 },
|
| 1784 |
}; |
| 1785 |
} |
| 1786 |
|
| 1787 |
if (TxLoopBack == (s->TxConfig & TxLoopBack))
|
| 1788 |
{
|
| 1789 |
size_t buf2_size; |
| 1790 |
uint8_t *buf2; |
| 1791 |
|
| 1792 |
if (iov) {
|
| 1793 |
buf2_size = iov_size(iov, 3);
|
| 1794 |
buf2 = qemu_malloc(buf2_size); |
| 1795 |
iov_to_buf(iov, 3, buf2, 0, buf2_size); |
| 1796 |
buf = buf2; |
| 1797 |
} |
| 1798 |
|
| 1799 |
DPRINTF("+++ transmit loopback mode\n");
|
| 1800 |
rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt); |
| 1801 |
|
| 1802 |
if (iov) {
|
| 1803 |
qemu_free(buf2); |
| 1804 |
} |
| 1805 |
} |
| 1806 |
else
|
| 1807 |
{
|
| 1808 |
if (iov) {
|
| 1809 |
qemu_sendv_packet(&s->nic->nc, iov, 3);
|
| 1810 |
} else {
|
| 1811 |
qemu_send_packet(&s->nic->nc, buf, size); |
| 1812 |
} |
| 1813 |
} |
| 1814 |
} |
| 1815 |
|
| 1816 |
static int rtl8139_transmit_one(RTL8139State *s, int descriptor) |
| 1817 |
{
|
| 1818 |
if (!rtl8139_transmitter_enabled(s))
|
| 1819 |
{
|
| 1820 |
DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
|
| 1821 |
"disabled\n", descriptor);
|
| 1822 |
return 0; |
| 1823 |
} |
| 1824 |
|
| 1825 |
if (s->TxStatus[descriptor] & TxHostOwns)
|
| 1826 |
{
|
| 1827 |
DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
|
| 1828 |
"(%08x)\n", descriptor, s->TxStatus[descriptor]);
|
| 1829 |
return 0; |
| 1830 |
} |
| 1831 |
|
| 1832 |
DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
|
| 1833 |
|
| 1834 |
int txsize = s->TxStatus[descriptor] & 0x1fff; |
| 1835 |
uint8_t txbuffer[0x2000];
|
| 1836 |
|
| 1837 |
DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
|
| 1838 |
txsize, s->TxAddr[descriptor]); |
| 1839 |
|
| 1840 |
cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize); |
| 1841 |
|
| 1842 |
/* Mark descriptor as transferred */
|
| 1843 |
s->TxStatus[descriptor] |= TxHostOwns; |
| 1844 |
s->TxStatus[descriptor] |= TxStatOK; |
| 1845 |
|
| 1846 |
rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); |
| 1847 |
|
| 1848 |
DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
|
| 1849 |
descriptor); |
| 1850 |
|
| 1851 |
/* update interrupt */
|
| 1852 |
s->IntrStatus |= TxOK; |
| 1853 |
rtl8139_update_irq(s); |
| 1854 |
|
| 1855 |
return 1; |
| 1856 |
} |
| 1857 |
|
| 1858 |
/* structures and macros for task offloading */
|
| 1859 |
typedef struct ip_header |
| 1860 |
{
|
| 1861 |
uint8_t ip_ver_len; /* version and header length */
|
| 1862 |
uint8_t ip_tos; /* type of service */
|
| 1863 |
uint16_t ip_len; /* total length */
|
| 1864 |
uint16_t ip_id; /* identification */
|
| 1865 |
uint16_t ip_off; /* fragment offset field */
|
| 1866 |
uint8_t ip_ttl; /* time to live */
|
| 1867 |
uint8_t ip_p; /* protocol */
|
| 1868 |
uint16_t ip_sum; /* checksum */
|
| 1869 |
uint32_t ip_src,ip_dst; /* source and dest address */
|
| 1870 |
} ip_header; |
| 1871 |
|
| 1872 |
#define IP_HEADER_VERSION_4 4 |
| 1873 |
#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf) |
| 1874 |
#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2) |
| 1875 |
|
| 1876 |
typedef struct tcp_header |
| 1877 |
{
|
| 1878 |
uint16_t th_sport; /* source port */
|
| 1879 |
uint16_t th_dport; /* destination port */
|
| 1880 |
uint32_t th_seq; /* sequence number */
|
| 1881 |
uint32_t th_ack; /* acknowledgement number */
|
| 1882 |
uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
|
| 1883 |
uint16_t th_win; /* window */
|
| 1884 |
uint16_t th_sum; /* checksum */
|
| 1885 |
uint16_t th_urp; /* urgent pointer */
|
| 1886 |
} tcp_header; |
| 1887 |
|
| 1888 |
typedef struct udp_header |
| 1889 |
{
|
| 1890 |
uint16_t uh_sport; /* source port */
|
| 1891 |
uint16_t uh_dport; /* destination port */
|
| 1892 |
uint16_t uh_ulen; /* udp length */
|
| 1893 |
uint16_t uh_sum; /* udp checksum */
|
| 1894 |
} udp_header; |
| 1895 |
|
| 1896 |
typedef struct ip_pseudo_header |
| 1897 |
{
|
| 1898 |
uint32_t ip_src; |
| 1899 |
uint32_t ip_dst; |
| 1900 |
uint8_t zeros; |
| 1901 |
uint8_t ip_proto; |
| 1902 |
uint16_t ip_payload; |
| 1903 |
} ip_pseudo_header; |
| 1904 |
|
| 1905 |
#define IP_PROTO_TCP 6 |
| 1906 |
#define IP_PROTO_UDP 17 |
| 1907 |
|
| 1908 |
#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2) |
| 1909 |
#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f) |
| 1910 |
#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
|
| 1911 |
|
| 1912 |
#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
|
| 1913 |
|
| 1914 |
#define TCP_FLAG_FIN 0x01 |
| 1915 |
#define TCP_FLAG_PUSH 0x08 |
| 1916 |
|
| 1917 |
/* produces ones' complement sum of data */
|
| 1918 |
static uint16_t ones_complement_sum(uint8_t *data, size_t len)
|
| 1919 |
{
|
| 1920 |
uint32_t result = 0;
|
| 1921 |
|
| 1922 |
for (; len > 1; data+=2, len-=2) |
| 1923 |
{
|
| 1924 |
result += *(uint16_t*)data; |
| 1925 |
} |
| 1926 |
|
| 1927 |
/* add the remainder byte */
|
| 1928 |
if (len)
|
| 1929 |
{
|
| 1930 |
uint8_t odd[2] = {*data, 0}; |
| 1931 |
result += *(uint16_t*)odd; |
| 1932 |
} |
| 1933 |
|
| 1934 |
while (result>>16) |
| 1935 |
result = (result & 0xffff) + (result >> 16); |
| 1936 |
|
| 1937 |
return result;
|
| 1938 |
} |
| 1939 |
|
| 1940 |
static uint16_t ip_checksum(void *data, size_t len) |
| 1941 |
{
|
| 1942 |
return ~ones_complement_sum((uint8_t*)data, len);
|
| 1943 |
} |
| 1944 |
|
| 1945 |
static int rtl8139_cplus_transmit_one(RTL8139State *s) |
| 1946 |
{
|
| 1947 |
if (!rtl8139_transmitter_enabled(s))
|
| 1948 |
{
|
| 1949 |
DPRINTF("+++ C+ mode: transmitter disabled\n");
|
| 1950 |
return 0; |
| 1951 |
} |
| 1952 |
|
| 1953 |
if (!rtl8139_cp_transmitter_enabled(s))
|
| 1954 |
{
|
| 1955 |
DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
|
| 1956 |
return 0 ; |
| 1957 |
} |
| 1958 |
|
| 1959 |
int descriptor = s->currCPlusTxDesc;
|
| 1960 |
|
| 1961 |
target_phys_addr_t cplus_tx_ring_desc = |
| 1962 |
rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); |
| 1963 |
|
| 1964 |
/* Normal priority ring */
|
| 1965 |
cplus_tx_ring_desc += 16 * descriptor;
|
| 1966 |
|
| 1967 |
DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
|
| 1968 |
"%08x0x%08x = 0x"TARGET_FMT_plx"\n", descriptor, s->TxAddr[1], |
| 1969 |
s->TxAddr[0], cplus_tx_ring_desc);
|
| 1970 |
|
| 1971 |
uint32_t val, txdw0,txdw1,txbufLO,txbufHI; |
| 1972 |
|
| 1973 |
cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
| 1974 |
txdw0 = le32_to_cpu(val); |
| 1975 |
cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4); |
| 1976 |
txdw1 = le32_to_cpu(val); |
| 1977 |
cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4); |
| 1978 |
txbufLO = le32_to_cpu(val); |
| 1979 |
cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4); |
| 1980 |
txbufHI = le32_to_cpu(val); |
| 1981 |
|
| 1982 |
DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
|
| 1983 |
txdw0, txdw1, txbufLO, txbufHI); |
| 1984 |
|
| 1985 |
/* w0 ownership flag */
|
| 1986 |
#define CP_TX_OWN (1<<31) |
| 1987 |
/* w0 end of ring flag */
|
| 1988 |
#define CP_TX_EOR (1<<30) |
| 1989 |
/* first segment of received packet flag */
|
| 1990 |
#define CP_TX_FS (1<<29) |
| 1991 |
/* last segment of received packet flag */
|
| 1992 |
#define CP_TX_LS (1<<28) |
| 1993 |
/* large send packet flag */
|
| 1994 |
#define CP_TX_LGSEN (1<<27) |
| 1995 |
/* large send MSS mask, bits 16...25 */
|
| 1996 |
#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) |
| 1997 |
|
| 1998 |
/* IP checksum offload flag */
|
| 1999 |
#define CP_TX_IPCS (1<<18) |
| 2000 |
/* UDP checksum offload flag */
|
| 2001 |
#define CP_TX_UDPCS (1<<17) |
| 2002 |
/* TCP checksum offload flag */
|
| 2003 |
#define CP_TX_TCPCS (1<<16) |
| 2004 |
|
| 2005 |
/* w0 bits 0...15 : buffer size */
|
| 2006 |
#define CP_TX_BUFFER_SIZE (1<<16) |
| 2007 |
#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) |
| 2008 |
/* w1 add tag flag */
|
| 2009 |
#define CP_TX_TAGC (1<<17) |
| 2010 |
/* w1 bits 0...15 : VLAN tag (big endian) */
|
| 2011 |
#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) |
| 2012 |
/* w2 low 32bit of Rx buffer ptr */
|
| 2013 |
/* w3 high 32bit of Rx buffer ptr */
|
| 2014 |
|
| 2015 |
/* set after transmission */
|
| 2016 |
/* FIFO underrun flag */
|
| 2017 |
#define CP_TX_STATUS_UNF (1<<25) |
| 2018 |
/* transmit error summary flag, valid if set any of three below */
|
| 2019 |
#define CP_TX_STATUS_TES (1<<23) |
| 2020 |
/* out-of-window collision flag */
|
| 2021 |
#define CP_TX_STATUS_OWC (1<<22) |
| 2022 |
/* link failure flag */
|
| 2023 |
#define CP_TX_STATUS_LNKF (1<<21) |
| 2024 |
/* excessive collisions flag */
|
| 2025 |
#define CP_TX_STATUS_EXC (1<<20) |
| 2026 |
|
| 2027 |
if (!(txdw0 & CP_TX_OWN))
|
| 2028 |
{
|
| 2029 |
DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
|
| 2030 |
return 0 ; |
| 2031 |
} |
| 2032 |
|
| 2033 |
DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
|
| 2034 |
|
| 2035 |
if (txdw0 & CP_TX_FS)
|
| 2036 |
{
|
| 2037 |
DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
|
| 2038 |
"descriptor\n", descriptor);
|
| 2039 |
|
| 2040 |
/* reset internal buffer offset */
|
| 2041 |
s->cplus_txbuffer_offset = 0;
|
| 2042 |
} |
| 2043 |
|
| 2044 |
int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
|
| 2045 |
target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); |
| 2046 |
|
| 2047 |
/* make sure we have enough space to assemble the packet */
|
| 2048 |
if (!s->cplus_txbuffer)
|
| 2049 |
{
|
| 2050 |
s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; |
| 2051 |
s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len); |
| 2052 |
s->cplus_txbuffer_offset = 0;
|
| 2053 |
|
| 2054 |
DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
|
| 2055 |
s->cplus_txbuffer_len); |
| 2056 |
} |
| 2057 |
|
| 2058 |
while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
|
| 2059 |
{
|
| 2060 |
s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE; |
| 2061 |
s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len); |
| 2062 |
|
| 2063 |
DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
|
| 2064 |
s->cplus_txbuffer_len); |
| 2065 |
} |
| 2066 |
|
| 2067 |
if (!s->cplus_txbuffer)
|
| 2068 |
{
|
| 2069 |
/* out of memory */
|
| 2070 |
|
| 2071 |
DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
|
| 2072 |
s->cplus_txbuffer_len); |
| 2073 |
|
| 2074 |
/* update tally counter */
|
| 2075 |
++s->tally_counters.TxERR; |
| 2076 |
++s->tally_counters.TxAbt; |
| 2077 |
|
| 2078 |
return 0; |
| 2079 |
} |
| 2080 |
|
| 2081 |
/* append more data to the packet */
|
| 2082 |
|
| 2083 |
DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
|
| 2084 |
TARGET_FMT_plx" to offset %d\n", txsize, tx_addr,
|
| 2085 |
s->cplus_txbuffer_offset); |
| 2086 |
|
| 2087 |
cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); |
| 2088 |
s->cplus_txbuffer_offset += txsize; |
| 2089 |
|
| 2090 |
/* seek to next Rx descriptor */
|
| 2091 |
if (txdw0 & CP_TX_EOR)
|
| 2092 |
{
|
| 2093 |
s->currCPlusTxDesc = 0;
|
| 2094 |
} |
| 2095 |
else
|
| 2096 |
{
|
| 2097 |
++s->currCPlusTxDesc; |
| 2098 |
if (s->currCPlusTxDesc >= 64) |
| 2099 |
s->currCPlusTxDesc = 0;
|
| 2100 |
} |
| 2101 |
|
| 2102 |
/* transfer ownership to target */
|
| 2103 |
txdw0 &= ~CP_RX_OWN; |
| 2104 |
|
| 2105 |
/* reset error indicator bits */
|
| 2106 |
txdw0 &= ~CP_TX_STATUS_UNF; |
| 2107 |
txdw0 &= ~CP_TX_STATUS_TES; |
| 2108 |
txdw0 &= ~CP_TX_STATUS_OWC; |
| 2109 |
txdw0 &= ~CP_TX_STATUS_LNKF; |
| 2110 |
txdw0 &= ~CP_TX_STATUS_EXC; |
| 2111 |
|
| 2112 |
/* update ring data */
|
| 2113 |
val = cpu_to_le32(txdw0); |
| 2114 |
cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
| 2115 |
|
| 2116 |
/* Now decide if descriptor being processed is holding the last segment of packet */
|
| 2117 |
if (txdw0 & CP_TX_LS)
|
| 2118 |
{
|
| 2119 |
uint8_t dot1q_buffer_space[VLAN_HLEN]; |
| 2120 |
uint16_t *dot1q_buffer; |
| 2121 |
|
| 2122 |
DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
|
| 2123 |
descriptor); |
| 2124 |
|
| 2125 |
/* can transfer fully assembled packet */
|
| 2126 |
|
| 2127 |
uint8_t *saved_buffer = s->cplus_txbuffer; |
| 2128 |
int saved_size = s->cplus_txbuffer_offset;
|
| 2129 |
int saved_buffer_len = s->cplus_txbuffer_len;
|
| 2130 |
|
| 2131 |
/* create vlan tag */
|
| 2132 |
if (txdw1 & CP_TX_TAGC) {
|
| 2133 |
/* the vlan tag is in BE byte order in the descriptor
|
| 2134 |
* BE + le_to_cpu() + ~swap()~ = cpu */
|
| 2135 |
DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", |
| 2136 |
bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); |
| 2137 |
|
| 2138 |
dot1q_buffer = (uint16_t *) dot1q_buffer_space; |
| 2139 |
dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
|
| 2140 |
/* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
|
| 2141 |
dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
|
| 2142 |
} else {
|
| 2143 |
dot1q_buffer = NULL;
|
| 2144 |
} |
| 2145 |
|
| 2146 |
/* reset the card space to protect from recursive call */
|
| 2147 |
s->cplus_txbuffer = NULL;
|
| 2148 |
s->cplus_txbuffer_offset = 0;
|
| 2149 |
s->cplus_txbuffer_len = 0;
|
| 2150 |
|
| 2151 |
if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
|
| 2152 |
{
|
| 2153 |
DPRINTF("+++ C+ mode offloaded task checksum\n");
|
| 2154 |
|
| 2155 |
/* ip packet header */
|
| 2156 |
ip_header *ip = NULL;
|
| 2157 |
int hlen = 0; |
| 2158 |
uint8_t ip_protocol = 0;
|
| 2159 |
uint16_t ip_data_len = 0;
|
| 2160 |
|
| 2161 |
uint8_t *eth_payload_data = NULL;
|
| 2162 |
size_t eth_payload_len = 0;
|
| 2163 |
|
| 2164 |
int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); |
| 2165 |
if (proto == ETH_P_IP)
|
| 2166 |
{
|
| 2167 |
DPRINTF("+++ C+ mode has IP packet\n");
|
| 2168 |
|
| 2169 |
/* not aligned */
|
| 2170 |
eth_payload_data = saved_buffer + ETH_HLEN; |
| 2171 |
eth_payload_len = saved_size - ETH_HLEN; |
| 2172 |
|
| 2173 |
ip = (ip_header*)eth_payload_data; |
| 2174 |
|
| 2175 |
if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
|
| 2176 |
DPRINTF("+++ C+ mode packet has bad IP version %d "
|
| 2177 |
"expected %d\n", IP_HEADER_VERSION(ip),
|
| 2178 |
IP_HEADER_VERSION_4); |
| 2179 |
ip = NULL;
|
| 2180 |
} else {
|
| 2181 |
hlen = IP_HEADER_LENGTH(ip); |
| 2182 |
ip_protocol = ip->ip_p; |
| 2183 |
ip_data_len = be16_to_cpu(ip->ip_len) - hlen; |
| 2184 |
} |
| 2185 |
} |
| 2186 |
|
| 2187 |
if (ip)
|
| 2188 |
{
|
| 2189 |
if (txdw0 & CP_TX_IPCS)
|
| 2190 |
{
|
| 2191 |
DPRINTF("+++ C+ mode need IP checksum\n");
|
| 2192 |
|
| 2193 |
if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */ |
| 2194 |
/* bad packet header len */
|
| 2195 |
/* or packet too short */
|
| 2196 |
} |
| 2197 |
else
|
| 2198 |
{
|
| 2199 |
ip->ip_sum = 0;
|
| 2200 |
ip->ip_sum = ip_checksum(ip, hlen); |
| 2201 |
DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
|
| 2202 |
hlen, ip->ip_sum); |
| 2203 |
} |
| 2204 |
} |
| 2205 |
|
| 2206 |
if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
|
| 2207 |
{
|
| 2208 |
int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; |
| 2209 |
|
| 2210 |
DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
|
| 2211 |
"frame data %d specified MSS=%d\n", ETH_MTU,
|
| 2212 |
ip_data_len, saved_size - ETH_HLEN, large_send_mss); |
| 2213 |
|
| 2214 |
int tcp_send_offset = 0; |
| 2215 |
int send_count = 0; |
| 2216 |
|
| 2217 |
/* maximum IP header length is 60 bytes */
|
| 2218 |
uint8_t saved_ip_header[60];
|
| 2219 |
|
| 2220 |
/* save IP header template; data area is used in tcp checksum calculation */
|
| 2221 |
memcpy(saved_ip_header, eth_payload_data, hlen); |
| 2222 |
|
| 2223 |
/* a placeholder for checksum calculation routine in tcp case */
|
| 2224 |
uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
|
| 2225 |
// size_t data_to_checksum_len = eth_payload_len - hlen + 12;
|
| 2226 |
|
| 2227 |
/* pointer to TCP header */
|
| 2228 |
tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); |
| 2229 |
|
| 2230 |
int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
|
| 2231 |
|
| 2232 |
/* ETH_MTU = ip header len + tcp header len + payload */
|
| 2233 |
int tcp_data_len = ip_data_len - tcp_hlen;
|
| 2234 |
int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
|
| 2235 |
|
| 2236 |
DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
|
| 2237 |
"data len %d TCP chunk size %d\n", ip_data_len,
|
| 2238 |
tcp_hlen, tcp_data_len, tcp_chunk_size); |
| 2239 |
|
| 2240 |
/* note the cycle below overwrites IP header data,
|
| 2241 |
but restores it from saved_ip_header before sending packet */
|
| 2242 |
|
| 2243 |
int is_last_frame = 0; |
| 2244 |
|
| 2245 |
for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) |
| 2246 |
{
|
| 2247 |
uint16_t chunk_size = tcp_chunk_size; |
| 2248 |
|
| 2249 |
/* check if this is the last frame */
|
| 2250 |
if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
|
| 2251 |
{
|
| 2252 |
is_last_frame = 1;
|
| 2253 |
chunk_size = tcp_data_len - tcp_send_offset; |
| 2254 |
} |
| 2255 |
|
| 2256 |
DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
|
| 2257 |
be32_to_cpu(p_tcp_hdr->th_seq)); |
| 2258 |
|
| 2259 |
/* add 4 TCP pseudoheader fields */
|
| 2260 |
/* copy IP source and destination fields */
|
| 2261 |
memcpy(data_to_checksum, saved_ip_header + 12, 8); |
| 2262 |
|
| 2263 |
DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
|
| 2264 |
"packet with %d bytes data\n", tcp_hlen +
|
| 2265 |
chunk_size); |
| 2266 |
|
| 2267 |
if (tcp_send_offset)
|
| 2268 |
{
|
| 2269 |
memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); |
| 2270 |
} |
| 2271 |
|
| 2272 |
/* keep PUSH and FIN flags only for the last frame */
|
| 2273 |
if (!is_last_frame)
|
| 2274 |
{
|
| 2275 |
TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN); |
| 2276 |
} |
| 2277 |
|
| 2278 |
/* recalculate TCP checksum */
|
| 2279 |
ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
| 2280 |
p_tcpip_hdr->zeros = 0;
|
| 2281 |
p_tcpip_hdr->ip_proto = IP_PROTO_TCP; |
| 2282 |
p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); |
| 2283 |
|
| 2284 |
p_tcp_hdr->th_sum = 0;
|
| 2285 |
|
| 2286 |
int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); |
| 2287 |
DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
|
| 2288 |
tcp_checksum); |
| 2289 |
|
| 2290 |
p_tcp_hdr->th_sum = tcp_checksum; |
| 2291 |
|
| 2292 |
/* restore IP header */
|
| 2293 |
memcpy(eth_payload_data, saved_ip_header, hlen); |
| 2294 |
|
| 2295 |
/* set IP data length and recalculate IP checksum */
|
| 2296 |
ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); |
| 2297 |
|
| 2298 |
/* increment IP id for subsequent frames */
|
| 2299 |
ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); |
| 2300 |
|
| 2301 |
ip->ip_sum = 0;
|
| 2302 |
ip->ip_sum = ip_checksum(eth_payload_data, hlen); |
| 2303 |
DPRINTF("+++ C+ mode TSO IP header len=%d "
|
| 2304 |
"checksum=%04x\n", hlen, ip->ip_sum);
|
| 2305 |
|
| 2306 |
int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
|
| 2307 |
DPRINTF("+++ C+ mode TSO transferring packet size "
|
| 2308 |
"%d\n", tso_send_size);
|
| 2309 |
rtl8139_transfer_frame(s, saved_buffer, tso_send_size, |
| 2310 |
0, (uint8_t *) dot1q_buffer);
|
| 2311 |
|
| 2312 |
/* add transferred count to TCP sequence number */
|
| 2313 |
p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq)); |
| 2314 |
++send_count; |
| 2315 |
} |
| 2316 |
|
| 2317 |
/* Stop sending this frame */
|
| 2318 |
saved_size = 0;
|
| 2319 |
} |
| 2320 |
else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) |
| 2321 |
{
|
| 2322 |
DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
|
| 2323 |
|
| 2324 |
/* maximum IP header length is 60 bytes */
|
| 2325 |
uint8_t saved_ip_header[60];
|
| 2326 |
memcpy(saved_ip_header, eth_payload_data, hlen); |
| 2327 |
|
| 2328 |
uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
|
| 2329 |
// size_t data_to_checksum_len = eth_payload_len - hlen + 12;
|
| 2330 |
|
| 2331 |
/* add 4 TCP pseudoheader fields */
|
| 2332 |
/* copy IP source and destination fields */
|
| 2333 |
memcpy(data_to_checksum, saved_ip_header + 12, 8); |
| 2334 |
|
| 2335 |
if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
|
| 2336 |
{
|
| 2337 |
DPRINTF("+++ C+ mode calculating TCP checksum for "
|
| 2338 |
"packet with %d bytes data\n", ip_data_len);
|
| 2339 |
|
| 2340 |
ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
| 2341 |
p_tcpip_hdr->zeros = 0;
|
| 2342 |
p_tcpip_hdr->ip_proto = IP_PROTO_TCP; |
| 2343 |
p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); |
| 2344 |
|
| 2345 |
tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
|
| 2346 |
|
| 2347 |
p_tcp_hdr->th_sum = 0;
|
| 2348 |
|
| 2349 |
int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
| 2350 |
DPRINTF("+++ C+ mode TCP checksum %04x\n",
|
| 2351 |
tcp_checksum); |
| 2352 |
|
| 2353 |
p_tcp_hdr->th_sum = tcp_checksum; |
| 2354 |
} |
| 2355 |
else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) |
| 2356 |
{
|
| 2357 |
DPRINTF("+++ C+ mode calculating UDP checksum for "
|
| 2358 |
"packet with %d bytes data\n", ip_data_len);
|
| 2359 |
|
| 2360 |
ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; |
| 2361 |
p_udpip_hdr->zeros = 0;
|
| 2362 |
p_udpip_hdr->ip_proto = IP_PROTO_UDP; |
| 2363 |
p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); |
| 2364 |
|
| 2365 |
udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
|
| 2366 |
|
| 2367 |
p_udp_hdr->uh_sum = 0;
|
| 2368 |
|
| 2369 |
int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
| 2370 |
DPRINTF("+++ C+ mode UDP checksum %04x\n",
|
| 2371 |
udp_checksum); |
| 2372 |
|
| 2373 |
p_udp_hdr->uh_sum = udp_checksum; |
| 2374 |
} |
| 2375 |
|
| 2376 |
/* restore IP header */
|
| 2377 |
memcpy(eth_payload_data, saved_ip_header, hlen); |
| 2378 |
} |
| 2379 |
} |
| 2380 |
} |
| 2381 |
|
| 2382 |
/* update tally counter */
|
| 2383 |
++s->tally_counters.TxOk; |
| 2384 |
|
| 2385 |
DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
|
| 2386 |
|
| 2387 |
rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
|
| 2388 |
(uint8_t *) dot1q_buffer); |
| 2389 |
|
| 2390 |
/* restore card space if there was no recursion and reset offset */
|
| 2391 |
if (!s->cplus_txbuffer)
|
| 2392 |
{
|
| 2393 |
s->cplus_txbuffer = saved_buffer; |
| 2394 |
s->cplus_txbuffer_len = saved_buffer_len; |
| 2395 |
s->cplus_txbuffer_offset = 0;
|
| 2396 |
} |
| 2397 |
else
|
| 2398 |
{
|
| 2399 |
qemu_free(saved_buffer); |
| 2400 |
} |
| 2401 |
} |
| 2402 |
else
|
| 2403 |
{
|
| 2404 |
DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
|
| 2405 |
} |
| 2406 |
|
| 2407 |
return 1; |
| 2408 |
} |
| 2409 |
|
| 2410 |
static void rtl8139_cplus_transmit(RTL8139State *s) |
| 2411 |
{
|
| 2412 |
int txcount = 0; |
| 2413 |
|
| 2414 |
while (rtl8139_cplus_transmit_one(s))
|
| 2415 |
{
|
| 2416 |
++txcount; |
| 2417 |
} |
| 2418 |
|
| 2419 |
/* Mark transfer completed */
|
| 2420 |
if (!txcount)
|
| 2421 |
{
|
| 2422 |
DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
|
| 2423 |
s->currCPlusTxDesc); |
| 2424 |
} |
| 2425 |
else
|
| 2426 |
{
|
| 2427 |
/* update interrupt status */
|
| 2428 |
s->IntrStatus |= TxOK; |
| 2429 |
rtl8139_update_irq(s); |
| 2430 |
} |
| 2431 |
} |
| 2432 |
|
| 2433 |
static void rtl8139_transmit(RTL8139State *s) |
| 2434 |
{
|
| 2435 |
int descriptor = s->currTxDesc, txcount = 0; |
| 2436 |
|
| 2437 |
/*while*/
|
| 2438 |
if (rtl8139_transmit_one(s, descriptor))
|
| 2439 |
{
|
| 2440 |
++s->currTxDesc; |
| 2441 |
s->currTxDesc %= 4;
|
| 2442 |
++txcount; |
| 2443 |
} |
| 2444 |
|
| 2445 |
/* Mark transfer completed */
|
| 2446 |
if (!txcount)
|
| 2447 |
{
|
| 2448 |
DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
|
| 2449 |
s->currTxDesc); |
| 2450 |
} |
| 2451 |
} |
| 2452 |
|
| 2453 |
static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) |
| 2454 |
{
|
| 2455 |
|
| 2456 |
int descriptor = txRegOffset/4; |
| 2457 |
|
| 2458 |
/* handle C+ transmit mode register configuration */
|
| 2459 |
|
| 2460 |
if (s->cplus_enabled)
|
| 2461 |
{
|
| 2462 |
DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
|
| 2463 |
"descriptor=%d\n", txRegOffset, val, descriptor);
|
| 2464 |
|
| 2465 |
/* handle Dump Tally Counters command */
|
| 2466 |
s->TxStatus[descriptor] = val; |
| 2467 |
|
| 2468 |
if (descriptor == 0 && (val & 0x8)) |
| 2469 |
{
|
| 2470 |
target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); |
| 2471 |
|
| 2472 |
/* dump tally counters to specified memory location */
|
| 2473 |
RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters); |
| 2474 |
|
| 2475 |
/* mark dump completed */
|
| 2476 |
s->TxStatus[0] &= ~0x8; |
| 2477 |
} |
| 2478 |
|
| 2479 |
return;
|
| 2480 |
} |
| 2481 |
|
| 2482 |
DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
|
| 2483 |
txRegOffset, val, descriptor); |
| 2484 |
|
| 2485 |
/* mask only reserved bits */
|
| 2486 |
val &= ~0xff00c000; /* these bits are reset on write */ |
| 2487 |
val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
|
| 2488 |
|
| 2489 |
s->TxStatus[descriptor] = val; |
| 2490 |
|
| 2491 |
/* attempt to start transmission */
|
| 2492 |
rtl8139_transmit(s); |
| 2493 |
} |
| 2494 |
|
| 2495 |
static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
|
| 2496 |
{
|
| 2497 |
uint32_t ret = s->TxStatus[txRegOffset/4];
|
| 2498 |
|
| 2499 |
DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
|
| 2500 |
|
| 2501 |
return ret;
|
| 2502 |
} |
| 2503 |
|
| 2504 |
static uint16_t rtl8139_TSAD_read(RTL8139State *s)
|
| 2505 |
{
|
| 2506 |
uint16_t ret = 0;
|
| 2507 |
|
| 2508 |
/* Simulate TSAD, it is read only anyway */
|
| 2509 |
|
| 2510 |
ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) |
| 2511 |
|((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) |
| 2512 |
|((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) |
| 2513 |
|((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) |
| 2514 |
|
| 2515 |
|((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) |
| 2516 |
|((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) |
| 2517 |
|((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) |
| 2518 |
|((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) |
| 2519 |
|
| 2520 |
|((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) |
| 2521 |
|((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) |
| 2522 |
|((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) |
| 2523 |
|((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) |
| 2524 |
|
| 2525 |
|((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) |
| 2526 |
|((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) |
| 2527 |
|((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) |
| 2528 |
|((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; |
| 2529 |
|
| 2530 |
|
| 2531 |
DPRINTF("TSAD read val=0x%04x\n", ret);
|
| 2532 |
|
| 2533 |
return ret;
|
| 2534 |
} |
| 2535 |
|
| 2536 |
static uint16_t rtl8139_CSCR_read(RTL8139State *s)
|
| 2537 |
{
|
| 2538 |
uint16_t ret = s->CSCR; |
| 2539 |
|
| 2540 |
DPRINTF("CSCR read val=0x%04x\n", ret);
|
| 2541 |
|
| 2542 |
return ret;
|
| 2543 |
} |
| 2544 |
|
| 2545 |
static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) |
| 2546 |
{
|
| 2547 |
DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
|
| 2548 |
|
| 2549 |
s->TxAddr[txAddrOffset/4] = val;
|
| 2550 |
} |
| 2551 |
|
| 2552 |
static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
|
| 2553 |
{
|
| 2554 |
uint32_t ret = s->TxAddr[txAddrOffset/4];
|
| 2555 |
|
| 2556 |
DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
|
| 2557 |
|
| 2558 |
return ret;
|
| 2559 |
} |
| 2560 |
|
| 2561 |
static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) |
| 2562 |
{
|
| 2563 |
DPRINTF("RxBufPtr write val=0x%04x\n", val);
|
| 2564 |
|
| 2565 |
/* this value is off by 16 */
|
| 2566 |
s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
|
| 2567 |
|
| 2568 |
DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
|
| 2569 |
s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); |
| 2570 |
} |
| 2571 |
|
| 2572 |
static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
|
| 2573 |
{
|
| 2574 |
/* this value is off by 16 */
|
| 2575 |
uint32_t ret = s->RxBufPtr - 0x10;
|
| 2576 |
|
| 2577 |
DPRINTF("RxBufPtr read val=0x%04x\n", ret);
|
| 2578 |
|
| 2579 |
return ret;
|
| 2580 |
} |
| 2581 |
|
| 2582 |
static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
|
| 2583 |
{
|
| 2584 |
/* this value is NOT off by 16 */
|
| 2585 |
uint32_t ret = s->RxBufAddr; |
| 2586 |
|
| 2587 |
DPRINTF("RxBufAddr read val=0x%04x\n", ret);
|
| 2588 |
|
| 2589 |
return ret;
|
| 2590 |
} |
| 2591 |
|
| 2592 |
static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) |
| 2593 |
{
|
| 2594 |
DPRINTF("RxBuf write val=0x%08x\n", val);
|
| 2595 |
|
| 2596 |
s->RxBuf = val; |
| 2597 |
|
| 2598 |
/* may need to reset rxring here */
|
| 2599 |
} |
| 2600 |
|
| 2601 |
static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
|
| 2602 |
{
|
| 2603 |
uint32_t ret = s->RxBuf; |
| 2604 |
|
| 2605 |
DPRINTF("RxBuf read val=0x%08x\n", ret);
|
| 2606 |
|
| 2607 |
return ret;
|
| 2608 |
} |
| 2609 |
|
| 2610 |
static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) |
| 2611 |
{
|
| 2612 |
DPRINTF("IntrMask write(w) val=0x%04x\n", val);
|
| 2613 |
|
| 2614 |
/* mask unwriteable bits */
|
| 2615 |
val = SET_MASKED(val, 0x1e00, s->IntrMask);
|
| 2616 |
|
| 2617 |
s->IntrMask = val; |
| 2618 |
|
| 2619 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
| 2620 |
rtl8139_update_irq(s); |
| 2621 |
|
| 2622 |
} |
| 2623 |
|
| 2624 |
static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
|
| 2625 |
{
|
| 2626 |
uint32_t ret = s->IntrMask; |
| 2627 |
|
| 2628 |
DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
|
| 2629 |
|
| 2630 |
return ret;
|
| 2631 |
} |
| 2632 |
|
| 2633 |
static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) |
| 2634 |
{
|
| 2635 |
DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
|
| 2636 |
|
| 2637 |
#if 0
|
| 2638 |
|
| 2639 |
/* writing to ISR has no effect */
|
| 2640 |
|
| 2641 |
return;
|
| 2642 |
|
| 2643 |
#else
|
| 2644 |
uint16_t newStatus = s->IntrStatus & ~val; |
| 2645 |
|
| 2646 |
/* mask unwriteable bits */
|
| 2647 |
newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
|
| 2648 |
|
| 2649 |
/* writing 1 to interrupt status register bit clears it */
|
| 2650 |
s->IntrStatus = 0;
|
| 2651 |
rtl8139_update_irq(s); |
| 2652 |
|
| 2653 |
s->IntrStatus = newStatus; |
| 2654 |
/*
|
| 2655 |
* Computing if we miss an interrupt here is not that correct but
|
| 2656 |
* considered that we should have had already an interrupt
|
| 2657 |
* and probably emulated is slower is better to assume this resetting was
|
| 2658 |
* done before testing on previous rtl8139_update_irq lead to IRQ loosing
|
| 2659 |
*/
|
| 2660 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
| 2661 |
rtl8139_update_irq(s); |
| 2662 |
|
| 2663 |
#endif
|
| 2664 |
} |
| 2665 |
|
| 2666 |
static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
|
| 2667 |
{
|
| 2668 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
| 2669 |
|
| 2670 |
uint32_t ret = s->IntrStatus; |
| 2671 |
|
| 2672 |
DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
|
| 2673 |
|
| 2674 |
#if 0
|
| 2675 |
|
| 2676 |
/* reading ISR clears all interrupts */
|
| 2677 |
s->IntrStatus = 0;
|
| 2678 |
|
| 2679 |
rtl8139_update_irq(s);
|
| 2680 |
|
| 2681 |
#endif
|
| 2682 |
|
| 2683 |
return ret;
|
| 2684 |
} |
| 2685 |
|
| 2686 |
static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) |
| 2687 |
{
|
| 2688 |
DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
|
| 2689 |
|
| 2690 |
/* mask unwriteable bits */
|
| 2691 |
val = SET_MASKED(val, 0xf000, s->MultiIntr);
|
| 2692 |
|
| 2693 |
s->MultiIntr = val; |
| 2694 |
} |
| 2695 |
|
| 2696 |
static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
|
| 2697 |
{
|
| 2698 |
uint32_t ret = s->MultiIntr; |
| 2699 |
|
| 2700 |
DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
|
| 2701 |
|
| 2702 |
return ret;
|
| 2703 |
} |
| 2704 |
|
| 2705 |
static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) |
| 2706 |
{
|
| 2707 |
RTL8139State *s = opaque; |
| 2708 |
|
| 2709 |
addr &= 0xff;
|
| 2710 |
|
| 2711 |
switch (addr)
|
| 2712 |
{
|
| 2713 |
case MAC0 ... MAC0+5: |
| 2714 |
s->phys[addr - MAC0] = val; |
| 2715 |
break;
|
| 2716 |
case MAC0+6 ... MAC0+7: |
| 2717 |
/* reserved */
|
| 2718 |
break;
|
| 2719 |
case MAR0 ... MAR0+7: |
| 2720 |
s->mult[addr - MAR0] = val; |
| 2721 |
break;
|
| 2722 |
case ChipCmd:
|
| 2723 |
rtl8139_ChipCmd_write(s, val); |
| 2724 |
break;
|
| 2725 |
case Cfg9346:
|
| 2726 |
rtl8139_Cfg9346_write(s, val); |
| 2727 |
break;
|
| 2728 |
case TxConfig: /* windows driver sometimes writes using byte-lenth call */ |
| 2729 |
rtl8139_TxConfig_writeb(s, val); |
| 2730 |
break;
|
| 2731 |
case Config0:
|
| 2732 |
rtl8139_Config0_write(s, val); |
| 2733 |
break;
|
| 2734 |
case Config1:
|
| 2735 |
rtl8139_Config1_write(s, val); |
| 2736 |
break;
|
| 2737 |
case Config3:
|
| 2738 |
rtl8139_Config3_write(s, val); |
| 2739 |
break;
|
| 2740 |
case Config4:
|
| 2741 |
rtl8139_Config4_write(s, val); |
| 2742 |
break;
|
| 2743 |
case Config5:
|
| 2744 |
rtl8139_Config5_write(s, val); |
| 2745 |
break;
|
| 2746 |
case MediaStatus:
|
| 2747 |
/* ignore */
|
| 2748 |
DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
|
| 2749 |
val); |
| 2750 |
break;
|
| 2751 |
|
| 2752 |
case HltClk:
|
| 2753 |
DPRINTF("HltClk write val=0x%08x\n", val);
|
| 2754 |
if (val == 'R') |
| 2755 |
{
|
| 2756 |
s->clock_enabled = 1;
|
| 2757 |
} |
| 2758 |
else if (val == 'H') |
| 2759 |
{
|
| 2760 |
s->clock_enabled = 0;
|
| 2761 |
} |
| 2762 |
break;
|
| 2763 |
|
| 2764 |
case TxThresh:
|
| 2765 |
DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
|
| 2766 |
s->TxThresh = val; |
| 2767 |
break;
|
| 2768 |
|
| 2769 |
case TxPoll:
|
| 2770 |
DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
|
| 2771 |
if (val & (1 << 7)) |
| 2772 |
{
|
| 2773 |
DPRINTF("C+ TxPoll high priority transmission (not "
|
| 2774 |
"implemented)\n");
|
| 2775 |
//rtl8139_cplus_transmit(s);
|
| 2776 |
} |
| 2777 |
if (val & (1 << 6)) |
| 2778 |
{
|
| 2779 |
DPRINTF("C+ TxPoll normal priority transmission\n");
|
| 2780 |
rtl8139_cplus_transmit(s); |
| 2781 |
} |
| 2782 |
|
| 2783 |
break;
|
| 2784 |
|
| 2785 |
default:
|
| 2786 |
DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
|
| 2787 |
val); |
| 2788 |
break;
|
| 2789 |
} |
| 2790 |
} |
| 2791 |
|
| 2792 |
static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) |
| 2793 |
{
|
| 2794 |
RTL8139State *s = opaque; |
| 2795 |
|
| 2796 |
addr &= 0xfe;
|
| 2797 |
|
| 2798 |
switch (addr)
|
| 2799 |
{
|
| 2800 |
case IntrMask:
|
| 2801 |
rtl8139_IntrMask_write(s, val); |
| 2802 |
break;
|
| 2803 |
|
| 2804 |
case IntrStatus:
|
| 2805 |
rtl8139_IntrStatus_write(s, val); |
| 2806 |
break;
|
| 2807 |
|
| 2808 |
case MultiIntr:
|
| 2809 |
rtl8139_MultiIntr_write(s, val); |
| 2810 |
break;
|
| 2811 |
|
| 2812 |
case RxBufPtr:
|
| 2813 |
rtl8139_RxBufPtr_write(s, val); |
| 2814 |
break;
|
| 2815 |
|
| 2816 |
case BasicModeCtrl:
|
| 2817 |
rtl8139_BasicModeCtrl_write(s, val); |
| 2818 |
break;
|
| 2819 |
case BasicModeStatus:
|
| 2820 |
rtl8139_BasicModeStatus_write(s, val); |
| 2821 |
break;
|
| 2822 |
case NWayAdvert:
|
| 2823 |
DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
|
| 2824 |
s->NWayAdvert = val; |
| 2825 |
break;
|
| 2826 |
case NWayLPAR:
|
| 2827 |
DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
|
| 2828 |
break;
|
| 2829 |
case NWayExpansion:
|
| 2830 |
DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
|
| 2831 |
s->NWayExpansion = val; |
| 2832 |
break;
|
| 2833 |
|
| 2834 |
case CpCmd:
|
| 2835 |
rtl8139_CpCmd_write(s, val); |
| 2836 |
break;
|
| 2837 |
|
| 2838 |
case IntrMitigate:
|
| 2839 |
rtl8139_IntrMitigate_write(s, val); |
| 2840 |
break;
|
| 2841 |
|
| 2842 |
default:
|
| 2843 |
DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
|
| 2844 |
addr, val); |
| 2845 |
|
| 2846 |
rtl8139_io_writeb(opaque, addr, val & 0xff);
|
| 2847 |
rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2848 |
break;
|
| 2849 |
} |
| 2850 |
} |
| 2851 |
|
| 2852 |
static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time) |
| 2853 |
{
|
| 2854 |
int64_t pci_time, next_time; |
| 2855 |
uint32_t low_pci; |
| 2856 |
|
| 2857 |
DPRINTF("entered rtl8139_set_next_tctr_time\n");
|
| 2858 |
|
| 2859 |
if (s->TimerExpire && current_time >= s->TimerExpire) {
|
| 2860 |
s->IntrStatus |= PCSTimeout; |
| 2861 |
rtl8139_update_irq(s); |
| 2862 |
} |
| 2863 |
|
| 2864 |
/* Set QEMU timer only if needed that is
|
| 2865 |
* - TimerInt <> 0 (we have a timer)
|
| 2866 |
* - mask = 1 (we want an interrupt timer)
|
| 2867 |
* - irq = 0 (irq is not already active)
|
| 2868 |
* If any of above change we need to compute timer again
|
| 2869 |
* Also we must check if timer is passed without QEMU timer
|
| 2870 |
*/
|
| 2871 |
s->TimerExpire = 0;
|
| 2872 |
if (!s->TimerInt) {
|
| 2873 |
return;
|
| 2874 |
} |
| 2875 |
|
| 2876 |
pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, |
| 2877 |
get_ticks_per_sec()); |
| 2878 |
low_pci = pci_time & 0xffffffff;
|
| 2879 |
pci_time = pci_time - low_pci + s->TimerInt; |
| 2880 |
if (low_pci >= s->TimerInt) {
|
| 2881 |
pci_time += 0x100000000LL;
|
| 2882 |
} |
| 2883 |
next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(), |
| 2884 |
PCI_FREQUENCY); |
| 2885 |
s->TimerExpire = next_time; |
| 2886 |
|
| 2887 |
if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) { |
| 2888 |
qemu_mod_timer(s->timer, next_time); |
| 2889 |
} |
| 2890 |
} |
| 2891 |
|
| 2892 |
static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) |
| 2893 |
{
|
| 2894 |
RTL8139State *s = opaque; |
| 2895 |
|
| 2896 |
addr &= 0xfc;
|
| 2897 |
|
| 2898 |
switch (addr)
|
| 2899 |
{
|
| 2900 |
case RxMissed:
|
| 2901 |
DPRINTF("RxMissed clearing on write\n");
|
| 2902 |
s->RxMissed = 0;
|
| 2903 |
break;
|
| 2904 |
|
| 2905 |
case TxConfig:
|
| 2906 |
rtl8139_TxConfig_write(s, val); |
| 2907 |
break;
|
| 2908 |
|
| 2909 |
case RxConfig:
|
| 2910 |
rtl8139_RxConfig_write(s, val); |
| 2911 |
break;
|
| 2912 |
|
| 2913 |
case TxStatus0 ... TxStatus0+4*4-1: |
| 2914 |
rtl8139_TxStatus_write(s, addr-TxStatus0, val); |
| 2915 |
break;
|
| 2916 |
|
| 2917 |
case TxAddr0 ... TxAddr0+4*4-1: |
| 2918 |
rtl8139_TxAddr_write(s, addr-TxAddr0, val); |
| 2919 |
break;
|
| 2920 |
|
| 2921 |
case RxBuf:
|
| 2922 |
rtl8139_RxBuf_write(s, val); |
| 2923 |
break;
|
| 2924 |
|
| 2925 |
case RxRingAddrLO:
|
| 2926 |
DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
|
| 2927 |
s->RxRingAddrLO = val; |
| 2928 |
break;
|
| 2929 |
|
| 2930 |
case RxRingAddrHI:
|
| 2931 |
DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
|
| 2932 |
s->RxRingAddrHI = val; |
| 2933 |
break;
|
| 2934 |
|
| 2935 |
case Timer:
|
| 2936 |
DPRINTF("TCTR Timer reset on write\n");
|
| 2937 |
s->TCTR_base = qemu_get_clock_ns(vm_clock); |
| 2938 |
rtl8139_set_next_tctr_time(s, s->TCTR_base); |
| 2939 |
break;
|
| 2940 |
|
| 2941 |
case FlashReg:
|
| 2942 |
DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
|
| 2943 |
if (s->TimerInt != val) {
|
| 2944 |
s->TimerInt = val; |
| 2945 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
| 2946 |
} |
| 2947 |
break;
|
| 2948 |
|
| 2949 |
default:
|
| 2950 |
DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
|
| 2951 |
addr, val); |
| 2952 |
rtl8139_io_writeb(opaque, addr, val & 0xff);
|
| 2953 |
rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2954 |
rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
| 2955 |
rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
| 2956 |
break;
|
| 2957 |
} |
| 2958 |
} |
| 2959 |
|
| 2960 |
static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) |
| 2961 |
{
|
| 2962 |
RTL8139State *s = opaque; |
| 2963 |
int ret;
|
| 2964 |
|
| 2965 |
addr &= 0xff;
|
| 2966 |
|
| 2967 |
switch (addr)
|
| 2968 |
{
|
| 2969 |
case MAC0 ... MAC0+5: |
| 2970 |
ret = s->phys[addr - MAC0]; |
| 2971 |
break;
|
| 2972 |
case MAC0+6 ... MAC0+7: |
| 2973 |
ret = 0;
|
| 2974 |
break;
|
| 2975 |
case MAR0 ... MAR0+7: |
| 2976 |
ret = s->mult[addr - MAR0]; |
| 2977 |
break;
|
| 2978 |
case ChipCmd:
|
| 2979 |
ret = rtl8139_ChipCmd_read(s); |
| 2980 |
break;
|
| 2981 |
case Cfg9346:
|
| 2982 |
ret = rtl8139_Cfg9346_read(s); |
| 2983 |
break;
|
| 2984 |
case Config0:
|
| 2985 |
ret = rtl8139_Config0_read(s); |
| 2986 |
break;
|
| 2987 |
case Config1:
|
| 2988 |
ret = rtl8139_Config1_read(s); |
| 2989 |
break;
|
| 2990 |
case Config3:
|
| 2991 |
ret = rtl8139_Config3_read(s); |
| 2992 |
break;
|
| 2993 |
case Config4:
|
| 2994 |
ret = rtl8139_Config4_read(s); |
| 2995 |
break;
|
| 2996 |
case Config5:
|
| 2997 |
ret = rtl8139_Config5_read(s); |
| 2998 |
break;
|
| 2999 |
|
| 3000 |
case MediaStatus:
|
| 3001 |
ret = 0xd0;
|
| 3002 |
DPRINTF("MediaStatus read 0x%x\n", ret);
|
| 3003 |
break;
|
| 3004 |
|
| 3005 |
case HltClk:
|
| 3006 |
ret = s->clock_enabled; |
| 3007 |
DPRINTF("HltClk read 0x%x\n", ret);
|
| 3008 |
break;
|
| 3009 |
|
| 3010 |
case PCIRevisionID:
|
| 3011 |
ret = RTL8139_PCI_REVID; |
| 3012 |
DPRINTF("PCI Revision ID read 0x%x\n", ret);
|
| 3013 |
break;
|
| 3014 |
|
| 3015 |
case TxThresh:
|
| 3016 |
ret = s->TxThresh; |
| 3017 |
DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
|
| 3018 |
break;
|
| 3019 |
|
| 3020 |
case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ |
| 3021 |
ret = s->TxConfig >> 24;
|
| 3022 |
DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
|
| 3023 |
break;
|
| 3024 |
|
| 3025 |
default:
|
| 3026 |
DPRINTF("not implemented read(b) addr=0x%x\n", addr);
|
| 3027 |
ret = 0;
|
| 3028 |
break;
|
| 3029 |
} |
| 3030 |
|
| 3031 |
return ret;
|
| 3032 |
} |
| 3033 |
|
| 3034 |
static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) |
| 3035 |
{
|
| 3036 |
RTL8139State *s = opaque; |
| 3037 |
uint32_t ret; |
| 3038 |
|
| 3039 |
addr &= 0xfe; /* mask lower bit */ |
| 3040 |
|
| 3041 |
switch (addr)
|
| 3042 |
{
|
| 3043 |
case IntrMask:
|
| 3044 |
ret = rtl8139_IntrMask_read(s); |
| 3045 |
break;
|
| 3046 |
|
| 3047 |
case IntrStatus:
|
| 3048 |
ret = rtl8139_IntrStatus_read(s); |
| 3049 |
break;
|
| 3050 |
|
| 3051 |
case MultiIntr:
|
| 3052 |
ret = rtl8139_MultiIntr_read(s); |
| 3053 |
break;
|
| 3054 |
|
| 3055 |
case RxBufPtr:
|
| 3056 |
ret = rtl8139_RxBufPtr_read(s); |
| 3057 |
break;
|
| 3058 |
|
| 3059 |
case RxBufAddr:
|
| 3060 |
ret = rtl8139_RxBufAddr_read(s); |
| 3061 |
break;
|
| 3062 |
|
| 3063 |
case BasicModeCtrl:
|
| 3064 |
ret = rtl8139_BasicModeCtrl_read(s); |
| 3065 |
break;
|
| 3066 |
case BasicModeStatus:
|
| 3067 |
ret = rtl8139_BasicModeStatus_read(s); |
| 3068 |
break;
|
| 3069 |
case NWayAdvert:
|
| 3070 |
ret = s->NWayAdvert; |
| 3071 |
DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
|
| 3072 |
break;
|
| 3073 |
case NWayLPAR:
|
| 3074 |
ret = s->NWayLPAR; |
| 3075 |
DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
|
| 3076 |
break;
|
| 3077 |
case NWayExpansion:
|
| 3078 |
ret = s->NWayExpansion; |
| 3079 |
DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
|
| 3080 |
break;
|
| 3081 |
|
| 3082 |
case CpCmd:
|
| 3083 |
ret = rtl8139_CpCmd_read(s); |
| 3084 |
break;
|
| 3085 |
|
| 3086 |
case IntrMitigate:
|
| 3087 |
ret = rtl8139_IntrMitigate_read(s); |
| 3088 |
break;
|
| 3089 |
|
| 3090 |
case TxSummary:
|
| 3091 |
ret = rtl8139_TSAD_read(s); |
| 3092 |
break;
|
| 3093 |
|
| 3094 |
case CSCR:
|
| 3095 |
ret = rtl8139_CSCR_read(s); |
| 3096 |
break;
|
| 3097 |
|
| 3098 |
default:
|
| 3099 |
DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
|
| 3100 |
|
| 3101 |
ret = rtl8139_io_readb(opaque, addr); |
| 3102 |
ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
| 3103 |
|
| 3104 |
DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
|
| 3105 |
break;
|
| 3106 |
} |
| 3107 |
|
| 3108 |
return ret;
|
| 3109 |
} |
| 3110 |
|
| 3111 |
static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) |
| 3112 |
{
|
| 3113 |
RTL8139State *s = opaque; |
| 3114 |
uint32_t ret; |
| 3115 |
|
| 3116 |
addr &= 0xfc; /* also mask low 2 bits */ |
| 3117 |
|
| 3118 |
switch (addr)
|
| 3119 |
{
|
| 3120 |
case RxMissed:
|
| 3121 |
ret = s->RxMissed; |
| 3122 |
|
| 3123 |
DPRINTF("RxMissed read val=0x%08x\n", ret);
|
| 3124 |
break;
|
| 3125 |
|
| 3126 |
case TxConfig:
|
| 3127 |
ret = rtl8139_TxConfig_read(s); |
| 3128 |
break;
|
| 3129 |
|
| 3130 |
case RxConfig:
|
| 3131 |
ret = rtl8139_RxConfig_read(s); |
| 3132 |
break;
|
| 3133 |
|
| 3134 |
case TxStatus0 ... TxStatus0+4*4-1: |
| 3135 |
ret = rtl8139_TxStatus_read(s, addr-TxStatus0); |
| 3136 |
break;
|
| 3137 |
|
| 3138 |
case TxAddr0 ... TxAddr0+4*4-1: |
| 3139 |
ret = rtl8139_TxAddr_read(s, addr-TxAddr0); |
| 3140 |
break;
|
| 3141 |
|
| 3142 |
case RxBuf:
|
| 3143 |
ret = rtl8139_RxBuf_read(s); |
| 3144 |
break;
|
| 3145 |
|
| 3146 |
case RxRingAddrLO:
|
| 3147 |
ret = s->RxRingAddrLO; |
| 3148 |
DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
|
| 3149 |
break;
|
| 3150 |
|
| 3151 |
case RxRingAddrHI:
|
| 3152 |
ret = s->RxRingAddrHI; |
| 3153 |
DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
|
| 3154 |
break;
|
| 3155 |
|
| 3156 |
case Timer:
|
| 3157 |
ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base, |
| 3158 |
PCI_FREQUENCY, get_ticks_per_sec()); |
| 3159 |
DPRINTF("TCTR Timer read val=0x%08x\n", ret);
|
| 3160 |
break;
|
| 3161 |
|
| 3162 |
case FlashReg:
|
| 3163 |
ret = s->TimerInt; |
| 3164 |
DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
|
| 3165 |
break;
|
| 3166 |
|
| 3167 |
default:
|
| 3168 |
DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
|
| 3169 |
|
| 3170 |
ret = rtl8139_io_readb(opaque, addr); |
| 3171 |
ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
| 3172 |
ret |= rtl8139_io_readb(opaque, addr + 2) << 16; |
| 3173 |
ret |= rtl8139_io_readb(opaque, addr + 3) << 24; |
| 3174 |
|
| 3175 |
DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
|
| 3176 |
break;
|
| 3177 |
} |
| 3178 |
|
| 3179 |
return ret;
|
| 3180 |
} |
| 3181 |
|
| 3182 |
/* */
|
| 3183 |
|
| 3184 |
static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
| 3185 |
{
|
| 3186 |
rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
| 3187 |
} |
| 3188 |
|
| 3189 |
static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
| 3190 |
{
|
| 3191 |
rtl8139_io_writew(opaque, addr & 0xFF, val);
|
| 3192 |
} |
| 3193 |
|
| 3194 |
static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
| 3195 |
{
|
| 3196 |
rtl8139_io_writel(opaque, addr & 0xFF, val);
|
| 3197 |
} |
| 3198 |
|
| 3199 |
static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr) |
| 3200 |
{
|
| 3201 |
return rtl8139_io_readb(opaque, addr & 0xFF); |
| 3202 |
} |
| 3203 |
|
| 3204 |
static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr) |
| 3205 |
{
|
| 3206 |
return rtl8139_io_readw(opaque, addr & 0xFF); |
| 3207 |
} |
| 3208 |
|
| 3209 |
static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr) |
| 3210 |
{
|
| 3211 |
return rtl8139_io_readl(opaque, addr & 0xFF); |
| 3212 |
} |
| 3213 |
|
| 3214 |
/* */
|
| 3215 |
|
| 3216 |
static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 3217 |
{
|
| 3218 |
rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
| 3219 |
} |
| 3220 |
|
| 3221 |
static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 3222 |
{
|
| 3223 |
rtl8139_io_writew(opaque, addr & 0xFF, val);
|
| 3224 |
} |
| 3225 |
|
| 3226 |
static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 3227 |
{
|
| 3228 |
rtl8139_io_writel(opaque, addr & 0xFF, val);
|
| 3229 |
} |
| 3230 |
|
| 3231 |
static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr) |
| 3232 |
{
|
| 3233 |
return rtl8139_io_readb(opaque, addr & 0xFF); |
| 3234 |
} |
| 3235 |
|
| 3236 |
static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr) |
| 3237 |
{
|
| 3238 |
uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
|
| 3239 |
return val;
|
| 3240 |
} |
| 3241 |
|
| 3242 |
static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr) |
| 3243 |
{
|
| 3244 |
uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
|
| 3245 |
return val;
|
| 3246 |
} |
| 3247 |
|
| 3248 |
static int rtl8139_post_load(void *opaque, int version_id) |
| 3249 |
{
|
| 3250 |
RTL8139State* s = opaque; |
| 3251 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
| 3252 |
if (version_id < 4) { |
| 3253 |
s->cplus_enabled = s->CpCmd != 0;
|
| 3254 |
} |
| 3255 |
|
| 3256 |
return 0; |
| 3257 |
} |
| 3258 |
|
| 3259 |
static bool rtl8139_hotplug_ready_needed(void *opaque) |
| 3260 |
{
|
| 3261 |
return qdev_machine_modified();
|
| 3262 |
} |
| 3263 |
|
| 3264 |
static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ |
| 3265 |
.name = "rtl8139/hotplug_ready",
|
| 3266 |
.version_id = 1,
|
| 3267 |
.minimum_version_id = 1,
|
| 3268 |
.minimum_version_id_old = 1,
|
| 3269 |
.fields = (VMStateField []) {
|
| 3270 |
VMSTATE_END_OF_LIST() |
| 3271 |
} |
| 3272 |
}; |
| 3273 |
|
| 3274 |
static void rtl8139_pre_save(void *opaque) |
| 3275 |
{
|
| 3276 |
RTL8139State* s = opaque; |
| 3277 |
int64_t current_time = qemu_get_clock_ns(vm_clock); |
| 3278 |
|
| 3279 |
/* set IntrStatus correctly */
|
| 3280 |
rtl8139_set_next_tctr_time(s, current_time); |
| 3281 |
s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, |
| 3282 |
get_ticks_per_sec()); |
| 3283 |
s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr; |
| 3284 |
} |
| 3285 |
|
| 3286 |
static const VMStateDescription vmstate_rtl8139 = { |
| 3287 |
.name = "rtl8139",
|
| 3288 |
.version_id = 4,
|
| 3289 |
.minimum_version_id = 3,
|
| 3290 |
.minimum_version_id_old = 3,
|
| 3291 |
.post_load = rtl8139_post_load, |
| 3292 |
.pre_save = rtl8139_pre_save, |
| 3293 |
.fields = (VMStateField []) {
|
| 3294 |
VMSTATE_PCI_DEVICE(dev, RTL8139State), |
| 3295 |
VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
|
| 3296 |
VMSTATE_BUFFER(mult, RTL8139State), |
| 3297 |
VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
|
| 3298 |
VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
|
| 3299 |
|
| 3300 |
VMSTATE_UINT32(RxBuf, RTL8139State), |
| 3301 |
VMSTATE_UINT32(RxBufferSize, RTL8139State), |
| 3302 |
VMSTATE_UINT32(RxBufPtr, RTL8139State), |
| 3303 |
VMSTATE_UINT32(RxBufAddr, RTL8139State), |
| 3304 |
|
| 3305 |
VMSTATE_UINT16(IntrStatus, RTL8139State), |
| 3306 |
VMSTATE_UINT16(IntrMask, RTL8139State), |
| 3307 |
|
| 3308 |
VMSTATE_UINT32(TxConfig, RTL8139State), |
| 3309 |
VMSTATE_UINT32(RxConfig, RTL8139State), |
| 3310 |
VMSTATE_UINT32(RxMissed, RTL8139State), |
| 3311 |
VMSTATE_UINT16(CSCR, RTL8139State), |
| 3312 |
|
| 3313 |
VMSTATE_UINT8(Cfg9346, RTL8139State), |
| 3314 |
VMSTATE_UINT8(Config0, RTL8139State), |
| 3315 |
VMSTATE_UINT8(Config1, RTL8139State), |
| 3316 |
VMSTATE_UINT8(Config3, RTL8139State), |
| 3317 |
VMSTATE_UINT8(Config4, RTL8139State), |
| 3318 |
VMSTATE_UINT8(Config5, RTL8139State), |
| 3319 |
|
| 3320 |
VMSTATE_UINT8(clock_enabled, RTL8139State), |
| 3321 |
VMSTATE_UINT8(bChipCmdState, RTL8139State), |
| 3322 |
|
| 3323 |
VMSTATE_UINT16(MultiIntr, RTL8139State), |
| 3324 |
|
| 3325 |
VMSTATE_UINT16(BasicModeCtrl, RTL8139State), |
| 3326 |
VMSTATE_UINT16(BasicModeStatus, RTL8139State), |
| 3327 |
VMSTATE_UINT16(NWayAdvert, RTL8139State), |
| 3328 |
VMSTATE_UINT16(NWayLPAR, RTL8139State), |
| 3329 |
VMSTATE_UINT16(NWayExpansion, RTL8139State), |
| 3330 |
|
| 3331 |
VMSTATE_UINT16(CpCmd, RTL8139State), |
| 3332 |
VMSTATE_UINT8(TxThresh, RTL8139State), |
| 3333 |
|
| 3334 |
VMSTATE_UNUSED(4),
|
| 3335 |
VMSTATE_MACADDR(conf.macaddr, RTL8139State), |
| 3336 |
VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), |
| 3337 |
|
| 3338 |
VMSTATE_UINT32(currTxDesc, RTL8139State), |
| 3339 |
VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), |
| 3340 |
VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), |
| 3341 |
VMSTATE_UINT32(RxRingAddrLO, RTL8139State), |
| 3342 |
VMSTATE_UINT32(RxRingAddrHI, RTL8139State), |
| 3343 |
|
| 3344 |
VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), |
| 3345 |
VMSTATE_INT32(eeprom.mode, RTL8139State), |
| 3346 |
VMSTATE_UINT32(eeprom.tick, RTL8139State), |
| 3347 |
VMSTATE_UINT8(eeprom.address, RTL8139State), |
| 3348 |
VMSTATE_UINT16(eeprom.input, RTL8139State), |
| 3349 |
VMSTATE_UINT16(eeprom.output, RTL8139State), |
| 3350 |
|
| 3351 |
VMSTATE_UINT8(eeprom.eecs, RTL8139State), |
| 3352 |
VMSTATE_UINT8(eeprom.eesk, RTL8139State), |
| 3353 |
VMSTATE_UINT8(eeprom.eedi, RTL8139State), |
| 3354 |
VMSTATE_UINT8(eeprom.eedo, RTL8139State), |
| 3355 |
|
| 3356 |
VMSTATE_UINT32(TCTR, RTL8139State), |
| 3357 |
VMSTATE_UINT32(TimerInt, RTL8139State), |
| 3358 |
VMSTATE_INT64(TCTR_base, RTL8139State), |
| 3359 |
|
| 3360 |
VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
|
| 3361 |
vmstate_tally_counters, RTL8139TallyCounters), |
| 3362 |
|
| 3363 |
VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
|
| 3364 |
VMSTATE_END_OF_LIST() |
| 3365 |
}, |
| 3366 |
.subsections = (VMStateSubsection []) {
|
| 3367 |
{
|
| 3368 |
.vmsd = &vmstate_rtl8139_hotplug_ready, |
| 3369 |
.needed = rtl8139_hotplug_ready_needed, |
| 3370 |
}, {
|
| 3371 |
/* empty */
|
| 3372 |
} |
| 3373 |
} |
| 3374 |
}; |
| 3375 |
|
| 3376 |
/***********************************************************/
|
| 3377 |
/* PCI RTL8139 definitions */
|
| 3378 |
|
| 3379 |
static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num, |
| 3380 |
pcibus_t addr, pcibus_t size, int type)
|
| 3381 |
{
|
| 3382 |
RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev); |
| 3383 |
|
| 3384 |
cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr); |
| 3385 |
} |
| 3386 |
|
| 3387 |
static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num, |
| 3388 |
pcibus_t addr, pcibus_t size, int type)
|
| 3389 |
{
|
| 3390 |
RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev); |
| 3391 |
|
| 3392 |
register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s); |
| 3393 |
register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s); |
| 3394 |
|
| 3395 |
register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s); |
| 3396 |
register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s); |
| 3397 |
|
| 3398 |
register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s); |
| 3399 |
register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s); |
| 3400 |
} |
| 3401 |
|
| 3402 |
static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = { |
| 3403 |
rtl8139_mmio_readb, |
| 3404 |
rtl8139_mmio_readw, |
| 3405 |
rtl8139_mmio_readl, |
| 3406 |
}; |
| 3407 |
|
| 3408 |
static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = { |
| 3409 |
rtl8139_mmio_writeb, |
| 3410 |
rtl8139_mmio_writew, |
| 3411 |
rtl8139_mmio_writel, |
| 3412 |
}; |
| 3413 |
|
| 3414 |
static void rtl8139_timer(void *opaque) |
| 3415 |
{
|
| 3416 |
RTL8139State *s = opaque; |
| 3417 |
|
| 3418 |
if (!s->clock_enabled)
|
| 3419 |
{
|
| 3420 |
DPRINTF(">>> timer: clock is not running\n");
|
| 3421 |
return;
|
| 3422 |
} |
| 3423 |
|
| 3424 |
s->IntrStatus |= PCSTimeout; |
| 3425 |
rtl8139_update_irq(s); |
| 3426 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
| 3427 |
} |
| 3428 |
|
| 3429 |
static void rtl8139_cleanup(VLANClientState *nc) |
| 3430 |
{
|
| 3431 |
RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
| 3432 |
|
| 3433 |
s->nic = NULL;
|
| 3434 |
} |
| 3435 |
|
| 3436 |
static int pci_rtl8139_uninit(PCIDevice *dev) |
| 3437 |
{
|
| 3438 |
RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev); |
| 3439 |
|
| 3440 |
cpu_unregister_io_memory(s->rtl8139_mmio_io_addr); |
| 3441 |
if (s->cplus_txbuffer) {
|
| 3442 |
qemu_free(s->cplus_txbuffer); |
| 3443 |
s->cplus_txbuffer = NULL;
|
| 3444 |
} |
| 3445 |
qemu_del_timer(s->timer); |
| 3446 |
qemu_free_timer(s->timer); |
| 3447 |
qemu_del_vlan_client(&s->nic->nc); |
| 3448 |
return 0; |
| 3449 |
} |
| 3450 |
|
| 3451 |
static NetClientInfo net_rtl8139_info = {
|
| 3452 |
.type = NET_CLIENT_TYPE_NIC, |
| 3453 |
.size = sizeof(NICState),
|
| 3454 |
.can_receive = rtl8139_can_receive, |
| 3455 |
.receive = rtl8139_receive, |
| 3456 |
.cleanup = rtl8139_cleanup, |
| 3457 |
}; |
| 3458 |
|
| 3459 |
static int pci_rtl8139_init(PCIDevice *dev) |
| 3460 |
{
|
| 3461 |
RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev); |
| 3462 |
uint8_t *pci_conf; |
| 3463 |
|
| 3464 |
pci_conf = s->dev.config; |
| 3465 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); |
| 3466 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139); |
| 3467 |
pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
|
| 3468 |
pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
| 3469 |
pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */ |
| 3470 |
/* TODO: start of capability list, but no capability
|
| 3471 |
* list bit in status register, and offset 0xdc seems unused. */
|
| 3472 |
pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
|
| 3473 |
|
| 3474 |
/* I/O handler for memory-mapped I/O */
|
| 3475 |
s->rtl8139_mmio_io_addr = |
| 3476 |
cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s, |
| 3477 |
DEVICE_LITTLE_ENDIAN); |
| 3478 |
|
| 3479 |
pci_register_bar(&s->dev, 0, 0x100, |
| 3480 |
PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map); |
| 3481 |
|
| 3482 |
pci_register_bar(&s->dev, 1, 0x100, |
| 3483 |
PCI_BASE_ADDRESS_SPACE_MEMORY, rtl8139_mmio_map); |
| 3484 |
|
| 3485 |
qemu_macaddr_default_if_unset(&s->conf.macaddr); |
| 3486 |
|
| 3487 |
/* prepare eeprom */
|
| 3488 |
s->eeprom.contents[0] = 0x8129; |
| 3489 |
#if 1 |
| 3490 |
/* PCI vendor and device ID should be mirrored here */
|
| 3491 |
s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
|
| 3492 |
s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
|
| 3493 |
#endif
|
| 3494 |
s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; |
| 3495 |
s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; |
| 3496 |
s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; |
| 3497 |
|
| 3498 |
s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, |
| 3499 |
dev->qdev.info->name, dev->qdev.id, s); |
| 3500 |
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
| 3501 |
|
| 3502 |
s->cplus_txbuffer = NULL;
|
| 3503 |
s->cplus_txbuffer_len = 0;
|
| 3504 |
s->cplus_txbuffer_offset = 0;
|
| 3505 |
|
| 3506 |
s->TimerExpire = 0;
|
| 3507 |
s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s); |
| 3508 |
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
| 3509 |
|
| 3510 |
add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
|
| 3511 |
|
| 3512 |
return 0; |
| 3513 |
} |
| 3514 |
|
| 3515 |
static PCIDeviceInfo rtl8139_info = {
|
| 3516 |
.qdev.name = "rtl8139",
|
| 3517 |
.qdev.size = sizeof(RTL8139State),
|
| 3518 |
.qdev.reset = rtl8139_reset, |
| 3519 |
.qdev.vmsd = &vmstate_rtl8139, |
| 3520 |
.init = pci_rtl8139_init, |
| 3521 |
.exit = pci_rtl8139_uninit, |
| 3522 |
.romfile = "pxe-rtl8139.rom",
|
| 3523 |
.qdev.props = (Property[]) {
|
| 3524 |
DEFINE_NIC_PROPERTIES(RTL8139State, conf), |
| 3525 |
DEFINE_PROP_END_OF_LIST(), |
| 3526 |
} |
| 3527 |
}; |
| 3528 |
|
| 3529 |
static void rtl8139_register_devices(void) |
| 3530 |
{
|
| 3531 |
pci_qdev_register(&rtl8139_info); |
| 3532 |
} |
| 3533 |
|
| 3534 |
device_init(rtl8139_register_devices) |