root / hw / sparc32_dma.c @ ed23fbd9
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1 | 67e999be | bellard | /*
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2 | 67e999be | bellard | * QEMU Sparc32 DMA controller emulation
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3 | 67e999be | bellard | *
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4 | 67e999be | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | 67e999be | bellard | *
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6 | 67e999be | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 67e999be | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 67e999be | bellard | * in the Software without restriction, including without limitation the rights
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9 | 67e999be | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 67e999be | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 67e999be | bellard | * furnished to do so, subject to the following conditions:
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12 | 67e999be | bellard | *
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13 | 67e999be | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 67e999be | bellard | * all copies or substantial portions of the Software.
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15 | 67e999be | bellard | *
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16 | 67e999be | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 67e999be | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 67e999be | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 67e999be | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 67e999be | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 67e999be | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 67e999be | bellard | * THE SOFTWARE.
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23 | 67e999be | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
26 | 87ecb68b | pbrook | #include "sun4m.h" |
27 | 67e999be | bellard | |
28 | 67e999be | bellard | /* debug DMA */
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29 | 67e999be | bellard | //#define DEBUG_DMA
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30 | 67e999be | bellard | |
31 | 67e999be | bellard | /*
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32 | 67e999be | bellard | * This is the DMA controller part of chip STP2000 (Master I/O), also
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33 | 67e999be | bellard | * produced as NCR89C100. See
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34 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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35 | 67e999be | bellard | * and
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36 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
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37 | 67e999be | bellard | */
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38 | 67e999be | bellard | |
39 | 67e999be | bellard | #ifdef DEBUG_DMA
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40 | 67e999be | bellard | #define DPRINTF(fmt, args...) \
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41 | 67e999be | bellard | do { printf("DMA: " fmt , ##args); } while (0) |
42 | 67e999be | bellard | #else
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43 | 67e999be | bellard | #define DPRINTF(fmt, args...)
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44 | 67e999be | bellard | #endif
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45 | 67e999be | bellard | |
46 | 5aca8c3b | blueswir1 | #define DMA_REGS 4 |
47 | 5aca8c3b | blueswir1 | #define DMA_SIZE (4 * sizeof(uint32_t)) |
48 | 5aca8c3b | blueswir1 | #define DMA_MAXADDR (DMA_SIZE - 1) |
49 | 67e999be | bellard | |
50 | 67e999be | bellard | #define DMA_VER 0xa0000000 |
51 | 67e999be | bellard | #define DMA_INTR 1 |
52 | 67e999be | bellard | #define DMA_INTREN 0x10 |
53 | 67e999be | bellard | #define DMA_WRITE_MEM 0x100 |
54 | 67e999be | bellard | #define DMA_LOADED 0x04000000 |
55 | 5aca8c3b | blueswir1 | #define DMA_DRAIN_FIFO 0x40 |
56 | 67e999be | bellard | #define DMA_RESET 0x80 |
57 | 67e999be | bellard | |
58 | 67e999be | bellard | typedef struct DMAState DMAState; |
59 | 67e999be | bellard | |
60 | 67e999be | bellard | struct DMAState {
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61 | 67e999be | bellard | uint32_t dmaregs[DMA_REGS]; |
62 | 5aca8c3b | blueswir1 | qemu_irq irq; |
63 | 2d069bab | blueswir1 | void *iommu;
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64 | 2d069bab | blueswir1 | qemu_irq dev_reset; |
65 | 67e999be | bellard | }; |
66 | 67e999be | bellard | |
67 | 9b94dc32 | bellard | /* Note: on sparc, the lance 16 bit bus is swapped */
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68 | 5fafdf24 | ths | void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
69 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
70 | 67e999be | bellard | { |
71 | 67e999be | bellard | DMAState *s = opaque; |
72 | 9b94dc32 | bellard | int i;
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73 | 67e999be | bellard | |
74 | 67e999be | bellard | DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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75 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
76 | 5aca8c3b | blueswir1 | addr |= s->dmaregs[3];
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77 | 9b94dc32 | bellard | if (do_bswap) {
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78 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
79 | 9b94dc32 | bellard | } else {
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80 | 9b94dc32 | bellard | addr &= ~1;
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81 | 9b94dc32 | bellard | len &= ~1;
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82 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
83 | 9b94dc32 | bellard | for(i = 0; i < len; i += 2) { |
84 | 9b94dc32 | bellard | bswap16s((uint16_t *)(buf + i)); |
85 | 9b94dc32 | bellard | } |
86 | 9b94dc32 | bellard | } |
87 | 67e999be | bellard | } |
88 | 67e999be | bellard | |
89 | 5fafdf24 | ths | void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
90 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
91 | 67e999be | bellard | { |
92 | 67e999be | bellard | DMAState *s = opaque; |
93 | 9b94dc32 | bellard | int l, i;
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94 | 9b94dc32 | bellard | uint16_t tmp_buf[32];
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95 | 67e999be | bellard | |
96 | 67e999be | bellard | DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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97 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
98 | 5aca8c3b | blueswir1 | addr |= s->dmaregs[3];
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99 | 9b94dc32 | bellard | if (do_bswap) {
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100 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, buf, len); |
101 | 9b94dc32 | bellard | } else {
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102 | 9b94dc32 | bellard | addr &= ~1;
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103 | 9b94dc32 | bellard | len &= ~1;
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104 | 9b94dc32 | bellard | while (len > 0) { |
105 | 9b94dc32 | bellard | l = len; |
106 | 9b94dc32 | bellard | if (l > sizeof(tmp_buf)) |
107 | 9b94dc32 | bellard | l = sizeof(tmp_buf);
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108 | 9b94dc32 | bellard | for(i = 0; i < l; i += 2) { |
109 | 9b94dc32 | bellard | tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
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110 | 9b94dc32 | bellard | } |
111 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l); |
112 | 9b94dc32 | bellard | len -= l; |
113 | 9b94dc32 | bellard | buf += l; |
114 | 9b94dc32 | bellard | addr += l; |
115 | 9b94dc32 | bellard | } |
116 | 9b94dc32 | bellard | } |
117 | 67e999be | bellard | } |
118 | 67e999be | bellard | |
119 | 70c0de96 | blueswir1 | static void dma_set_irq(void *opaque, int irq, int level) |
120 | 67e999be | bellard | { |
121 | 67e999be | bellard | DMAState *s = opaque; |
122 | 70c0de96 | blueswir1 | if (level) {
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123 | 9b5207aa | blueswir1 | DPRINTF("Raise IRQ\n");
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124 | 70c0de96 | blueswir1 | s->dmaregs[0] |= DMA_INTR;
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125 | 70c0de96 | blueswir1 | qemu_irq_raise(s->irq); |
126 | 70c0de96 | blueswir1 | } else {
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127 | 70c0de96 | blueswir1 | s->dmaregs[0] &= ~DMA_INTR;
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128 | 9b5207aa | blueswir1 | DPRINTF("Lower IRQ\n");
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129 | 70c0de96 | blueswir1 | qemu_irq_lower(s->irq); |
130 | 70c0de96 | blueswir1 | } |
131 | 67e999be | bellard | } |
132 | 67e999be | bellard | |
133 | 67e999be | bellard | void espdma_memory_read(void *opaque, uint8_t *buf, int len) |
134 | 67e999be | bellard | { |
135 | 67e999be | bellard | DMAState *s = opaque; |
136 | 67e999be | bellard | |
137 | 67e999be | bellard | DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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138 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
139 | 67e999be | bellard | sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
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140 | 67e999be | bellard | s->dmaregs[0] |= DMA_INTR;
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141 | 67e999be | bellard | s->dmaregs[1] += len;
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142 | 67e999be | bellard | } |
143 | 67e999be | bellard | |
144 | 67e999be | bellard | void espdma_memory_write(void *opaque, uint8_t *buf, int len) |
145 | 67e999be | bellard | { |
146 | 67e999be | bellard | DMAState *s = opaque; |
147 | 67e999be | bellard | |
148 | 67e999be | bellard | DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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149 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
150 | 67e999be | bellard | sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
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151 | 67e999be | bellard | s->dmaregs[0] |= DMA_INTR;
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152 | 67e999be | bellard | s->dmaregs[1] += len;
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153 | 67e999be | bellard | } |
154 | 67e999be | bellard | |
155 | 67e999be | bellard | static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr) |
156 | 67e999be | bellard | { |
157 | 67e999be | bellard | DMAState *s = opaque; |
158 | 67e999be | bellard | uint32_t saddr; |
159 | 67e999be | bellard | |
160 | 67e999be | bellard | saddr = (addr & DMA_MAXADDR) >> 2;
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161 | 5aca8c3b | blueswir1 | DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr, |
162 | 5aca8c3b | blueswir1 | s->dmaregs[saddr]); |
163 | 67e999be | bellard | |
164 | 67e999be | bellard | return s->dmaregs[saddr];
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165 | 67e999be | bellard | } |
166 | 67e999be | bellard | |
167 | 67e999be | bellard | static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
168 | 67e999be | bellard | { |
169 | 67e999be | bellard | DMAState *s = opaque; |
170 | 67e999be | bellard | uint32_t saddr; |
171 | 67e999be | bellard | |
172 | 67e999be | bellard | saddr = (addr & DMA_MAXADDR) >> 2;
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173 | 5aca8c3b | blueswir1 | DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr, |
174 | 5aca8c3b | blueswir1 | s->dmaregs[saddr], val); |
175 | 67e999be | bellard | switch (saddr) {
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176 | 67e999be | bellard | case 0: |
177 | d537cf6c | pbrook | if (!(val & DMA_INTREN)) {
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178 | 5aca8c3b | blueswir1 | DPRINTF("Lower IRQ\n");
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179 | 5aca8c3b | blueswir1 | qemu_irq_lower(s->irq); |
180 | d537cf6c | pbrook | } |
181 | 67e999be | bellard | if (val & DMA_RESET) {
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182 | 2d069bab | blueswir1 | qemu_irq_raise(s->dev_reset); |
183 | 2d069bab | blueswir1 | qemu_irq_lower(s->dev_reset); |
184 | 5aca8c3b | blueswir1 | } else if (val & DMA_DRAIN_FIFO) { |
185 | 5aca8c3b | blueswir1 | val &= ~DMA_DRAIN_FIFO; |
186 | 67e999be | bellard | } else if (val == 0) |
187 | 5aca8c3b | blueswir1 | val = DMA_DRAIN_FIFO; |
188 | 67e999be | bellard | val &= 0x0fffffff;
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189 | 67e999be | bellard | val |= DMA_VER; |
190 | 67e999be | bellard | break;
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191 | 67e999be | bellard | case 1: |
192 | 67e999be | bellard | s->dmaregs[0] |= DMA_LOADED;
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193 | 67e999be | bellard | break;
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194 | 67e999be | bellard | default:
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195 | 67e999be | bellard | break;
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196 | 67e999be | bellard | } |
197 | 67e999be | bellard | s->dmaregs[saddr] = val; |
198 | 67e999be | bellard | } |
199 | 67e999be | bellard | |
200 | 67e999be | bellard | static CPUReadMemoryFunc *dma_mem_read[3] = { |
201 | 7c560456 | blueswir1 | NULL,
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202 | 7c560456 | blueswir1 | NULL,
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203 | 67e999be | bellard | dma_mem_readl, |
204 | 67e999be | bellard | }; |
205 | 67e999be | bellard | |
206 | 67e999be | bellard | static CPUWriteMemoryFunc *dma_mem_write[3] = { |
207 | 7c560456 | blueswir1 | NULL,
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208 | 7c560456 | blueswir1 | NULL,
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209 | 67e999be | bellard | dma_mem_writel, |
210 | 67e999be | bellard | }; |
211 | 67e999be | bellard | |
212 | 67e999be | bellard | static void dma_reset(void *opaque) |
213 | 67e999be | bellard | { |
214 | 67e999be | bellard | DMAState *s = opaque; |
215 | 67e999be | bellard | |
216 | 5aca8c3b | blueswir1 | memset(s->dmaregs, 0, DMA_SIZE);
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217 | 67e999be | bellard | s->dmaregs[0] = DMA_VER;
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218 | 67e999be | bellard | } |
219 | 67e999be | bellard | |
220 | 67e999be | bellard | static void dma_save(QEMUFile *f, void *opaque) |
221 | 67e999be | bellard | { |
222 | 67e999be | bellard | DMAState *s = opaque; |
223 | 67e999be | bellard | unsigned int i; |
224 | 67e999be | bellard | |
225 | 67e999be | bellard | for (i = 0; i < DMA_REGS; i++) |
226 | 67e999be | bellard | qemu_put_be32s(f, &s->dmaregs[i]); |
227 | 67e999be | bellard | } |
228 | 67e999be | bellard | |
229 | 67e999be | bellard | static int dma_load(QEMUFile *f, void *opaque, int version_id) |
230 | 67e999be | bellard | { |
231 | 67e999be | bellard | DMAState *s = opaque; |
232 | 67e999be | bellard | unsigned int i; |
233 | 67e999be | bellard | |
234 | 5aca8c3b | blueswir1 | if (version_id != 2) |
235 | 67e999be | bellard | return -EINVAL;
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236 | 67e999be | bellard | for (i = 0; i < DMA_REGS; i++) |
237 | 67e999be | bellard | qemu_get_be32s(f, &s->dmaregs[i]); |
238 | 67e999be | bellard | |
239 | 67e999be | bellard | return 0; |
240 | 67e999be | bellard | } |
241 | 67e999be | bellard | |
242 | 70c0de96 | blueswir1 | void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
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243 | 2d069bab | blueswir1 | void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
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244 | 67e999be | bellard | { |
245 | 67e999be | bellard | DMAState *s; |
246 | 67e999be | bellard | int dma_io_memory;
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247 | 67e999be | bellard | |
248 | 67e999be | bellard | s = qemu_mallocz(sizeof(DMAState));
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249 | 67e999be | bellard | if (!s)
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250 | 67e999be | bellard | return NULL; |
251 | 67e999be | bellard | |
252 | 70c0de96 | blueswir1 | s->irq = parent_irq; |
253 | 67e999be | bellard | s->iommu = iommu; |
254 | 67e999be | bellard | |
255 | 67e999be | bellard | dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
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256 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory); |
257 | 67e999be | bellard | |
258 | 5aca8c3b | blueswir1 | register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s); |
259 | 67e999be | bellard | qemu_register_reset(dma_reset, s); |
260 | 70c0de96 | blueswir1 | *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
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261 | 67e999be | bellard | |
262 | 2d069bab | blueswir1 | *reset = &s->dev_reset; |
263 | 67e999be | bellard | |
264 | 2d069bab | blueswir1 | return s;
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265 | 67e999be | bellard | } |