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1 | 81fdc5f8 | ths | /*
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2 | 81fdc5f8 | ths | * CRIS helper routines
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3 | 81fdc5f8 | ths | *
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4 | 81fdc5f8 | ths | * Copyright (c) 2007 AXIS Communications
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5 | 81fdc5f8 | ths | * Written by Edgar E. Iglesias
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6 | 81fdc5f8 | ths | *
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7 | 81fdc5f8 | ths | * This library is free software; you can redistribute it and/or
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8 | 81fdc5f8 | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 81fdc5f8 | ths | * License as published by the Free Software Foundation; either
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10 | 81fdc5f8 | ths | * version 2 of the License, or (at your option) any later version.
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11 | 81fdc5f8 | ths | *
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12 | 81fdc5f8 | ths | * This library is distributed in the hope that it will be useful,
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13 | 81fdc5f8 | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 81fdc5f8 | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 81fdc5f8 | ths | * Lesser General Public License for more details.
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16 | 81fdc5f8 | ths | *
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17 | 81fdc5f8 | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 81fdc5f8 | ths | * License along with this library; if not, write to the Free Software
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19 | 81fdc5f8 | ths | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 81fdc5f8 | ths | */
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21 | 81fdc5f8 | ths | |
22 | 81fdc5f8 | ths | #include <assert.h> |
23 | 81fdc5f8 | ths | #include "exec.h" |
24 | 786c02f1 | edgar_igl | #include "mmu.h" |
25 | 30abcfc7 | edgar_igl | #include "helper.h" |
26 | 81fdc5f8 | ths | |
27 | e2eef170 | pbrook | #define D(x)
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28 | e2eef170 | pbrook | |
29 | e2eef170 | pbrook | #if !defined(CONFIG_USER_ONLY)
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30 | e2eef170 | pbrook | |
31 | 81fdc5f8 | ths | #define MMUSUFFIX _mmu
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32 | 81fdc5f8 | ths | |
33 | 81fdc5f8 | ths | #define SHIFT 0 |
34 | 81fdc5f8 | ths | #include "softmmu_template.h" |
35 | 81fdc5f8 | ths | |
36 | 81fdc5f8 | ths | #define SHIFT 1 |
37 | 81fdc5f8 | ths | #include "softmmu_template.h" |
38 | 81fdc5f8 | ths | |
39 | 81fdc5f8 | ths | #define SHIFT 2 |
40 | 81fdc5f8 | ths | #include "softmmu_template.h" |
41 | 81fdc5f8 | ths | |
42 | 81fdc5f8 | ths | #define SHIFT 3 |
43 | 81fdc5f8 | ths | #include "softmmu_template.h" |
44 | 81fdc5f8 | ths | |
45 | 81fdc5f8 | ths | /* Try to fill the TLB and return an exception if error. If retaddr is
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46 | 81fdc5f8 | ths | NULL, it means that the function was called in C code (i.e. not
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47 | 81fdc5f8 | ths | from generated code or from helper.c) */
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48 | 81fdc5f8 | ths | /* XXX: fix it to restore all registers */
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49 | 6ebbf390 | j_mayer | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
50 | 81fdc5f8 | ths | { |
51 | 81fdc5f8 | ths | TranslationBlock *tb; |
52 | 81fdc5f8 | ths | CPUState *saved_env; |
53 | 44f8625d | bellard | unsigned long pc; |
54 | 81fdc5f8 | ths | int ret;
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55 | 81fdc5f8 | ths | |
56 | 81fdc5f8 | ths | /* XXX: hack to restore env in all cases, even if not called from
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57 | 81fdc5f8 | ths | generated code */
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58 | 81fdc5f8 | ths | saved_env = env; |
59 | 81fdc5f8 | ths | env = cpu_single_env; |
60 | b41f7df0 | edgar_igl | |
61 | ef29a70d | edgar_igl | D(fprintf(logfile, "%s pc=%x tpc=%x ra=%x\n", __func__,
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62 | ef29a70d | edgar_igl | env->pc, env->debug1, retaddr)); |
63 | 6ebbf390 | j_mayer | ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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64 | 551bd27f | ths | if (unlikely(ret)) {
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65 | 81fdc5f8 | ths | if (retaddr) {
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66 | 81fdc5f8 | ths | /* now we have a real cpu fault */
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67 | 44f8625d | bellard | pc = (unsigned long)retaddr; |
68 | 81fdc5f8 | ths | tb = tb_find_pc(pc); |
69 | 81fdc5f8 | ths | if (tb) {
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70 | 81fdc5f8 | ths | /* the PC is inside the translated code. It means that we have
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71 | 81fdc5f8 | ths | a virtual CPU fault */
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72 | 81fdc5f8 | ths | cpu_restore_state(tb, env, pc, NULL);
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73 | 30abcfc7 | edgar_igl | |
74 | 30abcfc7 | edgar_igl | /* Evaluate flags after retranslation. */
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75 | 30abcfc7 | edgar_igl | helper_top_evaluate_flags(); |
76 | 81fdc5f8 | ths | } |
77 | 81fdc5f8 | ths | } |
78 | 81fdc5f8 | ths | cpu_loop_exit(); |
79 | 81fdc5f8 | ths | } |
80 | 81fdc5f8 | ths | env = saved_env; |
81 | 81fdc5f8 | ths | } |
82 | 81fdc5f8 | ths | |
83 | e2eef170 | pbrook | #endif
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84 | e2eef170 | pbrook | |
85 | dceaf394 | edgar_igl | void helper_raise_exception(uint32_t index)
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86 | 786c02f1 | edgar_igl | { |
87 | dceaf394 | edgar_igl | env->exception_index = index; |
88 | dceaf394 | edgar_igl | cpu_loop_exit(); |
89 | 786c02f1 | edgar_igl | } |
90 | 786c02f1 | edgar_igl | |
91 | cf1d97f0 | edgar_igl | void helper_tlb_flush_pid(uint32_t pid)
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92 | cf1d97f0 | edgar_igl | { |
93 | cf1d97f0 | edgar_igl | #if !defined(CONFIG_USER_ONLY)
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94 | cf1d97f0 | edgar_igl | cris_mmu_flush_pid(env, pid); |
95 | cf1d97f0 | edgar_igl | #endif
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96 | cf1d97f0 | edgar_igl | } |
97 | cf1d97f0 | edgar_igl | |
98 | 30abcfc7 | edgar_igl | void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
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99 | b41f7df0 | edgar_igl | { |
100 | b41f7df0 | edgar_igl | (fprintf(logfile, "%s: a0=%x a1=%x\n", __func__, a0, a1));
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101 | b41f7df0 | edgar_igl | } |
102 | b41f7df0 | edgar_igl | |
103 | b41f7df0 | edgar_igl | void helper_dummy(void) |
104 | b41f7df0 | edgar_igl | { |
105 | b41f7df0 | edgar_igl | |
106 | b41f7df0 | edgar_igl | } |
107 | b41f7df0 | edgar_igl | |
108 | cf1d97f0 | edgar_igl | /* Used by the tlb decoder. */
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109 | cf1d97f0 | edgar_igl | #define EXTRACT_FIELD(src, start, end) \
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110 | cf1d97f0 | edgar_igl | (((src) >> start) & ((1 << (end - start + 1)) - 1)) |
111 | cf1d97f0 | edgar_igl | |
112 | dceaf394 | edgar_igl | void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
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113 | dceaf394 | edgar_igl | { |
114 | dceaf394 | edgar_igl | uint32_t srs; |
115 | dceaf394 | edgar_igl | srs = env->pregs[PR_SRS]; |
116 | dceaf394 | edgar_igl | srs &= 3;
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117 | dceaf394 | edgar_igl | env->sregs[srs][sreg] = env->regs[reg]; |
118 | dceaf394 | edgar_igl | |
119 | dceaf394 | edgar_igl | #if !defined(CONFIG_USER_ONLY)
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120 | dceaf394 | edgar_igl | if (srs == 1 || srs == 2) { |
121 | dceaf394 | edgar_igl | if (sreg == 6) { |
122 | dceaf394 | edgar_igl | /* Writes to tlb-hi write to mm_cause as a side
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123 | dceaf394 | edgar_igl | effect. */
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124 | 6913ba56 | edgar_igl | env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg]; |
125 | 6913ba56 | edgar_igl | env->sregs[SFR_R_MM_CAUSE] = env->regs[reg]; |
126 | dceaf394 | edgar_igl | } |
127 | dceaf394 | edgar_igl | else if (sreg == 5) { |
128 | dceaf394 | edgar_igl | uint32_t set; |
129 | dceaf394 | edgar_igl | uint32_t idx; |
130 | dceaf394 | edgar_igl | uint32_t lo, hi; |
131 | dceaf394 | edgar_igl | uint32_t vaddr; |
132 | cf1d97f0 | edgar_igl | int tlb_v;
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133 | dceaf394 | edgar_igl | |
134 | dceaf394 | edgar_igl | idx = set = env->sregs[SFR_RW_MM_TLB_SEL]; |
135 | dceaf394 | edgar_igl | set >>= 4;
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136 | dceaf394 | edgar_igl | set &= 3;
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137 | dceaf394 | edgar_igl | |
138 | dceaf394 | edgar_igl | idx &= 15;
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139 | dceaf394 | edgar_igl | /* We've just made a write to tlb_lo. */
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140 | dceaf394 | edgar_igl | lo = env->sregs[SFR_RW_MM_TLB_LO]; |
141 | dceaf394 | edgar_igl | /* Writes are done via r_mm_cause. */
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142 | dceaf394 | edgar_igl | hi = env->sregs[SFR_R_MM_CAUSE]; |
143 | cf1d97f0 | edgar_igl | |
144 | cf1d97f0 | edgar_igl | vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
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145 | cf1d97f0 | edgar_igl | 13, 31); |
146 | cf1d97f0 | edgar_igl | vaddr <<= TARGET_PAGE_BITS; |
147 | cf1d97f0 | edgar_igl | tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
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148 | cf1d97f0 | edgar_igl | 3, 3); |
149 | dceaf394 | edgar_igl | env->tlbsets[srs - 1][set][idx].lo = lo;
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150 | dceaf394 | edgar_igl | env->tlbsets[srs - 1][set][idx].hi = hi;
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151 | cf1d97f0 | edgar_igl | |
152 | cf1d97f0 | edgar_igl | D(fprintf(logfile, |
153 | cf1d97f0 | edgar_igl | "tlb flush vaddr=%x v=%d pc=%x\n",
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154 | cf1d97f0 | edgar_igl | vaddr, tlb_v, env->pc)); |
155 | cf1d97f0 | edgar_igl | tlb_flush_page(env, vaddr); |
156 | dceaf394 | edgar_igl | } |
157 | dceaf394 | edgar_igl | } |
158 | dceaf394 | edgar_igl | #endif
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159 | dceaf394 | edgar_igl | } |
160 | dceaf394 | edgar_igl | |
161 | dceaf394 | edgar_igl | void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
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162 | dceaf394 | edgar_igl | { |
163 | dceaf394 | edgar_igl | uint32_t srs; |
164 | dceaf394 | edgar_igl | env->pregs[PR_SRS] &= 3;
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165 | dceaf394 | edgar_igl | srs = env->pregs[PR_SRS]; |
166 | dceaf394 | edgar_igl | |
167 | dceaf394 | edgar_igl | #if !defined(CONFIG_USER_ONLY)
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168 | dceaf394 | edgar_igl | if (srs == 1 || srs == 2) |
169 | dceaf394 | edgar_igl | { |
170 | dceaf394 | edgar_igl | uint32_t set; |
171 | dceaf394 | edgar_igl | uint32_t idx; |
172 | dceaf394 | edgar_igl | uint32_t lo, hi; |
173 | dceaf394 | edgar_igl | |
174 | dceaf394 | edgar_igl | idx = set = env->sregs[SFR_RW_MM_TLB_SEL]; |
175 | dceaf394 | edgar_igl | set >>= 4;
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176 | dceaf394 | edgar_igl | set &= 3;
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177 | dceaf394 | edgar_igl | idx &= 15;
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178 | dceaf394 | edgar_igl | |
179 | dceaf394 | edgar_igl | /* Update the mirror regs. */
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180 | dceaf394 | edgar_igl | hi = env->tlbsets[srs - 1][set][idx].hi;
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181 | dceaf394 | edgar_igl | lo = env->tlbsets[srs - 1][set][idx].lo;
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182 | dceaf394 | edgar_igl | env->sregs[SFR_RW_MM_TLB_HI] = hi; |
183 | dceaf394 | edgar_igl | env->sregs[SFR_RW_MM_TLB_LO] = lo; |
184 | dceaf394 | edgar_igl | } |
185 | dceaf394 | edgar_igl | #endif
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186 | dceaf394 | edgar_igl | env->regs[reg] = env->sregs[srs][sreg]; |
187 | dceaf394 | edgar_igl | RETURN(); |
188 | dceaf394 | edgar_igl | } |
189 | dceaf394 | edgar_igl | |
190 | dceaf394 | edgar_igl | static void cris_ccs_rshift(CPUState *env) |
191 | dceaf394 | edgar_igl | { |
192 | dceaf394 | edgar_igl | uint32_t ccs; |
193 | dceaf394 | edgar_igl | |
194 | dceaf394 | edgar_igl | /* Apply the ccs shift. */
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195 | dceaf394 | edgar_igl | ccs = env->pregs[PR_CCS]; |
196 | dceaf394 | edgar_igl | ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10); |
197 | dceaf394 | edgar_igl | if (ccs & U_FLAG)
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198 | dceaf394 | edgar_igl | { |
199 | dceaf394 | edgar_igl | /* Enter user mode. */
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200 | dceaf394 | edgar_igl | env->ksp = env->regs[R_SP]; |
201 | dceaf394 | edgar_igl | env->regs[R_SP] = env->pregs[PR_USP]; |
202 | dceaf394 | edgar_igl | } |
203 | dceaf394 | edgar_igl | |
204 | dceaf394 | edgar_igl | env->pregs[PR_CCS] = ccs; |
205 | dceaf394 | edgar_igl | } |
206 | dceaf394 | edgar_igl | |
207 | b41f7df0 | edgar_igl | void helper_rfe(void) |
208 | b41f7df0 | edgar_igl | { |
209 | bf443337 | edgar_igl | int rflag = env->pregs[PR_CCS] & R_FLAG;
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210 | bf443337 | edgar_igl | |
211 | b41f7df0 | edgar_igl | D(fprintf(logfile, "rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
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212 | b41f7df0 | edgar_igl | env->pregs[PR_ERP], env->pregs[PR_PID], |
213 | b41f7df0 | edgar_igl | env->pregs[PR_CCS], |
214 | b41f7df0 | edgar_igl | env->btarget)); |
215 | dceaf394 | edgar_igl | |
216 | dceaf394 | edgar_igl | cris_ccs_rshift(env); |
217 | dceaf394 | edgar_igl | |
218 | dceaf394 | edgar_igl | /* RFE sets the P_FLAG only if the R_FLAG is not set. */
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219 | bf443337 | edgar_igl | if (!rflag)
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220 | dceaf394 | edgar_igl | env->pregs[PR_CCS] |= P_FLAG; |
221 | b41f7df0 | edgar_igl | } |
222 | b41f7df0 | edgar_igl | |
223 | 5bf8f1ab | edgar_igl | void helper_rfn(void) |
224 | 5bf8f1ab | edgar_igl | { |
225 | 5bf8f1ab | edgar_igl | int rflag = env->pregs[PR_CCS] & R_FLAG;
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226 | 5bf8f1ab | edgar_igl | |
227 | 5bf8f1ab | edgar_igl | D(fprintf(logfile, "rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
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228 | 5bf8f1ab | edgar_igl | env->pregs[PR_ERP], env->pregs[PR_PID], |
229 | 5bf8f1ab | edgar_igl | env->pregs[PR_CCS], |
230 | 5bf8f1ab | edgar_igl | env->btarget)); |
231 | 5bf8f1ab | edgar_igl | |
232 | 5bf8f1ab | edgar_igl | cris_ccs_rshift(env); |
233 | 5bf8f1ab | edgar_igl | |
234 | 5bf8f1ab | edgar_igl | /* Set the P_FLAG only if the R_FLAG is not set. */
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235 | 5bf8f1ab | edgar_igl | if (!rflag)
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236 | 5bf8f1ab | edgar_igl | env->pregs[PR_CCS] |= P_FLAG; |
237 | 5bf8f1ab | edgar_igl | |
238 | 5bf8f1ab | edgar_igl | /* Always set the M flag. */
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239 | 5bf8f1ab | edgar_igl | env->pregs[PR_CCS] |= M_FLAG; |
240 | 5bf8f1ab | edgar_igl | } |
241 | 5bf8f1ab | edgar_igl | |
242 | b41f7df0 | edgar_igl | void helper_store(uint32_t a0)
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243 | b41f7df0 | edgar_igl | { |
244 | b41f7df0 | edgar_igl | if (env->pregs[PR_CCS] & P_FLAG )
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245 | b41f7df0 | edgar_igl | { |
246 | b41f7df0 | edgar_igl | cpu_abort(env, "cond_store_failed! pc=%x a0=%x\n",
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247 | b41f7df0 | edgar_igl | env->pc, a0); |
248 | b41f7df0 | edgar_igl | } |
249 | b41f7df0 | edgar_igl | } |
250 | b41f7df0 | edgar_igl | |
251 | 81fdc5f8 | ths | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
252 | 81fdc5f8 | ths | int is_asi)
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253 | 81fdc5f8 | ths | { |
254 | 786c02f1 | edgar_igl | D(printf("%s addr=%x w=%d ex=%d asi=%d\n",
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255 | 786c02f1 | edgar_igl | __func__, addr, is_write, is_exec, is_asi)); |
256 | 81fdc5f8 | ths | } |
257 | b41f7df0 | edgar_igl | |
258 | b41f7df0 | edgar_igl | static void evaluate_flags_writeback(uint32_t flags) |
259 | b41f7df0 | edgar_igl | { |
260 | b41f7df0 | edgar_igl | int x;
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261 | b41f7df0 | edgar_igl | |
262 | b41f7df0 | edgar_igl | /* Extended arithmetics, leave the z flag alone. */
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263 | 30abcfc7 | edgar_igl | x = env->cc_x; |
264 | b41f7df0 | edgar_igl | if ((x || env->cc_op == CC_OP_ADDC)
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265 | b41f7df0 | edgar_igl | && flags & Z_FLAG) |
266 | b41f7df0 | edgar_igl | env->cc_mask &= ~Z_FLAG; |
267 | b41f7df0 | edgar_igl | |
268 | b41f7df0 | edgar_igl | /* all insn clear the x-flag except setf or clrf. */
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269 | b41f7df0 | edgar_igl | env->pregs[PR_CCS] &= ~(env->cc_mask | X_FLAG); |
270 | b41f7df0 | edgar_igl | flags &= env->cc_mask; |
271 | b41f7df0 | edgar_igl | env->pregs[PR_CCS] |= flags; |
272 | b41f7df0 | edgar_igl | } |
273 | b41f7df0 | edgar_igl | |
274 | b41f7df0 | edgar_igl | void helper_evaluate_flags_muls(void) |
275 | b41f7df0 | edgar_igl | { |
276 | b41f7df0 | edgar_igl | uint32_t src; |
277 | b41f7df0 | edgar_igl | uint32_t dst; |
278 | b41f7df0 | edgar_igl | uint32_t res; |
279 | b41f7df0 | edgar_igl | uint32_t flags = 0;
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280 | dceaf394 | edgar_igl | int64_t tmp; |
281 | b41f7df0 | edgar_igl | int32_t mof; |
282 | b41f7df0 | edgar_igl | int dneg;
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283 | b41f7df0 | edgar_igl | |
284 | b41f7df0 | edgar_igl | src = env->cc_src; |
285 | b41f7df0 | edgar_igl | dst = env->cc_dest; |
286 | b41f7df0 | edgar_igl | res = env->cc_result; |
287 | b41f7df0 | edgar_igl | |
288 | b41f7df0 | edgar_igl | dneg = ((int32_t)res) < 0;
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289 | b41f7df0 | edgar_igl | |
290 | dceaf394 | edgar_igl | mof = env->pregs[PR_MOF]; |
291 | dceaf394 | edgar_igl | tmp = mof; |
292 | dceaf394 | edgar_igl | tmp <<= 32;
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293 | dceaf394 | edgar_igl | tmp |= res; |
294 | b41f7df0 | edgar_igl | if (tmp == 0) |
295 | b41f7df0 | edgar_igl | flags |= Z_FLAG; |
296 | b41f7df0 | edgar_igl | else if (tmp < 0) |
297 | b41f7df0 | edgar_igl | flags |= N_FLAG; |
298 | b41f7df0 | edgar_igl | if ((dneg && mof != -1) |
299 | b41f7df0 | edgar_igl | || (!dneg && mof != 0))
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300 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
301 | b41f7df0 | edgar_igl | evaluate_flags_writeback(flags); |
302 | b41f7df0 | edgar_igl | } |
303 | b41f7df0 | edgar_igl | |
304 | b41f7df0 | edgar_igl | void helper_evaluate_flags_mulu(void) |
305 | b41f7df0 | edgar_igl | { |
306 | b41f7df0 | edgar_igl | uint32_t src; |
307 | b41f7df0 | edgar_igl | uint32_t dst; |
308 | b41f7df0 | edgar_igl | uint32_t res; |
309 | b41f7df0 | edgar_igl | uint32_t flags = 0;
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310 | dceaf394 | edgar_igl | uint64_t tmp; |
311 | b41f7df0 | edgar_igl | uint32_t mof; |
312 | b41f7df0 | edgar_igl | |
313 | b41f7df0 | edgar_igl | src = env->cc_src; |
314 | b41f7df0 | edgar_igl | dst = env->cc_dest; |
315 | b41f7df0 | edgar_igl | res = env->cc_result; |
316 | b41f7df0 | edgar_igl | |
317 | dceaf394 | edgar_igl | mof = env->pregs[PR_MOF]; |
318 | dceaf394 | edgar_igl | tmp = mof; |
319 | dceaf394 | edgar_igl | tmp <<= 32;
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320 | dceaf394 | edgar_igl | tmp |= res; |
321 | b41f7df0 | edgar_igl | if (tmp == 0) |
322 | b41f7df0 | edgar_igl | flags |= Z_FLAG; |
323 | b41f7df0 | edgar_igl | else if (tmp >> 63) |
324 | b41f7df0 | edgar_igl | flags |= N_FLAG; |
325 | b41f7df0 | edgar_igl | if (mof)
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326 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
327 | b41f7df0 | edgar_igl | |
328 | b41f7df0 | edgar_igl | evaluate_flags_writeback(flags); |
329 | b41f7df0 | edgar_igl | } |
330 | b41f7df0 | edgar_igl | |
331 | b41f7df0 | edgar_igl | void helper_evaluate_flags_mcp(void) |
332 | b41f7df0 | edgar_igl | { |
333 | b41f7df0 | edgar_igl | uint32_t src; |
334 | b41f7df0 | edgar_igl | uint32_t dst; |
335 | b41f7df0 | edgar_igl | uint32_t res; |
336 | b41f7df0 | edgar_igl | uint32_t flags = 0;
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337 | b41f7df0 | edgar_igl | |
338 | b41f7df0 | edgar_igl | src = env->cc_src; |
339 | b41f7df0 | edgar_igl | dst = env->cc_dest; |
340 | b41f7df0 | edgar_igl | res = env->cc_result; |
341 | b41f7df0 | edgar_igl | |
342 | b41f7df0 | edgar_igl | if ((res & 0x80000000L) != 0L) |
343 | b41f7df0 | edgar_igl | { |
344 | b41f7df0 | edgar_igl | flags |= N_FLAG; |
345 | b41f7df0 | edgar_igl | if (((src & 0x80000000L) == 0L) |
346 | b41f7df0 | edgar_igl | && ((dst & 0x80000000L) == 0L)) |
347 | b41f7df0 | edgar_igl | { |
348 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
349 | b41f7df0 | edgar_igl | } |
350 | b41f7df0 | edgar_igl | else if (((src & 0x80000000L) != 0L) && |
351 | b41f7df0 | edgar_igl | ((dst & 0x80000000L) != 0L)) |
352 | b41f7df0 | edgar_igl | { |
353 | b41f7df0 | edgar_igl | flags |= R_FLAG; |
354 | b41f7df0 | edgar_igl | } |
355 | b41f7df0 | edgar_igl | } |
356 | b41f7df0 | edgar_igl | else
|
357 | b41f7df0 | edgar_igl | { |
358 | b41f7df0 | edgar_igl | if (res == 0L) |
359 | b41f7df0 | edgar_igl | flags |= Z_FLAG; |
360 | b41f7df0 | edgar_igl | if (((src & 0x80000000L) != 0L) |
361 | b41f7df0 | edgar_igl | && ((dst & 0x80000000L) != 0L)) |
362 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
363 | b41f7df0 | edgar_igl | if ((dst & 0x80000000L) != 0L |
364 | b41f7df0 | edgar_igl | || (src & 0x80000000L) != 0L) |
365 | b41f7df0 | edgar_igl | flags |= R_FLAG; |
366 | b41f7df0 | edgar_igl | } |
367 | b41f7df0 | edgar_igl | |
368 | b41f7df0 | edgar_igl | evaluate_flags_writeback(flags); |
369 | b41f7df0 | edgar_igl | } |
370 | b41f7df0 | edgar_igl | |
371 | b41f7df0 | edgar_igl | void helper_evaluate_flags_alu_4(void) |
372 | b41f7df0 | edgar_igl | { |
373 | b41f7df0 | edgar_igl | uint32_t src; |
374 | b41f7df0 | edgar_igl | uint32_t dst; |
375 | b41f7df0 | edgar_igl | uint32_t res; |
376 | b41f7df0 | edgar_igl | uint32_t flags = 0;
|
377 | b41f7df0 | edgar_igl | |
378 | b41f7df0 | edgar_igl | src = env->cc_src; |
379 | b41f7df0 | edgar_igl | dst = env->cc_dest; |
380 | 30abcfc7 | edgar_igl | |
381 | 30abcfc7 | edgar_igl | /* Reconstruct the result. */
|
382 | 30abcfc7 | edgar_igl | switch (env->cc_op)
|
383 | 30abcfc7 | edgar_igl | { |
384 | 30abcfc7 | edgar_igl | case CC_OP_SUB:
|
385 | 30abcfc7 | edgar_igl | res = dst - src; |
386 | 30abcfc7 | edgar_igl | break;
|
387 | 30abcfc7 | edgar_igl | case CC_OP_ADD:
|
388 | 30abcfc7 | edgar_igl | res = dst + src; |
389 | 30abcfc7 | edgar_igl | break;
|
390 | 30abcfc7 | edgar_igl | default:
|
391 | 30abcfc7 | edgar_igl | res = env->cc_result; |
392 | 30abcfc7 | edgar_igl | break;
|
393 | 30abcfc7 | edgar_igl | } |
394 | 30abcfc7 | edgar_igl | |
395 | 30abcfc7 | edgar_igl | if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
|
396 | 30abcfc7 | edgar_igl | src = ~src; |
397 | b41f7df0 | edgar_igl | |
398 | b41f7df0 | edgar_igl | if ((res & 0x80000000L) != 0L) |
399 | b41f7df0 | edgar_igl | { |
400 | b41f7df0 | edgar_igl | flags |= N_FLAG; |
401 | b41f7df0 | edgar_igl | if (((src & 0x80000000L) == 0L) |
402 | b41f7df0 | edgar_igl | && ((dst & 0x80000000L) == 0L)) |
403 | b41f7df0 | edgar_igl | { |
404 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
405 | b41f7df0 | edgar_igl | } |
406 | b41f7df0 | edgar_igl | else if (((src & 0x80000000L) != 0L) && |
407 | b41f7df0 | edgar_igl | ((dst & 0x80000000L) != 0L)) |
408 | b41f7df0 | edgar_igl | { |
409 | b41f7df0 | edgar_igl | flags |= C_FLAG; |
410 | b41f7df0 | edgar_igl | } |
411 | b41f7df0 | edgar_igl | } |
412 | b41f7df0 | edgar_igl | else
|
413 | b41f7df0 | edgar_igl | { |
414 | b41f7df0 | edgar_igl | if (res == 0L) |
415 | b41f7df0 | edgar_igl | flags |= Z_FLAG; |
416 | b41f7df0 | edgar_igl | if (((src & 0x80000000L) != 0L) |
417 | b41f7df0 | edgar_igl | && ((dst & 0x80000000L) != 0L)) |
418 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
419 | b41f7df0 | edgar_igl | if ((dst & 0x80000000L) != 0L |
420 | b41f7df0 | edgar_igl | || (src & 0x80000000L) != 0L) |
421 | b41f7df0 | edgar_igl | flags |= C_FLAG; |
422 | b41f7df0 | edgar_igl | } |
423 | b41f7df0 | edgar_igl | |
424 | b41f7df0 | edgar_igl | if (env->cc_op == CC_OP_SUB
|
425 | b41f7df0 | edgar_igl | || env->cc_op == CC_OP_CMP) { |
426 | b41f7df0 | edgar_igl | flags ^= C_FLAG; |
427 | b41f7df0 | edgar_igl | } |
428 | b41f7df0 | edgar_igl | evaluate_flags_writeback(flags); |
429 | b41f7df0 | edgar_igl | } |
430 | b41f7df0 | edgar_igl | |
431 | b41f7df0 | edgar_igl | void helper_evaluate_flags_move_4 (void) |
432 | b41f7df0 | edgar_igl | { |
433 | b41f7df0 | edgar_igl | uint32_t res; |
434 | b41f7df0 | edgar_igl | uint32_t flags = 0;
|
435 | b41f7df0 | edgar_igl | |
436 | b41f7df0 | edgar_igl | res = env->cc_result; |
437 | b41f7df0 | edgar_igl | |
438 | b41f7df0 | edgar_igl | if ((int32_t)res < 0) |
439 | b41f7df0 | edgar_igl | flags |= N_FLAG; |
440 | b41f7df0 | edgar_igl | else if (res == 0L) |
441 | b41f7df0 | edgar_igl | flags |= Z_FLAG; |
442 | b41f7df0 | edgar_igl | |
443 | b41f7df0 | edgar_igl | evaluate_flags_writeback(flags); |
444 | b41f7df0 | edgar_igl | } |
445 | b41f7df0 | edgar_igl | void helper_evaluate_flags_move_2 (void) |
446 | b41f7df0 | edgar_igl | { |
447 | b41f7df0 | edgar_igl | uint32_t src; |
448 | b41f7df0 | edgar_igl | uint32_t flags = 0;
|
449 | b41f7df0 | edgar_igl | uint16_t res; |
450 | b41f7df0 | edgar_igl | |
451 | b41f7df0 | edgar_igl | src = env->cc_src; |
452 | b41f7df0 | edgar_igl | res = env->cc_result; |
453 | b41f7df0 | edgar_igl | |
454 | b41f7df0 | edgar_igl | if ((int16_t)res < 0L) |
455 | b41f7df0 | edgar_igl | flags |= N_FLAG; |
456 | b41f7df0 | edgar_igl | else if (res == 0) |
457 | b41f7df0 | edgar_igl | flags |= Z_FLAG; |
458 | b41f7df0 | edgar_igl | |
459 | b41f7df0 | edgar_igl | evaluate_flags_writeback(flags); |
460 | b41f7df0 | edgar_igl | } |
461 | b41f7df0 | edgar_igl | |
462 | b41f7df0 | edgar_igl | /* TODO: This is expensive. We could split things up and only evaluate part of
|
463 | b41f7df0 | edgar_igl | CCR on a need to know basis. For now, we simply re-evaluate everything. */
|
464 | b41f7df0 | edgar_igl | void helper_evaluate_flags (void) |
465 | b41f7df0 | edgar_igl | { |
466 | b41f7df0 | edgar_igl | uint32_t src; |
467 | b41f7df0 | edgar_igl | uint32_t dst; |
468 | b41f7df0 | edgar_igl | uint32_t res; |
469 | b41f7df0 | edgar_igl | uint32_t flags = 0;
|
470 | b41f7df0 | edgar_igl | |
471 | b41f7df0 | edgar_igl | src = env->cc_src; |
472 | b41f7df0 | edgar_igl | dst = env->cc_dest; |
473 | b41f7df0 | edgar_igl | res = env->cc_result; |
474 | b41f7df0 | edgar_igl | |
475 | 30abcfc7 | edgar_igl | if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
|
476 | 30abcfc7 | edgar_igl | src = ~src; |
477 | b41f7df0 | edgar_igl | |
478 | b41f7df0 | edgar_igl | /* Now, evaluate the flags. This stuff is based on
|
479 | b41f7df0 | edgar_igl | Per Zander's CRISv10 simulator. */
|
480 | b41f7df0 | edgar_igl | switch (env->cc_size)
|
481 | b41f7df0 | edgar_igl | { |
482 | b41f7df0 | edgar_igl | case 1: |
483 | b41f7df0 | edgar_igl | if ((res & 0x80L) != 0L) |
484 | b41f7df0 | edgar_igl | { |
485 | b41f7df0 | edgar_igl | flags |= N_FLAG; |
486 | b41f7df0 | edgar_igl | if (((src & 0x80L) == 0L) |
487 | b41f7df0 | edgar_igl | && ((dst & 0x80L) == 0L)) |
488 | b41f7df0 | edgar_igl | { |
489 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
490 | b41f7df0 | edgar_igl | } |
491 | b41f7df0 | edgar_igl | else if (((src & 0x80L) != 0L) |
492 | b41f7df0 | edgar_igl | && ((dst & 0x80L) != 0L)) |
493 | b41f7df0 | edgar_igl | { |
494 | b41f7df0 | edgar_igl | flags |= C_FLAG; |
495 | b41f7df0 | edgar_igl | } |
496 | b41f7df0 | edgar_igl | } |
497 | b41f7df0 | edgar_igl | else
|
498 | b41f7df0 | edgar_igl | { |
499 | b41f7df0 | edgar_igl | if ((res & 0xFFL) == 0L) |
500 | b41f7df0 | edgar_igl | { |
501 | b41f7df0 | edgar_igl | flags |= Z_FLAG; |
502 | b41f7df0 | edgar_igl | } |
503 | b41f7df0 | edgar_igl | if (((src & 0x80L) != 0L) |
504 | b41f7df0 | edgar_igl | && ((dst & 0x80L) != 0L)) |
505 | b41f7df0 | edgar_igl | { |
506 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
507 | b41f7df0 | edgar_igl | } |
508 | b41f7df0 | edgar_igl | if ((dst & 0x80L) != 0L |
509 | b41f7df0 | edgar_igl | || (src & 0x80L) != 0L) |
510 | b41f7df0 | edgar_igl | { |
511 | b41f7df0 | edgar_igl | flags |= C_FLAG; |
512 | b41f7df0 | edgar_igl | } |
513 | b41f7df0 | edgar_igl | } |
514 | b41f7df0 | edgar_igl | break;
|
515 | b41f7df0 | edgar_igl | case 2: |
516 | b41f7df0 | edgar_igl | if ((res & 0x8000L) != 0L) |
517 | b41f7df0 | edgar_igl | { |
518 | b41f7df0 | edgar_igl | flags |= N_FLAG; |
519 | b41f7df0 | edgar_igl | if (((src & 0x8000L) == 0L) |
520 | b41f7df0 | edgar_igl | && ((dst & 0x8000L) == 0L)) |
521 | b41f7df0 | edgar_igl | { |
522 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
523 | b41f7df0 | edgar_igl | } |
524 | b41f7df0 | edgar_igl | else if (((src & 0x8000L) != 0L) |
525 | b41f7df0 | edgar_igl | && ((dst & 0x8000L) != 0L)) |
526 | b41f7df0 | edgar_igl | { |
527 | b41f7df0 | edgar_igl | flags |= C_FLAG; |
528 | b41f7df0 | edgar_igl | } |
529 | b41f7df0 | edgar_igl | } |
530 | b41f7df0 | edgar_igl | else
|
531 | b41f7df0 | edgar_igl | { |
532 | b41f7df0 | edgar_igl | if ((res & 0xFFFFL) == 0L) |
533 | b41f7df0 | edgar_igl | { |
534 | b41f7df0 | edgar_igl | flags |= Z_FLAG; |
535 | b41f7df0 | edgar_igl | } |
536 | b41f7df0 | edgar_igl | if (((src & 0x8000L) != 0L) |
537 | b41f7df0 | edgar_igl | && ((dst & 0x8000L) != 0L)) |
538 | b41f7df0 | edgar_igl | { |
539 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
540 | b41f7df0 | edgar_igl | } |
541 | b41f7df0 | edgar_igl | if ((dst & 0x8000L) != 0L |
542 | b41f7df0 | edgar_igl | || (src & 0x8000L) != 0L) |
543 | b41f7df0 | edgar_igl | { |
544 | b41f7df0 | edgar_igl | flags |= C_FLAG; |
545 | b41f7df0 | edgar_igl | } |
546 | b41f7df0 | edgar_igl | } |
547 | b41f7df0 | edgar_igl | break;
|
548 | b41f7df0 | edgar_igl | case 4: |
549 | b41f7df0 | edgar_igl | if ((res & 0x80000000L) != 0L) |
550 | b41f7df0 | edgar_igl | { |
551 | b41f7df0 | edgar_igl | flags |= N_FLAG; |
552 | b41f7df0 | edgar_igl | if (((src & 0x80000000L) == 0L) |
553 | b41f7df0 | edgar_igl | && ((dst & 0x80000000L) == 0L)) |
554 | b41f7df0 | edgar_igl | { |
555 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
556 | b41f7df0 | edgar_igl | } |
557 | b41f7df0 | edgar_igl | else if (((src & 0x80000000L) != 0L) && |
558 | b41f7df0 | edgar_igl | ((dst & 0x80000000L) != 0L)) |
559 | b41f7df0 | edgar_igl | { |
560 | b41f7df0 | edgar_igl | flags |= C_FLAG; |
561 | b41f7df0 | edgar_igl | } |
562 | b41f7df0 | edgar_igl | } |
563 | b41f7df0 | edgar_igl | else
|
564 | b41f7df0 | edgar_igl | { |
565 | b41f7df0 | edgar_igl | if (res == 0L) |
566 | b41f7df0 | edgar_igl | flags |= Z_FLAG; |
567 | b41f7df0 | edgar_igl | if (((src & 0x80000000L) != 0L) |
568 | b41f7df0 | edgar_igl | && ((dst & 0x80000000L) != 0L)) |
569 | b41f7df0 | edgar_igl | flags |= V_FLAG; |
570 | b41f7df0 | edgar_igl | if ((dst & 0x80000000L) != 0L |
571 | b41f7df0 | edgar_igl | || (src & 0x80000000L) != 0L) |
572 | b41f7df0 | edgar_igl | flags |= C_FLAG; |
573 | b41f7df0 | edgar_igl | } |
574 | b41f7df0 | edgar_igl | break;
|
575 | b41f7df0 | edgar_igl | default:
|
576 | b41f7df0 | edgar_igl | break;
|
577 | b41f7df0 | edgar_igl | } |
578 | b41f7df0 | edgar_igl | |
579 | b41f7df0 | edgar_igl | if (env->cc_op == CC_OP_SUB
|
580 | b41f7df0 | edgar_igl | || env->cc_op == CC_OP_CMP) { |
581 | b41f7df0 | edgar_igl | flags ^= C_FLAG; |
582 | b41f7df0 | edgar_igl | } |
583 | b41f7df0 | edgar_igl | evaluate_flags_writeback(flags); |
584 | b41f7df0 | edgar_igl | } |
585 | 30abcfc7 | edgar_igl | |
586 | 30abcfc7 | edgar_igl | void helper_top_evaluate_flags(void) |
587 | 30abcfc7 | edgar_igl | { |
588 | 30abcfc7 | edgar_igl | switch (env->cc_op)
|
589 | 30abcfc7 | edgar_igl | { |
590 | 30abcfc7 | edgar_igl | case CC_OP_MCP:
|
591 | 30abcfc7 | edgar_igl | helper_evaluate_flags_mcp(); |
592 | 30abcfc7 | edgar_igl | break;
|
593 | 30abcfc7 | edgar_igl | case CC_OP_MULS:
|
594 | 30abcfc7 | edgar_igl | helper_evaluate_flags_muls(); |
595 | 30abcfc7 | edgar_igl | break;
|
596 | 30abcfc7 | edgar_igl | case CC_OP_MULU:
|
597 | 30abcfc7 | edgar_igl | helper_evaluate_flags_mulu(); |
598 | 30abcfc7 | edgar_igl | break;
|
599 | 30abcfc7 | edgar_igl | case CC_OP_MOVE:
|
600 | 30abcfc7 | edgar_igl | case CC_OP_AND:
|
601 | 30abcfc7 | edgar_igl | case CC_OP_OR:
|
602 | 30abcfc7 | edgar_igl | case CC_OP_XOR:
|
603 | 30abcfc7 | edgar_igl | case CC_OP_ASR:
|
604 | 30abcfc7 | edgar_igl | case CC_OP_LSR:
|
605 | 30abcfc7 | edgar_igl | case CC_OP_LSL:
|
606 | 30abcfc7 | edgar_igl | switch (env->cc_size)
|
607 | 30abcfc7 | edgar_igl | { |
608 | 30abcfc7 | edgar_igl | case 4: |
609 | 30abcfc7 | edgar_igl | helper_evaluate_flags_move_4(); |
610 | 30abcfc7 | edgar_igl | break;
|
611 | 30abcfc7 | edgar_igl | case 2: |
612 | 30abcfc7 | edgar_igl | helper_evaluate_flags_move_2(); |
613 | 30abcfc7 | edgar_igl | break;
|
614 | 30abcfc7 | edgar_igl | default:
|
615 | 30abcfc7 | edgar_igl | helper_evaluate_flags(); |
616 | 30abcfc7 | edgar_igl | break;
|
617 | 30abcfc7 | edgar_igl | } |
618 | 30abcfc7 | edgar_igl | break;
|
619 | 30abcfc7 | edgar_igl | case CC_OP_FLAGS:
|
620 | 30abcfc7 | edgar_igl | /* live. */
|
621 | 30abcfc7 | edgar_igl | break;
|
622 | 30abcfc7 | edgar_igl | default:
|
623 | 30abcfc7 | edgar_igl | { |
624 | 30abcfc7 | edgar_igl | switch (env->cc_size)
|
625 | 30abcfc7 | edgar_igl | { |
626 | 30abcfc7 | edgar_igl | case 4: |
627 | 30abcfc7 | edgar_igl | helper_evaluate_flags_alu_4(); |
628 | 30abcfc7 | edgar_igl | break;
|
629 | 30abcfc7 | edgar_igl | default:
|
630 | 30abcfc7 | edgar_igl | helper_evaluate_flags(); |
631 | 30abcfc7 | edgar_igl | break;
|
632 | 30abcfc7 | edgar_igl | } |
633 | 30abcfc7 | edgar_igl | } |
634 | 30abcfc7 | edgar_igl | break;
|
635 | 30abcfc7 | edgar_igl | } |
636 | 30abcfc7 | edgar_igl | } |