root / target-mips / exec.h @ ed23fbd9
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1 | 6af0bf9c | bellard | #if !defined(__QEMU_MIPS_EXEC_H__)
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2 | 6af0bf9c | bellard | #define __QEMU_MIPS_EXEC_H__
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3 | 6af0bf9c | bellard | |
4 | 01dbbdf1 | bellard | //#define DEBUG_OP
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5 | 6af0bf9c | bellard | |
6 | c570fd16 | ths | #include "config.h" |
7 | 6af0bf9c | bellard | #include "mips-defs.h" |
8 | 6af0bf9c | bellard | #include "dyngen-exec.h" |
9 | 01179c38 | ths | #include "cpu-defs.h" |
10 | 6af0bf9c | bellard | |
11 | 6af0bf9c | bellard | register struct CPUMIPSState *env asm(AREG0); |
12 | 6af0bf9c | bellard | |
13 | 6af0bf9c | bellard | #include "cpu.h" |
14 | 6af0bf9c | bellard | #include "exec-all.h" |
15 | 6af0bf9c | bellard | |
16 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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17 | a9049a07 | bellard | #include "softmmu_exec.h" |
18 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
19 | 6af0bf9c | bellard | |
20 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val);
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21 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void); |
22 | 6ea83fed | bellard | void dump_fpu(CPUState *env);
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23 | 5fafdf24 | ths | void fpu_dump_state(CPUState *env, FILE *f,
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24 | 6ea83fed | bellard | int (*fpu_fprintf)(FILE *f, const char *fmt, ...), |
25 | 6ea83fed | bellard | int flags);
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26 | 6af0bf9c | bellard | |
27 | 6af0bf9c | bellard | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
28 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
29 | 6af0bf9c | bellard | void do_interrupt (CPUState *env);
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30 | 29929e34 | ths | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra); |
31 | 6af0bf9c | bellard | |
32 | 6af0bf9c | bellard | void cpu_loop_exit(void); |
33 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code); |
34 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception);
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35 | 6af0bf9c | bellard | |
36 | 5fafdf24 | ths | void cpu_dump_state(CPUState *env, FILE *f,
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37 | 6af0bf9c | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
38 | 6af0bf9c | bellard | int flags);
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39 | 6af0bf9c | bellard | void cpu_mips_irqctrl_init (void); |
40 | 6af0bf9c | bellard | uint32_t cpu_mips_get_random (CPUState *env); |
41 | 6af0bf9c | bellard | uint32_t cpu_mips_get_count (CPUState *env); |
42 | 6af0bf9c | bellard | void cpu_mips_store_count (CPUState *env, uint32_t value);
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43 | 6af0bf9c | bellard | void cpu_mips_store_compare (CPUState *env, uint32_t value);
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44 | 42532189 | ths | void cpu_mips_start_count(CPUState *env);
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45 | 42532189 | ths | void cpu_mips_stop_count(CPUState *env);
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46 | a4bc3afc | ths | void cpu_mips_update_irq (CPUState *env);
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47 | 6af0bf9c | bellard | void cpu_mips_clock_init (CPUState *env);
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48 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
49 | 6af0bf9c | bellard | |
50 | c904ef0e | ths | static inline void env_to_regs(void) |
51 | bfed01fc | ths | { |
52 | bfed01fc | ths | } |
53 | bfed01fc | ths | |
54 | c904ef0e | ths | static inline void regs_to_env(void) |
55 | bfed01fc | ths | { |
56 | bfed01fc | ths | } |
57 | bfed01fc | ths | |
58 | c904ef0e | ths | static inline int cpu_halted(CPUState *env) |
59 | 08fa4bab | ths | { |
60 | bfed01fc | ths | if (!env->halted)
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61 | bfed01fc | ths | return 0; |
62 | bfed01fc | ths | if (env->interrupt_request &
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63 | bfed01fc | ths | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { |
64 | bfed01fc | ths | env->halted = 0;
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65 | bfed01fc | ths | return 0; |
66 | bfed01fc | ths | } |
67 | bfed01fc | ths | return EXCP_HALTED;
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68 | bfed01fc | ths | } |
69 | bfed01fc | ths | |
70 | c904ef0e | ths | static inline void compute_hflags(CPUState *env) |
71 | 08fa4bab | ths | { |
72 | b8aa4598 | ths | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
73 | b8aa4598 | ths | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU); |
74 | 08fa4bab | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
75 | 08fa4bab | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
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76 | 671880e6 | ths | !(env->hflags & MIPS_HFLAG_DM)) { |
77 | 623a930e | ths | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
78 | 671880e6 | ths | } |
79 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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80 | 623a930e | ths | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
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81 | 08fa4bab | ths | (env->CP0_Status & (1 << CP0St_PX)) ||
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82 | 08fa4bab | ths | (env->CP0_Status & (1 << CP0St_UX)))
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83 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_64; |
84 | 08fa4bab | ths | #endif
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85 | 671880e6 | ths | if ((env->CP0_Status & (1 << CP0St_CU0)) || |
86 | 623a930e | ths | !(env->hflags & MIPS_HFLAG_KSU)) |
87 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_CP0; |
88 | 08fa4bab | ths | if (env->CP0_Status & (1 << CP0St_CU1)) |
89 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_FPU; |
90 | 08fa4bab | ths | if (env->CP0_Status & (1 << CP0St_FR)) |
91 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_F64; |
92 | b8aa4598 | ths | if (env->insn_flags & ISA_MIPS32R2) {
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93 | a139a3ad | ths | if (env->fpu->fcr0 & (1 << FCR0_F64)) |
94 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
95 | b8aa4598 | ths | } else if (env->insn_flags & ISA_MIPS32) { |
96 | b8aa4598 | ths | if (env->hflags & MIPS_HFLAG_64)
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97 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
98 | b8aa4598 | ths | } else if (env->insn_flags & ISA_MIPS4) { |
99 | b8aa4598 | ths | /* All supported MIPS IV CPUs use the XX (CU3) to enable
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100 | b8aa4598 | ths | and disable the MIPS IV extensions to the MIPS III ISA.
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101 | b8aa4598 | ths | Some other MIPS IV CPUs ignore the bit, so the check here
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102 | b8aa4598 | ths | would be too restrictive for them. */
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103 | b8aa4598 | ths | if (env->CP0_Status & (1 << CP0St_CU3)) |
104 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
105 | b8aa4598 | ths | } |
106 | 08fa4bab | ths | } |
107 | 08fa4bab | ths | |
108 | 6af0bf9c | bellard | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |