root / target-mips / mips-defs.h @ ed23fbd9
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1 | 6af0bf9c | bellard | #if !defined (__QEMU_MIPS_DEFS_H__)
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2 | 6af0bf9c | bellard | #define __QEMU_MIPS_DEFS_H__
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3 | 6af0bf9c | bellard | |
4 | 6af0bf9c | bellard | /* If we want to use host float regs... */
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5 | 6af0bf9c | bellard | //#define USE_HOST_FLOAT_REGS
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6 | 6af0bf9c | bellard | |
7 | e9c71dd1 | ths | /* Real pages are variable size... */
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8 | 6af0bf9c | bellard | #define TARGET_PAGE_BITS 12 |
9 | 814b9a47 | ths | #define MIPS_TLB_MAX 128 |
10 | 6af0bf9c | bellard | |
11 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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12 | c570fd16 | ths | #define TARGET_LONG_BITS 64 |
13 | c570fd16 | ths | #else
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14 | c570fd16 | ths | #define TARGET_LONG_BITS 32 |
15 | c570fd16 | ths | #endif
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16 | c570fd16 | ths | |
17 | dab6322b | ths | /* Even MIPS32 can have 36 bits physical address space. */
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18 | dab6322b | ths | #define TARGET_PHYS_ADDR_BITS 64 |
19 | dab6322b | ths | |
20 | e189e748 | ths | /* Masks used to mark instructions to indicate which ISA level they
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21 | e189e748 | ths | were introduced in. */
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22 | e189e748 | ths | #define ISA_MIPS1 0x00000001 |
23 | e189e748 | ths | #define ISA_MIPS2 0x00000002 |
24 | e189e748 | ths | #define ISA_MIPS3 0x00000004 |
25 | e189e748 | ths | #define ISA_MIPS4 0x00000008 |
26 | e189e748 | ths | #define ISA_MIPS5 0x00000010 |
27 | e189e748 | ths | #define ISA_MIPS32 0x00000020 |
28 | e189e748 | ths | #define ISA_MIPS32R2 0x00000040 |
29 | e189e748 | ths | #define ISA_MIPS64 0x00000080 |
30 | e189e748 | ths | #define ISA_MIPS64R2 0x00000100 |
31 | e189e748 | ths | |
32 | e9c71dd1 | ths | /* MIPS ASEs. */
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33 | e189e748 | ths | #define ASE_MIPS16 0x00001000 |
34 | e189e748 | ths | #define ASE_MIPS3D 0x00002000 |
35 | e189e748 | ths | #define ASE_MDMX 0x00004000 |
36 | e189e748 | ths | #define ASE_DSP 0x00008000 |
37 | e189e748 | ths | #define ASE_DSPR2 0x00010000 |
38 | 7385ac0b | ths | #define ASE_MT 0x00020000 |
39 | 7385ac0b | ths | #define ASE_SMARTMIPS 0x00040000 |
40 | e189e748 | ths | |
41 | e9c71dd1 | ths | /* Chip specific instructions. */
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42 | e9c71dd1 | ths | #define INSN_VR54XX 0x80000000 |
43 | e189e748 | ths | |
44 | e9c71dd1 | ths | /* MIPS CPU defines. */
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45 | e189e748 | ths | #define CPU_MIPS1 (ISA_MIPS1)
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46 | e189e748 | ths | #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
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47 | e189e748 | ths | #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
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48 | e189e748 | ths | #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
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49 | e9c71dd1 | ths | #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
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50 | e9c71dd1 | ths | |
51 | e189e748 | ths | #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
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52 | e189e748 | ths | |
53 | e9c71dd1 | ths | /* MIPS Technologies "Release 1" */
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54 | e189e748 | ths | #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
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55 | e189e748 | ths | #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
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56 | e189e748 | ths | |
57 | e9c71dd1 | ths | /* MIPS Technologies "Release 2" */
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58 | e189e748 | ths | #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
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59 | e189e748 | ths | #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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60 | e189e748 | ths | |
61 | 19221bda | ths | /* Strictly follow the architecture standard:
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62 | 19221bda | ths | - Disallow "special" instruction handling for PMON/SPIM.
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63 | 19221bda | ths | Note that we still maintain Count/Compare to match the host clock. */
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64 | b48cfdff | ths | //#define MIPS_STRICT_STANDARD 1
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65 | b48cfdff | ths | |
66 | 6af0bf9c | bellard | #endif /* !defined (__QEMU_MIPS_DEFS_H__) */ |