root / target-sh4 / translate.c @ ed23fbd9
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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 translation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #include <stdarg.h> |
21 | fdf9b3e8 | bellard | #include <stdlib.h> |
22 | fdf9b3e8 | bellard | #include <stdio.h> |
23 | fdf9b3e8 | bellard | #include <string.h> |
24 | fdf9b3e8 | bellard | #include <inttypes.h> |
25 | fdf9b3e8 | bellard | #include <assert.h> |
26 | fdf9b3e8 | bellard | |
27 | fdf9b3e8 | bellard | #define DEBUG_DISAS
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28 | fdf9b3e8 | bellard | #define SH4_DEBUG_DISAS
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29 | fdf9b3e8 | bellard | //#define SH4_SINGLE_STEP
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30 | fdf9b3e8 | bellard | |
31 | fdf9b3e8 | bellard | #include "cpu.h" |
32 | fdf9b3e8 | bellard | #include "exec-all.h" |
33 | fdf9b3e8 | bellard | #include "disas.h" |
34 | 988d7eaa | aurel32 | #include "helper.h" |
35 | 57fec1fe | bellard | #include "tcg-op.h" |
36 | ca10f867 | aurel32 | #include "qemu-common.h" |
37 | fdf9b3e8 | bellard | |
38 | fdf9b3e8 | bellard | typedef struct DisasContext { |
39 | fdf9b3e8 | bellard | struct TranslationBlock *tb;
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40 | fdf9b3e8 | bellard | target_ulong pc; |
41 | fdf9b3e8 | bellard | uint32_t sr; |
42 | eda9b09b | bellard | uint32_t fpscr; |
43 | fdf9b3e8 | bellard | uint16_t opcode; |
44 | fdf9b3e8 | bellard | uint32_t flags; |
45 | 823029f9 | ths | int bstate;
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46 | fdf9b3e8 | bellard | int memidx;
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47 | fdf9b3e8 | bellard | uint32_t delayed_pc; |
48 | fdf9b3e8 | bellard | int singlestep_enabled;
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49 | fdf9b3e8 | bellard | } DisasContext; |
50 | fdf9b3e8 | bellard | |
51 | 823029f9 | ths | enum {
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52 | 823029f9 | ths | BS_NONE = 0, /* We go out of the TB without reaching a branch or an |
53 | 823029f9 | ths | * exception condition
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54 | 823029f9 | ths | */
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55 | 823029f9 | ths | BS_STOP = 1, /* We want to stop translation for any reason */ |
56 | 823029f9 | ths | BS_BRANCH = 2, /* We reached a branch condition */ |
57 | 823029f9 | ths | BS_EXCP = 3, /* We reached an exception condition */ |
58 | 823029f9 | ths | }; |
59 | 823029f9 | ths | |
60 | 1e8864f7 | aurel32 | /* global register indexes */
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61 | 1e8864f7 | aurel32 | static TCGv cpu_env;
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62 | 1e8864f7 | aurel32 | static TCGv cpu_gregs[24]; |
63 | 3a8a44c4 | aurel32 | static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
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64 | 3a8a44c4 | aurel32 | static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
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65 | 1000822b | aurel32 | static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags;
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66 | 1000822b | aurel32 | |
67 | 1000822b | aurel32 | /* internal register indexes */
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68 | 1000822b | aurel32 | static TCGv cpu_flags, cpu_delayed_pc;
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69 | 1e8864f7 | aurel32 | |
70 | 1e8864f7 | aurel32 | /* dyngen register indexes */
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71 | 1e8864f7 | aurel32 | static TCGv cpu_T[2]; |
72 | 2e70f6ef | pbrook | |
73 | 2e70f6ef | pbrook | #include "gen-icount.h" |
74 | 2e70f6ef | pbrook | |
75 | a5f1b965 | blueswir1 | static void sh4_translate_init(void) |
76 | 2e70f6ef | pbrook | { |
77 | 1e8864f7 | aurel32 | int i;
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78 | 2e70f6ef | pbrook | static int done_init = 0; |
79 | 559dd74d | aurel32 | static const char * const gregnames[24] = { |
80 | 1e8864f7 | aurel32 | "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", |
81 | 1e8864f7 | aurel32 | "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", |
82 | 1e8864f7 | aurel32 | "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", |
83 | 1e8864f7 | aurel32 | "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1", |
84 | 1e8864f7 | aurel32 | "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1" |
85 | 1e8864f7 | aurel32 | }; |
86 | 1e8864f7 | aurel32 | |
87 | 2e70f6ef | pbrook | if (done_init)
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88 | 2e70f6ef | pbrook | return;
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89 | 1e8864f7 | aurel32 | |
90 | 2e70f6ef | pbrook | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
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91 | 1e8864f7 | aurel32 | cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG1, "T0"); |
92 | 1e8864f7 | aurel32 | cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG2, "T1"); |
93 | 1e8864f7 | aurel32 | |
94 | 1e8864f7 | aurel32 | for (i = 0; i < 24; i++) |
95 | 1e8864f7 | aurel32 | cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
96 | 1e8864f7 | aurel32 | offsetof(CPUState, gregs[i]), |
97 | 1e8864f7 | aurel32 | gregnames[i]); |
98 | 988d7eaa | aurel32 | |
99 | 3a8a44c4 | aurel32 | cpu_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
100 | 3a8a44c4 | aurel32 | offsetof(CPUState, pc), "PC");
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101 | 3a8a44c4 | aurel32 | cpu_sr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
102 | 3a8a44c4 | aurel32 | offsetof(CPUState, sr), "SR");
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103 | 3a8a44c4 | aurel32 | cpu_ssr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
104 | 3a8a44c4 | aurel32 | offsetof(CPUState, ssr), "SSR");
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105 | 3a8a44c4 | aurel32 | cpu_spc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
106 | 3a8a44c4 | aurel32 | offsetof(CPUState, spc), "SPC");
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107 | 3a8a44c4 | aurel32 | cpu_gbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
108 | 3a8a44c4 | aurel32 | offsetof(CPUState, gbr), "GBR");
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109 | 3a8a44c4 | aurel32 | cpu_vbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
110 | 3a8a44c4 | aurel32 | offsetof(CPUState, vbr), "VBR");
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111 | 3a8a44c4 | aurel32 | cpu_sgr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
112 | 3a8a44c4 | aurel32 | offsetof(CPUState, sgr), "SGR");
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113 | 3a8a44c4 | aurel32 | cpu_dbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
114 | 3a8a44c4 | aurel32 | offsetof(CPUState, dbr), "DBR");
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115 | 3a8a44c4 | aurel32 | cpu_mach = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
116 | 3a8a44c4 | aurel32 | offsetof(CPUState, mach), "MACH");
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117 | 3a8a44c4 | aurel32 | cpu_macl = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
118 | 3a8a44c4 | aurel32 | offsetof(CPUState, macl), "MACL");
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119 | 3a8a44c4 | aurel32 | cpu_pr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
120 | 3a8a44c4 | aurel32 | offsetof(CPUState, pr), "PR");
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121 | 3a8a44c4 | aurel32 | cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
122 | 3a8a44c4 | aurel32 | offsetof(CPUState, fpscr), "FPSCR");
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123 | 3a8a44c4 | aurel32 | cpu_fpul = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
124 | 3a8a44c4 | aurel32 | offsetof(CPUState, fpul), "FPUL");
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125 | 3a8a44c4 | aurel32 | |
126 | 1000822b | aurel32 | cpu_flags = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
127 | 1000822b | aurel32 | offsetof(CPUState, flags), "_flags_");
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128 | 1000822b | aurel32 | cpu_delayed_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, |
129 | 1000822b | aurel32 | offsetof(CPUState, delayed_pc), |
130 | 1000822b | aurel32 | "_delayed_pc_");
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131 | 1000822b | aurel32 | |
132 | 988d7eaa | aurel32 | /* register helpers */
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133 | 988d7eaa | aurel32 | #undef DEF_HELPER
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134 | 988d7eaa | aurel32 | #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
135 | 988d7eaa | aurel32 | #include "helper.h" |
136 | 988d7eaa | aurel32 | |
137 | 2e70f6ef | pbrook | done_init = 1;
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138 | 2e70f6ef | pbrook | } |
139 | 2e70f6ef | pbrook | |
140 | fdf9b3e8 | bellard | #ifdef CONFIG_USER_ONLY
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141 | fdf9b3e8 | bellard | |
142 | eda9b09b | bellard | #define GEN_OP_LD(width, reg) \
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143 | eda9b09b | bellard | void gen_op_ld##width##_T0_##reg (DisasContext *ctx) { \ |
144 | eda9b09b | bellard | gen_op_ld##width##_T0_##reg##_raw(); \ |
145 | fdf9b3e8 | bellard | } |
146 | eda9b09b | bellard | #define GEN_OP_ST(width, reg) \
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147 | eda9b09b | bellard | void gen_op_st##width##_##reg##_T1 (DisasContext *ctx) { \ |
148 | eda9b09b | bellard | gen_op_st##width##_##reg##_T1_raw(); \ |
149 | fdf9b3e8 | bellard | } |
150 | fdf9b3e8 | bellard | |
151 | fdf9b3e8 | bellard | #else
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152 | fdf9b3e8 | bellard | |
153 | eda9b09b | bellard | #define GEN_OP_LD(width, reg) \
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154 | eda9b09b | bellard | void gen_op_ld##width##_T0_##reg (DisasContext *ctx) { \ |
155 | eda9b09b | bellard | if (ctx->memidx) gen_op_ld##width##_T0_##reg##_kernel(); \ |
156 | eda9b09b | bellard | else gen_op_ld##width##_T0_##reg##_user();\ |
157 | fdf9b3e8 | bellard | } |
158 | eda9b09b | bellard | #define GEN_OP_ST(width, reg) \
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159 | eda9b09b | bellard | void gen_op_st##width##_##reg##_T1 (DisasContext *ctx) { \ |
160 | eda9b09b | bellard | if (ctx->memidx) gen_op_st##width##_##reg##_T1_kernel(); \ |
161 | eda9b09b | bellard | else gen_op_st##width##_##reg##_T1_user();\ |
162 | fdf9b3e8 | bellard | } |
163 | fdf9b3e8 | bellard | |
164 | fdf9b3e8 | bellard | #endif
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165 | fdf9b3e8 | bellard | |
166 | eda9b09b | bellard | GEN_OP_LD(ub, T0) |
167 | eda9b09b | bellard | GEN_OP_LD(b, T0) |
168 | eda9b09b | bellard | GEN_OP_ST(b, T0) |
169 | eda9b09b | bellard | GEN_OP_LD(uw, T0) |
170 | eda9b09b | bellard | GEN_OP_LD(w, T0) |
171 | eda9b09b | bellard | GEN_OP_ST(w, T0) |
172 | eda9b09b | bellard | GEN_OP_LD(l, T0) |
173 | eda9b09b | bellard | GEN_OP_ST(l, T0) |
174 | eda9b09b | bellard | GEN_OP_LD(fl, FT0) |
175 | eda9b09b | bellard | GEN_OP_ST(fl, FT0) |
176 | eda9b09b | bellard | GEN_OP_LD(fq, DT0) |
177 | eda9b09b | bellard | GEN_OP_ST(fq, DT0) |
178 | fdf9b3e8 | bellard | |
179 | fdf9b3e8 | bellard | void cpu_dump_state(CPUState * env, FILE * f,
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180 | fdf9b3e8 | bellard | int (*cpu_fprintf) (FILE * f, const char *fmt, ...), |
181 | fdf9b3e8 | bellard | int flags)
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182 | fdf9b3e8 | bellard | { |
183 | fdf9b3e8 | bellard | int i;
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184 | eda9b09b | bellard | cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
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185 | eda9b09b | bellard | env->pc, env->sr, env->pr, env->fpscr); |
186 | 274a9e70 | aurel32 | cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
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187 | 274a9e70 | aurel32 | env->spc, env->ssr, env->gbr, env->vbr); |
188 | 274a9e70 | aurel32 | cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
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189 | 274a9e70 | aurel32 | env->sgr, env->dbr, env->delayed_pc, env->fpul); |
190 | fdf9b3e8 | bellard | for (i = 0; i < 24; i += 4) { |
191 | fdf9b3e8 | bellard | cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
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192 | fdf9b3e8 | bellard | i, env->gregs[i], i + 1, env->gregs[i + 1], |
193 | fdf9b3e8 | bellard | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); |
194 | fdf9b3e8 | bellard | } |
195 | fdf9b3e8 | bellard | if (env->flags & DELAY_SLOT) {
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196 | fdf9b3e8 | bellard | cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
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197 | fdf9b3e8 | bellard | env->delayed_pc); |
198 | fdf9b3e8 | bellard | } else if (env->flags & DELAY_SLOT_CONDITIONAL) { |
199 | fdf9b3e8 | bellard | cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
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200 | fdf9b3e8 | bellard | env->delayed_pc); |
201 | fdf9b3e8 | bellard | } |
202 | fdf9b3e8 | bellard | } |
203 | fdf9b3e8 | bellard | |
204 | fdf9b3e8 | bellard | void cpu_sh4_reset(CPUSH4State * env)
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205 | fdf9b3e8 | bellard | { |
206 | 9c2a9ea1 | pbrook | #if defined(CONFIG_USER_ONLY)
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207 | 4c909d14 | ths | env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */
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208 | 9c2a9ea1 | pbrook | #else
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209 | fdf9b3e8 | bellard | env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */ |
210 | 9c2a9ea1 | pbrook | #endif
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211 | fdf9b3e8 | bellard | env->vbr = 0;
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212 | fdf9b3e8 | bellard | env->pc = 0xA0000000;
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213 | ea6cf6be | ths | #if defined(CONFIG_USER_ONLY)
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214 | ea6cf6be | ths | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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215 | b0b3de89 | bellard | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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216 | ea6cf6be | ths | #else
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217 | ea6cf6be | ths | env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ |
218 | b0b3de89 | bellard | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
219 | ea6cf6be | ths | #endif
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220 | fdf9b3e8 | bellard | env->mmucr = 0;
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221 | fdf9b3e8 | bellard | } |
222 | fdf9b3e8 | bellard | |
223 | aaed909a | bellard | CPUSH4State *cpu_sh4_init(const char *cpu_model) |
224 | fdf9b3e8 | bellard | { |
225 | fdf9b3e8 | bellard | CPUSH4State *env; |
226 | fdf9b3e8 | bellard | |
227 | fdf9b3e8 | bellard | env = qemu_mallocz(sizeof(CPUSH4State));
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228 | fdf9b3e8 | bellard | if (!env)
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229 | fdf9b3e8 | bellard | return NULL; |
230 | fdf9b3e8 | bellard | cpu_exec_init(env); |
231 | 2e70f6ef | pbrook | sh4_translate_init(); |
232 | fdf9b3e8 | bellard | cpu_sh4_reset(env); |
233 | fdf9b3e8 | bellard | tlb_flush(env, 1);
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234 | fdf9b3e8 | bellard | return env;
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235 | fdf9b3e8 | bellard | } |
236 | fdf9b3e8 | bellard | |
237 | fdf9b3e8 | bellard | static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
238 | fdf9b3e8 | bellard | { |
239 | fdf9b3e8 | bellard | TranslationBlock *tb; |
240 | fdf9b3e8 | bellard | tb = ctx->tb; |
241 | fdf9b3e8 | bellard | |
242 | fdf9b3e8 | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
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243 | fdf9b3e8 | bellard | !ctx->singlestep_enabled) { |
244 | fdf9b3e8 | bellard | /* Use a direct jump if in same page and singlestep not enabled */
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245 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
246 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, dest); |
247 | 57fec1fe | bellard | tcg_gen_exit_tb((long) tb + n);
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248 | fdf9b3e8 | bellard | } else {
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249 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, dest); |
250 | 57fec1fe | bellard | if (ctx->singlestep_enabled)
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251 | e6afc2f4 | aurel32 | tcg_gen_helper_0_0(helper_debug); |
252 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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253 | fdf9b3e8 | bellard | } |
254 | fdf9b3e8 | bellard | } |
255 | fdf9b3e8 | bellard | |
256 | fdf9b3e8 | bellard | static void gen_jump(DisasContext * ctx) |
257 | fdf9b3e8 | bellard | { |
258 | fdf9b3e8 | bellard | if (ctx->delayed_pc == (uint32_t) - 1) { |
259 | fdf9b3e8 | bellard | /* Target is not statically known, it comes necessarily from a
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260 | fdf9b3e8 | bellard | delayed jump as immediate jump are conditinal jumps */
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261 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
262 | fdf9b3e8 | bellard | if (ctx->singlestep_enabled)
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263 | e6afc2f4 | aurel32 | tcg_gen_helper_0_0(helper_debug); |
264 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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265 | fdf9b3e8 | bellard | } else {
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266 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ctx->delayed_pc);
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267 | fdf9b3e8 | bellard | } |
268 | fdf9b3e8 | bellard | } |
269 | fdf9b3e8 | bellard | |
270 | 1000822b | aurel32 | static inline void gen_branch_slot(uint32_t delayed_pc, int t) |
271 | 1000822b | aurel32 | { |
272 | 1000822b | aurel32 | int label = gen_new_label();
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273 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); |
274 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_sr, SR_T);
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275 | 1000822b | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], t ? SR_T : 0, label); |
276 | 1000822b | aurel32 | tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
277 | 1000822b | aurel32 | gen_set_label(label); |
278 | 1000822b | aurel32 | } |
279 | 1000822b | aurel32 | |
280 | fdf9b3e8 | bellard | /* Immediate conditional jump (bt or bf) */
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281 | fdf9b3e8 | bellard | static void gen_conditional_jump(DisasContext * ctx, |
282 | fdf9b3e8 | bellard | target_ulong ift, target_ulong ifnott) |
283 | fdf9b3e8 | bellard | { |
284 | fdf9b3e8 | bellard | int l1;
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285 | fdf9b3e8 | bellard | |
286 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
287 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_sr, SR_T);
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288 | 1000822b | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], SR_T, l1);
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289 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ifnott);
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290 | fdf9b3e8 | bellard | gen_set_label(l1); |
291 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 1, ift);
|
292 | fdf9b3e8 | bellard | } |
293 | fdf9b3e8 | bellard | |
294 | fdf9b3e8 | bellard | /* Delayed conditional jump (bt or bf) */
|
295 | fdf9b3e8 | bellard | static void gen_delayed_conditional_jump(DisasContext * ctx) |
296 | fdf9b3e8 | bellard | { |
297 | fdf9b3e8 | bellard | int l1;
|
298 | fdf9b3e8 | bellard | |
299 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
300 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_flags, DELAY_SLOT_TRUE);
|
301 | 1000822b | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], DELAY_SLOT_TRUE, l1);
|
302 | 823029f9 | ths | gen_goto_tb(ctx, 1, ctx->pc + 2); |
303 | fdf9b3e8 | bellard | gen_set_label(l1); |
304 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE); |
305 | 9c2a9ea1 | pbrook | gen_jump(ctx); |
306 | fdf9b3e8 | bellard | } |
307 | fdf9b3e8 | bellard | |
308 | a4625612 | aurel32 | static inline void gen_set_t(void) |
309 | a4625612 | aurel32 | { |
310 | a4625612 | aurel32 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); |
311 | a4625612 | aurel32 | } |
312 | a4625612 | aurel32 | |
313 | a4625612 | aurel32 | static inline void gen_clr_t(void) |
314 | a4625612 | aurel32 | { |
315 | a4625612 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
316 | a4625612 | aurel32 | } |
317 | a4625612 | aurel32 | |
318 | a4625612 | aurel32 | static inline void gen_cmp(int cond, TCGv t0, TCGv t1) |
319 | a4625612 | aurel32 | { |
320 | a4625612 | aurel32 | int label1 = gen_new_label();
|
321 | a4625612 | aurel32 | int label2 = gen_new_label();
|
322 | a4625612 | aurel32 | tcg_gen_brcond_i32(cond, t1, t0, label1); |
323 | a4625612 | aurel32 | gen_clr_t(); |
324 | a4625612 | aurel32 | tcg_gen_br(label2); |
325 | a4625612 | aurel32 | gen_set_label(label1); |
326 | a4625612 | aurel32 | gen_set_t(); |
327 | a4625612 | aurel32 | gen_set_label(label2); |
328 | a4625612 | aurel32 | } |
329 | a4625612 | aurel32 | |
330 | a4625612 | aurel32 | static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) |
331 | a4625612 | aurel32 | { |
332 | a4625612 | aurel32 | int label1 = gen_new_label();
|
333 | a4625612 | aurel32 | int label2 = gen_new_label();
|
334 | a4625612 | aurel32 | tcg_gen_brcondi_i32(cond, t0, imm, label1); |
335 | a4625612 | aurel32 | gen_clr_t(); |
336 | a4625612 | aurel32 | tcg_gen_br(label2); |
337 | a4625612 | aurel32 | gen_set_label(label1); |
338 | a4625612 | aurel32 | gen_set_t(); |
339 | a4625612 | aurel32 | gen_set_label(label2); |
340 | a4625612 | aurel32 | } |
341 | a4625612 | aurel32 | |
342 | 1000822b | aurel32 | static inline void gen_store_flags(uint32_t flags) |
343 | 1000822b | aurel32 | { |
344 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
345 | 1000822b | aurel32 | tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); |
346 | 1000822b | aurel32 | } |
347 | 1000822b | aurel32 | |
348 | fdf9b3e8 | bellard | #define B3_0 (ctx->opcode & 0xf) |
349 | fdf9b3e8 | bellard | #define B6_4 ((ctx->opcode >> 4) & 0x7) |
350 | fdf9b3e8 | bellard | #define B7_4 ((ctx->opcode >> 4) & 0xf) |
351 | fdf9b3e8 | bellard | #define B7_0 (ctx->opcode & 0xff) |
352 | fdf9b3e8 | bellard | #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) |
353 | fdf9b3e8 | bellard | #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ |
354 | fdf9b3e8 | bellard | (ctx->opcode & 0xfff))
|
355 | fdf9b3e8 | bellard | #define B11_8 ((ctx->opcode >> 8) & 0xf) |
356 | fdf9b3e8 | bellard | #define B15_12 ((ctx->opcode >> 12) & 0xf) |
357 | fdf9b3e8 | bellard | |
358 | fdf9b3e8 | bellard | #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ |
359 | fdf9b3e8 | bellard | (x) + 16 : (x))
|
360 | fdf9b3e8 | bellard | |
361 | fdf9b3e8 | bellard | #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ |
362 | fdf9b3e8 | bellard | ? (x) + 16 : (x))
|
363 | fdf9b3e8 | bellard | |
364 | eda9b09b | bellard | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
365 | f09111e0 | ths | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
366 | eda9b09b | bellard | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
367 | ea6cf6be | ths | #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
368 | eda9b09b | bellard | |
369 | fdf9b3e8 | bellard | #define CHECK_NOT_DELAY_SLOT \
|
370 | fdf9b3e8 | bellard | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
|
371 | e6afc2f4 | aurel32 | {tcg_gen_helper_0_0(helper_raise_slot_illegal_instruction); ctx->bstate = BS_EXCP; \ |
372 | fdf9b3e8 | bellard | return;}
|
373 | fdf9b3e8 | bellard | |
374 | 823029f9 | ths | void _decode_opc(DisasContext * ctx)
|
375 | fdf9b3e8 | bellard | { |
376 | fdf9b3e8 | bellard | #if 0
|
377 | fdf9b3e8 | bellard | fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
|
378 | fdf9b3e8 | bellard | #endif
|
379 | fdf9b3e8 | bellard | switch (ctx->opcode) {
|
380 | fdf9b3e8 | bellard | case 0x0019: /* div0u */ |
381 | 3a8a44c4 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); |
382 | fdf9b3e8 | bellard | return;
|
383 | fdf9b3e8 | bellard | case 0x000b: /* rts */ |
384 | 1000822b | aurel32 | CHECK_NOT_DELAY_SLOT |
385 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr); |
386 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
387 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
388 | fdf9b3e8 | bellard | return;
|
389 | fdf9b3e8 | bellard | case 0x0028: /* clrmac */ |
390 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_mach, 0);
|
391 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_macl, 0);
|
392 | fdf9b3e8 | bellard | return;
|
393 | fdf9b3e8 | bellard | case 0x0048: /* clrs */ |
394 | 3a8a44c4 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); |
395 | fdf9b3e8 | bellard | return;
|
396 | fdf9b3e8 | bellard | case 0x0008: /* clrt */ |
397 | a4625612 | aurel32 | gen_clr_t(); |
398 | fdf9b3e8 | bellard | return;
|
399 | fdf9b3e8 | bellard | case 0x0038: /* ldtlb */ |
400 | ea2b542a | aurel32 | #if defined(CONFIG_USER_ONLY)
|
401 | fdf9b3e8 | bellard | assert(0); /* XXXXX */ |
402 | ea2b542a | aurel32 | #else
|
403 | e6afc2f4 | aurel32 | tcg_gen_helper_0_0(helper_ldtlb); |
404 | ea2b542a | aurel32 | #endif
|
405 | fdf9b3e8 | bellard | return;
|
406 | c5e814b2 | ths | case 0x002b: /* rte */ |
407 | 1000822b | aurel32 | CHECK_NOT_DELAY_SLOT |
408 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_sr, cpu_ssr); |
409 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); |
410 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
411 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
412 | fdf9b3e8 | bellard | return;
|
413 | fdf9b3e8 | bellard | case 0x0058: /* sets */ |
414 | 3a8a44c4 | aurel32 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); |
415 | fdf9b3e8 | bellard | return;
|
416 | fdf9b3e8 | bellard | case 0x0018: /* sett */ |
417 | a4625612 | aurel32 | gen_set_t(); |
418 | fdf9b3e8 | bellard | return;
|
419 | 24988dc2 | aurel32 | case 0xfbfd: /* frchg */ |
420 | eda9b09b | bellard | gen_op_frchg(); |
421 | 823029f9 | ths | ctx->bstate = BS_STOP; |
422 | fdf9b3e8 | bellard | return;
|
423 | 24988dc2 | aurel32 | case 0xf3fd: /* fschg */ |
424 | eda9b09b | bellard | gen_op_fschg(); |
425 | 823029f9 | ths | ctx->bstate = BS_STOP; |
426 | fdf9b3e8 | bellard | return;
|
427 | fdf9b3e8 | bellard | case 0x0009: /* nop */ |
428 | fdf9b3e8 | bellard | return;
|
429 | fdf9b3e8 | bellard | case 0x001b: /* sleep */ |
430 | 833ed386 | aurel32 | if (ctx->memidx) {
|
431 | e6afc2f4 | aurel32 | tcg_gen_helper_0_0(helper_sleep); |
432 | 833ed386 | aurel32 | } else {
|
433 | e6afc2f4 | aurel32 | tcg_gen_helper_0_0(helper_raise_illegal_instruction); |
434 | 833ed386 | aurel32 | ctx->bstate = BS_EXCP; |
435 | 833ed386 | aurel32 | } |
436 | fdf9b3e8 | bellard | return;
|
437 | fdf9b3e8 | bellard | } |
438 | fdf9b3e8 | bellard | |
439 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf000) { |
440 | fdf9b3e8 | bellard | case 0x1000: /* mov.l Rm,@(disp,Rn) */ |
441 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
442 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
443 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0 * 4); |
444 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
445 | fdf9b3e8 | bellard | return;
|
446 | fdf9b3e8 | bellard | case 0x5000: /* mov.l @(disp,Rm),Rn */ |
447 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
448 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0 * 4); |
449 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
450 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
451 | fdf9b3e8 | bellard | return;
|
452 | 24988dc2 | aurel32 | case 0xe000: /* mov #imm,Rn */ |
453 | 1e8864f7 | aurel32 | tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], B7_0s); |
454 | fdf9b3e8 | bellard | return;
|
455 | fdf9b3e8 | bellard | case 0x9000: /* mov.w @(disp,PC),Rn */ |
456 | 3bf73a49 | aurel32 | tcg_gen_movi_i32(cpu_T[0], ctx->pc + 4 + B7_0 * 2); |
457 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
458 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
459 | fdf9b3e8 | bellard | return;
|
460 | fdf9b3e8 | bellard | case 0xd000: /* mov.l @(disp,PC),Rn */ |
461 | 3bf73a49 | aurel32 | tcg_gen_movi_i32(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3); |
462 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
463 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
464 | fdf9b3e8 | bellard | return;
|
465 | 24988dc2 | aurel32 | case 0x7000: /* add #imm,Rn */ |
466 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], B7_0s); |
467 | fdf9b3e8 | bellard | return;
|
468 | fdf9b3e8 | bellard | case 0xa000: /* bra disp */ |
469 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
470 | 1000822b | aurel32 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
471 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); |
472 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
473 | fdf9b3e8 | bellard | return;
|
474 | fdf9b3e8 | bellard | case 0xb000: /* bsr disp */ |
475 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
476 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
477 | 1000822b | aurel32 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
478 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); |
479 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
480 | fdf9b3e8 | bellard | return;
|
481 | fdf9b3e8 | bellard | } |
482 | fdf9b3e8 | bellard | |
483 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf00f) { |
484 | fdf9b3e8 | bellard | case 0x6003: /* mov Rm,Rn */ |
485 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
486 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
487 | fdf9b3e8 | bellard | return;
|
488 | fdf9b3e8 | bellard | case 0x2000: /* mov.b Rm,@Rn */ |
489 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
490 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
491 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
492 | fdf9b3e8 | bellard | return;
|
493 | fdf9b3e8 | bellard | case 0x2001: /* mov.w Rm,@Rn */ |
494 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
495 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
496 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
497 | fdf9b3e8 | bellard | return;
|
498 | fdf9b3e8 | bellard | case 0x2002: /* mov.l Rm,@Rn */ |
499 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
500 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
501 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
502 | fdf9b3e8 | bellard | return;
|
503 | fdf9b3e8 | bellard | case 0x6000: /* mov.b @Rm,Rn */ |
504 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
505 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
506 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
507 | fdf9b3e8 | bellard | return;
|
508 | fdf9b3e8 | bellard | case 0x6001: /* mov.w @Rm,Rn */ |
509 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
510 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
511 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
512 | fdf9b3e8 | bellard | return;
|
513 | fdf9b3e8 | bellard | case 0x6002: /* mov.l @Rm,Rn */ |
514 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
515 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
516 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
517 | fdf9b3e8 | bellard | return;
|
518 | fdf9b3e8 | bellard | case 0x2004: /* mov.b Rm,@-Rn */ |
519 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
520 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
521 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 1); /* modify register status */ |
522 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
523 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], |
524 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 1); /* recover register status */ |
525 | 559dd74d | aurel32 | gen_op_stb_T0_T1(ctx); /* might cause re-execution */
|
526 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
527 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 1); /* modify register status */ |
528 | fdf9b3e8 | bellard | return;
|
529 | fdf9b3e8 | bellard | case 0x2005: /* mov.w Rm,@-Rn */ |
530 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
531 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
532 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 2);
|
533 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
534 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], |
535 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 2);
|
536 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
537 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
538 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 2);
|
539 | fdf9b3e8 | bellard | return;
|
540 | fdf9b3e8 | bellard | case 0x2006: /* mov.l Rm,@-Rn */ |
541 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
542 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
543 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 4);
|
544 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
545 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], |
546 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 4);
|
547 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
548 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], |
549 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 4);
|
550 | fdf9b3e8 | bellard | return;
|
551 | eda9b09b | bellard | case 0x6004: /* mov.b @Rm+,Rn */ |
552 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
553 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
554 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
555 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
556 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
557 | 559dd74d | aurel32 | cpu_gregs[REG(B7_4)], 1);
|
558 | fdf9b3e8 | bellard | return;
|
559 | fdf9b3e8 | bellard | case 0x6005: /* mov.w @Rm+,Rn */ |
560 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
561 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
562 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
563 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
564 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
565 | 559dd74d | aurel32 | cpu_gregs[REG(B7_4)], 2);
|
566 | fdf9b3e8 | bellard | return;
|
567 | fdf9b3e8 | bellard | case 0x6006: /* mov.l @Rm+,Rn */ |
568 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
569 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
570 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
571 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
572 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
573 | 559dd74d | aurel32 | cpu_gregs[REG(B7_4)], 4);
|
574 | fdf9b3e8 | bellard | return;
|
575 | fdf9b3e8 | bellard | case 0x0004: /* mov.b Rm,@(R0,Rn) */ |
576 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
577 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
578 | 559dd74d | aurel32 | tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]); |
579 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
580 | fdf9b3e8 | bellard | return;
|
581 | fdf9b3e8 | bellard | case 0x0005: /* mov.w Rm,@(R0,Rn) */ |
582 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
583 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
584 | 559dd74d | aurel32 | tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]); |
585 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
586 | fdf9b3e8 | bellard | return;
|
587 | fdf9b3e8 | bellard | case 0x0006: /* mov.l Rm,@(R0,Rn) */ |
588 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
589 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
590 | 559dd74d | aurel32 | tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]); |
591 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
592 | fdf9b3e8 | bellard | return;
|
593 | fdf9b3e8 | bellard | case 0x000c: /* mov.b @(R0,Rm),Rn */ |
594 | 559dd74d | aurel32 | tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
595 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
596 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
597 | fdf9b3e8 | bellard | return;
|
598 | fdf9b3e8 | bellard | case 0x000d: /* mov.w @(R0,Rm),Rn */ |
599 | 559dd74d | aurel32 | tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
600 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
601 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
602 | fdf9b3e8 | bellard | return;
|
603 | fdf9b3e8 | bellard | case 0x000e: /* mov.l @(R0,Rm),Rn */ |
604 | 559dd74d | aurel32 | tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
605 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
606 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
607 | fdf9b3e8 | bellard | return;
|
608 | fdf9b3e8 | bellard | case 0x6008: /* swap.b Rm,Rn */ |
609 | 559dd74d | aurel32 | tcg_gen_andi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)], 0xffff0000);
|
610 | 559dd74d | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0xff); |
611 | 559dd74d | aurel32 | tcg_gen_shli_i32(cpu_T[0], cpu_T[0], 8); |
612 | 559dd74d | aurel32 | tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]);
|
613 | 559dd74d | aurel32 | tcg_gen_shri_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 8); |
614 | 559dd74d | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff); |
615 | 559dd74d | aurel32 | tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]);
|
616 | fdf9b3e8 | bellard | return;
|
617 | fdf9b3e8 | bellard | case 0x6009: /* swap.w Rm,Rn */ |
618 | 559dd74d | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0xffff); |
619 | 559dd74d | aurel32 | tcg_gen_shli_i32(cpu_T[0], cpu_T[0], 16); |
620 | 559dd74d | aurel32 | tcg_gen_shri_i32(cpu_T[1], cpu_gregs[REG(B7_4)], 16); |
621 | 559dd74d | aurel32 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff); |
622 | 559dd74d | aurel32 | tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_T[0], cpu_T[1]); |
623 | fdf9b3e8 | bellard | return;
|
624 | fdf9b3e8 | bellard | case 0x200d: /* xtrct Rm,Rn */ |
625 | 559dd74d | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0xffff); |
626 | 559dd74d | aurel32 | tcg_gen_shli_i32(cpu_T[0], cpu_T[0], 16); |
627 | 559dd74d | aurel32 | tcg_gen_shri_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 16); |
628 | 559dd74d | aurel32 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff); |
629 | 5aa3b1ea | aurel32 | tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_T[0], cpu_T[1]); |
630 | fdf9b3e8 | bellard | return;
|
631 | fdf9b3e8 | bellard | case 0x300c: /* add Rm,Rn */ |
632 | 559dd74d | aurel32 | tcg_gen_add_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
633 | fdf9b3e8 | bellard | return;
|
634 | fdf9b3e8 | bellard | case 0x300e: /* addc Rm,Rn */ |
635 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
636 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
637 | fdf9b3e8 | bellard | gen_op_addc_T0_T1(); |
638 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
|
639 | fdf9b3e8 | bellard | return;
|
640 | fdf9b3e8 | bellard | case 0x300f: /* addv Rm,Rn */ |
641 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
642 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
643 | fdf9b3e8 | bellard | gen_op_addv_T0_T1(); |
644 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
|
645 | fdf9b3e8 | bellard | return;
|
646 | fdf9b3e8 | bellard | case 0x2009: /* and Rm,Rn */ |
647 | 559dd74d | aurel32 | tcg_gen_and_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
648 | fdf9b3e8 | bellard | return;
|
649 | fdf9b3e8 | bellard | case 0x3000: /* cmp/eq Rm,Rn */ |
650 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
651 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
652 | a4625612 | aurel32 | gen_cmp(TCG_COND_EQ, cpu_T[0], cpu_T[1]); |
653 | fdf9b3e8 | bellard | return;
|
654 | fdf9b3e8 | bellard | case 0x3003: /* cmp/ge Rm,Rn */ |
655 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
656 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
657 | a4625612 | aurel32 | gen_cmp(TCG_COND_GE, cpu_T[0], cpu_T[1]); |
658 | fdf9b3e8 | bellard | return;
|
659 | fdf9b3e8 | bellard | case 0x3007: /* cmp/gt Rm,Rn */ |
660 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
661 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
662 | a4625612 | aurel32 | gen_cmp(TCG_COND_GT, cpu_T[0], cpu_T[1]); |
663 | fdf9b3e8 | bellard | return;
|
664 | fdf9b3e8 | bellard | case 0x3006: /* cmp/hi Rm,Rn */ |
665 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
666 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
667 | a4625612 | aurel32 | gen_cmp(TCG_COND_GTU, cpu_T[0], cpu_T[1]); |
668 | fdf9b3e8 | bellard | return;
|
669 | fdf9b3e8 | bellard | case 0x3002: /* cmp/hs Rm,Rn */ |
670 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
671 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
672 | a4625612 | aurel32 | gen_cmp(TCG_COND_GEU, cpu_T[0], cpu_T[1]); |
673 | fdf9b3e8 | bellard | return;
|
674 | fdf9b3e8 | bellard | case 0x200c: /* cmp/str Rm,Rn */ |
675 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
676 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
677 | fdf9b3e8 | bellard | gen_op_cmp_str_T0_T1(); |
678 | fdf9b3e8 | bellard | return;
|
679 | fdf9b3e8 | bellard | case 0x2007: /* div0s Rm,Rn */ |
680 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
681 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
682 | fdf9b3e8 | bellard | gen_op_div0s_T0_T1(); |
683 | fdf9b3e8 | bellard | return;
|
684 | fdf9b3e8 | bellard | case 0x3004: /* div1 Rm,Rn */ |
685 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
686 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
687 | fdf9b3e8 | bellard | gen_op_div1_T0_T1(); |
688 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
|
689 | fdf9b3e8 | bellard | return;
|
690 | fdf9b3e8 | bellard | case 0x300d: /* dmuls.l Rm,Rn */ |
691 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
692 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
693 | fdf9b3e8 | bellard | gen_op_dmulsl_T0_T1(); |
694 | fdf9b3e8 | bellard | return;
|
695 | fdf9b3e8 | bellard | case 0x3005: /* dmulu.l Rm,Rn */ |
696 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
697 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
698 | fdf9b3e8 | bellard | gen_op_dmulul_T0_T1(); |
699 | fdf9b3e8 | bellard | return;
|
700 | fdf9b3e8 | bellard | case 0x600e: /* exts.b Rm,Rn */ |
701 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
702 | 3bf73a49 | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff); |
703 | 3bf73a49 | aurel32 | tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]); |
704 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
705 | fdf9b3e8 | bellard | return;
|
706 | fdf9b3e8 | bellard | case 0x600f: /* exts.w Rm,Rn */ |
707 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
708 | 3bf73a49 | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff); |
709 | 3bf73a49 | aurel32 | tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]); |
710 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
711 | fdf9b3e8 | bellard | return;
|
712 | fdf9b3e8 | bellard | case 0x600c: /* extu.b Rm,Rn */ |
713 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
714 | 3bf73a49 | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff); |
715 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
716 | fdf9b3e8 | bellard | return;
|
717 | fdf9b3e8 | bellard | case 0x600d: /* extu.w Rm,Rn */ |
718 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
719 | 3bf73a49 | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff); |
720 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
721 | fdf9b3e8 | bellard | return;
|
722 | 24988dc2 | aurel32 | case 0x000f: /* mac.l @Rm+,@Rn+ */ |
723 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
724 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
725 | 829337a6 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
726 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
727 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
728 | fdf9b3e8 | bellard | gen_op_macl_T0_T1(); |
729 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], cpu_gregs[REG(B7_4)], 4);
|
730 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
731 | fdf9b3e8 | bellard | return;
|
732 | fdf9b3e8 | bellard | case 0x400f: /* mac.w @Rm+,@Rn+ */ |
733 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
734 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
735 | 829337a6 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
736 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
737 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
738 | fdf9b3e8 | bellard | gen_op_macw_T0_T1(); |
739 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);
|
740 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], cpu_gregs[REG(B7_4)], 2);
|
741 | fdf9b3e8 | bellard | return;
|
742 | fdf9b3e8 | bellard | case 0x0007: /* mul.l Rm,Rn */ |
743 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
744 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
745 | fdf9b3e8 | bellard | gen_op_mull_T0_T1(); |
746 | fdf9b3e8 | bellard | return;
|
747 | fdf9b3e8 | bellard | case 0x200f: /* muls.w Rm,Rn */ |
748 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
749 | 3bf73a49 | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff); |
750 | 3bf73a49 | aurel32 | tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]); |
751 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
752 | 3bf73a49 | aurel32 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff); |
753 | 3bf73a49 | aurel32 | tcg_gen_ext16s_i32(cpu_T[1], cpu_T[1]); |
754 | fdf9b3e8 | bellard | gen_op_mulsw_T0_T1(); |
755 | fdf9b3e8 | bellard | return;
|
756 | fdf9b3e8 | bellard | case 0x200e: /* mulu.w Rm,Rn */ |
757 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
758 | 3bf73a49 | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff); |
759 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
760 | 3bf73a49 | aurel32 | tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff); |
761 | fdf9b3e8 | bellard | gen_op_muluw_T0_T1(); |
762 | fdf9b3e8 | bellard | return;
|
763 | fdf9b3e8 | bellard | case 0x600b: /* neg Rm,Rn */ |
764 | 559dd74d | aurel32 | tcg_gen_neg_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
765 | fdf9b3e8 | bellard | return;
|
766 | fdf9b3e8 | bellard | case 0x600a: /* negc Rm,Rn */ |
767 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
768 | fdf9b3e8 | bellard | gen_op_negc_T0(); |
769 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
770 | fdf9b3e8 | bellard | return;
|
771 | fdf9b3e8 | bellard | case 0x6007: /* not Rm,Rn */ |
772 | 559dd74d | aurel32 | tcg_gen_not_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
773 | fdf9b3e8 | bellard | return;
|
774 | fdf9b3e8 | bellard | case 0x200b: /* or Rm,Rn */ |
775 | 559dd74d | aurel32 | tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
776 | fdf9b3e8 | bellard | return;
|
777 | fdf9b3e8 | bellard | case 0x400c: /* shad Rm,Rn */ |
778 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
779 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
780 | fdf9b3e8 | bellard | gen_op_shad_T0_T1(); |
781 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
|
782 | fdf9b3e8 | bellard | return;
|
783 | fdf9b3e8 | bellard | case 0x400d: /* shld Rm,Rn */ |
784 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
785 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
786 | fdf9b3e8 | bellard | gen_op_shld_T0_T1(); |
787 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
|
788 | fdf9b3e8 | bellard | return;
|
789 | fdf9b3e8 | bellard | case 0x3008: /* sub Rm,Rn */ |
790 | 559dd74d | aurel32 | tcg_gen_sub_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
791 | fdf9b3e8 | bellard | return;
|
792 | fdf9b3e8 | bellard | case 0x300a: /* subc Rm,Rn */ |
793 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
794 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
795 | fdf9b3e8 | bellard | gen_op_subc_T0_T1(); |
796 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
|
797 | fdf9b3e8 | bellard | return;
|
798 | fdf9b3e8 | bellard | case 0x300b: /* subv Rm,Rn */ |
799 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
800 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
801 | fdf9b3e8 | bellard | gen_op_subv_T0_T1(); |
802 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]);
|
803 | fdf9b3e8 | bellard | return;
|
804 | fdf9b3e8 | bellard | case 0x2008: /* tst Rm,Rn */ |
805 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
806 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
807 | a4625612 | aurel32 | tcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1]); |
808 | a4625612 | aurel32 | gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
809 | fdf9b3e8 | bellard | return;
|
810 | fdf9b3e8 | bellard | case 0x200a: /* xor Rm,Rn */ |
811 | 559dd74d | aurel32 | tcg_gen_xor_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
812 | fdf9b3e8 | bellard | return;
|
813 | e67888a7 | ths | case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
814 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
815 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
816 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
817 | eda9b09b | bellard | } else {
|
818 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
819 | eda9b09b | bellard | gen_op_fmov_FT0_frN(FREG(B11_8)); |
820 | eda9b09b | bellard | } |
821 | eda9b09b | bellard | return;
|
822 | e67888a7 | ths | case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ |
823 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
824 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
825 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
826 | eda9b09b | bellard | gen_op_stfq_DT0_T1(ctx); |
827 | eda9b09b | bellard | } else {
|
828 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
829 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
830 | eda9b09b | bellard | gen_op_stfl_FT0_T1(ctx); |
831 | eda9b09b | bellard | } |
832 | eda9b09b | bellard | return;
|
833 | e67888a7 | ths | case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ |
834 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
835 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
836 | eda9b09b | bellard | gen_op_ldfq_T0_DT0(ctx); |
837 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
838 | eda9b09b | bellard | } else {
|
839 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
840 | eda9b09b | bellard | gen_op_ldfl_T0_FT0(ctx); |
841 | f09111e0 | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
842 | eda9b09b | bellard | } |
843 | eda9b09b | bellard | return;
|
844 | e67888a7 | ths | case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ |
845 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
846 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
847 | eda9b09b | bellard | gen_op_ldfq_T0_DT0(ctx); |
848 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
849 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
850 | 559dd74d | aurel32 | cpu_gregs[REG(B7_4)], 8);
|
851 | eda9b09b | bellard | } else {
|
852 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
853 | eda9b09b | bellard | gen_op_ldfl_T0_FT0(ctx); |
854 | f09111e0 | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
855 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], |
856 | 559dd74d | aurel32 | cpu_gregs[REG(B7_4)], 4);
|
857 | eda9b09b | bellard | } |
858 | eda9b09b | bellard | return;
|
859 | e67888a7 | ths | case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
860 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
861 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
862 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
863 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
864 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
865 | eda9b09b | bellard | gen_op_stfq_DT0_T1(ctx); |
866 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
867 | eda9b09b | bellard | } else {
|
868 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
869 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
870 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
871 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
872 | eda9b09b | bellard | gen_op_stfl_FT0_T1(ctx); |
873 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
874 | eda9b09b | bellard | } |
875 | eda9b09b | bellard | return;
|
876 | e67888a7 | ths | case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
877 | 559dd74d | aurel32 | tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]); |
878 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
879 | eda9b09b | bellard | gen_op_ldfq_T0_DT0(ctx); |
880 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
881 | eda9b09b | bellard | } else {
|
882 | eda9b09b | bellard | gen_op_ldfl_T0_FT0(ctx); |
883 | f09111e0 | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
884 | eda9b09b | bellard | } |
885 | eda9b09b | bellard | return;
|
886 | e67888a7 | ths | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ |
887 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
888 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
889 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
890 | 559dd74d | aurel32 | tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]); |
891 | eda9b09b | bellard | gen_op_stfq_DT0_T1(ctx); |
892 | eda9b09b | bellard | } else {
|
893 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
894 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
895 | 559dd74d | aurel32 | tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]); |
896 | eda9b09b | bellard | gen_op_stfl_FT0_T1(ctx); |
897 | eda9b09b | bellard | } |
898 | eda9b09b | bellard | return;
|
899 | e67888a7 | ths | case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
900 | e67888a7 | ths | case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
901 | e67888a7 | ths | case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
902 | e67888a7 | ths | case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
903 | e67888a7 | ths | case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
904 | e67888a7 | ths | case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
905 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
906 | ea6cf6be | ths | if (ctx->opcode & 0x0110) |
907 | ea6cf6be | ths | break; /* illegal instruction */ |
908 | ea6cf6be | ths | gen_op_fmov_drN_DT1(DREG(B7_4)); |
909 | ea6cf6be | ths | gen_op_fmov_drN_DT0(DREG(B11_8)); |
910 | ea6cf6be | ths | } |
911 | ea6cf6be | ths | else {
|
912 | ea6cf6be | ths | gen_op_fmov_frN_FT1(FREG(B7_4)); |
913 | ea6cf6be | ths | gen_op_fmov_frN_FT0(FREG(B11_8)); |
914 | ea6cf6be | ths | } |
915 | ea6cf6be | ths | |
916 | ea6cf6be | ths | switch (ctx->opcode & 0xf00f) { |
917 | ea6cf6be | ths | case 0xf000: /* fadd Rm,Rn */ |
918 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fadd_DT() : gen_op_fadd_FT(); |
919 | ea6cf6be | ths | break;
|
920 | ea6cf6be | ths | case 0xf001: /* fsub Rm,Rn */ |
921 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fsub_DT() : gen_op_fsub_FT(); |
922 | ea6cf6be | ths | break;
|
923 | ea6cf6be | ths | case 0xf002: /* fmul Rm,Rn */ |
924 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fmul_DT() : gen_op_fmul_FT(); |
925 | ea6cf6be | ths | break;
|
926 | ea6cf6be | ths | case 0xf003: /* fdiv Rm,Rn */ |
927 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fdiv_DT() : gen_op_fdiv_FT(); |
928 | ea6cf6be | ths | break;
|
929 | ea6cf6be | ths | case 0xf004: /* fcmp/eq Rm,Rn */ |
930 | 24988dc2 | aurel32 | ctx->fpscr & FPSCR_PR ? gen_op_fcmp_eq_DT() : gen_op_fcmp_eq_FT(); |
931 | ea6cf6be | ths | return;
|
932 | ea6cf6be | ths | case 0xf005: /* fcmp/gt Rm,Rn */ |
933 | 24988dc2 | aurel32 | ctx->fpscr & FPSCR_PR ? gen_op_fcmp_gt_DT() : gen_op_fcmp_gt_FT(); |
934 | ea6cf6be | ths | return;
|
935 | ea6cf6be | ths | } |
936 | ea6cf6be | ths | |
937 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
938 | ea6cf6be | ths | gen_op_fmov_DT0_drN(DREG(B11_8)); |
939 | ea6cf6be | ths | } |
940 | ea6cf6be | ths | else {
|
941 | ea6cf6be | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
942 | ea6cf6be | ths | } |
943 | ea6cf6be | ths | return;
|
944 | fdf9b3e8 | bellard | } |
945 | fdf9b3e8 | bellard | |
946 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xff00) { |
947 | fdf9b3e8 | bellard | case 0xc900: /* and #imm,R0 */ |
948 | 559dd74d | aurel32 | tcg_gen_andi_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0); |
949 | fdf9b3e8 | bellard | return;
|
950 | 24988dc2 | aurel32 | case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
951 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
952 | 3a8a44c4 | aurel32 | tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr); |
953 | 829337a6 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
954 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
955 | 559dd74d | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0); |
956 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
957 | fdf9b3e8 | bellard | return;
|
958 | fdf9b3e8 | bellard | case 0x8b00: /* bf label */ |
959 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
960 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 2,
|
961 | fdf9b3e8 | bellard | ctx->pc + 4 + B7_0s * 2); |
962 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
963 | fdf9b3e8 | bellard | return;
|
964 | fdf9b3e8 | bellard | case 0x8f00: /* bf/s label */ |
965 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
966 | 1000822b | aurel32 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0); |
967 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
968 | fdf9b3e8 | bellard | return;
|
969 | fdf9b3e8 | bellard | case 0x8900: /* bt label */ |
970 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
971 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, |
972 | fdf9b3e8 | bellard | ctx->pc + 2);
|
973 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
974 | fdf9b3e8 | bellard | return;
|
975 | fdf9b3e8 | bellard | case 0x8d00: /* bt/s label */ |
976 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
977 | 1000822b | aurel32 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1); |
978 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
979 | fdf9b3e8 | bellard | return;
|
980 | fdf9b3e8 | bellard | case 0x8800: /* cmp/eq #imm,R0 */ |
981 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
982 | a4625612 | aurel32 | gen_cmp_imm(TCG_COND_EQ, cpu_T[0], B7_0s);
|
983 | fdf9b3e8 | bellard | return;
|
984 | fdf9b3e8 | bellard | case 0xc400: /* mov.b @(disp,GBR),R0 */ |
985 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
986 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0); |
987 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
988 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
989 | fdf9b3e8 | bellard | return;
|
990 | fdf9b3e8 | bellard | case 0xc500: /* mov.w @(disp,GBR),R0 */ |
991 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
992 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 2); |
993 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
994 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
995 | fdf9b3e8 | bellard | return;
|
996 | fdf9b3e8 | bellard | case 0xc600: /* mov.l @(disp,GBR),R0 */ |
997 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
998 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 4); |
999 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1000 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
1001 | fdf9b3e8 | bellard | return;
|
1002 | fdf9b3e8 | bellard | case 0xc000: /* mov.b R0,@(disp,GBR) */ |
1003 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
1004 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0); |
1005 | 829337a6 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
1006 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
1007 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
1008 | fdf9b3e8 | bellard | return;
|
1009 | fdf9b3e8 | bellard | case 0xc100: /* mov.w R0,@(disp,GBR) */ |
1010 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
1011 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 2); |
1012 | 829337a6 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
1013 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
1014 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
1015 | fdf9b3e8 | bellard | return;
|
1016 | fdf9b3e8 | bellard | case 0xc200: /* mov.l R0,@(disp,GBR) */ |
1017 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
1018 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 4); |
1019 | 829337a6 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
1020 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
1021 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
1022 | fdf9b3e8 | bellard | return;
|
1023 | fdf9b3e8 | bellard | case 0x8000: /* mov.b R0,@(disp,Rn) */ |
1024 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
1025 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]);
|
1026 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0); |
1027 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
1028 | fdf9b3e8 | bellard | return;
|
1029 | fdf9b3e8 | bellard | case 0x8100: /* mov.w R0,@(disp,Rn) */ |
1030 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
1031 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]);
|
1032 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0 * 2); |
1033 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
1034 | fdf9b3e8 | bellard | return;
|
1035 | fdf9b3e8 | bellard | case 0x8400: /* mov.b @(disp,Rn),R0 */ |
1036 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
1037 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0); |
1038 | 8c2cc7ce | ths | gen_op_ldb_T0_T0(ctx); |
1039 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
1040 | fdf9b3e8 | bellard | return;
|
1041 | fdf9b3e8 | bellard | case 0x8500: /* mov.w @(disp,Rn),R0 */ |
1042 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
1043 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0 * 2); |
1044 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
1045 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]); |
1046 | fdf9b3e8 | bellard | return;
|
1047 | fdf9b3e8 | bellard | case 0xc700: /* mova @(disp,PC),R0 */ |
1048 | 1e8864f7 | aurel32 | tcg_gen_movi_i32(cpu_gregs[REG(0)],
|
1049 | 1e8864f7 | aurel32 | ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
1050 | fdf9b3e8 | bellard | return;
|
1051 | fdf9b3e8 | bellard | case 0xcb00: /* or #imm,R0 */ |
1052 | 559dd74d | aurel32 | tcg_gen_ori_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0); |
1053 | fdf9b3e8 | bellard | return;
|
1054 | 24988dc2 | aurel32 | case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
1055 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
1056 | 3a8a44c4 | aurel32 | tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr); |
1057 | 3bf73a49 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_T[1]); |
1058 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
1059 | 559dd74d | aurel32 | tcg_gen_ori_i32(cpu_T[0], cpu_T[0], B7_0); |
1060 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
1061 | fdf9b3e8 | bellard | return;
|
1062 | fdf9b3e8 | bellard | case 0xc300: /* trapa #imm */ |
1063 | e6afc2f4 | aurel32 | CHECK_NOT_DELAY_SLOT |
1064 | e6afc2f4 | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx->pc); |
1065 | e6afc2f4 | aurel32 | tcg_gen_movi_i32(cpu_T[0], B7_0);
|
1066 | e6afc2f4 | aurel32 | tcg_gen_helper_0_1(helper_trapa, cpu_T[0]);
|
1067 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1068 | fdf9b3e8 | bellard | return;
|
1069 | fdf9b3e8 | bellard | case 0xc800: /* tst #imm,R0 */ |
1070 | a4625612 | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(0)], B7_0); |
1071 | a4625612 | aurel32 | gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
1072 | fdf9b3e8 | bellard | return;
|
1073 | 24988dc2 | aurel32 | case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
1074 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
1075 | 3a8a44c4 | aurel32 | tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr); |
1076 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
1077 | a4625612 | aurel32 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0); |
1078 | a4625612 | aurel32 | gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
1079 | fdf9b3e8 | bellard | return;
|
1080 | fdf9b3e8 | bellard | case 0xca00: /* xor #imm,R0 */ |
1081 | 559dd74d | aurel32 | tcg_gen_xori_i32(cpu_gregs[REG(0)], cpu_gregs[REG(0)], B7_0); |
1082 | fdf9b3e8 | bellard | return;
|
1083 | 24988dc2 | aurel32 | case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
1084 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
1085 | 3a8a44c4 | aurel32 | tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr); |
1086 | 829337a6 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
1087 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
1088 | 559dd74d | aurel32 | tcg_gen_xori_i32(cpu_T[0], cpu_T[0], B7_0); |
1089 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
1090 | fdf9b3e8 | bellard | return;
|
1091 | fdf9b3e8 | bellard | } |
1092 | fdf9b3e8 | bellard | |
1093 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf08f) { |
1094 | fdf9b3e8 | bellard | case 0x408e: /* ldc Rm,Rn_BANK */ |
1095 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1096 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[ALTREG(B6_4)], cpu_T[0]);
|
1097 | fdf9b3e8 | bellard | return;
|
1098 | fdf9b3e8 | bellard | case 0x4087: /* ldc.l @Rm+,Rn_BANK */ |
1099 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1100 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1101 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[ALTREG(B6_4)], cpu_T[0]);
|
1102 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
1103 | fdf9b3e8 | bellard | return;
|
1104 | fdf9b3e8 | bellard | case 0x0082: /* stc Rm_BANK,Rn */ |
1105 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]);
|
1106 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
1107 | fdf9b3e8 | bellard | return;
|
1108 | fdf9b3e8 | bellard | case 0x4083: /* stc.l Rm_BANK,@-Rn */ |
1109 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
1110 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
1111 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]);
|
1112 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
1113 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
1114 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
1115 | fdf9b3e8 | bellard | return;
|
1116 | fdf9b3e8 | bellard | } |
1117 | fdf9b3e8 | bellard | |
1118 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf0ff) { |
1119 | fdf9b3e8 | bellard | case 0x0023: /* braf Rn */ |
1120 | 1e8864f7 | aurel32 | CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1121 | 1000822b | aurel32 | tcg_gen_addi_i32(cpu_delayed_pc, cpu_T[0], ctx->pc + 4); |
1122 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1123 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1124 | fdf9b3e8 | bellard | return;
|
1125 | fdf9b3e8 | bellard | case 0x0003: /* bsrf Rn */ |
1126 | 1e8864f7 | aurel32 | CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1127 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
1128 | 1000822b | aurel32 | tcg_gen_add_i32(cpu_delayed_pc, cpu_T[0], cpu_pr);
|
1129 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1130 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1131 | fdf9b3e8 | bellard | return;
|
1132 | fdf9b3e8 | bellard | case 0x4015: /* cmp/pl Rn */ |
1133 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1134 | a4625612 | aurel32 | gen_cmp_imm(TCG_COND_GT, cpu_T[0], 0); |
1135 | fdf9b3e8 | bellard | return;
|
1136 | fdf9b3e8 | bellard | case 0x4011: /* cmp/pz Rn */ |
1137 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1138 | a4625612 | aurel32 | gen_cmp_imm(TCG_COND_GE, cpu_T[0], 0); |
1139 | fdf9b3e8 | bellard | return;
|
1140 | fdf9b3e8 | bellard | case 0x4010: /* dt Rn */ |
1141 | a4625612 | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
|
1142 | a4625612 | aurel32 | gen_cmp_imm(TCG_COND_EQ, cpu_gregs[REG(B11_8)], 0);
|
1143 | fdf9b3e8 | bellard | return;
|
1144 | fdf9b3e8 | bellard | case 0x402b: /* jmp @Rn */ |
1145 | 1e8864f7 | aurel32 | CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1146 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_T[0]);
|
1147 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1148 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1149 | fdf9b3e8 | bellard | return;
|
1150 | fdf9b3e8 | bellard | case 0x400b: /* jsr @Rn */ |
1151 | 1e8864f7 | aurel32 | CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1152 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
1153 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_T[0]);
|
1154 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1155 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1156 | fdf9b3e8 | bellard | return;
|
1157 | fdf9b3e8 | bellard | #define LDST(reg,ldnum,ldpnum,ldop,stnum,stpnum,stop,extrald) \
|
1158 | fdf9b3e8 | bellard | case ldnum: \
|
1159 | 1e8864f7 | aurel32 | tcg_gen_mov_i32 (cpu_T[0], cpu_gregs[REG(B11_8)]); \
|
1160 | fdf9b3e8 | bellard | gen_op_##ldop##_T0_##reg (); \ |
1161 | fdf9b3e8 | bellard | extrald \ |
1162 | fdf9b3e8 | bellard | return; \
|
1163 | fdf9b3e8 | bellard | case ldpnum: \
|
1164 | 1e8864f7 | aurel32 | tcg_gen_mov_i32 (cpu_T[0], cpu_gregs[REG(B11_8)]); \
|
1165 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0 (ctx); \ |
1166 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], \ |
1167 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 4); \
|
1168 | fdf9b3e8 | bellard | gen_op_##ldop##_T0_##reg (); \ |
1169 | fdf9b3e8 | bellard | extrald \ |
1170 | fdf9b3e8 | bellard | return; \
|
1171 | fdf9b3e8 | bellard | case stnum: \
|
1172 | 8f99cc6c | aurel32 | gen_op_##stop##_##reg##_T0 (); \ |
1173 | 1e8864f7 | aurel32 | tcg_gen_mov_i32 (cpu_gregs[REG(B11_8)], cpu_T[0]); \
|
1174 | fdf9b3e8 | bellard | return; \
|
1175 | fdf9b3e8 | bellard | case stpnum: \
|
1176 | fdf9b3e8 | bellard | gen_op_##stop##_##reg##_T0 (); \ |
1177 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], \ |
1178 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 4); \
|
1179 | 1e8864f7 | aurel32 | tcg_gen_mov_i32 (cpu_T[1], cpu_gregs[REG(B11_8)]); \
|
1180 | 559dd74d | aurel32 | tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], \ |
1181 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 4); \
|
1182 | fdf9b3e8 | bellard | gen_op_stl_T0_T1 (ctx); \ |
1183 | 559dd74d | aurel32 | tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], \ |
1184 | 559dd74d | aurel32 | cpu_gregs[REG(B11_8)], 4); \
|
1185 | fdf9b3e8 | bellard | return;
|
1186 | 823029f9 | ths | LDST(sr, 0x400e, 0x4007, ldc, 0x0002, 0x4003, stc, ctx->bstate = |
1187 | 823029f9 | ths | BS_STOP;) |
1188 | eda9b09b | bellard | LDST(gbr, 0x401e, 0x4017, ldc, 0x0012, 0x4013, stc,) |
1189 | eda9b09b | bellard | LDST(vbr, 0x402e, 0x4027, ldc, 0x0022, 0x4023, stc,) |
1190 | eda9b09b | bellard | LDST(ssr, 0x403e, 0x4037, ldc, 0x0032, 0x4033, stc,) |
1191 | eda9b09b | bellard | LDST(spc, 0x404e, 0x4047, ldc, 0x0042, 0x4043, stc,) |
1192 | eda9b09b | bellard | LDST(dbr, 0x40fa, 0x40f6, ldc, 0x00fa, 0x40f2, stc,) |
1193 | eda9b09b | bellard | LDST(mach, 0x400a, 0x4006, lds, 0x000a, 0x4002, sts,) |
1194 | eda9b09b | bellard | LDST(macl, 0x401a, 0x4016, lds, 0x001a, 0x4012, sts,) |
1195 | eda9b09b | bellard | LDST(pr, 0x402a, 0x4026, lds, 0x002a, 0x4022, sts,) |
1196 | 8bf5a804 | ths | LDST(fpul, 0x405a, 0x4056, lds, 0x005a, 0x4052, sts,) |
1197 | 823029f9 | ths | LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->bstate = |
1198 | 823029f9 | ths | BS_STOP;) |
1199 | fdf9b3e8 | bellard | case 0x00c3: /* movca.l R0,@Rm */ |
1200 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); |
1201 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
1202 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
1203 | fdf9b3e8 | bellard | return;
|
1204 | fdf9b3e8 | bellard | case 0x0029: /* movt Rn */ |
1205 | 3a8a44c4 | aurel32 | tcg_gen_andi_i32(cpu_gregs[REG(B11_8)], cpu_sr, SR_T); |
1206 | fdf9b3e8 | bellard | return;
|
1207 | fdf9b3e8 | bellard | case 0x0093: /* ocbi @Rn */ |
1208 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1209 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1210 | fdf9b3e8 | bellard | return;
|
1211 | 24988dc2 | aurel32 | case 0x00a3: /* ocbp @Rn */ |
1212 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1213 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1214 | fdf9b3e8 | bellard | return;
|
1215 | fdf9b3e8 | bellard | case 0x00b3: /* ocbwb @Rn */ |
1216 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1217 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1218 | fdf9b3e8 | bellard | return;
|
1219 | fdf9b3e8 | bellard | case 0x0083: /* pref @Rn */ |
1220 | fdf9b3e8 | bellard | return;
|
1221 | fdf9b3e8 | bellard | case 0x4024: /* rotcl Rn */ |
1222 | fdf9b3e8 | bellard | gen_op_rotcl_Rn(REG(B11_8)); |
1223 | fdf9b3e8 | bellard | return;
|
1224 | fdf9b3e8 | bellard | case 0x4025: /* rotcr Rn */ |
1225 | fdf9b3e8 | bellard | gen_op_rotcr_Rn(REG(B11_8)); |
1226 | fdf9b3e8 | bellard | return;
|
1227 | fdf9b3e8 | bellard | case 0x4004: /* rotl Rn */ |
1228 | fdf9b3e8 | bellard | gen_op_rotl_Rn(REG(B11_8)); |
1229 | fdf9b3e8 | bellard | return;
|
1230 | fdf9b3e8 | bellard | case 0x4005: /* rotr Rn */ |
1231 | fdf9b3e8 | bellard | gen_op_rotr_Rn(REG(B11_8)); |
1232 | fdf9b3e8 | bellard | return;
|
1233 | fdf9b3e8 | bellard | case 0x4000: /* shll Rn */ |
1234 | fdf9b3e8 | bellard | case 0x4020: /* shal Rn */ |
1235 | fdf9b3e8 | bellard | gen_op_shal_Rn(REG(B11_8)); |
1236 | fdf9b3e8 | bellard | return;
|
1237 | fdf9b3e8 | bellard | case 0x4021: /* shar Rn */ |
1238 | fdf9b3e8 | bellard | gen_op_shar_Rn(REG(B11_8)); |
1239 | fdf9b3e8 | bellard | return;
|
1240 | fdf9b3e8 | bellard | case 0x4001: /* shlr Rn */ |
1241 | fdf9b3e8 | bellard | gen_op_shlr_Rn(REG(B11_8)); |
1242 | fdf9b3e8 | bellard | return;
|
1243 | fdf9b3e8 | bellard | case 0x4008: /* shll2 Rn */ |
1244 | 559dd74d | aurel32 | tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);
|
1245 | fdf9b3e8 | bellard | return;
|
1246 | fdf9b3e8 | bellard | case 0x4018: /* shll8 Rn */ |
1247 | 559dd74d | aurel32 | tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
1248 | fdf9b3e8 | bellard | return;
|
1249 | fdf9b3e8 | bellard | case 0x4028: /* shll16 Rn */ |
1250 | 559dd74d | aurel32 | tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 16);
|
1251 | fdf9b3e8 | bellard | return;
|
1252 | fdf9b3e8 | bellard | case 0x4009: /* shlr2 Rn */ |
1253 | 559dd74d | aurel32 | tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);
|
1254 | fdf9b3e8 | bellard | return;
|
1255 | fdf9b3e8 | bellard | case 0x4019: /* shlr8 Rn */ |
1256 | 559dd74d | aurel32 | tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 8);
|
1257 | fdf9b3e8 | bellard | return;
|
1258 | fdf9b3e8 | bellard | case 0x4029: /* shlr16 Rn */ |
1259 | 559dd74d | aurel32 | tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 16);
|
1260 | fdf9b3e8 | bellard | return;
|
1261 | fdf9b3e8 | bellard | case 0x401b: /* tas.b @Rn */ |
1262 | 1e8864f7 | aurel32 | tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1263 | 829337a6 | aurel32 | tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); |
1264 | 825c69ce | aurel32 | gen_op_ldub_T0_T0(ctx); |
1265 | a4625612 | aurel32 | gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0); |
1266 | 559dd74d | aurel32 | tcg_gen_ori_i32(cpu_T[0], cpu_T[0], 0x80); |
1267 | 825c69ce | aurel32 | gen_op_stb_T0_T1(ctx); |
1268 | fdf9b3e8 | bellard | return;
|
1269 | e67888a7 | ths | case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
1270 | eda9b09b | bellard | gen_op_movl_fpul_FT0(); |
1271 | eda9b09b | bellard | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1272 | eda9b09b | bellard | return;
|
1273 | e67888a7 | ths | case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
1274 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1275 | eda9b09b | bellard | gen_op_movl_FT0_fpul(); |
1276 | eda9b09b | bellard | return;
|
1277 | e67888a7 | ths | case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
1278 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1279 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1280 | ea6cf6be | ths | break; /* illegal instruction */ |
1281 | ea6cf6be | ths | gen_op_float_DT(); |
1282 | ea6cf6be | ths | gen_op_fmov_DT0_drN(DREG(B11_8)); |
1283 | ea6cf6be | ths | } |
1284 | ea6cf6be | ths | else {
|
1285 | ea6cf6be | ths | gen_op_float_FT(); |
1286 | ea6cf6be | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1287 | ea6cf6be | ths | } |
1288 | ea6cf6be | ths | return;
|
1289 | e67888a7 | ths | case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1290 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1291 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1292 | ea6cf6be | ths | break; /* illegal instruction */ |
1293 | ea6cf6be | ths | gen_op_fmov_drN_DT0(DREG(B11_8)); |
1294 | ea6cf6be | ths | gen_op_ftrc_DT(); |
1295 | ea6cf6be | ths | } |
1296 | ea6cf6be | ths | else {
|
1297 | ea6cf6be | ths | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1298 | ea6cf6be | ths | gen_op_ftrc_FT(); |
1299 | ea6cf6be | ths | } |
1300 | ea6cf6be | ths | return;
|
1301 | 24988dc2 | aurel32 | case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
1302 | 24988dc2 | aurel32 | gen_op_fneg_frN(FREG(B11_8)); |
1303 | 24988dc2 | aurel32 | return;
|
1304 | 24988dc2 | aurel32 | case 0xf05d: /* fabs FRn/DRn */ |
1305 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1306 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1307 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1308 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(DREG(B11_8)); |
1309 | 24988dc2 | aurel32 | gen_op_fabs_DT(); |
1310 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(DREG(B11_8)); |
1311 | 24988dc2 | aurel32 | } else {
|
1312 | 24988dc2 | aurel32 | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1313 | 24988dc2 | aurel32 | gen_op_fabs_FT(); |
1314 | 24988dc2 | aurel32 | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1315 | 24988dc2 | aurel32 | } |
1316 | 24988dc2 | aurel32 | return;
|
1317 | 24988dc2 | aurel32 | case 0xf06d: /* fsqrt FRn */ |
1318 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1319 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1320 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1321 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(FREG(B11_8)); |
1322 | 24988dc2 | aurel32 | gen_op_fsqrt_DT(); |
1323 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(FREG(B11_8)); |
1324 | 24988dc2 | aurel32 | } else {
|
1325 | 24988dc2 | aurel32 | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1326 | 24988dc2 | aurel32 | gen_op_fsqrt_FT(); |
1327 | 24988dc2 | aurel32 | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1328 | 24988dc2 | aurel32 | } |
1329 | 24988dc2 | aurel32 | return;
|
1330 | 24988dc2 | aurel32 | case 0xf07d: /* fsrra FRn */ |
1331 | 24988dc2 | aurel32 | break;
|
1332 | e67888a7 | ths | case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
1333 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1334 | 3bf73a49 | aurel32 | tcg_gen_movi_i32(cpu_T[0], 0); |
1335 | ea6cf6be | ths | gen_op_fmov_T0_frN(FREG(B11_8)); |
1336 | ea6cf6be | ths | return;
|
1337 | ea6cf6be | ths | } |
1338 | ea6cf6be | ths | break;
|
1339 | e67888a7 | ths | case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
1340 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1341 | 3bf73a49 | aurel32 | tcg_gen_movi_i32(cpu_T[0], 0x3f800000); |
1342 | ea6cf6be | ths | gen_op_fmov_T0_frN(FREG(B11_8)); |
1343 | ea6cf6be | ths | return;
|
1344 | ea6cf6be | ths | } |
1345 | ea6cf6be | ths | break;
|
1346 | 24988dc2 | aurel32 | case 0xf0ad: /* fcnvsd FPUL,DRn */ |
1347 | 24988dc2 | aurel32 | gen_op_movl_fpul_FT0(); |
1348 | 24988dc2 | aurel32 | gen_op_fcnvsd_FT_DT(); |
1349 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(DREG(B11_8)); |
1350 | 24988dc2 | aurel32 | return;
|
1351 | 24988dc2 | aurel32 | case 0xf0bd: /* fcnvds DRn,FPUL */ |
1352 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(DREG(B11_8)); |
1353 | 24988dc2 | aurel32 | gen_op_fcnvds_DT_FT(); |
1354 | 24988dc2 | aurel32 | gen_op_movl_FT0_fpul(); |
1355 | 24988dc2 | aurel32 | return;
|
1356 | fdf9b3e8 | bellard | } |
1357 | fdf9b3e8 | bellard | |
1358 | fdf9b3e8 | bellard | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
|
1359 | fdf9b3e8 | bellard | ctx->opcode, ctx->pc); |
1360 | e6afc2f4 | aurel32 | tcg_gen_helper_0_0(helper_raise_illegal_instruction); |
1361 | 823029f9 | ths | ctx->bstate = BS_EXCP; |
1362 | 823029f9 | ths | } |
1363 | 823029f9 | ths | |
1364 | 823029f9 | ths | void decode_opc(DisasContext * ctx)
|
1365 | 823029f9 | ths | { |
1366 | 823029f9 | ths | uint32_t old_flags = ctx->flags; |
1367 | 823029f9 | ths | |
1368 | 823029f9 | ths | _decode_opc(ctx); |
1369 | 823029f9 | ths | |
1370 | 823029f9 | ths | if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
1371 | 823029f9 | ths | if (ctx->flags & DELAY_SLOT_CLEARME) {
|
1372 | 1000822b | aurel32 | gen_store_flags(0);
|
1373 | 274a9e70 | aurel32 | } else {
|
1374 | 274a9e70 | aurel32 | /* go out of the delay slot */
|
1375 | 274a9e70 | aurel32 | uint32_t new_flags = ctx->flags; |
1376 | 274a9e70 | aurel32 | new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
1377 | 1000822b | aurel32 | gen_store_flags(new_flags); |
1378 | 823029f9 | ths | } |
1379 | 823029f9 | ths | ctx->flags = 0;
|
1380 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1381 | 823029f9 | ths | if (old_flags & DELAY_SLOT_CONDITIONAL) {
|
1382 | 823029f9 | ths | gen_delayed_conditional_jump(ctx); |
1383 | 823029f9 | ths | } else if (old_flags & DELAY_SLOT) { |
1384 | 823029f9 | ths | gen_jump(ctx); |
1385 | 823029f9 | ths | } |
1386 | 823029f9 | ths | |
1387 | 823029f9 | ths | } |
1388 | 274a9e70 | aurel32 | |
1389 | 274a9e70 | aurel32 | /* go into a delay slot */
|
1390 | 274a9e70 | aurel32 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
|
1391 | 1000822b | aurel32 | gen_store_flags(ctx->flags); |
1392 | fdf9b3e8 | bellard | } |
1393 | fdf9b3e8 | bellard | |
1394 | 2cfc5f17 | ths | static inline void |
1395 | 820e00f2 | ths | gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1396 | 820e00f2 | ths | int search_pc)
|
1397 | fdf9b3e8 | bellard | { |
1398 | fdf9b3e8 | bellard | DisasContext ctx; |
1399 | fdf9b3e8 | bellard | target_ulong pc_start; |
1400 | fdf9b3e8 | bellard | static uint16_t *gen_opc_end;
|
1401 | 355fb23d | pbrook | int i, ii;
|
1402 | 2e70f6ef | pbrook | int num_insns;
|
1403 | 2e70f6ef | pbrook | int max_insns;
|
1404 | fdf9b3e8 | bellard | |
1405 | fdf9b3e8 | bellard | pc_start = tb->pc; |
1406 | fdf9b3e8 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
1407 | fdf9b3e8 | bellard | ctx.pc = pc_start; |
1408 | 823029f9 | ths | ctx.flags = (uint32_t)tb->flags; |
1409 | 823029f9 | ths | ctx.bstate = BS_NONE; |
1410 | fdf9b3e8 | bellard | ctx.sr = env->sr; |
1411 | eda9b09b | bellard | ctx.fpscr = env->fpscr; |
1412 | fdf9b3e8 | bellard | ctx.memidx = (env->sr & SR_MD) ? 1 : 0; |
1413 | 9854bc46 | pbrook | /* We don't know if the delayed pc came from a dynamic or static branch,
|
1414 | 9854bc46 | pbrook | so assume it is a dynamic branch. */
|
1415 | 823029f9 | ths | ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |
1416 | fdf9b3e8 | bellard | ctx.tb = tb; |
1417 | fdf9b3e8 | bellard | ctx.singlestep_enabled = env->singlestep_enabled; |
1418 | fdf9b3e8 | bellard | |
1419 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
1420 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_CPU) {
|
1421 | fdf9b3e8 | bellard | fprintf(logfile, |
1422 | fdf9b3e8 | bellard | "------------------------------------------------\n");
|
1423 | fdf9b3e8 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
1424 | fdf9b3e8 | bellard | } |
1425 | fdf9b3e8 | bellard | #endif
|
1426 | fdf9b3e8 | bellard | |
1427 | 355fb23d | pbrook | ii = -1;
|
1428 | 2e70f6ef | pbrook | num_insns = 0;
|
1429 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
1430 | 2e70f6ef | pbrook | if (max_insns == 0) |
1431 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
1432 | 2e70f6ef | pbrook | gen_icount_start(); |
1433 | 823029f9 | ths | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
|
1434 | fdf9b3e8 | bellard | if (env->nb_breakpoints > 0) { |
1435 | fdf9b3e8 | bellard | for (i = 0; i < env->nb_breakpoints; i++) { |
1436 | fdf9b3e8 | bellard | if (ctx.pc == env->breakpoints[i]) {
|
1437 | fdf9b3e8 | bellard | /* We have hit a breakpoint - make sure PC is up-to-date */
|
1438 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
1439 | e6afc2f4 | aurel32 | tcg_gen_helper_0_0(helper_debug); |
1440 | 823029f9 | ths | ctx.bstate = BS_EXCP; |
1441 | fdf9b3e8 | bellard | break;
|
1442 | fdf9b3e8 | bellard | } |
1443 | fdf9b3e8 | bellard | } |
1444 | fdf9b3e8 | bellard | } |
1445 | 355fb23d | pbrook | if (search_pc) {
|
1446 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1447 | 355fb23d | pbrook | if (ii < i) {
|
1448 | 355fb23d | pbrook | ii++; |
1449 | 355fb23d | pbrook | while (ii < i)
|
1450 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1451 | 355fb23d | pbrook | } |
1452 | 355fb23d | pbrook | gen_opc_pc[ii] = ctx.pc; |
1453 | 823029f9 | ths | gen_opc_hflags[ii] = ctx.flags; |
1454 | 355fb23d | pbrook | gen_opc_instr_start[ii] = 1;
|
1455 | 2e70f6ef | pbrook | gen_opc_icount[ii] = num_insns; |
1456 | 355fb23d | pbrook | } |
1457 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1458 | 2e70f6ef | pbrook | gen_io_start(); |
1459 | fdf9b3e8 | bellard | #if 0
|
1460 | fdf9b3e8 | bellard | fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
|
1461 | fdf9b3e8 | bellard | fflush(stderr);
|
1462 | fdf9b3e8 | bellard | #endif
|
1463 | fdf9b3e8 | bellard | ctx.opcode = lduw_code(ctx.pc); |
1464 | fdf9b3e8 | bellard | decode_opc(&ctx); |
1465 | 2e70f6ef | pbrook | num_insns++; |
1466 | fdf9b3e8 | bellard | ctx.pc += 2;
|
1467 | fdf9b3e8 | bellard | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
1468 | fdf9b3e8 | bellard | break;
|
1469 | fdf9b3e8 | bellard | if (env->singlestep_enabled)
|
1470 | fdf9b3e8 | bellard | break;
|
1471 | 2e70f6ef | pbrook | if (num_insns >= max_insns)
|
1472 | 2e70f6ef | pbrook | break;
|
1473 | fdf9b3e8 | bellard | #ifdef SH4_SINGLE_STEP
|
1474 | fdf9b3e8 | bellard | break;
|
1475 | fdf9b3e8 | bellard | #endif
|
1476 | fdf9b3e8 | bellard | } |
1477 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
1478 | 2e70f6ef | pbrook | gen_io_end(); |
1479 | fdf9b3e8 | bellard | if (env->singlestep_enabled) {
|
1480 | e6afc2f4 | aurel32 | tcg_gen_helper_0_0(helper_debug); |
1481 | 823029f9 | ths | } else {
|
1482 | 823029f9 | ths | switch (ctx.bstate) {
|
1483 | 823029f9 | ths | case BS_STOP:
|
1484 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
1485 | 823029f9 | ths | /* fall through */
|
1486 | 823029f9 | ths | case BS_NONE:
|
1487 | 823029f9 | ths | if (ctx.flags) {
|
1488 | 1000822b | aurel32 | gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME); |
1489 | 823029f9 | ths | } |
1490 | 823029f9 | ths | gen_goto_tb(&ctx, 0, ctx.pc);
|
1491 | 823029f9 | ths | break;
|
1492 | 823029f9 | ths | case BS_EXCP:
|
1493 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
1494 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
1495 | 823029f9 | ths | break;
|
1496 | 823029f9 | ths | case BS_BRANCH:
|
1497 | 823029f9 | ths | default:
|
1498 | 823029f9 | ths | break;
|
1499 | 823029f9 | ths | } |
1500 | fdf9b3e8 | bellard | } |
1501 | 823029f9 | ths | |
1502 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
1503 | fdf9b3e8 | bellard | *gen_opc_ptr = INDEX_op_end; |
1504 | 355fb23d | pbrook | if (search_pc) {
|
1505 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1506 | 355fb23d | pbrook | ii++; |
1507 | 355fb23d | pbrook | while (ii <= i)
|
1508 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1509 | 355fb23d | pbrook | } else {
|
1510 | 355fb23d | pbrook | tb->size = ctx.pc - pc_start; |
1511 | 2e70f6ef | pbrook | tb->icount = num_insns; |
1512 | 355fb23d | pbrook | } |
1513 | fdf9b3e8 | bellard | |
1514 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
1515 | fdf9b3e8 | bellard | #ifdef SH4_DEBUG_DISAS
|
1516 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM)
|
1517 | fdf9b3e8 | bellard | fprintf(logfile, "\n");
|
1518 | fdf9b3e8 | bellard | #endif
|
1519 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
1520 | fdf9b3e8 | bellard | fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */ |
1521 | fdf9b3e8 | bellard | target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
|
1522 | fdf9b3e8 | bellard | fprintf(logfile, "\n");
|
1523 | fdf9b3e8 | bellard | } |
1524 | fdf9b3e8 | bellard | #endif
|
1525 | fdf9b3e8 | bellard | } |
1526 | fdf9b3e8 | bellard | |
1527 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
1528 | fdf9b3e8 | bellard | { |
1529 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
1530 | fdf9b3e8 | bellard | } |
1531 | fdf9b3e8 | bellard | |
1532 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
1533 | fdf9b3e8 | bellard | { |
1534 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
1535 | fdf9b3e8 | bellard | } |
1536 | d2856f1a | aurel32 | |
1537 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
1538 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
1539 | d2856f1a | aurel32 | { |
1540 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
1541 | d2856f1a | aurel32 | env->flags = gen_opc_hflags[pc_pos]; |
1542 | d2856f1a | aurel32 | } |