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1	7a3f1944	bellard	/*
2	7a3f1944	bellard	SPARC translation
3	7a3f1944	bellard
4	7a3f1944	bellard	Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5	3475187d	bellard	Copyright (C) 2003-2005 Fabrice Bellard
6	7a3f1944	bellard
7	7a3f1944	bellard	This library is free software; you can redistribute it and/or
8	7a3f1944	bellard	modify it under the terms of the GNU Lesser General Public
9	7a3f1944	bellard	License as published by the Free Software Foundation; either
10	7a3f1944	bellard	version 2 of the License, or (at your option) any later version.
11	7a3f1944	bellard
12	7a3f1944	bellard	This library is distributed in the hope that it will be useful,
13	7a3f1944	bellard	but WITHOUT ANY WARRANTY; without even the implied warranty of
14	7a3f1944	bellard	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15	7a3f1944	bellard	Lesser General Public License for more details.
16	7a3f1944	bellard
17	7a3f1944	bellard	You should have received a copy of the GNU Lesser General Public
18	7a3f1944	bellard	License along with this library; if not, write to the Free Software
19	7a3f1944	bellard	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20	7a3f1944	bellard	*/
21	7a3f1944	bellard
22	7a3f1944	bellard	#include <stdarg.h>
23	7a3f1944	bellard	#include <stdlib.h>
24	7a3f1944	bellard	#include <stdio.h>
25	7a3f1944	bellard	#include <string.h>
26	7a3f1944	bellard	#include <inttypes.h>
27	7a3f1944	bellard
28	7a3f1944	bellard	#include "cpu.h"
29	7a3f1944	bellard	#include "exec-all.h"
30	7a3f1944	bellard	#include "disas.h"
31	1a2fb1c0	blueswir1	#include "helper.h"
32	57fec1fe	bellard	#include "tcg-op.h"
33	7a3f1944	bellard
34	7a3f1944	bellard	#define DEBUG_DISAS
35	7a3f1944	bellard
36	72cbca10	bellard	#define DYNAMIC_PC 1 /* dynamic pc value */
37	72cbca10	bellard	#define JUMP_PC 2 /* dynamic pc value which takes only two values
38	72cbca10	bellard	according to jump_pc[T2] */
39	72cbca10	bellard
40	1a2fb1c0	blueswir1	/* global register indexes */
41	d987963a	blueswir1	static TCGv cpu_env, cpu_regwptr;
42	77f193da	blueswir1	static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
43	48d5c82b	blueswir1	static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
44	6ae20372	blueswir1	static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
45	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
46	dc99a3f2	blueswir1	static TCGv cpu_xcc;
47	dc99a3f2	blueswir1	#endif
48	1a2fb1c0	blueswir1	/* local register indexes (only used inside old micro ops) */
49	8911f501	blueswir1	static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
50	1a2fb1c0	blueswir1
51	2e70f6ef	pbrook	#include "gen-icount.h"
52	2e70f6ef	pbrook
53	7a3f1944	bellard	typedef struct DisasContext {
54	0f8a249a	blueswir1	target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
55	0f8a249a	blueswir1	target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
56	72cbca10	bellard	target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
57	cf495bcf	bellard	int is_br;
58	e8af50a3	bellard	int mem_idx;
59	a80dde08	bellard	int fpu_enabled;
60	2cade6a3	blueswir1	int address_mask_32bit;
61	cf495bcf	bellard	struct TranslationBlock *tb;
62	5578ceab	blueswir1	sparc_def_t *def;
63	7a3f1944	bellard	} DisasContext;
64	7a3f1944	bellard
65	3475187d	bellard	// This function uses non-native bit order
66	7a3f1944	bellard	#define GET_FIELD(X, FROM, TO) \
67	7a3f1944	bellard	((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
68	7a3f1944	bellard
69	3475187d	bellard	// This function uses the order in the manuals, i.e. bit 0 is 2^0
70	3475187d	bellard	#define GET_FIELD_SP(X, FROM, TO) \
71	3475187d	bellard	GET_FIELD(X, 31 - (TO), 31 - (FROM))
72	3475187d	bellard
73	3475187d	bellard	#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
74	46d38ba8	blueswir1	#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
75	3475187d	bellard
76	3475187d	bellard	#ifdef TARGET_SPARC64
77	19f329ad	blueswir1	#define FFPREG(r) (r)
78	0387d928	blueswir1	#define DFPREG(r) (((r & 1) << 5) \| (r & 0x1e))
79	1f587329	blueswir1	#define QFPREG(r) (((r & 1) << 5) \| (r & 0x1c))
80	3475187d	bellard	#else
81	19f329ad	blueswir1	#define FFPREG(r) (r)
82	c185970a	blueswir1	#define DFPREG(r) (r & 0x1e)
83	1f587329	blueswir1	#define QFPREG(r) (r & 0x1c)
84	3475187d	bellard	#endif
85	3475187d	bellard
86	3475187d	bellard	static int sign_extend(int x, int len)
87	3475187d	bellard	{
88	3475187d	bellard	len = 32 - len;
89	3475187d	bellard	return (x << len) >> len;
90	3475187d	bellard	}
91	3475187d	bellard
92	7a3f1944	bellard	#define IS_IMM (insn & (1<<13))
93	7a3f1944	bellard
94	ff07ec83	blueswir1	/* floating point registers moves */
95	ff07ec83	blueswir1	static void gen_op_load_fpr_FT0(unsigned int src)
96	ff07ec83	blueswir1	{
97	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
98	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
99	3475187d	bellard	}
100	ff07ec83	blueswir1
101	ff07ec83	blueswir1	static void gen_op_load_fpr_FT1(unsigned int src)
102	ff07ec83	blueswir1	{
103	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
104	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
105	e8af50a3	bellard	}
106	e8af50a3	bellard
107	ff07ec83	blueswir1	static void gen_op_store_FT0_fpr(unsigned int dst)
108	ff07ec83	blueswir1	{
109	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
110	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
111	ff07ec83	blueswir1	}
112	ff07ec83	blueswir1
113	ff07ec83	blueswir1	static void gen_op_load_fpr_DT0(unsigned int src)
114	ff07ec83	blueswir1	{
115	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
116	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
117	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
118	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
119	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
120	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
121	ff07ec83	blueswir1	}
122	ff07ec83	blueswir1
123	ff07ec83	blueswir1	static void gen_op_load_fpr_DT1(unsigned int src)
124	ff07ec83	blueswir1	{
125	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
126	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
127	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
128	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
129	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
130	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
131	ff07ec83	blueswir1	}
132	ff07ec83	blueswir1
133	ff07ec83	blueswir1	static void gen_op_store_DT0_fpr(unsigned int dst)
134	ff07ec83	blueswir1	{
135	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
136	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
137	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
138	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
139	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
140	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
141	ff07ec83	blueswir1	}
142	ff07ec83	blueswir1
143	ff07ec83	blueswir1	static void gen_op_load_fpr_QT0(unsigned int src)
144	ff07ec83	blueswir1	{
145	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
146	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
147	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
148	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
149	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
150	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
151	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
152	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
153	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
154	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
155	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
156	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
157	ff07ec83	blueswir1	}
158	ff07ec83	blueswir1
159	ff07ec83	blueswir1	static void gen_op_load_fpr_QT1(unsigned int src)
160	ff07ec83	blueswir1	{
161	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
162	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
163	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
164	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
165	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
166	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
167	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
168	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
169	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
170	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
171	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
172	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
173	ff07ec83	blueswir1	}
174	ff07ec83	blueswir1
175	ff07ec83	blueswir1	static void gen_op_store_QT0_fpr(unsigned int dst)
176	ff07ec83	blueswir1	{
177	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
178	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
179	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
180	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
181	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
182	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
183	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
184	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
185	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
186	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
187	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
188	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
189	ff07ec83	blueswir1	}
190	1f587329	blueswir1
191	81ad8ba2	blueswir1	/* moves */
192	81ad8ba2	blueswir1	#ifdef CONFIG_USER_ONLY
193	3475187d	bellard	#define supervisor(dc) 0
194	81ad8ba2	blueswir1	#ifdef TARGET_SPARC64
195	e9ebed4d	blueswir1	#define hypervisor(dc) 0
196	81ad8ba2	blueswir1	#endif
197	3475187d	bellard	#else
198	6f27aba6	blueswir1	#define supervisor(dc) (dc->mem_idx >= 1)
199	81ad8ba2	blueswir1	#ifdef TARGET_SPARC64
200	81ad8ba2	blueswir1	#define hypervisor(dc) (dc->mem_idx == 2)
201	6f27aba6	blueswir1	#else
202	3475187d	bellard	#endif
203	81ad8ba2	blueswir1	#endif
204	81ad8ba2	blueswir1
205	2cade6a3	blueswir1	#ifdef TARGET_SPARC64
206	2cade6a3	blueswir1	#ifndef TARGET_ABI32
207	2cade6a3	blueswir1	#define AM_CHECK(dc) ((dc)->address_mask_32bit)
208	1a2fb1c0	blueswir1	#else
209	2cade6a3	blueswir1	#define AM_CHECK(dc) (1)
210	2cade6a3	blueswir1	#endif
211	1a2fb1c0	blueswir1	#endif
212	3391c818	blueswir1
213	2cade6a3	blueswir1	static inline void gen_address_mask(DisasContext *dc, TCGv addr)
214	2cade6a3	blueswir1	{
215	2cade6a3	blueswir1	#ifdef TARGET_SPARC64
216	2cade6a3	blueswir1	if (AM_CHECK(dc))
217	2cade6a3	blueswir1	tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
218	2cade6a3	blueswir1	#endif
219	2cade6a3	blueswir1	}
220	2cade6a3	blueswir1
221	1a2fb1c0	blueswir1	static inline void gen_movl_reg_TN(int reg, TCGv tn)
222	81ad8ba2	blueswir1	{
223	1a2fb1c0	blueswir1	if (reg == 0)
224	1a2fb1c0	blueswir1	tcg_gen_movi_tl(tn, 0);
225	1a2fb1c0	blueswir1	else if (reg < 8)
226	f5069b26	blueswir1	tcg_gen_mov_tl(tn, cpu_gregs[reg]);
227	1a2fb1c0	blueswir1	else {
228	1a2fb1c0	blueswir1	tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
229	81ad8ba2	blueswir1	}
230	81ad8ba2	blueswir1	}
231	81ad8ba2	blueswir1
232	1a2fb1c0	blueswir1	static inline void gen_movl_TN_reg(int reg, TCGv tn)
233	81ad8ba2	blueswir1	{
234	1a2fb1c0	blueswir1	if (reg == 0)
235	1a2fb1c0	blueswir1	return;
236	1a2fb1c0	blueswir1	else if (reg < 8)
237	f5069b26	blueswir1	tcg_gen_mov_tl(cpu_gregs[reg], tn);
238	1a2fb1c0	blueswir1	else {
239	1a2fb1c0	blueswir1	tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
240	81ad8ba2	blueswir1	}
241	81ad8ba2	blueswir1	}
242	81ad8ba2	blueswir1
243	5fafdf24	ths	static inline void gen_goto_tb(DisasContext *s, int tb_num,
244	6e256c93	bellard	target_ulong pc, target_ulong npc)
245	6e256c93	bellard	{
246	6e256c93	bellard	TranslationBlock *tb;
247	6e256c93	bellard
248	6e256c93	bellard	tb = s->tb;
249	6e256c93	bellard	if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
250	6e256c93	bellard	(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
251	6e256c93	bellard	/* jump to same page: we can use a direct jump */
252	57fec1fe	bellard	tcg_gen_goto_tb(tb_num);
253	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, pc);
254	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc);
255	57fec1fe	bellard	tcg_gen_exit_tb((long)tb + tb_num);
256	6e256c93	bellard	} else {
257	6e256c93	bellard	/* jump to another page: currently not optimized */
258	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, pc);
259	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc);
260	57fec1fe	bellard	tcg_gen_exit_tb(0);
261	6e256c93	bellard	}
262	6e256c93	bellard	}
263	6e256c93	bellard
264	19f329ad	blueswir1	// XXX suboptimal
265	19f329ad	blueswir1	static inline void gen_mov_reg_N(TCGv reg, TCGv src)
266	19f329ad	blueswir1	{
267	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
268	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
269	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
270	19f329ad	blueswir1	}
271	19f329ad	blueswir1
272	19f329ad	blueswir1	static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
273	19f329ad	blueswir1	{
274	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
275	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
276	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
277	19f329ad	blueswir1	}
278	19f329ad	blueswir1
279	19f329ad	blueswir1	static inline void gen_mov_reg_V(TCGv reg, TCGv src)
280	19f329ad	blueswir1	{
281	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
282	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
283	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
284	19f329ad	blueswir1	}
285	19f329ad	blueswir1
286	19f329ad	blueswir1	static inline void gen_mov_reg_C(TCGv reg, TCGv src)
287	19f329ad	blueswir1	{
288	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
289	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
290	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
291	19f329ad	blueswir1	}
292	19f329ad	blueswir1
293	ce5b3c3d	blueswir1	static inline void gen_cc_clear_icc(void)
294	dc99a3f2	blueswir1	{
295	dc99a3f2	blueswir1	tcg_gen_movi_i32(cpu_psr, 0);
296	ce5b3c3d	blueswir1	}
297	ce5b3c3d	blueswir1
298	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
299	ce5b3c3d	blueswir1	static inline void gen_cc_clear_xcc(void)
300	ce5b3c3d	blueswir1	{
301	dc99a3f2	blueswir1	tcg_gen_movi_i32(cpu_xcc, 0);
302	dc99a3f2	blueswir1	}
303	ce5b3c3d	blueswir1	#endif
304	dc99a3f2	blueswir1
305	dc99a3f2	blueswir1	/* old op:
306	dc99a3f2	blueswir1	if (!T0)
307	dc99a3f2	blueswir1	env->psr \|= PSR_ZERO;
308	dc99a3f2	blueswir1	if ((int32_t) T0 < 0)
309	dc99a3f2	blueswir1	env->psr \|= PSR_NEG;
310	dc99a3f2	blueswir1	*/
311	ce5b3c3d	blueswir1	static inline void gen_cc_NZ_icc(TCGv dst)
312	dc99a3f2	blueswir1	{
313	8911f501	blueswir1	TCGv r_temp;
314	dc99a3f2	blueswir1	int l1, l2;
315	dc99a3f2	blueswir1
316	dc99a3f2	blueswir1	l1 = gen_new_label();
317	dc99a3f2	blueswir1	l2 = gen_new_label();
318	8911f501	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
319	8911f501	blueswir1	tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
320	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
321	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
322	dc99a3f2	blueswir1	gen_set_label(l1);
323	bdf46ea2	blueswir1	tcg_gen_ext_i32_tl(r_temp, dst);
324	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
325	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
326	dc99a3f2	blueswir1	gen_set_label(l2);
327	2ea815ca	blueswir1	tcg_temp_free(r_temp);
328	ce5b3c3d	blueswir1	}
329	ce5b3c3d	blueswir1
330	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
331	ce5b3c3d	blueswir1	static inline void gen_cc_NZ_xcc(TCGv dst)
332	ce5b3c3d	blueswir1	{
333	ce5b3c3d	blueswir1	int l1, l2;
334	ce5b3c3d	blueswir1
335	ce5b3c3d	blueswir1	l1 = gen_new_label();
336	ce5b3c3d	blueswir1	l2 = gen_new_label();
337	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
338	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
339	ce5b3c3d	blueswir1	gen_set_label(l1);
340	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
341	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
342	ce5b3c3d	blueswir1	gen_set_label(l2);
343	dc99a3f2	blueswir1	}
344	ce5b3c3d	blueswir1	#endif
345	dc99a3f2	blueswir1
346	dc99a3f2	blueswir1	/* old op:
347	dc99a3f2	blueswir1	if (T0 < src1)
348	dc99a3f2	blueswir1	env->psr \|= PSR_CARRY;
349	dc99a3f2	blueswir1	*/
350	ce5b3c3d	blueswir1	static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
351	dc99a3f2	blueswir1	{
352	2ae72bce	blueswir1	TCGv r_temp1, r_temp2;
353	dc99a3f2	blueswir1	int l1;
354	dc99a3f2	blueswir1
355	dc99a3f2	blueswir1	l1 = gen_new_label();
356	2ae72bce	blueswir1	r_temp1 = tcg_temp_new(TCG_TYPE_TL);
357	2ae72bce	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_TL);
358	2ae72bce	blueswir1	tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
359	2ae72bce	blueswir1	tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
360	2ae72bce	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
361	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
362	dc99a3f2	blueswir1	gen_set_label(l1);
363	2ae72bce	blueswir1	tcg_temp_free(r_temp1);
364	2ae72bce	blueswir1	tcg_temp_free(r_temp2);
365	ce5b3c3d	blueswir1	}
366	ce5b3c3d	blueswir1
367	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
368	ce5b3c3d	blueswir1	static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
369	ce5b3c3d	blueswir1	{
370	ce5b3c3d	blueswir1	int l1;
371	dc99a3f2	blueswir1
372	ce5b3c3d	blueswir1	l1 = gen_new_label();
373	ce5b3c3d	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
374	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
375	ce5b3c3d	blueswir1	gen_set_label(l1);
376	dc99a3f2	blueswir1	}
377	ce5b3c3d	blueswir1	#endif
378	dc99a3f2	blueswir1
379	dc99a3f2	blueswir1	/* old op:
380	dc99a3f2	blueswir1	if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
381	dc99a3f2	blueswir1	env->psr \|= PSR_OVF;
382	dc99a3f2	blueswir1	*/
383	ce5b3c3d	blueswir1	static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
384	dc99a3f2	blueswir1	{
385	0425bee5	blueswir1	TCGv r_temp;
386	dc99a3f2	blueswir1
387	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
388	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
389	dc99a3f2	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
390	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
391	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
392	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
393	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
394	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
395	2ea815ca	blueswir1	tcg_temp_free(r_temp);
396	653ccb80	blueswir1	tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
397	ce5b3c3d	blueswir1	}
398	ce5b3c3d	blueswir1
399	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
400	ce5b3c3d	blueswir1	static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
401	ce5b3c3d	blueswir1	{
402	ce5b3c3d	blueswir1	TCGv r_temp;
403	ce5b3c3d	blueswir1
404	ce5b3c3d	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
405	ce5b3c3d	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
406	ce5b3c3d	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
407	ce5b3c3d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
408	ce5b3c3d	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
409	ce5b3c3d	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
410	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
411	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
412	2ea815ca	blueswir1	tcg_temp_free(r_temp);
413	653ccb80	blueswir1	tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
414	dc99a3f2	blueswir1	}
415	ce5b3c3d	blueswir1	#endif
416	dc99a3f2	blueswir1
417	dc99a3f2	blueswir1	static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
418	dc99a3f2	blueswir1	{
419	2ea815ca	blueswir1	TCGv r_temp, r_const;
420	dc99a3f2	blueswir1	int l1;
421	dc99a3f2	blueswir1
422	dc99a3f2	blueswir1	l1 = gen_new_label();
423	dc99a3f2	blueswir1
424	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
425	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
426	dc99a3f2	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
427	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
428	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
429	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
430	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
431	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
432	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
433	2ea815ca	blueswir1	tcg_temp_free(r_const);
434	dc99a3f2	blueswir1	gen_set_label(l1);
435	2ea815ca	blueswir1	tcg_temp_free(r_temp);
436	dc99a3f2	blueswir1	}
437	dc99a3f2	blueswir1
438	dc99a3f2	blueswir1	static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
439	dc99a3f2	blueswir1	{
440	dc99a3f2	blueswir1	int l1;
441	dc99a3f2	blueswir1
442	dc99a3f2	blueswir1	l1 = gen_new_label();
443	0425bee5	blueswir1	tcg_gen_or_tl(cpu_tmp0, src1, src2);
444	0425bee5	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
445	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
446	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
447	dc99a3f2	blueswir1	gen_set_label(l1);
448	dc99a3f2	blueswir1	}
449	dc99a3f2	blueswir1
450	dc99a3f2	blueswir1	static inline void gen_tag_tv(TCGv src1, TCGv src2)
451	dc99a3f2	blueswir1	{
452	dc99a3f2	blueswir1	int l1;
453	2ea815ca	blueswir1	TCGv r_const;
454	dc99a3f2	blueswir1
455	dc99a3f2	blueswir1	l1 = gen_new_label();
456	0425bee5	blueswir1	tcg_gen_or_tl(cpu_tmp0, src1, src2);
457	0425bee5	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
458	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
459	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
460	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
461	2ea815ca	blueswir1	tcg_temp_free(r_const);
462	dc99a3f2	blueswir1	gen_set_label(l1);
463	dc99a3f2	blueswir1	}
464	dc99a3f2	blueswir1
465	4af984a7	blueswir1	static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
466	dc99a3f2	blueswir1	{
467	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
468	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
469	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
470	ce5b3c3d	blueswir1	gen_cc_clear_icc();
471	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
472	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
473	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
474	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
475	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
476	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
477	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
478	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
479	ce5b3c3d	blueswir1	#endif
480	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
481	dc99a3f2	blueswir1	}
482	dc99a3f2	blueswir1
483	4af984a7	blueswir1	static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
484	dc99a3f2	blueswir1	{
485	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
486	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
487	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
488	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
489	ce5b3c3d	blueswir1	gen_cc_clear_icc();
490	5c6a0628	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
491	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
492	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
493	5c6a0628	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
494	ce5b3c3d	blueswir1	#endif
495	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
496	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
497	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
498	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
499	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
500	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
501	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
502	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
503	ce5b3c3d	blueswir1	#endif
504	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
505	dc99a3f2	blueswir1	}
506	dc99a3f2	blueswir1
507	4af984a7	blueswir1	static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
508	dc99a3f2	blueswir1	{
509	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
510	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
511	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
512	ce5b3c3d	blueswir1	gen_cc_clear_icc();
513	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
514	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
515	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
516	6f551262	blueswir1	gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
517	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
518	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
519	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
520	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
521	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
522	ce5b3c3d	blueswir1	#endif
523	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
524	dc99a3f2	blueswir1	}
525	dc99a3f2	blueswir1
526	4af984a7	blueswir1	static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
527	dc99a3f2	blueswir1	{
528	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
529	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
530	6f551262	blueswir1	gen_tag_tv(cpu_cc_src, cpu_cc_src2);
531	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
532	5c6a0628	blueswir1	gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
533	ce5b3c3d	blueswir1	gen_cc_clear_icc();
534	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
535	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
536	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
537	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
538	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
539	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
540	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
541	ce5b3c3d	blueswir1	#endif
542	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
543	dc99a3f2	blueswir1	}
544	dc99a3f2	blueswir1
545	dc99a3f2	blueswir1	/* old op:
546	dc99a3f2	blueswir1	if (src1 < T1)
547	dc99a3f2	blueswir1	env->psr \|= PSR_CARRY;
548	dc99a3f2	blueswir1	*/
549	ce5b3c3d	blueswir1	static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
550	dc99a3f2	blueswir1	{
551	8911f501	blueswir1	TCGv r_temp1, r_temp2;
552	dc99a3f2	blueswir1	int l1;
553	dc99a3f2	blueswir1
554	dc99a3f2	blueswir1	l1 = gen_new_label();
555	8911f501	blueswir1	r_temp1 = tcg_temp_new(TCG_TYPE_TL);
556	8911f501	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_TL);
557	8911f501	blueswir1	tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
558	8911f501	blueswir1	tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
559	8911f501	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
560	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
561	dc99a3f2	blueswir1	gen_set_label(l1);
562	2ea815ca	blueswir1	tcg_temp_free(r_temp1);
563	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
564	ce5b3c3d	blueswir1	}
565	ce5b3c3d	blueswir1
566	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
567	ce5b3c3d	blueswir1	static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
568	ce5b3c3d	blueswir1	{
569	ce5b3c3d	blueswir1	int l1;
570	dc99a3f2	blueswir1
571	ce5b3c3d	blueswir1	l1 = gen_new_label();
572	ce5b3c3d	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
573	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
574	ce5b3c3d	blueswir1	gen_set_label(l1);
575	dc99a3f2	blueswir1	}
576	ce5b3c3d	blueswir1	#endif
577	dc99a3f2	blueswir1
578	dc99a3f2	blueswir1	/* old op:
579	dc99a3f2	blueswir1	if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
580	dc99a3f2	blueswir1	env->psr \|= PSR_OVF;
581	dc99a3f2	blueswir1	*/
582	ce5b3c3d	blueswir1	static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
583	dc99a3f2	blueswir1	{
584	0425bee5	blueswir1	TCGv r_temp;
585	dc99a3f2	blueswir1
586	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
587	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
588	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
589	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
590	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
591	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
592	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
593	653ccb80	blueswir1	tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
594	2ea815ca	blueswir1	tcg_temp_free(r_temp);
595	ce5b3c3d	blueswir1	}
596	ce5b3c3d	blueswir1
597	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
598	ce5b3c3d	blueswir1	static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
599	ce5b3c3d	blueswir1	{
600	ce5b3c3d	blueswir1	TCGv r_temp;
601	ce5b3c3d	blueswir1
602	ce5b3c3d	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
603	ce5b3c3d	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
604	ce5b3c3d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
605	ce5b3c3d	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
606	ce5b3c3d	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
607	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
608	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
609	653ccb80	blueswir1	tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
610	2ea815ca	blueswir1	tcg_temp_free(r_temp);
611	dc99a3f2	blueswir1	}
612	ce5b3c3d	blueswir1	#endif
613	dc99a3f2	blueswir1
614	dc99a3f2	blueswir1	static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
615	dc99a3f2	blueswir1	{
616	2ea815ca	blueswir1	TCGv r_temp, r_const;
617	dc99a3f2	blueswir1	int l1;
618	dc99a3f2	blueswir1
619	dc99a3f2	blueswir1	l1 = gen_new_label();
620	dc99a3f2	blueswir1
621	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
622	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
623	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
624	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
625	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
626	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
627	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
628	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
629	2ea815ca	blueswir1	tcg_temp_free(r_const);
630	dc99a3f2	blueswir1	gen_set_label(l1);
631	2ea815ca	blueswir1	tcg_temp_free(r_temp);
632	dc99a3f2	blueswir1	}
633	dc99a3f2	blueswir1
634	4af984a7	blueswir1	static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
635	dc99a3f2	blueswir1	{
636	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
637	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
638	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
639	ce5b3c3d	blueswir1	gen_cc_clear_icc();
640	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
641	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
642	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
643	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
644	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
645	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
646	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
647	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
648	ce5b3c3d	blueswir1	#endif
649	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
650	dc99a3f2	blueswir1	}
651	dc99a3f2	blueswir1
652	4af984a7	blueswir1	static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
653	dc99a3f2	blueswir1	{
654	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
655	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
656	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
657	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
658	ce5b3c3d	blueswir1	gen_cc_clear_icc();
659	5c6a0628	blueswir1	gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
660	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
661	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
662	5c6a0628	blueswir1	gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
663	ce5b3c3d	blueswir1	#endif
664	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
665	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
666	ba28189b	blueswir1	gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
667	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
668	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
669	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
670	ba28189b	blueswir1	gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
671	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
672	ce5b3c3d	blueswir1	#endif
673	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
674	dc99a3f2	blueswir1	}
675	dc99a3f2	blueswir1
676	4af984a7	blueswir1	static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
677	dc99a3f2	blueswir1	{
678	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
679	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
680	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
681	ce5b3c3d	blueswir1	gen_cc_clear_icc();
682	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
683	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
684	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
685	6f551262	blueswir1	gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
686	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
687	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
688	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
689	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
690	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
691	ce5b3c3d	blueswir1	#endif
692	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
693	dc99a3f2	blueswir1	}
694	dc99a3f2	blueswir1
695	4af984a7	blueswir1	static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
696	dc99a3f2	blueswir1	{
697	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
698	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
699	6f551262	blueswir1	gen_tag_tv(cpu_cc_src, cpu_cc_src2);
700	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
701	5c6a0628	blueswir1	gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
702	ce5b3c3d	blueswir1	gen_cc_clear_icc();
703	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
704	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
705	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
706	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
707	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
708	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
709	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
710	ce5b3c3d	blueswir1	#endif
711	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
712	dc99a3f2	blueswir1	}
713	dc99a3f2	blueswir1
714	4af984a7	blueswir1	static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
715	d9bdab86	blueswir1	{
716	7127fe84	blueswir1	TCGv r_temp, r_temp2;
717	6f551262	blueswir1	int l1;
718	d9bdab86	blueswir1
719	d9bdab86	blueswir1	l1 = gen_new_label();
720	d9bdab86	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
721	7127fe84	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I32);
722	d9bdab86	blueswir1
723	d9bdab86	blueswir1	/* old op:
724	d9bdab86	blueswir1	if (!(env->y & 1))
725	d9bdab86	blueswir1	T1 = 0;
726	d9bdab86	blueswir1	*/
727	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
728	7127fe84	blueswir1	tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
729	7127fe84	blueswir1	tcg_gen_trunc_tl_i32(r_temp2, r_temp);
730	7127fe84	blueswir1	tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
731	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
732	cb63669a	pbrook	tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
733	d9bdab86	blueswir1	tcg_gen_movi_tl(cpu_cc_src2, 0);
734	6f551262	blueswir1	gen_set_label(l1);
735	d9bdab86	blueswir1
736	d9bdab86	blueswir1	// b2 = T0 & 1;
737	d9bdab86	blueswir1	// env->y = (b2 << 31) \| (env->y >> 1);
738	6f551262	blueswir1	tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
739	7127fe84	blueswir1	tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
740	7127fe84	blueswir1	tcg_gen_shli_i32(r_temp2, r_temp2, 31);
741	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
742	8911f501	blueswir1	tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
743	7127fe84	blueswir1	tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
744	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
745	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
746	d9bdab86	blueswir1
747	d9bdab86	blueswir1	// b1 = N ^ V;
748	d9bdab86	blueswir1	gen_mov_reg_N(cpu_tmp0, cpu_psr);
749	d9bdab86	blueswir1	gen_mov_reg_V(r_temp, cpu_psr);
750	d9bdab86	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
751	2ea815ca	blueswir1	tcg_temp_free(r_temp);
752	d9bdab86	blueswir1
753	d9bdab86	blueswir1	// T0 = (b1 << 31) \| (T0 >> 1);
754	d9bdab86	blueswir1	// src1 = T0;
755	d9bdab86	blueswir1	tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
756	6f551262	blueswir1	tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
757	d9bdab86	blueswir1	tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
758	d9bdab86	blueswir1
759	d9bdab86	blueswir1	/* do addition and update flags */
760	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
761	d9bdab86	blueswir1
762	ce5b3c3d	blueswir1	gen_cc_clear_icc();
763	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
764	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
765	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
766	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
767	d9bdab86	blueswir1	}
768	d9bdab86	blueswir1
769	4af984a7	blueswir1	static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
770	8879d139	blueswir1	{
771	8879d139	blueswir1	TCGv r_temp, r_temp2;
772	8879d139	blueswir1
773	8879d139	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_I64);
774	8879d139	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I64);
775	8879d139	blueswir1
776	4af984a7	blueswir1	tcg_gen_extu_tl_i64(r_temp, src2);
777	4af984a7	blueswir1	tcg_gen_extu_tl_i64(r_temp2, src1);
778	8879d139	blueswir1	tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
779	8879d139	blueswir1
780	8879d139	blueswir1	tcg_gen_shri_i64(r_temp, r_temp2, 32);
781	8879d139	blueswir1	tcg_gen_trunc_i64_i32(r_temp, r_temp);
782	8879d139	blueswir1	tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
783	2ea815ca	blueswir1	tcg_temp_free(r_temp);
784	8879d139	blueswir1	#ifdef TARGET_SPARC64
785	4af984a7	blueswir1	tcg_gen_mov_i64(dst, r_temp2);
786	8879d139	blueswir1	#else
787	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, r_temp2);
788	8879d139	blueswir1	#endif
789	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
790	8879d139	blueswir1	}
791	8879d139	blueswir1
792	4af984a7	blueswir1	static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
793	8879d139	blueswir1	{
794	8879d139	blueswir1	TCGv r_temp, r_temp2;
795	8879d139	blueswir1
796	8879d139	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_I64);
797	8879d139	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I64);
798	8879d139	blueswir1
799	4af984a7	blueswir1	tcg_gen_ext_tl_i64(r_temp, src2);
800	4af984a7	blueswir1	tcg_gen_ext_tl_i64(r_temp2, src1);
801	8879d139	blueswir1	tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
802	8879d139	blueswir1
803	8879d139	blueswir1	tcg_gen_shri_i64(r_temp, r_temp2, 32);
804	8879d139	blueswir1	tcg_gen_trunc_i64_i32(r_temp, r_temp);
805	8879d139	blueswir1	tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
806	2ea815ca	blueswir1	tcg_temp_free(r_temp);
807	8879d139	blueswir1	#ifdef TARGET_SPARC64
808	4af984a7	blueswir1	tcg_gen_mov_i64(dst, r_temp2);
809	8879d139	blueswir1	#else
810	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, r_temp2);
811	8879d139	blueswir1	#endif
812	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
813	8879d139	blueswir1	}
814	8879d139	blueswir1
815	1a7b60e7	blueswir1	#ifdef TARGET_SPARC64
816	8911f501	blueswir1	static inline void gen_trap_ifdivzero_tl(TCGv divisor)
817	1a7b60e7	blueswir1	{
818	2ea815ca	blueswir1	TCGv r_const;
819	1a7b60e7	blueswir1	int l1;
820	1a7b60e7	blueswir1
821	1a7b60e7	blueswir1	l1 = gen_new_label();
822	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
823	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_DIV_ZERO);
824	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
825	2ea815ca	blueswir1	tcg_temp_free(r_const);
826	1a7b60e7	blueswir1	gen_set_label(l1);
827	1a7b60e7	blueswir1	}
828	1a7b60e7	blueswir1
829	4af984a7	blueswir1	static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
830	1a7b60e7	blueswir1	{
831	1a7b60e7	blueswir1	int l1, l2;
832	1a7b60e7	blueswir1
833	1a7b60e7	blueswir1	l1 = gen_new_label();
834	1a7b60e7	blueswir1	l2 = gen_new_label();
835	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
836	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
837	5c6a0628	blueswir1	gen_trap_ifdivzero_tl(cpu_cc_src2);
838	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
839	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
840	4af984a7	blueswir1	tcg_gen_movi_i64(dst, INT64_MIN);
841	06b3e1b3	blueswir1	tcg_gen_br(l2);
842	1a7b60e7	blueswir1	gen_set_label(l1);
843	6f551262	blueswir1	tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
844	1a7b60e7	blueswir1	gen_set_label(l2);
845	1a7b60e7	blueswir1	}
846	1a7b60e7	blueswir1	#endif
847	1a7b60e7	blueswir1
848	4af984a7	blueswir1	static inline void gen_op_div_cc(TCGv dst)
849	dc99a3f2	blueswir1	{
850	dc99a3f2	blueswir1	int l1;
851	dc99a3f2	blueswir1
852	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
853	ce5b3c3d	blueswir1	gen_cc_clear_icc();
854	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
855	dc99a3f2	blueswir1	l1 = gen_new_label();
856	5c6a0628	blueswir1	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
857	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
858	dc99a3f2	blueswir1	gen_set_label(l1);
859	dc99a3f2	blueswir1	}
860	dc99a3f2	blueswir1
861	4af984a7	blueswir1	static inline void gen_op_logic_cc(TCGv dst)
862	dc99a3f2	blueswir1	{
863	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
864	ba28189b	blueswir1
865	ce5b3c3d	blueswir1	gen_cc_clear_icc();
866	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
867	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
868	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
869	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
870	ce5b3c3d	blueswir1	#endif
871	dc99a3f2	blueswir1	}
872	dc99a3f2	blueswir1
873	19f329ad	blueswir1	// 1
874	19f329ad	blueswir1	static inline void gen_op_eval_ba(TCGv dst)
875	19f329ad	blueswir1	{
876	19f329ad	blueswir1	tcg_gen_movi_tl(dst, 1);
877	19f329ad	blueswir1	}
878	19f329ad	blueswir1
879	19f329ad	blueswir1	// Z
880	19f329ad	blueswir1	static inline void gen_op_eval_be(TCGv dst, TCGv src)
881	19f329ad	blueswir1	{
882	19f329ad	blueswir1	gen_mov_reg_Z(dst, src);
883	19f329ad	blueswir1	}
884	19f329ad	blueswir1
885	19f329ad	blueswir1	// Z \| (N ^ V)
886	19f329ad	blueswir1	static inline void gen_op_eval_ble(TCGv dst, TCGv src)
887	19f329ad	blueswir1	{
888	0425bee5	blueswir1	gen_mov_reg_N(cpu_tmp0, src);
889	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
890	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
891	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
892	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
893	19f329ad	blueswir1	}
894	19f329ad	blueswir1
895	19f329ad	blueswir1	// N ^ V
896	19f329ad	blueswir1	static inline void gen_op_eval_bl(TCGv dst, TCGv src)
897	19f329ad	blueswir1	{
898	0425bee5	blueswir1	gen_mov_reg_V(cpu_tmp0, src);
899	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
900	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
901	19f329ad	blueswir1	}
902	19f329ad	blueswir1
903	19f329ad	blueswir1	// C \| Z
904	19f329ad	blueswir1	static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
905	19f329ad	blueswir1	{
906	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
907	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
908	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
909	19f329ad	blueswir1	}
910	19f329ad	blueswir1
911	19f329ad	blueswir1	// C
912	19f329ad	blueswir1	static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
913	19f329ad	blueswir1	{
914	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
915	19f329ad	blueswir1	}
916	19f329ad	blueswir1
917	19f329ad	blueswir1	// V
918	19f329ad	blueswir1	static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
919	19f329ad	blueswir1	{
920	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
921	19f329ad	blueswir1	}
922	19f329ad	blueswir1
923	19f329ad	blueswir1	// 0
924	19f329ad	blueswir1	static inline void gen_op_eval_bn(TCGv dst)
925	19f329ad	blueswir1	{
926	19f329ad	blueswir1	tcg_gen_movi_tl(dst, 0);
927	19f329ad	blueswir1	}
928	19f329ad	blueswir1
929	19f329ad	blueswir1	// N
930	19f329ad	blueswir1	static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
931	19f329ad	blueswir1	{
932	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
933	19f329ad	blueswir1	}
934	19f329ad	blueswir1
935	19f329ad	blueswir1	// !Z
936	19f329ad	blueswir1	static inline void gen_op_eval_bne(TCGv dst, TCGv src)
937	19f329ad	blueswir1	{
938	19f329ad	blueswir1	gen_mov_reg_Z(dst, src);
939	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
940	19f329ad	blueswir1	}
941	19f329ad	blueswir1
942	19f329ad	blueswir1	// !(Z \| (N ^ V))
943	19f329ad	blueswir1	static inline void gen_op_eval_bg(TCGv dst, TCGv src)
944	19f329ad	blueswir1	{
945	0425bee5	blueswir1	gen_mov_reg_N(cpu_tmp0, src);
946	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
947	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
948	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
949	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
950	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
951	19f329ad	blueswir1	}
952	19f329ad	blueswir1
953	19f329ad	blueswir1	// !(N ^ V)
954	19f329ad	blueswir1	static inline void gen_op_eval_bge(TCGv dst, TCGv src)
955	19f329ad	blueswir1	{
956	0425bee5	blueswir1	gen_mov_reg_V(cpu_tmp0, src);
957	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
958	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
959	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
960	19f329ad	blueswir1	}
961	19f329ad	blueswir1
962	19f329ad	blueswir1	// !(C \| Z)
963	19f329ad	blueswir1	static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
964	19f329ad	blueswir1	{
965	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
966	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
967	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
968	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
969	19f329ad	blueswir1	}
970	19f329ad	blueswir1
971	19f329ad	blueswir1	// !C
972	19f329ad	blueswir1	static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
973	19f329ad	blueswir1	{
974	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
975	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
976	19f329ad	blueswir1	}
977	19f329ad	blueswir1
978	19f329ad	blueswir1	// !N
979	19f329ad	blueswir1	static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
980	19f329ad	blueswir1	{
981	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
982	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
983	19f329ad	blueswir1	}
984	19f329ad	blueswir1
985	19f329ad	blueswir1	// !V
986	19f329ad	blueswir1	static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
987	19f329ad	blueswir1	{
988	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
989	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
990	19f329ad	blueswir1	}
991	19f329ad	blueswir1
992	19f329ad	blueswir1	/*
993	19f329ad	blueswir1	FPSR bit field FCC1 \| FCC0:
994	19f329ad	blueswir1	0 =
995	19f329ad	blueswir1	1 <
996	19f329ad	blueswir1	2 >
997	19f329ad	blueswir1	3 unordered
998	19f329ad	blueswir1	*/
999	19f329ad	blueswir1	static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
1000	19f329ad	blueswir1	unsigned int fcc_offset)
1001	19f329ad	blueswir1	{
1002	ba6a9d8c	blueswir1	tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
1003	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
1004	19f329ad	blueswir1	}
1005	19f329ad	blueswir1
1006	19f329ad	blueswir1	static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1007	19f329ad	blueswir1	unsigned int fcc_offset)
1008	19f329ad	blueswir1	{
1009	ba6a9d8c	blueswir1	tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
1010	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
1011	19f329ad	blueswir1	}
1012	19f329ad	blueswir1
1013	19f329ad	blueswir1	// !0: FCC0 \| FCC1
1014	19f329ad	blueswir1	static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1015	19f329ad	blueswir1	unsigned int fcc_offset)
1016	19f329ad	blueswir1	{
1017	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1018	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1019	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
1020	19f329ad	blueswir1	}
1021	19f329ad	blueswir1
1022	19f329ad	blueswir1	// 1 or 2: FCC0 ^ FCC1
1023	19f329ad	blueswir1	static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1024	19f329ad	blueswir1	unsigned int fcc_offset)
1025	19f329ad	blueswir1	{
1026	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1027	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1028	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1029	19f329ad	blueswir1	}
1030	19f329ad	blueswir1
1031	19f329ad	blueswir1	// 1 or 3: FCC0
1032	19f329ad	blueswir1	static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1033	19f329ad	blueswir1	unsigned int fcc_offset)
1034	19f329ad	blueswir1	{
1035	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1036	19f329ad	blueswir1	}
1037	19f329ad	blueswir1
1038	19f329ad	blueswir1	// 1: FCC0 & !FCC1
1039	19f329ad	blueswir1	static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1040	19f329ad	blueswir1	unsigned int fcc_offset)
1041	19f329ad	blueswir1	{
1042	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1043	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1044	0425bee5	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1045	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1046	19f329ad	blueswir1	}
1047	19f329ad	blueswir1
1048	19f329ad	blueswir1	// 2 or 3: FCC1
1049	19f329ad	blueswir1	static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1050	19f329ad	blueswir1	unsigned int fcc_offset)
1051	19f329ad	blueswir1	{
1052	19f329ad	blueswir1	gen_mov_reg_FCC1(dst, src, fcc_offset);
1053	19f329ad	blueswir1	}
1054	19f329ad	blueswir1
1055	19f329ad	blueswir1	// 2: !FCC0 & FCC1
1056	19f329ad	blueswir1	static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1057	19f329ad	blueswir1	unsigned int fcc_offset)
1058	19f329ad	blueswir1	{
1059	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1060	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1061	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1062	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1063	19f329ad	blueswir1	}
1064	19f329ad	blueswir1
1065	19f329ad	blueswir1	// 3: FCC0 & FCC1
1066	19f329ad	blueswir1	static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1067	19f329ad	blueswir1	unsigned int fcc_offset)
1068	19f329ad	blueswir1	{
1069	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1070	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1071	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1072	19f329ad	blueswir1	}
1073	19f329ad	blueswir1
1074	19f329ad	blueswir1	// 0: !(FCC0 \| FCC1)
1075	19f329ad	blueswir1	static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1076	19f329ad	blueswir1	unsigned int fcc_offset)
1077	19f329ad	blueswir1	{
1078	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1079	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1080	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
1081	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1082	19f329ad	blueswir1	}
1083	19f329ad	blueswir1
1084	19f329ad	blueswir1	// 0 or 3: !(FCC0 ^ FCC1)
1085	19f329ad	blueswir1	static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1086	19f329ad	blueswir1	unsigned int fcc_offset)
1087	19f329ad	blueswir1	{
1088	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1089	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1090	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1091	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1092	19f329ad	blueswir1	}
1093	19f329ad	blueswir1
1094	19f329ad	blueswir1	// 0 or 2: !FCC0
1095	19f329ad	blueswir1	static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1096	19f329ad	blueswir1	unsigned int fcc_offset)
1097	19f329ad	blueswir1	{
1098	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1099	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1100	19f329ad	blueswir1	}
1101	19f329ad	blueswir1
1102	19f329ad	blueswir1	// !1: !(FCC0 & !FCC1)
1103	19f329ad	blueswir1	static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1104	19f329ad	blueswir1	unsigned int fcc_offset)
1105	19f329ad	blueswir1	{
1106	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1107	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1108	0425bee5	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1109	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1110	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1111	19f329ad	blueswir1	}
1112	19f329ad	blueswir1
1113	19f329ad	blueswir1	// 0 or 1: !FCC1
1114	19f329ad	blueswir1	static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1115	19f329ad	blueswir1	unsigned int fcc_offset)
1116	19f329ad	blueswir1	{
1117	19f329ad	blueswir1	gen_mov_reg_FCC1(dst, src, fcc_offset);
1118	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1119	19f329ad	blueswir1	}
1120	19f329ad	blueswir1
1121	19f329ad	blueswir1	// !2: !(!FCC0 & FCC1)
1122	19f329ad	blueswir1	static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1123	19f329ad	blueswir1	unsigned int fcc_offset)
1124	19f329ad	blueswir1	{
1125	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1126	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1127	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1128	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1129	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1130	19f329ad	blueswir1	}
1131	19f329ad	blueswir1
1132	19f329ad	blueswir1	// !3: !(FCC0 & FCC1)
1133	19f329ad	blueswir1	static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1134	19f329ad	blueswir1	unsigned int fcc_offset)
1135	19f329ad	blueswir1	{
1136	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1137	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1138	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1139	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1140	19f329ad	blueswir1	}
1141	19f329ad	blueswir1
1142	46525e1f	blueswir1	static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1143	19f329ad	blueswir1	target_ulong pc2, TCGv r_cond)
1144	83469015	bellard	{
1145	83469015	bellard	int l1;
1146	83469015	bellard
1147	83469015	bellard	l1 = gen_new_label();
1148	83469015	bellard
1149	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1150	83469015	bellard
1151	6e256c93	bellard	gen_goto_tb(dc, 0, pc1, pc1 + 4);
1152	83469015	bellard
1153	83469015	bellard	gen_set_label(l1);
1154	6e256c93	bellard	gen_goto_tb(dc, 1, pc2, pc2 + 4);
1155	83469015	bellard	}
1156	83469015	bellard
1157	46525e1f	blueswir1	static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1158	19f329ad	blueswir1	target_ulong pc2, TCGv r_cond)
1159	83469015	bellard	{
1160	83469015	bellard	int l1;
1161	83469015	bellard
1162	83469015	bellard	l1 = gen_new_label();
1163	83469015	bellard
1164	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1165	83469015	bellard
1166	6e256c93	bellard	gen_goto_tb(dc, 0, pc2, pc1);
1167	83469015	bellard
1168	83469015	bellard	gen_set_label(l1);
1169	6e256c93	bellard	gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1170	83469015	bellard	}
1171	83469015	bellard
1172	19f329ad	blueswir1	static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1173	19f329ad	blueswir1	TCGv r_cond)
1174	83469015	bellard	{
1175	83469015	bellard	int l1, l2;
1176	83469015	bellard
1177	83469015	bellard	l1 = gen_new_label();
1178	83469015	bellard	l2 = gen_new_label();
1179	19f329ad	blueswir1
1180	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1181	83469015	bellard
1182	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc1);
1183	06b3e1b3	blueswir1	tcg_gen_br(l2);
1184	83469015	bellard
1185	83469015	bellard	gen_set_label(l1);
1186	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc2);
1187	83469015	bellard	gen_set_label(l2);
1188	83469015	bellard	}
1189	83469015	bellard
1190	4af984a7	blueswir1	/* call this function before using the condition register as it may
1191	4af984a7	blueswir1	have been set for a jump */
1192	4af984a7	blueswir1	static inline void flush_cond(DisasContext *dc, TCGv cond)
1193	83469015	bellard	{
1194	83469015	bellard	if (dc->npc == JUMP_PC) {
1195	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1196	83469015	bellard	dc->npc = DYNAMIC_PC;
1197	83469015	bellard	}
1198	83469015	bellard	}
1199	83469015	bellard
1200	4af984a7	blueswir1	static inline void save_npc(DisasContext *dc, TCGv cond)
1201	72cbca10	bellard	{
1202	72cbca10	bellard	if (dc->npc == JUMP_PC) {
1203	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1204	72cbca10	bellard	dc->npc = DYNAMIC_PC;
1205	72cbca10	bellard	} else if (dc->npc != DYNAMIC_PC) {
1206	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, dc->npc);
1207	72cbca10	bellard	}
1208	72cbca10	bellard	}
1209	72cbca10	bellard
1210	4af984a7	blueswir1	static inline void save_state(DisasContext *dc, TCGv cond)
1211	72cbca10	bellard	{
1212	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
1213	4af984a7	blueswir1	save_npc(dc, cond);
1214	72cbca10	bellard	}
1215	72cbca10	bellard
1216	4af984a7	blueswir1	static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1217	0bee699e	bellard	{
1218	0bee699e	bellard	if (dc->npc == JUMP_PC) {
1219	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1220	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1221	0bee699e	bellard	dc->pc = DYNAMIC_PC;
1222	0bee699e	bellard	} else if (dc->npc == DYNAMIC_PC) {
1223	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1224	0bee699e	bellard	dc->pc = DYNAMIC_PC;
1225	0bee699e	bellard	} else {
1226	0bee699e	bellard	dc->pc = dc->npc;
1227	0bee699e	bellard	}
1228	0bee699e	bellard	}
1229	0bee699e	bellard
1230	38bc628b	blueswir1	static inline void gen_op_next_insn(void)
1231	38bc628b	blueswir1	{
1232	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1233	48d5c82b	blueswir1	tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1234	38bc628b	blueswir1	}
1235	38bc628b	blueswir1
1236	19f329ad	blueswir1	static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1237	19f329ad	blueswir1	{
1238	19f329ad	blueswir1	TCGv r_src;
1239	3475187d	bellard
1240	3475187d	bellard	#ifdef TARGET_SPARC64
1241	19f329ad	blueswir1	if (cc)
1242	dc99a3f2	blueswir1	r_src = cpu_xcc;
1243	19f329ad	blueswir1	else
1244	dc99a3f2	blueswir1	r_src = cpu_psr;
1245	3475187d	bellard	#else
1246	dc99a3f2	blueswir1	r_src = cpu_psr;
1247	3475187d	bellard	#endif
1248	19f329ad	blueswir1	switch (cond) {
1249	19f329ad	blueswir1	case 0x0:
1250	19f329ad	blueswir1	gen_op_eval_bn(r_dst);
1251	19f329ad	blueswir1	break;
1252	19f329ad	blueswir1	case 0x1:
1253	19f329ad	blueswir1	gen_op_eval_be(r_dst, r_src);
1254	19f329ad	blueswir1	break;
1255	19f329ad	blueswir1	case 0x2:
1256	19f329ad	blueswir1	gen_op_eval_ble(r_dst, r_src);
1257	19f329ad	blueswir1	break;
1258	19f329ad	blueswir1	case 0x3:
1259	19f329ad	blueswir1	gen_op_eval_bl(r_dst, r_src);
1260	19f329ad	blueswir1	break;
1261	19f329ad	blueswir1	case 0x4:
1262	19f329ad	blueswir1	gen_op_eval_bleu(r_dst, r_src);
1263	19f329ad	blueswir1	break;
1264	19f329ad	blueswir1	case 0x5:
1265	19f329ad	blueswir1	gen_op_eval_bcs(r_dst, r_src);
1266	19f329ad	blueswir1	break;
1267	19f329ad	blueswir1	case 0x6:
1268	19f329ad	blueswir1	gen_op_eval_bneg(r_dst, r_src);
1269	19f329ad	blueswir1	break;
1270	19f329ad	blueswir1	case 0x7:
1271	19f329ad	blueswir1	gen_op_eval_bvs(r_dst, r_src);
1272	19f329ad	blueswir1	break;
1273	19f329ad	blueswir1	case 0x8:
1274	19f329ad	blueswir1	gen_op_eval_ba(r_dst);
1275	19f329ad	blueswir1	break;
1276	19f329ad	blueswir1	case 0x9:
1277	19f329ad	blueswir1	gen_op_eval_bne(r_dst, r_src);
1278	19f329ad	blueswir1	break;
1279	19f329ad	blueswir1	case 0xa:
1280	19f329ad	blueswir1	gen_op_eval_bg(r_dst, r_src);
1281	19f329ad	blueswir1	break;
1282	19f329ad	blueswir1	case 0xb:
1283	19f329ad	blueswir1	gen_op_eval_bge(r_dst, r_src);
1284	19f329ad	blueswir1	break;
1285	19f329ad	blueswir1	case 0xc:
1286	19f329ad	blueswir1	gen_op_eval_bgu(r_dst, r_src);
1287	19f329ad	blueswir1	break;
1288	19f329ad	blueswir1	case 0xd:
1289	19f329ad	blueswir1	gen_op_eval_bcc(r_dst, r_src);
1290	19f329ad	blueswir1	break;
1291	19f329ad	blueswir1	case 0xe:
1292	19f329ad	blueswir1	gen_op_eval_bpos(r_dst, r_src);
1293	19f329ad	blueswir1	break;
1294	19f329ad	blueswir1	case 0xf:
1295	19f329ad	blueswir1	gen_op_eval_bvc(r_dst, r_src);
1296	19f329ad	blueswir1	break;
1297	19f329ad	blueswir1	}
1298	19f329ad	blueswir1	}
1299	7a3f1944	bellard
1300	19f329ad	blueswir1	static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1301	e8af50a3	bellard	{
1302	19f329ad	blueswir1	unsigned int offset;
1303	19f329ad	blueswir1
1304	19f329ad	blueswir1	switch (cc) {
1305	19f329ad	blueswir1	default:
1306	19f329ad	blueswir1	case 0x0:
1307	19f329ad	blueswir1	offset = 0;
1308	19f329ad	blueswir1	break;
1309	19f329ad	blueswir1	case 0x1:
1310	19f329ad	blueswir1	offset = 32 - 10;
1311	19f329ad	blueswir1	break;
1312	19f329ad	blueswir1	case 0x2:
1313	19f329ad	blueswir1	offset = 34 - 10;
1314	19f329ad	blueswir1	break;
1315	19f329ad	blueswir1	case 0x3:
1316	19f329ad	blueswir1	offset = 36 - 10;
1317	19f329ad	blueswir1	break;
1318	19f329ad	blueswir1	}
1319	19f329ad	blueswir1
1320	19f329ad	blueswir1	switch (cond) {
1321	19f329ad	blueswir1	case 0x0:
1322	19f329ad	blueswir1	gen_op_eval_bn(r_dst);
1323	19f329ad	blueswir1	break;
1324	19f329ad	blueswir1	case 0x1:
1325	87e92502	blueswir1	gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1326	19f329ad	blueswir1	break;
1327	19f329ad	blueswir1	case 0x2:
1328	87e92502	blueswir1	gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1329	19f329ad	blueswir1	break;
1330	19f329ad	blueswir1	case 0x3:
1331	87e92502	blueswir1	gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1332	19f329ad	blueswir1	break;
1333	19f329ad	blueswir1	case 0x4:
1334	87e92502	blueswir1	gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1335	19f329ad	blueswir1	break;
1336	19f329ad	blueswir1	case 0x5:
1337	87e92502	blueswir1	gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1338	19f329ad	blueswir1	break;
1339	19f329ad	blueswir1	case 0x6:
1340	87e92502	blueswir1	gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1341	19f329ad	blueswir1	break;
1342	19f329ad	blueswir1	case 0x7:
1343	87e92502	blueswir1	gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1344	19f329ad	blueswir1	break;
1345	19f329ad	blueswir1	case 0x8:
1346	19f329ad	blueswir1	gen_op_eval_ba(r_dst);
1347	19f329ad	blueswir1	break;
1348	19f329ad	blueswir1	case 0x9:
1349	87e92502	blueswir1	gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1350	19f329ad	blueswir1	break;
1351	19f329ad	blueswir1	case 0xa:
1352	87e92502	blueswir1	gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1353	19f329ad	blueswir1	break;
1354	19f329ad	blueswir1	case 0xb:
1355	87e92502	blueswir1	gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1356	19f329ad	blueswir1	break;
1357	19f329ad	blueswir1	case 0xc:
1358	87e92502	blueswir1	gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1359	19f329ad	blueswir1	break;
1360	19f329ad	blueswir1	case 0xd:
1361	87e92502	blueswir1	gen_op_eval_fble(r_dst, cpu_fsr, offset);
1362	19f329ad	blueswir1	break;
1363	19f329ad	blueswir1	case 0xe:
1364	87e92502	blueswir1	gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1365	19f329ad	blueswir1	break;
1366	19f329ad	blueswir1	case 0xf:
1367	87e92502	blueswir1	gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1368	19f329ad	blueswir1	break;
1369	19f329ad	blueswir1	}
1370	e8af50a3	bellard	}
1371	00f219bf	blueswir1
1372	19f329ad	blueswir1	#ifdef TARGET_SPARC64
1373	00f219bf	blueswir1	// Inverted logic
1374	00f219bf	blueswir1	static const int gen_tcg_cond_reg[8] = {
1375	00f219bf	blueswir1	-1,
1376	00f219bf	blueswir1	TCG_COND_NE,
1377	00f219bf	blueswir1	TCG_COND_GT,
1378	00f219bf	blueswir1	TCG_COND_GE,
1379	00f219bf	blueswir1	-1,
1380	00f219bf	blueswir1	TCG_COND_EQ,
1381	00f219bf	blueswir1	TCG_COND_LE,
1382	00f219bf	blueswir1	TCG_COND_LT,
1383	00f219bf	blueswir1	};
1384	19f329ad	blueswir1
1385	4af984a7	blueswir1	static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1386	19f329ad	blueswir1	{
1387	19f329ad	blueswir1	int l1;
1388	19f329ad	blueswir1
1389	19f329ad	blueswir1	l1 = gen_new_label();
1390	0425bee5	blueswir1	tcg_gen_movi_tl(r_dst, 0);
1391	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1392	19f329ad	blueswir1	tcg_gen_movi_tl(r_dst, 1);
1393	19f329ad	blueswir1	gen_set_label(l1);
1394	19f329ad	blueswir1	}
1395	3475187d	bellard	#endif
1396	cf495bcf	bellard
1397	0bee699e	bellard	/* XXX: potentially incorrect if dynamic npc */
1398	4af984a7	blueswir1	static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1399	4af984a7	blueswir1	TCGv r_cond)
1400	7a3f1944	bellard	{
1401	cf495bcf	bellard	unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1402	af7bf89b	bellard	target_ulong target = dc->pc + offset;
1403	5fafdf24	ths
1404	cf495bcf	bellard	if (cond == 0x0) {
1405	0f8a249a	blueswir1	/* unconditional not taken */
1406	0f8a249a	blueswir1	if (a) {
1407	0f8a249a	blueswir1	dc->pc = dc->npc + 4;
1408	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1409	0f8a249a	blueswir1	} else {
1410	0f8a249a	blueswir1	dc->pc = dc->npc;
1411	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1412	0f8a249a	blueswir1	}
1413	cf495bcf	bellard	} else if (cond == 0x8) {
1414	0f8a249a	blueswir1	/* unconditional taken */
1415	0f8a249a	blueswir1	if (a) {
1416	0f8a249a	blueswir1	dc->pc = target;
1417	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1418	0f8a249a	blueswir1	} else {
1419	0f8a249a	blueswir1	dc->pc = dc->npc;
1420	0f8a249a	blueswir1	dc->npc = target;
1421	0f8a249a	blueswir1	}
1422	cf495bcf	bellard	} else {
1423	4af984a7	blueswir1	flush_cond(dc, r_cond);
1424	4af984a7	blueswir1	gen_cond(r_cond, cc, cond);
1425	0f8a249a	blueswir1	if (a) {
1426	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1427	cf495bcf	bellard	dc->is_br = 1;
1428	0f8a249a	blueswir1	} else {
1429	cf495bcf	bellard	dc->pc = dc->npc;
1430	72cbca10	bellard	dc->jump_pc[0] = target;
1431	72cbca10	bellard	dc->jump_pc[1] = dc->npc + 4;
1432	72cbca10	bellard	dc->npc = JUMP_PC;
1433	0f8a249a	blueswir1	}
1434	cf495bcf	bellard	}
1435	7a3f1944	bellard	}
1436	7a3f1944	bellard
1437	0bee699e	bellard	/* XXX: potentially incorrect if dynamic npc */
1438	4af984a7	blueswir1	static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1439	4af984a7	blueswir1	TCGv r_cond)
1440	e8af50a3	bellard	{
1441	e8af50a3	bellard	unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1442	af7bf89b	bellard	target_ulong target = dc->pc + offset;
1443	af7bf89b	bellard
1444	e8af50a3	bellard	if (cond == 0x0) {
1445	0f8a249a	blueswir1	/* unconditional not taken */
1446	0f8a249a	blueswir1	if (a) {
1447	0f8a249a	blueswir1	dc->pc = dc->npc + 4;
1448	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1449	0f8a249a	blueswir1	} else {
1450	0f8a249a	blueswir1	dc->pc = dc->npc;
1451	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1452	0f8a249a	blueswir1	}
1453	e8af50a3	bellard	} else if (cond == 0x8) {
1454	0f8a249a	blueswir1	/* unconditional taken */
1455	0f8a249a	blueswir1	if (a) {
1456	0f8a249a	blueswir1	dc->pc = target;
1457	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1458	0f8a249a	blueswir1	} else {
1459	0f8a249a	blueswir1	dc->pc = dc->npc;
1460	0f8a249a	blueswir1	dc->npc = target;
1461	0f8a249a	blueswir1	}
1462	e8af50a3	bellard	} else {
1463	4af984a7	blueswir1	flush_cond(dc, r_cond);
1464	4af984a7	blueswir1	gen_fcond(r_cond, cc, cond);
1465	0f8a249a	blueswir1	if (a) {
1466	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1467	e8af50a3	bellard	dc->is_br = 1;
1468	0f8a249a	blueswir1	} else {
1469	e8af50a3	bellard	dc->pc = dc->npc;
1470	e8af50a3	bellard	dc->jump_pc[0] = target;
1471	e8af50a3	bellard	dc->jump_pc[1] = dc->npc + 4;
1472	e8af50a3	bellard	dc->npc = JUMP_PC;
1473	0f8a249a	blueswir1	}
1474	e8af50a3	bellard	}
1475	e8af50a3	bellard	}
1476	e8af50a3	bellard
1477	3475187d	bellard	#ifdef TARGET_SPARC64
1478	3475187d	bellard	/* XXX: potentially incorrect if dynamic npc */
1479	4af984a7	blueswir1	static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1480	4af984a7	blueswir1	TCGv r_cond, TCGv r_reg)
1481	7a3f1944	bellard	{
1482	3475187d	bellard	unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1483	3475187d	bellard	target_ulong target = dc->pc + offset;
1484	3475187d	bellard
1485	4af984a7	blueswir1	flush_cond(dc, r_cond);
1486	4af984a7	blueswir1	gen_cond_reg(r_cond, cond, r_reg);
1487	3475187d	bellard	if (a) {
1488	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1489	0f8a249a	blueswir1	dc->is_br = 1;
1490	3475187d	bellard	} else {
1491	0f8a249a	blueswir1	dc->pc = dc->npc;
1492	0f8a249a	blueswir1	dc->jump_pc[0] = target;
1493	0f8a249a	blueswir1	dc->jump_pc[1] = dc->npc + 4;
1494	0f8a249a	blueswir1	dc->npc = JUMP_PC;
1495	3475187d	bellard	}
1496	7a3f1944	bellard	}
1497	7a3f1944	bellard
1498	3475187d	bellard	static GenOpFunc * const gen_fcmps[4] = {
1499	7e8c2b6c	blueswir1	helper_fcmps,
1500	7e8c2b6c	blueswir1	helper_fcmps_fcc1,
1501	7e8c2b6c	blueswir1	helper_fcmps_fcc2,
1502	7e8c2b6c	blueswir1	helper_fcmps_fcc3,
1503	3475187d	bellard	};
1504	3475187d	bellard
1505	3475187d	bellard	static GenOpFunc * const gen_fcmpd[4] = {
1506	7e8c2b6c	blueswir1	helper_fcmpd,
1507	7e8c2b6c	blueswir1	helper_fcmpd_fcc1,
1508	7e8c2b6c	blueswir1	helper_fcmpd_fcc2,
1509	7e8c2b6c	blueswir1	helper_fcmpd_fcc3,
1510	3475187d	bellard	};
1511	417454b0	blueswir1
1512	1f587329	blueswir1	static GenOpFunc * const gen_fcmpq[4] = {
1513	7e8c2b6c	blueswir1	helper_fcmpq,
1514	7e8c2b6c	blueswir1	helper_fcmpq_fcc1,
1515	7e8c2b6c	blueswir1	helper_fcmpq_fcc2,
1516	7e8c2b6c	blueswir1	helper_fcmpq_fcc3,
1517	1f587329	blueswir1	};
1518	1f587329	blueswir1
1519	417454b0	blueswir1	static GenOpFunc * const gen_fcmpes[4] = {
1520	7e8c2b6c	blueswir1	helper_fcmpes,
1521	7e8c2b6c	blueswir1	helper_fcmpes_fcc1,
1522	7e8c2b6c	blueswir1	helper_fcmpes_fcc2,
1523	7e8c2b6c	blueswir1	helper_fcmpes_fcc3,
1524	417454b0	blueswir1	};
1525	417454b0	blueswir1
1526	417454b0	blueswir1	static GenOpFunc * const gen_fcmped[4] = {
1527	7e8c2b6c	blueswir1	helper_fcmped,
1528	7e8c2b6c	blueswir1	helper_fcmped_fcc1,
1529	7e8c2b6c	blueswir1	helper_fcmped_fcc2,
1530	7e8c2b6c	blueswir1	helper_fcmped_fcc3,
1531	417454b0	blueswir1	};
1532	417454b0	blueswir1
1533	1f587329	blueswir1	static GenOpFunc * const gen_fcmpeq[4] = {
1534	7e8c2b6c	blueswir1	helper_fcmpeq,
1535	7e8c2b6c	blueswir1	helper_fcmpeq_fcc1,
1536	7e8c2b6c	blueswir1	helper_fcmpeq_fcc2,
1537	7e8c2b6c	blueswir1	helper_fcmpeq_fcc3,
1538	1f587329	blueswir1	};
1539	7e8c2b6c	blueswir1
1540	7e8c2b6c	blueswir1	static inline void gen_op_fcmps(int fccno)
1541	7e8c2b6c	blueswir1	{
1542	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmps[fccno]);
1543	7e8c2b6c	blueswir1	}
1544	7e8c2b6c	blueswir1
1545	7e8c2b6c	blueswir1	static inline void gen_op_fcmpd(int fccno)
1546	7e8c2b6c	blueswir1	{
1547	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1548	7e8c2b6c	blueswir1	}
1549	7e8c2b6c	blueswir1
1550	7e8c2b6c	blueswir1	static inline void gen_op_fcmpq(int fccno)
1551	7e8c2b6c	blueswir1	{
1552	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1553	7e8c2b6c	blueswir1	}
1554	7e8c2b6c	blueswir1
1555	7e8c2b6c	blueswir1	static inline void gen_op_fcmpes(int fccno)
1556	7e8c2b6c	blueswir1	{
1557	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1558	7e8c2b6c	blueswir1	}
1559	7e8c2b6c	blueswir1
1560	7e8c2b6c	blueswir1	static inline void gen_op_fcmped(int fccno)
1561	7e8c2b6c	blueswir1	{
1562	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmped[fccno]);
1563	7e8c2b6c	blueswir1	}
1564	7e8c2b6c	blueswir1
1565	7e8c2b6c	blueswir1	static inline void gen_op_fcmpeq(int fccno)
1566	7e8c2b6c	blueswir1	{
1567	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1568	7e8c2b6c	blueswir1	}
1569	7e8c2b6c	blueswir1
1570	7e8c2b6c	blueswir1	#else
1571	7e8c2b6c	blueswir1
1572	7e8c2b6c	blueswir1	static inline void gen_op_fcmps(int fccno)
1573	7e8c2b6c	blueswir1	{
1574	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmps);
1575	7e8c2b6c	blueswir1	}
1576	7e8c2b6c	blueswir1
1577	7e8c2b6c	blueswir1	static inline void gen_op_fcmpd(int fccno)
1578	7e8c2b6c	blueswir1	{
1579	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpd);
1580	7e8c2b6c	blueswir1	}
1581	7e8c2b6c	blueswir1
1582	7e8c2b6c	blueswir1	static inline void gen_op_fcmpq(int fccno)
1583	7e8c2b6c	blueswir1	{
1584	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpq);
1585	7e8c2b6c	blueswir1	}
1586	7e8c2b6c	blueswir1
1587	7e8c2b6c	blueswir1	static inline void gen_op_fcmpes(int fccno)
1588	7e8c2b6c	blueswir1	{
1589	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpes);
1590	7e8c2b6c	blueswir1	}
1591	7e8c2b6c	blueswir1
1592	7e8c2b6c	blueswir1	static inline void gen_op_fcmped(int fccno)
1593	7e8c2b6c	blueswir1	{
1594	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmped);
1595	7e8c2b6c	blueswir1	}
1596	7e8c2b6c	blueswir1
1597	7e8c2b6c	blueswir1	static inline void gen_op_fcmpeq(int fccno)
1598	7e8c2b6c	blueswir1	{
1599	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq);
1600	7e8c2b6c	blueswir1	}
1601	7e8c2b6c	blueswir1	#endif
1602	7e8c2b6c	blueswir1
1603	134d77a1	blueswir1	static inline void gen_op_fpexception_im(int fsr_flags)
1604	134d77a1	blueswir1	{
1605	2ea815ca	blueswir1	TCGv r_const;
1606	2ea815ca	blueswir1
1607	87e92502	blueswir1	tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1608	87e92502	blueswir1	tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1609	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_FP_EXCP);
1610	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
1611	2ea815ca	blueswir1	tcg_temp_free(r_const);
1612	134d77a1	blueswir1	}
1613	134d77a1	blueswir1
1614	4af984a7	blueswir1	static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1615	a80dde08	bellard	{
1616	a80dde08	bellard	#if !defined(CONFIG_USER_ONLY)
1617	a80dde08	bellard	if (!dc->fpu_enabled) {
1618	2ea815ca	blueswir1	TCGv r_const;
1619	2ea815ca	blueswir1
1620	4af984a7	blueswir1	save_state(dc, r_cond);
1621	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_NFPU_INSN);
1622	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
1623	2ea815ca	blueswir1	tcg_temp_free(r_const);
1624	a80dde08	bellard	dc->is_br = 1;
1625	a80dde08	bellard	return 1;
1626	a80dde08	bellard	}
1627	a80dde08	bellard	#endif
1628	a80dde08	bellard	return 0;
1629	a80dde08	bellard	}
1630	a80dde08	bellard
1631	7e8c2b6c	blueswir1	static inline void gen_op_clear_ieee_excp_and_FTT(void)
1632	7e8c2b6c	blueswir1	{
1633	87e92502	blueswir1	tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK \| FSR_CEXC_MASK));
1634	7e8c2b6c	blueswir1	}
1635	7e8c2b6c	blueswir1
1636	7e8c2b6c	blueswir1	static inline void gen_clear_float_exceptions(void)
1637	7e8c2b6c	blueswir1	{
1638	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_clear_float_exceptions);
1639	7e8c2b6c	blueswir1	}
1640	7e8c2b6c	blueswir1
1641	1a2fb1c0	blueswir1	/* asi moves */
1642	1a2fb1c0	blueswir1	#ifdef TARGET_SPARC64
1643	0425bee5	blueswir1	static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1644	1a2fb1c0	blueswir1	{
1645	95f9397c	blueswir1	int asi;
1646	0425bee5	blueswir1	TCGv r_asi;
1647	1a2fb1c0	blueswir1
1648	1a2fb1c0	blueswir1	if (IS_IMM) {
1649	0425bee5	blueswir1	r_asi = tcg_temp_new(TCG_TYPE_I32);
1650	0425bee5	blueswir1	tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1651	1a2fb1c0	blueswir1	} else {
1652	1a2fb1c0	blueswir1	asi = GET_FIELD(insn, 19, 26);
1653	0425bee5	blueswir1	r_asi = tcg_const_i32(asi);
1654	1a2fb1c0	blueswir1	}
1655	0425bee5	blueswir1	return r_asi;
1656	0425bee5	blueswir1	}
1657	0425bee5	blueswir1
1658	77f193da	blueswir1	static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1659	77f193da	blueswir1	int sign)
1660	0425bee5	blueswir1	{
1661	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1662	0425bee5	blueswir1
1663	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1664	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1665	2ea815ca	blueswir1	r_sign = tcg_const_i32(sign);
1666	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1667	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1668	2ea815ca	blueswir1	tcg_temp_free(r_size);
1669	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1670	1a2fb1c0	blueswir1	}
1671	1a2fb1c0	blueswir1
1672	4af984a7	blueswir1	static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1673	1a2fb1c0	blueswir1	{
1674	2ea815ca	blueswir1	TCGv r_asi, r_size;
1675	1a2fb1c0	blueswir1
1676	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1677	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1678	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1679	2ea815ca	blueswir1	tcg_temp_free(r_size);
1680	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1681	1a2fb1c0	blueswir1	}
1682	1a2fb1c0	blueswir1
1683	4af984a7	blueswir1	static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1684	1a2fb1c0	blueswir1	{
1685	2ea815ca	blueswir1	TCGv r_asi, r_size, r_rd;
1686	1a2fb1c0	blueswir1
1687	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1688	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1689	2ea815ca	blueswir1	r_rd = tcg_const_i32(rd);
1690	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1691	2ea815ca	blueswir1	tcg_temp_free(r_rd);
1692	2ea815ca	blueswir1	tcg_temp_free(r_size);
1693	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1694	1a2fb1c0	blueswir1	}
1695	1a2fb1c0	blueswir1
1696	4af984a7	blueswir1	static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1697	1a2fb1c0	blueswir1	{
1698	2ea815ca	blueswir1	TCGv r_asi, r_size, r_rd;
1699	1a2fb1c0	blueswir1
1700	31741a27	blueswir1	r_asi = gen_get_asi(insn, addr);
1701	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1702	2ea815ca	blueswir1	r_rd = tcg_const_i32(rd);
1703	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1704	2ea815ca	blueswir1	tcg_temp_free(r_rd);
1705	2ea815ca	blueswir1	tcg_temp_free(r_size);
1706	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1707	1a2fb1c0	blueswir1	}
1708	1a2fb1c0	blueswir1
1709	4af984a7	blueswir1	static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1710	1a2fb1c0	blueswir1	{
1711	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1712	1a2fb1c0	blueswir1
1713	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1714	2ea815ca	blueswir1	r_size = tcg_const_i32(4);
1715	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1716	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1717	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1718	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1719	2ea815ca	blueswir1	tcg_temp_free(r_size);
1720	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1721	8d96d209	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1722	1a2fb1c0	blueswir1	}
1723	1a2fb1c0	blueswir1
1724	db166940	blueswir1	static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1725	1a2fb1c0	blueswir1	{
1726	db166940	blueswir1	TCGv r_asi, r_rd;
1727	1a2fb1c0	blueswir1
1728	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1729	db166940	blueswir1	r_rd = tcg_const_i32(rd);
1730	db166940	blueswir1	tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd);
1731	db166940	blueswir1	tcg_temp_free(r_rd);
1732	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1733	0425bee5	blueswir1	}
1734	0425bee5	blueswir1
1735	4af984a7	blueswir1	static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1736	0425bee5	blueswir1	{
1737	2ea815ca	blueswir1	TCGv r_temp, r_asi, r_size;
1738	0425bee5	blueswir1
1739	8d96d209	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
1740	0425bee5	blueswir1	gen_movl_reg_TN(rd + 1, r_temp);
1741	4af984a7	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1742	0425bee5	blueswir1	r_temp);
1743	2ea815ca	blueswir1	tcg_temp_free(r_temp);
1744	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1745	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1746	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1747	2ea815ca	blueswir1	tcg_temp_free(r_size);
1748	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1749	1a2fb1c0	blueswir1	}
1750	1a2fb1c0	blueswir1
1751	77f193da	blueswir1	static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1752	77f193da	blueswir1	int rd)
1753	1a2fb1c0	blueswir1	{
1754	1a2fb1c0	blueswir1	TCGv r_val1, r_asi;
1755	1a2fb1c0	blueswir1
1756	ef28fd86	blueswir1	r_val1 = tcg_temp_new(TCG_TYPE_TL);
1757	1a2fb1c0	blueswir1	gen_movl_reg_TN(rd, r_val1);
1758	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1759	4af984a7	blueswir1	tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1760	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1761	2ea815ca	blueswir1	tcg_temp_free(r_val1);
1762	1a2fb1c0	blueswir1	}
1763	1a2fb1c0	blueswir1
1764	77f193da	blueswir1	static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1765	77f193da	blueswir1	int rd)
1766	1a2fb1c0	blueswir1	{
1767	8911f501	blueswir1	TCGv r_asi;
1768	1a2fb1c0	blueswir1
1769	8911f501	blueswir1	gen_movl_reg_TN(rd, cpu_tmp64);
1770	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1771	4af984a7	blueswir1	tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1772	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1773	1a2fb1c0	blueswir1	}
1774	1a2fb1c0	blueswir1
1775	1a2fb1c0	blueswir1	#elif !defined(CONFIG_USER_ONLY)
1776	1a2fb1c0	blueswir1
1777	77f193da	blueswir1	static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1778	77f193da	blueswir1	int sign)
1779	1a2fb1c0	blueswir1	{
1780	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1781	1a2fb1c0	blueswir1
1782	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1783	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1784	2ea815ca	blueswir1	r_sign = tcg_const_i32(sign);
1785	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1786	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1787	2ea815ca	blueswir1	tcg_temp_free(r_size);
1788	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1789	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1790	1a2fb1c0	blueswir1	}
1791	1a2fb1c0	blueswir1
1792	4af984a7	blueswir1	static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1793	1a2fb1c0	blueswir1	{
1794	2ea815ca	blueswir1	TCGv r_asi, r_size;
1795	1a2fb1c0	blueswir1
1796	4af984a7	blueswir1	tcg_gen_extu_tl_i64(cpu_tmp64, src);
1797	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1798	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1799	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1800	2ea815ca	blueswir1	tcg_temp_free(r_size);
1801	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1802	1a2fb1c0	blueswir1	}
1803	1a2fb1c0	blueswir1
1804	4af984a7	blueswir1	static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1805	1a2fb1c0	blueswir1	{
1806	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1807	1a2fb1c0	blueswir1
1808	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1809	2ea815ca	blueswir1	r_size = tcg_const_i32(4);
1810	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1811	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1812	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1813	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1814	2ea815ca	blueswir1	tcg_temp_free(r_size);
1815	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1816	8d96d209	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1817	1a2fb1c0	blueswir1	}
1818	1a2fb1c0	blueswir1
1819	db166940	blueswir1	static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1820	1a2fb1c0	blueswir1	{
1821	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1822	1a2fb1c0	blueswir1
1823	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1824	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1825	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1826	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1827	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1828	2ea815ca	blueswir1	tcg_temp_free(r_size);
1829	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1830	db166940	blueswir1	tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
1831	db166940	blueswir1	gen_movl_TN_reg(rd + 1, cpu_tmp0);
1832	8911f501	blueswir1	tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1833	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1834	db166940	blueswir1	gen_movl_TN_reg(rd, hi);
1835	0425bee5	blueswir1	}
1836	0425bee5	blueswir1
1837	4af984a7	blueswir1	static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1838	0425bee5	blueswir1	{
1839	2ea815ca	blueswir1	TCGv r_temp, r_asi, r_size;
1840	0425bee5	blueswir1
1841	8d96d209	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
1842	0425bee5	blueswir1	gen_movl_reg_TN(rd + 1, r_temp);
1843	4af984a7	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1844	2ea815ca	blueswir1	tcg_temp_free(r_temp);
1845	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1846	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1847	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1848	2ea815ca	blueswir1	tcg_temp_free(r_size);
1849	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1850	1a2fb1c0	blueswir1	}
1851	1a2fb1c0	blueswir1	#endif
1852	1a2fb1c0	blueswir1
1853	1a2fb1c0	blueswir1	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
1854	4af984a7	blueswir1	static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1855	1a2fb1c0	blueswir1	{
1856	2ea815ca	blueswir1	TCGv r_val, r_asi, r_size;
1857	1a2fb1c0	blueswir1
1858	4af984a7	blueswir1	gen_ld_asi(dst, addr, insn, 1, 0);
1859	1a2fb1c0	blueswir1
1860	2ea815ca	blueswir1	r_val = tcg_const_i64(0xffULL);
1861	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1862	2ea815ca	blueswir1	r_size = tcg_const_i32(1);
1863	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1864	2ea815ca	blueswir1	tcg_temp_free(r_size);
1865	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1866	2ea815ca	blueswir1	tcg_temp_free(r_val);
1867	1a2fb1c0	blueswir1	}
1868	1a2fb1c0	blueswir1	#endif
1869	1a2fb1c0	blueswir1
1870	9322a4bf	blueswir1	static inline TCGv get_src1(unsigned int insn, TCGv def)
1871	9322a4bf	blueswir1	{
1872	9322a4bf	blueswir1	TCGv r_rs1 = def;
1873	9322a4bf	blueswir1	unsigned int rs1;
1874	9322a4bf	blueswir1
1875	9322a4bf	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
1876	9322a4bf	blueswir1	if (rs1 == 0)
1877	5c6a0628	blueswir1	r_rs1 = tcg_const_tl(0); // XXX how to free?
1878	9322a4bf	blueswir1	else if (rs1 < 8)
1879	5c6a0628	blueswir1	r_rs1 = cpu_gregs[rs1];
1880	9322a4bf	blueswir1	else
1881	9322a4bf	blueswir1	tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1882	9322a4bf	blueswir1	return r_rs1;
1883	9322a4bf	blueswir1	}
1884	9322a4bf	blueswir1
1885	a49d9390	blueswir1	static inline TCGv get_src2(unsigned int insn, TCGv def)
1886	a49d9390	blueswir1	{
1887	a49d9390	blueswir1	TCGv r_rs2 = def;
1888	a49d9390	blueswir1	unsigned int rs2;
1889	a49d9390	blueswir1
1890	a49d9390	blueswir1	if (IS_IMM) { /* immediate */
1891	a49d9390	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
1892	2ea815ca	blueswir1	r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1893	a49d9390	blueswir1	} else { /* register */
1894	a49d9390	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
1895	a49d9390	blueswir1	if (rs2 == 0)
1896	2ea815ca	blueswir1	r_rs2 = tcg_const_tl(0); // XXX how to free?
1897	a49d9390	blueswir1	else if (rs2 < 8)
1898	a49d9390	blueswir1	r_rs2 = cpu_gregs[rs2];
1899	a49d9390	blueswir1	else
1900	a49d9390	blueswir1	tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1901	a49d9390	blueswir1	}
1902	a49d9390	blueswir1	return r_rs2;
1903	a49d9390	blueswir1	}
1904	a49d9390	blueswir1
1905	64a88d5d	blueswir1	#define CHECK_IU_FEATURE(dc, FEATURE) \
1906	5578ceab	blueswir1	if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1907	64a88d5d	blueswir1	goto illegal_insn;
1908	64a88d5d	blueswir1	#define CHECK_FPU_FEATURE(dc, FEATURE) \
1909	5578ceab	blueswir1	if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1910	64a88d5d	blueswir1	goto nfpu_insn;
1911	64a88d5d	blueswir1
1912	0bee699e	bellard	/* before an instruction, dc->pc must be static */
1913	cf495bcf	bellard	static void disas_sparc_insn(DisasContext * dc)
1914	cf495bcf	bellard	{
1915	cf495bcf	bellard	unsigned int insn, opc, rs1, rs2, rd;
1916	7a3f1944	bellard
1917	a8c768c0	blueswir1	if (unlikely(loglevel & CPU_LOG_TB_OP))
1918	a8c768c0	blueswir1	tcg_gen_debug_insn_start(dc->pc);
1919	0fa85d43	bellard	insn = ldl_code(dc->pc);
1920	cf495bcf	bellard	opc = GET_FIELD(insn, 0, 1);
1921	7a3f1944	bellard
1922	cf495bcf	bellard	rd = GET_FIELD(insn, 2, 6);
1923	6ae20372	blueswir1
1924	5c6a0628	blueswir1	cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1925	5c6a0628	blueswir1	cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1926	6ae20372	blueswir1
1927	cf495bcf	bellard	switch (opc) {
1928	0f8a249a	blueswir1	case 0: /* branches/sethi */
1929	0f8a249a	blueswir1	{
1930	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 9);
1931	0f8a249a	blueswir1	int32_t target;
1932	0f8a249a	blueswir1	switch (xop) {
1933	3475187d	bellard	#ifdef TARGET_SPARC64
1934	0f8a249a	blueswir1	case 0x1: /* V9 BPcc */
1935	0f8a249a	blueswir1	{
1936	0f8a249a	blueswir1	int cc;
1937	0f8a249a	blueswir1
1938	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 18);
1939	0f8a249a	blueswir1	target = sign_extend(target, 18);
1940	0f8a249a	blueswir1	target <<= 2;
1941	0f8a249a	blueswir1	cc = GET_FIELD_SP(insn, 20, 21);
1942	0f8a249a	blueswir1	if (cc == 0)
1943	6ae20372	blueswir1	do_branch(dc, target, insn, 0, cpu_cond);
1944	0f8a249a	blueswir1	else if (cc == 2)
1945	6ae20372	blueswir1	do_branch(dc, target, insn, 1, cpu_cond);
1946	0f8a249a	blueswir1	else
1947	0f8a249a	blueswir1	goto illegal_insn;
1948	0f8a249a	blueswir1	goto jmp_insn;
1949	0f8a249a	blueswir1	}
1950	0f8a249a	blueswir1	case 0x3: /* V9 BPr */
1951	0f8a249a	blueswir1	{
1952	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 13) \|
1953	13846e70	bellard	(GET_FIELD_SP(insn, 20, 21) << 14);
1954	0f8a249a	blueswir1	target = sign_extend(target, 16);
1955	0f8a249a	blueswir1	target <<= 2;
1956	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
1957	6ae20372	blueswir1	do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1958	0f8a249a	blueswir1	goto jmp_insn;
1959	0f8a249a	blueswir1	}
1960	0f8a249a	blueswir1	case 0x5: /* V9 FBPcc */
1961	0f8a249a	blueswir1	{
1962	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 20, 21);
1963	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
1964	a80dde08	bellard	goto jmp_insn;
1965	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 18);
1966	0f8a249a	blueswir1	target = sign_extend(target, 19);
1967	0f8a249a	blueswir1	target <<= 2;
1968	6ae20372	blueswir1	do_fbranch(dc, target, insn, cc, cpu_cond);
1969	0f8a249a	blueswir1	goto jmp_insn;
1970	0f8a249a	blueswir1	}
1971	a4d17f19	blueswir1	#else
1972	0f8a249a	blueswir1	case 0x7: /* CBN+x */
1973	0f8a249a	blueswir1	{
1974	0f8a249a	blueswir1	goto ncp_insn;
1975	0f8a249a	blueswir1	}
1976	0f8a249a	blueswir1	#endif
1977	0f8a249a	blueswir1	case 0x2: /* BN+x */
1978	0f8a249a	blueswir1	{
1979	0f8a249a	blueswir1	target = GET_FIELD(insn, 10, 31);
1980	0f8a249a	blueswir1	target = sign_extend(target, 22);
1981	0f8a249a	blueswir1	target <<= 2;
1982	6ae20372	blueswir1	do_branch(dc, target, insn, 0, cpu_cond);
1983	0f8a249a	blueswir1	goto jmp_insn;
1984	0f8a249a	blueswir1	}
1985	0f8a249a	blueswir1	case 0x6: /* FBN+x */
1986	0f8a249a	blueswir1	{
1987	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
1988	a80dde08	bellard	goto jmp_insn;
1989	0f8a249a	blueswir1	target = GET_FIELD(insn, 10, 31);
1990	0f8a249a	blueswir1	target = sign_extend(target, 22);
1991	0f8a249a	blueswir1	target <<= 2;
1992	6ae20372	blueswir1	do_fbranch(dc, target, insn, 0, cpu_cond);
1993	0f8a249a	blueswir1	goto jmp_insn;
1994	0f8a249a	blueswir1	}
1995	0f8a249a	blueswir1	case 0x4: /* SETHI */
1996	0f8a249a	blueswir1	if (rd) { // nop
1997	0f8a249a	blueswir1	uint32_t value = GET_FIELD(insn, 10, 31);
1998	2ea815ca	blueswir1	TCGv r_const;
1999	2ea815ca	blueswir1
2000	2ea815ca	blueswir1	r_const = tcg_const_tl(value << 10);
2001	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2002	2ea815ca	blueswir1	tcg_temp_free(r_const);
2003	0f8a249a	blueswir1	}
2004	0f8a249a	blueswir1	break;
2005	0f8a249a	blueswir1	case 0x0: /* UNIMPL */
2006	0f8a249a	blueswir1	default:
2007	3475187d	bellard	goto illegal_insn;
2008	0f8a249a	blueswir1	}
2009	0f8a249a	blueswir1	break;
2010	0f8a249a	blueswir1	}
2011	0f8a249a	blueswir1	break;
2012	cf495bcf	bellard	case 1:
2013	0f8a249a	blueswir1	/CALL/ {
2014	0f8a249a	blueswir1	target_long target = GET_FIELDs(insn, 2, 31) << 2;
2015	2ea815ca	blueswir1	TCGv r_const;
2016	cf495bcf	bellard
2017	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
2018	2ea815ca	blueswir1	gen_movl_TN_reg(15, r_const);
2019	2ea815ca	blueswir1	tcg_temp_free(r_const);
2020	0f8a249a	blueswir1	target += dc->pc;
2021	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
2022	0f8a249a	blueswir1	dc->npc = target;
2023	0f8a249a	blueswir1	}
2024	0f8a249a	blueswir1	goto jmp_insn;
2025	0f8a249a	blueswir1	case 2: /* FPU & Logical Operations */
2026	0f8a249a	blueswir1	{
2027	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 12);
2028	0f8a249a	blueswir1	if (xop == 0x3a) { /* generate trap */
2029	cf495bcf	bellard	int cond;
2030	3475187d	bellard
2031	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2032	0f8a249a	blueswir1	if (IS_IMM) {
2033	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 25, 31);
2034	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2035	cf495bcf	bellard	} else {
2036	cf495bcf	bellard	rs2 = GET_FIELD(insn, 27, 31);
2037	0f8a249a	blueswir1	if (rs2 != 0) {
2038	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2039	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2040	6f551262	blueswir1	} else
2041	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
2042	cf495bcf	bellard	}
2043	cf495bcf	bellard	cond = GET_FIELD(insn, 3, 6);
2044	cf495bcf	bellard	if (cond == 0x8) {
2045	6ae20372	blueswir1	save_state(dc, cpu_cond);
2046	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_trap, cpu_dst);
2047	af7bf89b	bellard	} else if (cond != 0) {
2048	748b9d8e	blueswir1	TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2049	3475187d	bellard	#ifdef TARGET_SPARC64
2050	0f8a249a	blueswir1	/* V9 icc/xcc */
2051	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 11, 12);
2052	748b9d8e	blueswir1
2053	6ae20372	blueswir1	save_state(dc, cpu_cond);
2054	0f8a249a	blueswir1	if (cc == 0)
2055	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
2056	0f8a249a	blueswir1	else if (cc == 2)
2057	748b9d8e	blueswir1	gen_cond(r_cond, 1, cond);
2058	0f8a249a	blueswir1	else
2059	0f8a249a	blueswir1	goto illegal_insn;
2060	3475187d	bellard	#else
2061	6ae20372	blueswir1	save_state(dc, cpu_cond);
2062	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
2063	3475187d	bellard	#endif
2064	6ae20372	blueswir1	tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2065	2ea815ca	blueswir1	tcg_temp_free(r_cond);
2066	cf495bcf	bellard	}
2067	a80dde08	bellard	gen_op_next_insn();
2068	57fec1fe	bellard	tcg_gen_exit_tb(0);
2069	a80dde08	bellard	dc->is_br = 1;
2070	a80dde08	bellard	goto jmp_insn;
2071	cf495bcf	bellard	} else if (xop == 0x28) {
2072	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
2073	cf495bcf	bellard	switch(rs1) {
2074	cf495bcf	bellard	case 0: /* rdy */
2075	65fe7b09	blueswir1	#ifndef TARGET_SPARC64
2076	65fe7b09	blueswir1	case 0x01 ... 0x0e: /* undefined in the SPARCv8
2077	65fe7b09	blueswir1	manual, rdy on the microSPARC
2078	65fe7b09	blueswir1	II */
2079	65fe7b09	blueswir1	case 0x0f: /* stbar in the SPARCv8 manual,
2080	65fe7b09	blueswir1	rdy on the microSPARC II */
2081	65fe7b09	blueswir1	case 0x10 ... 0x1f: /* implementation-dependent in the
2082	65fe7b09	blueswir1	SPARCv8 manual, rdy on the
2083	65fe7b09	blueswir1	microSPARC II */
2084	65fe7b09	blueswir1	#endif
2085	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2086	77f193da	blueswir1	offsetof(CPUSPARCState, y));
2087	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2088	cf495bcf	bellard	break;
2089	3475187d	bellard	#ifdef TARGET_SPARC64
2090	0f8a249a	blueswir1	case 0x2: /* V9 rdccr */
2091	6ae20372	blueswir1	tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2092	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2093	3475187d	bellard	break;
2094	0f8a249a	blueswir1	case 0x3: /* V9 rdasi */
2095	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2096	77f193da	blueswir1	offsetof(CPUSPARCState, asi));
2097	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2098	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2099	3475187d	bellard	break;
2100	0f8a249a	blueswir1	case 0x4: /* V9 rdtick */
2101	ccd4a219	blueswir1	{
2102	ccd4a219	blueswir1	TCGv r_tickptr;
2103	ccd4a219	blueswir1
2104	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2105	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2106	ccd4a219	blueswir1	offsetof(CPUState, tick));
2107	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2108	ccd4a219	blueswir1	r_tickptr);
2109	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2110	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2111	ccd4a219	blueswir1	}
2112	3475187d	bellard	break;
2113	0f8a249a	blueswir1	case 0x5: /* V9 rdpc */
2114	2ea815ca	blueswir1	{
2115	2ea815ca	blueswir1	TCGv r_const;
2116	2ea815ca	blueswir1
2117	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
2118	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2119	2ea815ca	blueswir1	tcg_temp_free(r_const);
2120	2ea815ca	blueswir1	}
2121	0f8a249a	blueswir1	break;
2122	0f8a249a	blueswir1	case 0x6: /* V9 rdfprs */
2123	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2124	77f193da	blueswir1	offsetof(CPUSPARCState, fprs));
2125	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2126	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2127	3475187d	bellard	break;
2128	65fe7b09	blueswir1	case 0xf: /* V9 membar */
2129	65fe7b09	blueswir1	break; /* no effect */
2130	0f8a249a	blueswir1	case 0x13: /* Graphics Status */
2131	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2132	725cb90b	bellard	goto jmp_insn;
2133	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2134	77f193da	blueswir1	offsetof(CPUSPARCState, gsr));
2135	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2136	725cb90b	bellard	break;
2137	0f8a249a	blueswir1	case 0x17: /* Tick compare */
2138	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2139	77f193da	blueswir1	offsetof(CPUSPARCState, tick_cmpr));
2140	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2141	83469015	bellard	break;
2142	0f8a249a	blueswir1	case 0x18: /* System tick */
2143	ccd4a219	blueswir1	{
2144	ccd4a219	blueswir1	TCGv r_tickptr;
2145	ccd4a219	blueswir1
2146	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2147	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2148	ccd4a219	blueswir1	offsetof(CPUState, stick));
2149	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2150	ccd4a219	blueswir1	r_tickptr);
2151	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2152	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2153	ccd4a219	blueswir1	}
2154	83469015	bellard	break;
2155	0f8a249a	blueswir1	case 0x19: /* System tick compare */
2156	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2157	77f193da	blueswir1	offsetof(CPUSPARCState, stick_cmpr));
2158	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2159	83469015	bellard	break;
2160	0f8a249a	blueswir1	case 0x10: /* Performance Control */
2161	0f8a249a	blueswir1	case 0x11: /* Performance Instrumentation Counter */
2162	0f8a249a	blueswir1	case 0x12: /* Dispatch Control */
2163	0f8a249a	blueswir1	case 0x14: /* Softint set, WO */
2164	0f8a249a	blueswir1	case 0x15: /* Softint clear, WO */
2165	0f8a249a	blueswir1	case 0x16: /* Softint write */
2166	3475187d	bellard	#endif
2167	3475187d	bellard	default:
2168	cf495bcf	bellard	goto illegal_insn;
2169	cf495bcf	bellard	}
2170	e8af50a3	bellard	#if !defined(CONFIG_USER_ONLY)
2171	e9ebed4d	blueswir1	} else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2172	3475187d	bellard	#ifndef TARGET_SPARC64
2173	0f8a249a	blueswir1	if (!supervisor(dc))
2174	0f8a249a	blueswir1	goto priv_insn;
2175	6ae20372	blueswir1	tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2176	e9ebed4d	blueswir1	#else
2177	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
2178	e9ebed4d	blueswir1	if (!hypervisor(dc))
2179	e9ebed4d	blueswir1	goto priv_insn;
2180	e9ebed4d	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
2181	e9ebed4d	blueswir1	switch (rs1) {
2182	e9ebed4d	blueswir1	case 0: // hpstate
2183	e9ebed4d	blueswir1	// gen_op_rdhpstate();
2184	e9ebed4d	blueswir1	break;
2185	e9ebed4d	blueswir1	case 1: // htstate
2186	e9ebed4d	blueswir1	// gen_op_rdhtstate();
2187	e9ebed4d	blueswir1	break;
2188	e9ebed4d	blueswir1	case 3: // hintp
2189	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2190	77f193da	blueswir1	offsetof(CPUSPARCState, hintp));
2191	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2192	e9ebed4d	blueswir1	break;
2193	e9ebed4d	blueswir1	case 5: // htba
2194	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2195	77f193da	blueswir1	offsetof(CPUSPARCState, htba));
2196	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2197	e9ebed4d	blueswir1	break;
2198	e9ebed4d	blueswir1	case 6: // hver
2199	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2200	77f193da	blueswir1	offsetof(CPUSPARCState, hver));
2201	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2202	e9ebed4d	blueswir1	break;
2203	e9ebed4d	blueswir1	case 31: // hstick_cmpr
2204	8d7d8c4b	blueswir1	tcg_gen_ld_tl(cpu_dst, cpu_env,
2205	8d7d8c4b	blueswir1	offsetof(CPUSPARCState, hstick_cmpr));
2206	e9ebed4d	blueswir1	break;
2207	e9ebed4d	blueswir1	default:
2208	e9ebed4d	blueswir1	goto illegal_insn;
2209	e9ebed4d	blueswir1	}
2210	e9ebed4d	blueswir1	#endif
2211	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2212	e8af50a3	bellard	break;
2213	3475187d	bellard	} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2214	0f8a249a	blueswir1	if (!supervisor(dc))
2215	0f8a249a	blueswir1	goto priv_insn;
2216	3475187d	bellard	#ifdef TARGET_SPARC64
2217	3475187d	bellard	rs1 = GET_FIELD(insn, 13, 17);
2218	0f8a249a	blueswir1	switch (rs1) {
2219	0f8a249a	blueswir1	case 0: // tpc
2220	375ee38b	blueswir1	{
2221	375ee38b	blueswir1	TCGv r_tsptr;
2222	375ee38b	blueswir1
2223	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2224	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2225	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2226	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2227	375ee38b	blueswir1	offsetof(trap_state, tpc));
2228	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2229	375ee38b	blueswir1	}
2230	0f8a249a	blueswir1	break;
2231	0f8a249a	blueswir1	case 1: // tnpc
2232	375ee38b	blueswir1	{
2233	375ee38b	blueswir1	TCGv r_tsptr;
2234	375ee38b	blueswir1
2235	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2236	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2237	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2238	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2239	375ee38b	blueswir1	offsetof(trap_state, tnpc));
2240	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2241	375ee38b	blueswir1	}
2242	0f8a249a	blueswir1	break;
2243	0f8a249a	blueswir1	case 2: // tstate
2244	375ee38b	blueswir1	{
2245	375ee38b	blueswir1	TCGv r_tsptr;
2246	375ee38b	blueswir1
2247	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2248	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2249	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2250	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2251	375ee38b	blueswir1	offsetof(trap_state, tstate));
2252	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2253	375ee38b	blueswir1	}
2254	0f8a249a	blueswir1	break;
2255	0f8a249a	blueswir1	case 3: // tt
2256	375ee38b	blueswir1	{
2257	375ee38b	blueswir1	TCGv r_tsptr;
2258	375ee38b	blueswir1
2259	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2260	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2261	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2262	ece43b8d	blueswir1	tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2263	375ee38b	blueswir1	offsetof(trap_state, tt));
2264	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2265	375ee38b	blueswir1	}
2266	0f8a249a	blueswir1	break;
2267	0f8a249a	blueswir1	case 4: // tick
2268	ccd4a219	blueswir1	{
2269	ccd4a219	blueswir1	TCGv r_tickptr;
2270	ccd4a219	blueswir1
2271	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2272	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2273	ccd4a219	blueswir1	offsetof(CPUState, tick));
2274	ece43b8d	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2275	ccd4a219	blueswir1	r_tickptr);
2276	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2277	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2278	ccd4a219	blueswir1	}
2279	0f8a249a	blueswir1	break;
2280	0f8a249a	blueswir1	case 5: // tba
2281	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2282	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
2283	0f8a249a	blueswir1	break;
2284	0f8a249a	blueswir1	case 6: // pstate
2285	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2286	77f193da	blueswir1	offsetof(CPUSPARCState, pstate));
2287	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2288	0f8a249a	blueswir1	break;
2289	0f8a249a	blueswir1	case 7: // tl
2290	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2291	77f193da	blueswir1	offsetof(CPUSPARCState, tl));
2292	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2293	0f8a249a	blueswir1	break;
2294	0f8a249a	blueswir1	case 8: // pil
2295	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2296	77f193da	blueswir1	offsetof(CPUSPARCState, psrpil));
2297	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2298	0f8a249a	blueswir1	break;
2299	0f8a249a	blueswir1	case 9: // cwp
2300	ece43b8d	blueswir1	tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2301	0f8a249a	blueswir1	break;
2302	0f8a249a	blueswir1	case 10: // cansave
2303	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2304	77f193da	blueswir1	offsetof(CPUSPARCState, cansave));
2305	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2306	0f8a249a	blueswir1	break;
2307	0f8a249a	blueswir1	case 11: // canrestore
2308	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2309	77f193da	blueswir1	offsetof(CPUSPARCState, canrestore));
2310	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2311	0f8a249a	blueswir1	break;
2312	0f8a249a	blueswir1	case 12: // cleanwin
2313	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2314	77f193da	blueswir1	offsetof(CPUSPARCState, cleanwin));
2315	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2316	0f8a249a	blueswir1	break;
2317	0f8a249a	blueswir1	case 13: // otherwin
2318	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2319	77f193da	blueswir1	offsetof(CPUSPARCState, otherwin));
2320	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2321	0f8a249a	blueswir1	break;
2322	0f8a249a	blueswir1	case 14: // wstate
2323	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2324	77f193da	blueswir1	offsetof(CPUSPARCState, wstate));
2325	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2326	0f8a249a	blueswir1	break;
2327	e9ebed4d	blueswir1	case 16: // UA2005 gl
2328	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, GL);
2329	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2330	77f193da	blueswir1	offsetof(CPUSPARCState, gl));
2331	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2332	e9ebed4d	blueswir1	break;
2333	e9ebed4d	blueswir1	case 26: // UA2005 strand status
2334	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
2335	e9ebed4d	blueswir1	if (!hypervisor(dc))
2336	e9ebed4d	blueswir1	goto priv_insn;
2337	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2338	77f193da	blueswir1	offsetof(CPUSPARCState, ssr));
2339	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2340	e9ebed4d	blueswir1	break;
2341	0f8a249a	blueswir1	case 31: // ver
2342	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2343	77f193da	blueswir1	offsetof(CPUSPARCState, version));
2344	0f8a249a	blueswir1	break;
2345	0f8a249a	blueswir1	case 15: // fq
2346	0f8a249a	blueswir1	default:
2347	0f8a249a	blueswir1	goto illegal_insn;
2348	0f8a249a	blueswir1	}
2349	3475187d	bellard	#else
2350	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2351	77f193da	blueswir1	offsetof(CPUSPARCState, wim));
2352	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2353	3475187d	bellard	#endif
2354	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2355	e8af50a3	bellard	break;
2356	3475187d	bellard	} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2357	3475187d	bellard	#ifdef TARGET_SPARC64
2358	c5f2f668	blueswir1	save_state(dc, cpu_cond);
2359	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_flushw);
2360	3475187d	bellard	#else
2361	0f8a249a	blueswir1	if (!supervisor(dc))
2362	0f8a249a	blueswir1	goto priv_insn;
2363	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2364	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2365	3475187d	bellard	#endif
2366	e8af50a3	bellard	break;
2367	e8af50a3	bellard	#endif
2368	0f8a249a	blueswir1	} else if (xop == 0x34) { /* FPU Operations */
2369	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2370	a80dde08	bellard	goto jmp_insn;
2371	0f8a249a	blueswir1	gen_op_clear_ieee_excp_and_FTT();
2372	e8af50a3	bellard	rs1 = GET_FIELD(insn, 13, 17);
2373	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2374	0f8a249a	blueswir1	xop = GET_FIELD(insn, 18, 26);
2375	0f8a249a	blueswir1	switch (xop) {
2376	0f8a249a	blueswir1	case 0x1: /* fmovs */
2377	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs2);
2378	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2379	0f8a249a	blueswir1	break;
2380	0f8a249a	blueswir1	case 0x5: /* fnegs */
2381	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2382	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegs);
2383	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2384	0f8a249a	blueswir1	break;
2385	0f8a249a	blueswir1	case 0x9: /* fabss */
2386	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2387	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabss);
2388	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2389	0f8a249a	blueswir1	break;
2390	0f8a249a	blueswir1	case 0x29: /* fsqrts */
2391	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FSQRT);
2392	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2393	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2394	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrts);
2395	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2396	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2397	0f8a249a	blueswir1	break;
2398	0f8a249a	blueswir1	case 0x2a: /* fsqrtd */
2399	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FSQRT);
2400	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2401	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2402	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrtd);
2403	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2404	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2405	0f8a249a	blueswir1	break;
2406	0f8a249a	blueswir1	case 0x2b: /* fsqrtq */
2407	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2408	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2409	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2410	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrtq);
2411	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2412	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2413	1f587329	blueswir1	break;
2414	0f8a249a	blueswir1	case 0x41:
2415	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2416	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2417	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2418	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fadds);
2419	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2420	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2421	0f8a249a	blueswir1	break;
2422	0f8a249a	blueswir1	case 0x42:
2423	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2424	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2425	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2426	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faddd);
2427	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2428	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2429	0f8a249a	blueswir1	break;
2430	0f8a249a	blueswir1	case 0x43: /* faddq */
2431	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2432	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2433	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2434	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2435	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faddq);
2436	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2437	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2438	1f587329	blueswir1	break;
2439	0f8a249a	blueswir1	case 0x45:
2440	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2441	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2442	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2443	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubs);
2444	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2445	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2446	0f8a249a	blueswir1	break;
2447	0f8a249a	blueswir1	case 0x46:
2448	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2449	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2450	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2451	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubd);
2452	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2453	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2454	0f8a249a	blueswir1	break;
2455	0f8a249a	blueswir1	case 0x47: /* fsubq */
2456	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2457	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2458	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2459	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2460	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubq);
2461	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2462	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2463	1f587329	blueswir1	break;
2464	64a88d5d	blueswir1	case 0x49: /* fmuls */
2465	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2466	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2467	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2468	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2469	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuls);
2470	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2471	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2472	0f8a249a	blueswir1	break;
2473	64a88d5d	blueswir1	case 0x4a: /* fmuld */
2474	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2475	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2476	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2477	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2478	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld);
2479	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2480	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2481	0f8a249a	blueswir1	break;
2482	0f8a249a	blueswir1	case 0x4b: /* fmulq */
2483	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2484	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2485	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2486	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2487	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2488	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmulq);
2489	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2490	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2491	1f587329	blueswir1	break;
2492	0f8a249a	blueswir1	case 0x4d:
2493	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2494	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2495	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2496	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivs);
2497	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2498	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2499	0f8a249a	blueswir1	break;
2500	0f8a249a	blueswir1	case 0x4e:
2501	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2502	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2503	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2504	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivd);
2505	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2506	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2507	0f8a249a	blueswir1	break;
2508	0f8a249a	blueswir1	case 0x4f: /* fdivq */
2509	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2510	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2511	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2512	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2513	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivq);
2514	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2515	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2516	1f587329	blueswir1	break;
2517	0f8a249a	blueswir1	case 0x69:
2518	e30b4678	blueswir1	CHECK_FPU_FEATURE(dc, FSMULD);
2519	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2520	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2521	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2522	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsmuld);
2523	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2524	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2525	0f8a249a	blueswir1	break;
2526	0f8a249a	blueswir1	case 0x6e: /* fdmulq */
2527	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2528	1f587329	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2529	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2530	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2531	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdmulq);
2532	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2533	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2534	1f587329	blueswir1	break;
2535	0f8a249a	blueswir1	case 0xc4:
2536	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2537	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2538	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitos);
2539	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2540	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2541	0f8a249a	blueswir1	break;
2542	0f8a249a	blueswir1	case 0xc6:
2543	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2544	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2545	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtos);
2546	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2547	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2548	0f8a249a	blueswir1	break;
2549	0f8a249a	blueswir1	case 0xc7: /* fqtos */
2550	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2551	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2552	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2553	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtos);
2554	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2555	1f587329	blueswir1	gen_op_store_FT0_fpr(rd);
2556	1f587329	blueswir1	break;
2557	0f8a249a	blueswir1	case 0xc8:
2558	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2559	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitod);
2560	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2561	0f8a249a	blueswir1	break;
2562	0f8a249a	blueswir1	case 0xc9:
2563	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2564	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstod);
2565	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2566	0f8a249a	blueswir1	break;
2567	0f8a249a	blueswir1	case 0xcb: /* fqtod */
2568	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2569	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2570	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2571	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtod);
2572	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2573	1f587329	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2574	1f587329	blueswir1	break;
2575	0f8a249a	blueswir1	case 0xcc: /* fitoq */
2576	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2577	1f587329	blueswir1	gen_op_load_fpr_FT1(rs2);
2578	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitoq);
2579	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2580	1f587329	blueswir1	break;
2581	0f8a249a	blueswir1	case 0xcd: /* fstoq */
2582	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2583	1f587329	blueswir1	gen_op_load_fpr_FT1(rs2);
2584	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstoq);
2585	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2586	1f587329	blueswir1	break;
2587	0f8a249a	blueswir1	case 0xce: /* fdtoq */
2588	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2589	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2590	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtoq);
2591	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2592	1f587329	blueswir1	break;
2593	0f8a249a	blueswir1	case 0xd1:
2594	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2595	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2596	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstoi);
2597	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2598	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2599	0f8a249a	blueswir1	break;
2600	0f8a249a	blueswir1	case 0xd2:
2601	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2602	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2603	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtoi);
2604	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2605	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2606	0f8a249a	blueswir1	break;
2607	0f8a249a	blueswir1	case 0xd3: /* fqtoi */
2608	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2609	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2610	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2611	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtoi);
2612	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2613	1f587329	blueswir1	gen_op_store_FT0_fpr(rd);
2614	1f587329	blueswir1	break;
2615	3475187d	bellard	#ifdef TARGET_SPARC64
2616	0f8a249a	blueswir1	case 0x2: /* V9 fmovd */
2617	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
2618	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2619	0f8a249a	blueswir1	break;
2620	1f587329	blueswir1	case 0x3: /* V9 fmovq */
2621	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2622	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs2));
2623	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2624	1f587329	blueswir1	break;
2625	0f8a249a	blueswir1	case 0x6: /* V9 fnegd */
2626	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2627	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegd);
2628	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2629	0f8a249a	blueswir1	break;
2630	1f587329	blueswir1	case 0x7: /* V9 fnegq */
2631	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2632	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2633	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegq);
2634	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2635	1f587329	blueswir1	break;
2636	0f8a249a	blueswir1	case 0xa: /* V9 fabsd */
2637	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2638	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabsd);
2639	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2640	0f8a249a	blueswir1	break;
2641	1f587329	blueswir1	case 0xb: /* V9 fabsq */
2642	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2643	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2644	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabsq);
2645	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2646	1f587329	blueswir1	break;
2647	0f8a249a	blueswir1	case 0x81: /* V9 fstox */
2648	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2649	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2650	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstox);
2651	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2652	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2653	0f8a249a	blueswir1	break;
2654	0f8a249a	blueswir1	case 0x82: /* V9 fdtox */
2655	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2656	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2657	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtox);
2658	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2659	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2660	0f8a249a	blueswir1	break;
2661	1f587329	blueswir1	case 0x83: /* V9 fqtox */
2662	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2663	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2664	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2665	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtox);
2666	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2667	1f587329	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2668	1f587329	blueswir1	break;
2669	0f8a249a	blueswir1	case 0x84: /* V9 fxtos */
2670	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2671	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2672	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtos);
2673	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2674	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2675	0f8a249a	blueswir1	break;
2676	0f8a249a	blueswir1	case 0x88: /* V9 fxtod */
2677	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2678	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2679	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtod);
2680	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2681	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2682	0f8a249a	blueswir1	break;
2683	0f8a249a	blueswir1	case 0x8c: /* V9 fxtoq */
2684	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2685	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2686	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2687	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtoq);
2688	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2689	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2690	1f587329	blueswir1	break;
2691	1f587329	blueswir1	#endif
2692	0f8a249a	blueswir1	default:
2693	0f8a249a	blueswir1	goto illegal_insn;
2694	0f8a249a	blueswir1	}
2695	0f8a249a	blueswir1	} else if (xop == 0x35) { /* FPU Operations */
2696	3475187d	bellard	#ifdef TARGET_SPARC64
2697	0f8a249a	blueswir1	int cond;
2698	3475187d	bellard	#endif
2699	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2700	a80dde08	bellard	goto jmp_insn;
2701	0f8a249a	blueswir1	gen_op_clear_ieee_excp_and_FTT();
2702	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
2703	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2704	0f8a249a	blueswir1	xop = GET_FIELD(insn, 18, 26);
2705	3475187d	bellard	#ifdef TARGET_SPARC64
2706	0f8a249a	blueswir1	if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2707	dcf24905	blueswir1	int l1;
2708	dcf24905	blueswir1
2709	dcf24905	blueswir1	l1 = gen_new_label();
2710	0f8a249a	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2711	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2712	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2713	cb63669a	pbrook	0, l1);
2714	19f329ad	blueswir1	gen_op_load_fpr_FT0(rs2);
2715	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2716	dcf24905	blueswir1	gen_set_label(l1);
2717	0f8a249a	blueswir1	break;
2718	0f8a249a	blueswir1	} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2719	dcf24905	blueswir1	int l1;
2720	dcf24905	blueswir1
2721	dcf24905	blueswir1	l1 = gen_new_label();
2722	0f8a249a	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2723	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2724	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2725	cb63669a	pbrook	0, l1);
2726	19f329ad	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
2727	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2728	dcf24905	blueswir1	gen_set_label(l1);
2729	0f8a249a	blueswir1	break;
2730	0f8a249a	blueswir1	} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2731	dcf24905	blueswir1	int l1;
2732	dcf24905	blueswir1
2733	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2734	dcf24905	blueswir1	l1 = gen_new_label();
2735	1f587329	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2736	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2737	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2738	cb63669a	pbrook	0, l1);
2739	19f329ad	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs2));
2740	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2741	dcf24905	blueswir1	gen_set_label(l1);
2742	1f587329	blueswir1	break;
2743	0f8a249a	blueswir1	}
2744	0f8a249a	blueswir1	#endif
2745	0f8a249a	blueswir1	switch (xop) {
2746	3475187d	bellard	#ifdef TARGET_SPARC64
2747	19f329ad	blueswir1	#define FMOVCC(size_FDQ, fcc) \
2748	19f329ad	blueswir1	{ \
2749	0425bee5	blueswir1	TCGv r_cond; \
2750	19f329ad	blueswir1	int l1; \
2751	19f329ad	blueswir1	\
2752	19f329ad	blueswir1	l1 = gen_new_label(); \
2753	19f329ad	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL); \
2754	19f329ad	blueswir1	cond = GET_FIELD_SP(insn, 14, 17); \
2755	19f329ad	blueswir1	gen_fcond(r_cond, fcc, cond); \
2756	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2757	cb63669a	pbrook	0, l1); \
2758	77f193da	blueswir1	glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2759	77f193da	blueswir1	(glue(size_FDQ, FPREG(rs2))); \
2760	77f193da	blueswir1	glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2761	77f193da	blueswir1	(glue(size_FDQ, FPREG(rd))); \
2762	19f329ad	blueswir1	gen_set_label(l1); \
2763	2ea815ca	blueswir1	tcg_temp_free(r_cond); \
2764	19f329ad	blueswir1	}
2765	0f8a249a	blueswir1	case 0x001: /* V9 fmovscc %fcc0 */
2766	19f329ad	blueswir1	FMOVCC(F, 0);
2767	0f8a249a	blueswir1	break;
2768	0f8a249a	blueswir1	case 0x002: /* V9 fmovdcc %fcc0 */
2769	19f329ad	blueswir1	FMOVCC(D, 0);
2770	0f8a249a	blueswir1	break;
2771	0f8a249a	blueswir1	case 0x003: /* V9 fmovqcc %fcc0 */
2772	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2773	19f329ad	blueswir1	FMOVCC(Q, 0);
2774	1f587329	blueswir1	break;
2775	0f8a249a	blueswir1	case 0x041: /* V9 fmovscc %fcc1 */
2776	19f329ad	blueswir1	FMOVCC(F, 1);
2777	0f8a249a	blueswir1	break;
2778	0f8a249a	blueswir1	case 0x042: /* V9 fmovdcc %fcc1 */
2779	19f329ad	blueswir1	FMOVCC(D, 1);
2780	0f8a249a	blueswir1	break;
2781	0f8a249a	blueswir1	case 0x043: /* V9 fmovqcc %fcc1 */
2782	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2783	19f329ad	blueswir1	FMOVCC(Q, 1);
2784	1f587329	blueswir1	break;
2785	0f8a249a	blueswir1	case 0x081: /* V9 fmovscc %fcc2 */
2786	19f329ad	blueswir1	FMOVCC(F, 2);
2787	0f8a249a	blueswir1	break;
2788	0f8a249a	blueswir1	case 0x082: /* V9 fmovdcc %fcc2 */
2789	19f329ad	blueswir1	FMOVCC(D, 2);
2790	0f8a249a	blueswir1	break;
2791	0f8a249a	blueswir1	case 0x083: /* V9 fmovqcc %fcc2 */
2792	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2793	19f329ad	blueswir1	FMOVCC(Q, 2);
2794	1f587329	blueswir1	break;
2795	0f8a249a	blueswir1	case 0x0c1: /* V9 fmovscc %fcc3 */
2796	19f329ad	blueswir1	FMOVCC(F, 3);
2797	0f8a249a	blueswir1	break;
2798	0f8a249a	blueswir1	case 0x0c2: /* V9 fmovdcc %fcc3 */
2799	19f329ad	blueswir1	FMOVCC(D, 3);
2800	0f8a249a	blueswir1	break;
2801	0f8a249a	blueswir1	case 0x0c3: /* V9 fmovqcc %fcc3 */
2802	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2803	19f329ad	blueswir1	FMOVCC(Q, 3);
2804	1f587329	blueswir1	break;
2805	19f329ad	blueswir1	#undef FMOVCC
2806	19f329ad	blueswir1	#define FMOVCC(size_FDQ, icc) \
2807	19f329ad	blueswir1	{ \
2808	0425bee5	blueswir1	TCGv r_cond; \
2809	19f329ad	blueswir1	int l1; \
2810	19f329ad	blueswir1	\
2811	19f329ad	blueswir1	l1 = gen_new_label(); \
2812	19f329ad	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL); \
2813	19f329ad	blueswir1	cond = GET_FIELD_SP(insn, 14, 17); \
2814	19f329ad	blueswir1	gen_cond(r_cond, icc, cond); \
2815	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2816	cb63669a	pbrook	0, l1); \
2817	77f193da	blueswir1	glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2818	77f193da	blueswir1	(glue(size_FDQ, FPREG(rs2))); \
2819	77f193da	blueswir1	glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2820	77f193da	blueswir1	(glue(size_FDQ, FPREG(rd))); \
2821	19f329ad	blueswir1	gen_set_label(l1); \
2822	2ea815ca	blueswir1	tcg_temp_free(r_cond); \
2823	19f329ad	blueswir1	}
2824	19f329ad	blueswir1
2825	0f8a249a	blueswir1	case 0x101: /* V9 fmovscc %icc */
2826	19f329ad	blueswir1	FMOVCC(F, 0);
2827	0f8a249a	blueswir1	break;
2828	0f8a249a	blueswir1	case 0x102: /* V9 fmovdcc %icc */
2829	19f329ad	blueswir1	FMOVCC(D, 0);
2830	0f8a249a	blueswir1	case 0x103: /* V9 fmovqcc %icc */
2831	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2832	64a88d5d	blueswir1	FMOVCC(Q, 0);
2833	1f587329	blueswir1	break;
2834	0f8a249a	blueswir1	case 0x181: /* V9 fmovscc %xcc */
2835	19f329ad	blueswir1	FMOVCC(F, 1);
2836	0f8a249a	blueswir1	break;
2837	0f8a249a	blueswir1	case 0x182: /* V9 fmovdcc %xcc */
2838	19f329ad	blueswir1	FMOVCC(D, 1);
2839	0f8a249a	blueswir1	break;
2840	0f8a249a	blueswir1	case 0x183: /* V9 fmovqcc %xcc */
2841	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2842	19f329ad	blueswir1	FMOVCC(Q, 1);
2843	1f587329	blueswir1	break;
2844	19f329ad	blueswir1	#undef FMOVCC
2845	1f587329	blueswir1	#endif
2846	1f587329	blueswir1	case 0x51: /* fcmps, V9 %fcc */
2847	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2848	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2849	7e8c2b6c	blueswir1	gen_op_fcmps(rd & 3);
2850	0f8a249a	blueswir1	break;
2851	1f587329	blueswir1	case 0x52: /* fcmpd, V9 %fcc */
2852	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2853	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2854	7e8c2b6c	blueswir1	gen_op_fcmpd(rd & 3);
2855	0f8a249a	blueswir1	break;
2856	1f587329	blueswir1	case 0x53: /* fcmpq, V9 %fcc */
2857	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2858	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2859	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2860	7e8c2b6c	blueswir1	gen_op_fcmpq(rd & 3);
2861	1f587329	blueswir1	break;
2862	0f8a249a	blueswir1	case 0x55: /* fcmpes, V9 %fcc */
2863	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2864	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2865	7e8c2b6c	blueswir1	gen_op_fcmpes(rd & 3);
2866	0f8a249a	blueswir1	break;
2867	0f8a249a	blueswir1	case 0x56: /* fcmped, V9 %fcc */
2868	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2869	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2870	7e8c2b6c	blueswir1	gen_op_fcmped(rd & 3);
2871	0f8a249a	blueswir1	break;
2872	1f587329	blueswir1	case 0x57: /* fcmpeq, V9 %fcc */
2873	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2874	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2875	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2876	7e8c2b6c	blueswir1	gen_op_fcmpeq(rd & 3);
2877	1f587329	blueswir1	break;
2878	0f8a249a	blueswir1	default:
2879	0f8a249a	blueswir1	goto illegal_insn;
2880	0f8a249a	blueswir1	}
2881	0f8a249a	blueswir1	} else if (xop == 0x2) {
2882	0f8a249a	blueswir1	// clr/mov shortcut
2883	e80cfcfc	bellard
2884	e80cfcfc	bellard	rs1 = GET_FIELD(insn, 13, 17);
2885	0f8a249a	blueswir1	if (rs1 == 0) {
2886	1a2fb1c0	blueswir1	// or %g0, x, y -> mov T0, x; mov y, T0
2887	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2888	2ea815ca	blueswir1	TCGv r_const;
2889	2ea815ca	blueswir1
2890	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
2891	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
2892	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2893	2ea815ca	blueswir1	tcg_temp_free(r_const);
2894	0f8a249a	blueswir1	} else { /* register */
2895	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2896	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_dst);
2897	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2898	0f8a249a	blueswir1	}
2899	0f8a249a	blueswir1	} else {
2900	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2901	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2902	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
2903	6ae20372	blueswir1	tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2904	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2905	0f8a249a	blueswir1	} else { /* register */
2906	0f8a249a	blueswir1	// or x, %g0, y -> mov T1, x; mov y, T1
2907	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2908	0f8a249a	blueswir1	if (rs2 != 0) {
2909	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2910	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2911	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2912	6f551262	blueswir1	} else
2913	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_src1);
2914	0f8a249a	blueswir1	}
2915	0f8a249a	blueswir1	}
2916	83469015	bellard	#ifdef TARGET_SPARC64
2917	0f8a249a	blueswir1	} else if (xop == 0x25) { /* sll, V9 sllx */
2918	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2919	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2920	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2921	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2922	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2923	1a2fb1c0	blueswir1	} else {
2924	01b1fa6d	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f);
2925	1a2fb1c0	blueswir1	}
2926	0f8a249a	blueswir1	} else { /* register */
2927	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2928	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2929	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2930	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2931	1a2fb1c0	blueswir1	} else {
2932	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2933	1a2fb1c0	blueswir1	}
2934	01b1fa6d	blueswir1	tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2935	83469015	bellard	}
2936	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2937	0f8a249a	blueswir1	} else if (xop == 0x26) { /* srl, V9 srlx */
2938	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2939	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2940	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2941	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2942	6ae20372	blueswir1	tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2943	1a2fb1c0	blueswir1	} else {
2944	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2945	6ae20372	blueswir1	tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2946	1a2fb1c0	blueswir1	}
2947	0f8a249a	blueswir1	} else { /* register */
2948	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2949	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2950	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2951	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2952	6ae20372	blueswir1	tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2953	1a2fb1c0	blueswir1	} else {
2954	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2955	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2956	6ae20372	blueswir1	tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2957	1a2fb1c0	blueswir1	}
2958	83469015	bellard	}
2959	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2960	0f8a249a	blueswir1	} else if (xop == 0x27) { /* sra, V9 srax */
2961	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2962	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2963	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2964	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2965	6ae20372	blueswir1	tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2966	1a2fb1c0	blueswir1	} else {
2967	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2968	6ae20372	blueswir1	tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2969	6ae20372	blueswir1	tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2970	1a2fb1c0	blueswir1	}
2971	0f8a249a	blueswir1	} else { /* register */
2972	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2973	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2974	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2975	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2976	6ae20372	blueswir1	tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2977	1a2fb1c0	blueswir1	} else {
2978	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2979	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2980	01b1fa6d	blueswir1	tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2981	6ae20372	blueswir1	tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2982	1a2fb1c0	blueswir1	}
2983	83469015	bellard	}
2984	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2985	83469015	bellard	#endif
2986	fcc72045	blueswir1	} else if (xop < 0x36) {
2987	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2988	a49d9390	blueswir1	cpu_src2 = get_src2(insn, cpu_src2);
2989	cf495bcf	bellard	if (xop < 0x20) {
2990	cf495bcf	bellard	switch (xop & ~0x10) {
2991	cf495bcf	bellard	case 0x0:
2992	cf495bcf	bellard	if (xop & 0x10)
2993	6ae20372	blueswir1	gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2994	cf495bcf	bellard	else
2995	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2996	cf495bcf	bellard	break;
2997	cf495bcf	bellard	case 0x1:
2998	6ae20372	blueswir1	tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2999	cf495bcf	bellard	if (xop & 0x10)
3000	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3001	cf495bcf	bellard	break;
3002	cf495bcf	bellard	case 0x2:
3003	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3004	0f8a249a	blueswir1	if (xop & 0x10)
3005	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3006	0f8a249a	blueswir1	break;
3007	cf495bcf	bellard	case 0x3:
3008	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3009	cf495bcf	bellard	if (xop & 0x10)
3010	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3011	cf495bcf	bellard	break;
3012	cf495bcf	bellard	case 0x4:
3013	cf495bcf	bellard	if (xop & 0x10)
3014	6ae20372	blueswir1	gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3015	cf495bcf	bellard	else
3016	6ae20372	blueswir1	tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3017	cf495bcf	bellard	break;
3018	cf495bcf	bellard	case 0x5:
3019	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3020	6ae20372	blueswir1	tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3021	cf495bcf	bellard	if (xop & 0x10)
3022	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3023	cf495bcf	bellard	break;
3024	cf495bcf	bellard	case 0x6:
3025	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3026	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3027	cf495bcf	bellard	if (xop & 0x10)
3028	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3029	cf495bcf	bellard	break;
3030	cf495bcf	bellard	case 0x7:
3031	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3032	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3033	cf495bcf	bellard	if (xop & 0x10)
3034	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3035	cf495bcf	bellard	break;
3036	cf495bcf	bellard	case 0x8:
3037	cf495bcf	bellard	if (xop & 0x10)
3038	6ae20372	blueswir1	gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3039	38bc628b	blueswir1	else {
3040	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
3041	6ae20372	blueswir1	tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3042	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3043	38bc628b	blueswir1	}
3044	cf495bcf	bellard	break;
3045	ded3ab80	pbrook	#ifdef TARGET_SPARC64
3046	0f8a249a	blueswir1	case 0x9: /* V9 mulx */
3047	6ae20372	blueswir1	tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3048	ded3ab80	pbrook	break;
3049	ded3ab80	pbrook	#endif
3050	cf495bcf	bellard	case 0xa:
3051	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, MUL);
3052	6ae20372	blueswir1	gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3053	cf495bcf	bellard	if (xop & 0x10)
3054	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3055	cf495bcf	bellard	break;
3056	cf495bcf	bellard	case 0xb:
3057	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, MUL);
3058	6ae20372	blueswir1	gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3059	cf495bcf	bellard	if (xop & 0x10)
3060	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3061	cf495bcf	bellard	break;
3062	cf495bcf	bellard	case 0xc:
3063	cf495bcf	bellard	if (xop & 0x10)
3064	6ae20372	blueswir1	gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3065	38bc628b	blueswir1	else {
3066	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
3067	6ae20372	blueswir1	tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3068	6ae20372	blueswir1	tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3069	38bc628b	blueswir1	}
3070	cf495bcf	bellard	break;
3071	ded3ab80	pbrook	#ifdef TARGET_SPARC64
3072	0f8a249a	blueswir1	case 0xd: /* V9 udivx */
3073	07bf2857	blueswir1	tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3074	07bf2857	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3075	07bf2857	blueswir1	gen_trap_ifdivzero_tl(cpu_cc_src2);
3076	07bf2857	blueswir1	tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3077	ded3ab80	pbrook	break;
3078	ded3ab80	pbrook	#endif
3079	cf495bcf	bellard	case 0xe:
3080	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, DIV);
3081	77f193da	blueswir1	tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3082	77f193da	blueswir1	cpu_src2);
3083	cf495bcf	bellard	if (xop & 0x10)
3084	6ae20372	blueswir1	gen_op_div_cc(cpu_dst);
3085	cf495bcf	bellard	break;
3086	cf495bcf	bellard	case 0xf:
3087	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, DIV);
3088	77f193da	blueswir1	tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3089	77f193da	blueswir1	cpu_src2);
3090	cf495bcf	bellard	if (xop & 0x10)
3091	6ae20372	blueswir1	gen_op_div_cc(cpu_dst);
3092	cf495bcf	bellard	break;
3093	cf495bcf	bellard	default:
3094	cf495bcf	bellard	goto illegal_insn;
3095	cf495bcf	bellard	}
3096	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3097	cf495bcf	bellard	} else {
3098	cf495bcf	bellard	switch (xop) {
3099	0f8a249a	blueswir1	case 0x20: /* taddcc */
3100	6ae20372	blueswir1	gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3101	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3102	0f8a249a	blueswir1	break;
3103	0f8a249a	blueswir1	case 0x21: /* tsubcc */
3104	6ae20372	blueswir1	gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3105	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3106	0f8a249a	blueswir1	break;
3107	0f8a249a	blueswir1	case 0x22: /* taddcctv */
3108	6ae20372	blueswir1	save_state(dc, cpu_cond);
3109	6ae20372	blueswir1	gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3110	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3111	0f8a249a	blueswir1	break;
3112	0f8a249a	blueswir1	case 0x23: /* tsubcctv */
3113	6ae20372	blueswir1	save_state(dc, cpu_cond);
3114	6ae20372	blueswir1	gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3115	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3116	0f8a249a	blueswir1	break;
3117	cf495bcf	bellard	case 0x24: /* mulscc */
3118	6ae20372	blueswir1	gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3119	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3120	cf495bcf	bellard	break;
3121	83469015	bellard	#ifndef TARGET_SPARC64
3122	0f8a249a	blueswir1	case 0x25: /* sll */
3123	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3124	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3125	e35298cd	blueswir1	tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3126	e35298cd	blueswir1	} else { /* register */
3127	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3128	e35298cd	blueswir1	tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3129	e35298cd	blueswir1	}
3130	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3131	cf495bcf	bellard	break;
3132	83469015	bellard	case 0x26: /* srl */
3133	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3134	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3135	e35298cd	blueswir1	tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3136	e35298cd	blueswir1	} else { /* register */
3137	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3138	e35298cd	blueswir1	tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3139	e35298cd	blueswir1	}
3140	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3141	cf495bcf	bellard	break;
3142	83469015	bellard	case 0x27: /* sra */
3143	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3144	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3145	e35298cd	blueswir1	tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3146	e35298cd	blueswir1	} else { /* register */
3147	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3148	e35298cd	blueswir1	tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3149	e35298cd	blueswir1	}
3150	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3151	cf495bcf	bellard	break;
3152	83469015	bellard	#endif
3153	cf495bcf	bellard	case 0x30:
3154	cf495bcf	bellard	{
3155	cf495bcf	bellard	switch(rd) {
3156	3475187d	bellard	case 0: /* wry */
3157	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3158	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3159	77f193da	blueswir1	offsetof(CPUSPARCState, y));
3160	cf495bcf	bellard	break;
3161	65fe7b09	blueswir1	#ifndef TARGET_SPARC64
3162	65fe7b09	blueswir1	case 0x01 ... 0x0f: /* undefined in the
3163	65fe7b09	blueswir1	SPARCv8 manual, nop
3164	65fe7b09	blueswir1	on the microSPARC
3165	65fe7b09	blueswir1	II */
3166	65fe7b09	blueswir1	case 0x10 ... 0x1f: /* implementation-dependent
3167	65fe7b09	blueswir1	in the SPARCv8
3168	65fe7b09	blueswir1	manual, nop on the
3169	65fe7b09	blueswir1	microSPARC II */
3170	65fe7b09	blueswir1	break;
3171	65fe7b09	blueswir1	#else
3172	0f8a249a	blueswir1	case 0x2: /* V9 wrccr */
3173	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3174	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3175	0f8a249a	blueswir1	break;
3176	0f8a249a	blueswir1	case 0x3: /* V9 wrasi */
3177	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3178	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3179	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3180	77f193da	blueswir1	offsetof(CPUSPARCState, asi));
3181	0f8a249a	blueswir1	break;
3182	0f8a249a	blueswir1	case 0x6: /* V9 wrfprs */
3183	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3184	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3185	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3186	77f193da	blueswir1	offsetof(CPUSPARCState, fprs));
3187	6ae20372	blueswir1	save_state(dc, cpu_cond);
3188	3299908c	blueswir1	gen_op_next_insn();
3189	57fec1fe	bellard	tcg_gen_exit_tb(0);
3190	3299908c	blueswir1	dc->is_br = 1;
3191	0f8a249a	blueswir1	break;
3192	0f8a249a	blueswir1	case 0xf: /* V9 sir, nop if user */
3193	3475187d	bellard	#if !defined(CONFIG_USER_ONLY)
3194	0f8a249a	blueswir1	if (supervisor(dc))
3195	1a2fb1c0	blueswir1	; // XXX
3196	3475187d	bellard	#endif
3197	0f8a249a	blueswir1	break;
3198	0f8a249a	blueswir1	case 0x13: /* Graphics Status */
3199	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
3200	725cb90b	bellard	goto jmp_insn;
3201	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3202	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3203	77f193da	blueswir1	offsetof(CPUSPARCState, gsr));
3204	0f8a249a	blueswir1	break;
3205	0f8a249a	blueswir1	case 0x17: /* Tick compare */
3206	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3207	0f8a249a	blueswir1	if (!supervisor(dc))
3208	0f8a249a	blueswir1	goto illegal_insn;
3209	83469015	bellard	#endif
3210	ccd4a219	blueswir1	{
3211	ccd4a219	blueswir1	TCGv r_tickptr;
3212	ccd4a219	blueswir1
3213	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3214	6ae20372	blueswir1	cpu_src2);
3215	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3216	77f193da	blueswir1	offsetof(CPUSPARCState,
3217	77f193da	blueswir1	tick_cmpr));
3218	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3219	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3220	ccd4a219	blueswir1	offsetof(CPUState, tick));
3221	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3222	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3223	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3224	ccd4a219	blueswir1	}
3225	0f8a249a	blueswir1	break;
3226	0f8a249a	blueswir1	case 0x18: /* System tick */
3227	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3228	0f8a249a	blueswir1	if (!supervisor(dc))
3229	0f8a249a	blueswir1	goto illegal_insn;
3230	83469015	bellard	#endif
3231	ccd4a219	blueswir1	{
3232	ccd4a219	blueswir1	TCGv r_tickptr;
3233	ccd4a219	blueswir1
3234	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1,
3235	6ae20372	blueswir1	cpu_src2);
3236	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3237	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3238	ccd4a219	blueswir1	offsetof(CPUState, stick));
3239	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_count,
3240	6ae20372	blueswir1	r_tickptr, cpu_dst);
3241	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3242	ccd4a219	blueswir1	}
3243	0f8a249a	blueswir1	break;
3244	0f8a249a	blueswir1	case 0x19: /* System tick compare */
3245	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3246	0f8a249a	blueswir1	if (!supervisor(dc))
3247	0f8a249a	blueswir1	goto illegal_insn;
3248	3475187d	bellard	#endif
3249	ccd4a219	blueswir1	{
3250	ccd4a219	blueswir1	TCGv r_tickptr;
3251	ccd4a219	blueswir1
3252	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3253	6ae20372	blueswir1	cpu_src2);
3254	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3255	77f193da	blueswir1	offsetof(CPUSPARCState,
3256	77f193da	blueswir1	stick_cmpr));
3257	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3258	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3259	ccd4a219	blueswir1	offsetof(CPUState, stick));
3260	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3261	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3262	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3263	ccd4a219	blueswir1	}
3264	0f8a249a	blueswir1	break;
3265	83469015	bellard
3266	0f8a249a	blueswir1	case 0x10: /* Performance Control */
3267	77f193da	blueswir1	case 0x11: /* Performance Instrumentation
3268	77f193da	blueswir1	Counter */
3269	0f8a249a	blueswir1	case 0x12: /* Dispatch Control */
3270	0f8a249a	blueswir1	case 0x14: /* Softint set */
3271	0f8a249a	blueswir1	case 0x15: /* Softint clear */
3272	0f8a249a	blueswir1	case 0x16: /* Softint write */
3273	83469015	bellard	#endif
3274	3475187d	bellard	default:
3275	cf495bcf	bellard	goto illegal_insn;
3276	cf495bcf	bellard	}
3277	cf495bcf	bellard	}
3278	cf495bcf	bellard	break;
3279	e8af50a3	bellard	#if !defined(CONFIG_USER_ONLY)
3280	af7bf89b	bellard	case 0x31: /* wrpsr, V9 saved, restored */
3281	e8af50a3	bellard	{
3282	0f8a249a	blueswir1	if (!supervisor(dc))
3283	0f8a249a	blueswir1	goto priv_insn;
3284	3475187d	bellard	#ifdef TARGET_SPARC64
3285	0f8a249a	blueswir1	switch (rd) {
3286	0f8a249a	blueswir1	case 0:
3287	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_saved);
3288	0f8a249a	blueswir1	break;
3289	0f8a249a	blueswir1	case 1:
3290	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restored);
3291	0f8a249a	blueswir1	break;
3292	e9ebed4d	blueswir1	case 2: /* UA2005 allclean */
3293	e9ebed4d	blueswir1	case 3: /* UA2005 otherw */
3294	e9ebed4d	blueswir1	case 4: /* UA2005 normalw */
3295	e9ebed4d	blueswir1	case 5: /* UA2005 invalw */
3296	e9ebed4d	blueswir1	// XXX
3297	0f8a249a	blueswir1	default:
3298	3475187d	bellard	goto illegal_insn;
3299	3475187d	bellard	}
3300	3475187d	bellard	#else
3301	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3302	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3303	6ae20372	blueswir1	save_state(dc, cpu_cond);
3304	9e61bde5	bellard	gen_op_next_insn();
3305	57fec1fe	bellard	tcg_gen_exit_tb(0);
3306	0f8a249a	blueswir1	dc->is_br = 1;
3307	3475187d	bellard	#endif
3308	e8af50a3	bellard	}
3309	e8af50a3	bellard	break;
3310	af7bf89b	bellard	case 0x32: /* wrwim, V9 wrpr */
3311	e8af50a3	bellard	{
3312	0f8a249a	blueswir1	if (!supervisor(dc))
3313	0f8a249a	blueswir1	goto priv_insn;
3314	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3315	3475187d	bellard	#ifdef TARGET_SPARC64
3316	0f8a249a	blueswir1	switch (rd) {
3317	0f8a249a	blueswir1	case 0: // tpc
3318	375ee38b	blueswir1	{
3319	375ee38b	blueswir1	TCGv r_tsptr;
3320	375ee38b	blueswir1
3321	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3322	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3323	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3324	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3325	375ee38b	blueswir1	offsetof(trap_state, tpc));
3326	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3327	375ee38b	blueswir1	}
3328	0f8a249a	blueswir1	break;
3329	0f8a249a	blueswir1	case 1: // tnpc
3330	375ee38b	blueswir1	{
3331	375ee38b	blueswir1	TCGv r_tsptr;
3332	375ee38b	blueswir1
3333	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3334	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3335	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3336	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3337	375ee38b	blueswir1	offsetof(trap_state, tnpc));
3338	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3339	375ee38b	blueswir1	}
3340	0f8a249a	blueswir1	break;
3341	0f8a249a	blueswir1	case 2: // tstate
3342	375ee38b	blueswir1	{
3343	375ee38b	blueswir1	TCGv r_tsptr;
3344	375ee38b	blueswir1
3345	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3346	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3347	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3348	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3349	77f193da	blueswir1	offsetof(trap_state,
3350	77f193da	blueswir1	tstate));
3351	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3352	375ee38b	blueswir1	}
3353	0f8a249a	blueswir1	break;
3354	0f8a249a	blueswir1	case 3: // tt
3355	375ee38b	blueswir1	{
3356	375ee38b	blueswir1	TCGv r_tsptr;
3357	375ee38b	blueswir1
3358	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3359	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3360	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3361	ece43b8d	blueswir1	tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3362	375ee38b	blueswir1	offsetof(trap_state, tt));
3363	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3364	375ee38b	blueswir1	}
3365	0f8a249a	blueswir1	break;
3366	0f8a249a	blueswir1	case 4: // tick
3367	ccd4a219	blueswir1	{
3368	ccd4a219	blueswir1	TCGv r_tickptr;
3369	ccd4a219	blueswir1
3370	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3371	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3372	ccd4a219	blueswir1	offsetof(CPUState, tick));
3373	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_count,
3374	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3375	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3376	ccd4a219	blueswir1	}
3377	0f8a249a	blueswir1	break;
3378	0f8a249a	blueswir1	case 5: // tba
3379	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3380	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
3381	0f8a249a	blueswir1	break;
3382	0f8a249a	blueswir1	case 6: // pstate
3383	6ae20372	blueswir1	save_state(dc, cpu_cond);
3384	ece43b8d	blueswir1	tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3385	ded3ab80	pbrook	gen_op_next_insn();
3386	57fec1fe	bellard	tcg_gen_exit_tb(0);
3387	ded3ab80	pbrook	dc->is_br = 1;
3388	0f8a249a	blueswir1	break;
3389	0f8a249a	blueswir1	case 7: // tl
3390	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3391	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3392	77f193da	blueswir1	offsetof(CPUSPARCState, tl));
3393	0f8a249a	blueswir1	break;
3394	0f8a249a	blueswir1	case 8: // pil
3395	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3396	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3397	77f193da	blueswir1	offsetof(CPUSPARCState,
3398	77f193da	blueswir1	psrpil));
3399	0f8a249a	blueswir1	break;
3400	0f8a249a	blueswir1	case 9: // cwp
3401	ece43b8d	blueswir1	tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3402	0f8a249a	blueswir1	break;
3403	0f8a249a	blueswir1	case 10: // cansave
3404	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3405	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3406	77f193da	blueswir1	offsetof(CPUSPARCState,
3407	77f193da	blueswir1	cansave));
3408	0f8a249a	blueswir1	break;
3409	0f8a249a	blueswir1	case 11: // canrestore
3410	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3411	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3412	77f193da	blueswir1	offsetof(CPUSPARCState,
3413	77f193da	blueswir1	canrestore));
3414	0f8a249a	blueswir1	break;
3415	0f8a249a	blueswir1	case 12: // cleanwin
3416	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3417	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3418	77f193da	blueswir1	offsetof(CPUSPARCState,
3419	77f193da	blueswir1	cleanwin));
3420	0f8a249a	blueswir1	break;
3421	0f8a249a	blueswir1	case 13: // otherwin
3422	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3423	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3424	77f193da	blueswir1	offsetof(CPUSPARCState,
3425	77f193da	blueswir1	otherwin));
3426	0f8a249a	blueswir1	break;
3427	0f8a249a	blueswir1	case 14: // wstate
3428	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3429	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3430	77f193da	blueswir1	offsetof(CPUSPARCState,
3431	77f193da	blueswir1	wstate));
3432	0f8a249a	blueswir1	break;
3433	e9ebed4d	blueswir1	case 16: // UA2005 gl
3434	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, GL);
3435	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3436	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3437	77f193da	blueswir1	offsetof(CPUSPARCState, gl));
3438	e9ebed4d	blueswir1	break;
3439	e9ebed4d	blueswir1	case 26: // UA2005 strand status
3440	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
3441	e9ebed4d	blueswir1	if (!hypervisor(dc))
3442	e9ebed4d	blueswir1	goto priv_insn;
3443	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3444	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3445	77f193da	blueswir1	offsetof(CPUSPARCState, ssr));
3446	e9ebed4d	blueswir1	break;
3447	0f8a249a	blueswir1	default:
3448	0f8a249a	blueswir1	goto illegal_insn;
3449	0f8a249a	blueswir1	}
3450	3475187d	bellard	#else
3451	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3452	c93e7817	blueswir1	if (dc->def->nwindows != 32)
3453	c93e7817	blueswir1	tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
3454	c93e7817	blueswir1	(1 << dc->def->nwindows) - 1);
3455	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3456	77f193da	blueswir1	offsetof(CPUSPARCState, wim));
3457	3475187d	bellard	#endif
3458	e8af50a3	bellard	}
3459	e8af50a3	bellard	break;
3460	e9ebed4d	blueswir1	case 0x33: /* wrtbr, UA2005 wrhpr */
3461	e8af50a3	bellard	{
3462	e9ebed4d	blueswir1	#ifndef TARGET_SPARC64
3463	0f8a249a	blueswir1	if (!supervisor(dc))
3464	0f8a249a	blueswir1	goto priv_insn;
3465	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3466	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3467	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
3468	e9ebed4d	blueswir1	#else
3469	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
3470	e9ebed4d	blueswir1	if (!hypervisor(dc))
3471	e9ebed4d	blueswir1	goto priv_insn;
3472	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3473	e9ebed4d	blueswir1	switch (rd) {
3474	e9ebed4d	blueswir1	case 0: // hpstate
3475	e9ebed4d	blueswir1	// XXX gen_op_wrhpstate();
3476	6ae20372	blueswir1	save_state(dc, cpu_cond);
3477	e9ebed4d	blueswir1	gen_op_next_insn();
3478	57fec1fe	bellard	tcg_gen_exit_tb(0);
3479	e9ebed4d	blueswir1	dc->is_br = 1;
3480	e9ebed4d	blueswir1	break;
3481	e9ebed4d	blueswir1	case 1: // htstate
3482	e9ebed4d	blueswir1	// XXX gen_op_wrhtstate();
3483	e9ebed4d	blueswir1	break;
3484	e9ebed4d	blueswir1	case 3: // hintp
3485	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3486	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3487	77f193da	blueswir1	offsetof(CPUSPARCState, hintp));
3488	e9ebed4d	blueswir1	break;
3489	e9ebed4d	blueswir1	case 5: // htba
3490	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3491	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3492	77f193da	blueswir1	offsetof(CPUSPARCState, htba));
3493	e9ebed4d	blueswir1	break;
3494	e9ebed4d	blueswir1	case 31: // hstick_cmpr
3495	ccd4a219	blueswir1	{
3496	ccd4a219	blueswir1	TCGv r_tickptr;
3497	ccd4a219	blueswir1
3498	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3499	77f193da	blueswir1	offsetof(CPUSPARCState,
3500	77f193da	blueswir1	hstick_cmpr));
3501	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3502	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3503	ccd4a219	blueswir1	offsetof(CPUState, hstick));
3504	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3505	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3506	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3507	ccd4a219	blueswir1	}
3508	e9ebed4d	blueswir1	break;
3509	e9ebed4d	blueswir1	case 6: // hver readonly
3510	e9ebed4d	blueswir1	default:
3511	e9ebed4d	blueswir1	goto illegal_insn;
3512	e9ebed4d	blueswir1	}
3513	e9ebed4d	blueswir1	#endif
3514	e8af50a3	bellard	}
3515	e8af50a3	bellard	break;
3516	e8af50a3	bellard	#endif
3517	3475187d	bellard	#ifdef TARGET_SPARC64
3518	0f8a249a	blueswir1	case 0x2c: /* V9 movcc */
3519	0f8a249a	blueswir1	{
3520	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 11, 12);
3521	0f8a249a	blueswir1	int cond = GET_FIELD_SP(insn, 14, 17);
3522	748b9d8e	blueswir1	TCGv r_cond;
3523	00f219bf	blueswir1	int l1;
3524	00f219bf	blueswir1
3525	748b9d8e	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL);
3526	0f8a249a	blueswir1	if (insn & (1 << 18)) {
3527	0f8a249a	blueswir1	if (cc == 0)
3528	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
3529	0f8a249a	blueswir1	else if (cc == 2)
3530	748b9d8e	blueswir1	gen_cond(r_cond, 1, cond);
3531	0f8a249a	blueswir1	else
3532	0f8a249a	blueswir1	goto illegal_insn;
3533	0f8a249a	blueswir1	} else {
3534	748b9d8e	blueswir1	gen_fcond(r_cond, cc, cond);
3535	0f8a249a	blueswir1	}
3536	00f219bf	blueswir1
3537	00f219bf	blueswir1	l1 = gen_new_label();
3538	00f219bf	blueswir1
3539	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3540	00f219bf	blueswir1	if (IS_IMM) { /* immediate */
3541	2ea815ca	blueswir1	TCGv r_const;
3542	2ea815ca	blueswir1
3543	00f219bf	blueswir1	rs2 = GET_FIELD_SPs(insn, 0, 10);
3544	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
3545	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
3546	2ea815ca	blueswir1	tcg_temp_free(r_const);
3547	00f219bf	blueswir1	} else {
3548	00f219bf	blueswir1	rs2 = GET_FIELD_SP(insn, 0, 4);
3549	9c6c6662	blueswir1	gen_movl_reg_TN(rs2, cpu_tmp0);
3550	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
3551	00f219bf	blueswir1	}
3552	00f219bf	blueswir1	gen_set_label(l1);
3553	2ea815ca	blueswir1	tcg_temp_free(r_cond);
3554	0f8a249a	blueswir1	break;
3555	0f8a249a	blueswir1	}
3556	0f8a249a	blueswir1	case 0x2d: /* V9 sdivx */
3557	6ae20372	blueswir1	gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3558	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3559	0f8a249a	blueswir1	break;
3560	0f8a249a	blueswir1	case 0x2e: /* V9 popc */
3561	0f8a249a	blueswir1	{
3562	a49d9390	blueswir1	cpu_src2 = get_src2(insn, cpu_src2);
3563	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_popc, cpu_dst,
3564	6ae20372	blueswir1	cpu_src2);
3565	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3566	0f8a249a	blueswir1	}
3567	0f8a249a	blueswir1	case 0x2f: /* V9 movr */
3568	0f8a249a	blueswir1	{
3569	0f8a249a	blueswir1	int cond = GET_FIELD_SP(insn, 10, 12);
3570	00f219bf	blueswir1	int l1;
3571	00f219bf	blueswir1
3572	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3573	00f219bf	blueswir1
3574	00f219bf	blueswir1	l1 = gen_new_label();
3575	00f219bf	blueswir1
3576	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3577	cb63669a	pbrook	cpu_src1, 0, l1);
3578	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
3579	2ea815ca	blueswir1	TCGv r_const;
3580	2ea815ca	blueswir1
3581	0f8a249a	blueswir1	rs2 = GET_FIELD_SPs(insn, 0, 9);
3582	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
3583	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
3584	2ea815ca	blueswir1	tcg_temp_free(r_const);
3585	00f219bf	blueswir1	} else {
3586	0f8a249a	blueswir1	rs2 = GET_FIELD_SP(insn, 0, 4);
3587	9c6c6662	blueswir1	gen_movl_reg_TN(rs2, cpu_tmp0);
3588	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
3589	0f8a249a	blueswir1	}
3590	00f219bf	blueswir1	gen_set_label(l1);
3591	0f8a249a	blueswir1	break;
3592	0f8a249a	blueswir1	}
3593	0f8a249a	blueswir1	#endif
3594	0f8a249a	blueswir1	default:
3595	0f8a249a	blueswir1	goto illegal_insn;
3596	0f8a249a	blueswir1	}
3597	0f8a249a	blueswir1	}
3598	3299908c	blueswir1	} else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3599	3299908c	blueswir1	#ifdef TARGET_SPARC64
3600	3299908c	blueswir1	int opf = GET_FIELD_SP(insn, 5, 13);
3601	3299908c	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
3602	3299908c	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
3603	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
3604	e9ebed4d	blueswir1	goto jmp_insn;
3605	3299908c	blueswir1
3606	3299908c	blueswir1	switch (opf) {
3607	e9ebed4d	blueswir1	case 0x000: /* VIS I edge8cc */
3608	e9ebed4d	blueswir1	case 0x001: /* VIS II edge8n */
3609	e9ebed4d	blueswir1	case 0x002: /* VIS I edge8lcc */
3610	e9ebed4d	blueswir1	case 0x003: /* VIS II edge8ln */
3611	e9ebed4d	blueswir1	case 0x004: /* VIS I edge16cc */
3612	e9ebed4d	blueswir1	case 0x005: /* VIS II edge16n */
3613	e9ebed4d	blueswir1	case 0x006: /* VIS I edge16lcc */
3614	e9ebed4d	blueswir1	case 0x007: /* VIS II edge16ln */
3615	e9ebed4d	blueswir1	case 0x008: /* VIS I edge32cc */
3616	e9ebed4d	blueswir1	case 0x009: /* VIS II edge32n */
3617	e9ebed4d	blueswir1	case 0x00a: /* VIS I edge32lcc */
3618	e9ebed4d	blueswir1	case 0x00b: /* VIS II edge32ln */
3619	e9ebed4d	blueswir1	// XXX
3620	e9ebed4d	blueswir1	goto illegal_insn;
3621	e9ebed4d	blueswir1	case 0x010: /* VIS I array8 */
3622	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3623	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3624	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3625	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3626	6ae20372	blueswir1	cpu_src2);
3627	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3628	e9ebed4d	blueswir1	break;
3629	e9ebed4d	blueswir1	case 0x012: /* VIS I array16 */
3630	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3631	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3632	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3633	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3634	6ae20372	blueswir1	cpu_src2);
3635	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3636	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3637	e9ebed4d	blueswir1	break;
3638	e9ebed4d	blueswir1	case 0x014: /* VIS I array32 */
3639	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3640	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3641	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3642	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3643	6ae20372	blueswir1	cpu_src2);
3644	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3645	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3646	e9ebed4d	blueswir1	break;
3647	3299908c	blueswir1	case 0x018: /* VIS I alignaddr */
3648	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3649	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3650	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3651	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3652	6ae20372	blueswir1	cpu_src2);
3653	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3654	3299908c	blueswir1	break;
3655	e9ebed4d	blueswir1	case 0x019: /* VIS II bmask */
3656	3299908c	blueswir1	case 0x01a: /* VIS I alignaddrl */
3657	3299908c	blueswir1	// XXX
3658	e9ebed4d	blueswir1	goto illegal_insn;
3659	e9ebed4d	blueswir1	case 0x020: /* VIS I fcmple16 */
3660	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3661	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3662	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3663	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmple16);
3664	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3665	e9ebed4d	blueswir1	break;
3666	e9ebed4d	blueswir1	case 0x022: /* VIS I fcmpne16 */
3667	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3668	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3669	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3670	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpne16);
3671	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3672	3299908c	blueswir1	break;
3673	e9ebed4d	blueswir1	case 0x024: /* VIS I fcmple32 */
3674	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3675	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3676	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3677	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmple32);
3678	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3679	e9ebed4d	blueswir1	break;
3680	e9ebed4d	blueswir1	case 0x026: /* VIS I fcmpne32 */
3681	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3682	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3683	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3684	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpne32);
3685	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3686	e9ebed4d	blueswir1	break;
3687	e9ebed4d	blueswir1	case 0x028: /* VIS I fcmpgt16 */
3688	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3689	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3690	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3691	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpgt16);
3692	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3693	e9ebed4d	blueswir1	break;
3694	e9ebed4d	blueswir1	case 0x02a: /* VIS I fcmpeq16 */
3695	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3696	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3697	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3698	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq16);
3699	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3700	e9ebed4d	blueswir1	break;
3701	e9ebed4d	blueswir1	case 0x02c: /* VIS I fcmpgt32 */
3702	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3703	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3704	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3705	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpgt32);
3706	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3707	e9ebed4d	blueswir1	break;
3708	e9ebed4d	blueswir1	case 0x02e: /* VIS I fcmpeq32 */
3709	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3710	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3711	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3712	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq32);
3713	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3714	e9ebed4d	blueswir1	break;
3715	e9ebed4d	blueswir1	case 0x031: /* VIS I fmul8x16 */
3716	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3717	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3718	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3719	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16);
3720	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3721	e9ebed4d	blueswir1	break;
3722	e9ebed4d	blueswir1	case 0x033: /* VIS I fmul8x16au */
3723	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3724	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3725	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3726	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16au);
3727	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3728	e9ebed4d	blueswir1	break;
3729	e9ebed4d	blueswir1	case 0x035: /* VIS I fmul8x16al */
3730	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3731	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3732	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3733	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16al);
3734	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3735	e9ebed4d	blueswir1	break;
3736	e9ebed4d	blueswir1	case 0x036: /* VIS I fmul8sux16 */
3737	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3738	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3739	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3740	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8sux16);
3741	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3742	e9ebed4d	blueswir1	break;
3743	e9ebed4d	blueswir1	case 0x037: /* VIS I fmul8ulx16 */
3744	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3745	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3746	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3747	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8ulx16);
3748	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3749	e9ebed4d	blueswir1	break;
3750	e9ebed4d	blueswir1	case 0x038: /* VIS I fmuld8sux16 */
3751	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3752	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3753	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3754	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld8sux16);
3755	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3756	e9ebed4d	blueswir1	break;
3757	e9ebed4d	blueswir1	case 0x039: /* VIS I fmuld8ulx16 */
3758	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3759	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3760	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3761	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld8ulx16);
3762	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3763	e9ebed4d	blueswir1	break;
3764	e9ebed4d	blueswir1	case 0x03a: /* VIS I fpack32 */
3765	e9ebed4d	blueswir1	case 0x03b: /* VIS I fpack16 */
3766	e9ebed4d	blueswir1	case 0x03d: /* VIS I fpackfix */
3767	e9ebed4d	blueswir1	case 0x03e: /* VIS I pdist */
3768	e9ebed4d	blueswir1	// XXX
3769	e9ebed4d	blueswir1	goto illegal_insn;
3770	3299908c	blueswir1	case 0x048: /* VIS I faligndata */
3771	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3772	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3773	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3774	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faligndata);
3775	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3776	3299908c	blueswir1	break;
3777	e9ebed4d	blueswir1	case 0x04b: /* VIS I fpmerge */
3778	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3779	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3780	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3781	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpmerge);
3782	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3783	e9ebed4d	blueswir1	break;
3784	e9ebed4d	blueswir1	case 0x04c: /* VIS II bshuffle */
3785	e9ebed4d	blueswir1	// XXX
3786	e9ebed4d	blueswir1	goto illegal_insn;
3787	e9ebed4d	blueswir1	case 0x04d: /* VIS I fexpand */
3788	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3789	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3790	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3791	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fexpand);
3792	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3793	e9ebed4d	blueswir1	break;
3794	e9ebed4d	blueswir1	case 0x050: /* VIS I fpadd16 */
3795	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3796	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3797	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3798	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd16);
3799	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3800	e9ebed4d	blueswir1	break;
3801	e9ebed4d	blueswir1	case 0x051: /* VIS I fpadd16s */
3802	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3803	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3804	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3805	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd16s);
3806	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3807	e9ebed4d	blueswir1	break;
3808	e9ebed4d	blueswir1	case 0x052: /* VIS I fpadd32 */
3809	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3810	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3811	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3812	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32);
3813	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3814	e9ebed4d	blueswir1	break;
3815	e9ebed4d	blueswir1	case 0x053: /* VIS I fpadd32s */
3816	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3817	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3818	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3819	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32s);
3820	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3821	e9ebed4d	blueswir1	break;
3822	e9ebed4d	blueswir1	case 0x054: /* VIS I fpsub16 */
3823	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3824	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3825	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3826	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub16);
3827	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3828	e9ebed4d	blueswir1	break;
3829	e9ebed4d	blueswir1	case 0x055: /* VIS I fpsub16s */
3830	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3831	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3832	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3833	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub16s);
3834	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3835	e9ebed4d	blueswir1	break;
3836	e9ebed4d	blueswir1	case 0x056: /* VIS I fpsub32 */
3837	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3838	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3839	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3840	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32);
3841	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3842	e9ebed4d	blueswir1	break;
3843	e9ebed4d	blueswir1	case 0x057: /* VIS I fpsub32s */
3844	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3845	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3846	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3847	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub32s);
3848	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3849	e9ebed4d	blueswir1	break;
3850	3299908c	blueswir1	case 0x060: /* VIS I fzero */
3851	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3852	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_DT0_0);
3853	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3854	3299908c	blueswir1	break;
3855	3299908c	blueswir1	case 0x061: /* VIS I fzeros */
3856	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3857	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_FT0_0);
3858	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
3859	3299908c	blueswir1	break;
3860	e9ebed4d	blueswir1	case 0x062: /* VIS I fnor */
3861	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3862	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3863	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3864	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnor);
3865	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3866	e9ebed4d	blueswir1	break;
3867	e9ebed4d	blueswir1	case 0x063: /* VIS I fnors */
3868	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3869	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3870	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3871	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnors);
3872	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3873	e9ebed4d	blueswir1	break;
3874	e9ebed4d	blueswir1	case 0x064: /* VIS I fandnot2 */
3875	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3876	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3877	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
3878	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnot);
3879	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3880	e9ebed4d	blueswir1	break;
3881	e9ebed4d	blueswir1	case 0x065: /* VIS I fandnot2s */
3882	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3883	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
3884	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs2);
3885	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnots);
3886	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3887	e9ebed4d	blueswir1	break;
3888	e9ebed4d	blueswir1	case 0x066: /* VIS I fnot2 */
3889	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3890	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3891	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3892	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3893	e9ebed4d	blueswir1	break;
3894	e9ebed4d	blueswir1	case 0x067: /* VIS I fnot2s */
3895	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3896	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3897	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3898	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3899	e9ebed4d	blueswir1	break;
3900	e9ebed4d	blueswir1	case 0x068: /* VIS I fandnot1 */
3901	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3902	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3903	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3904	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnot);
3905	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3906	e9ebed4d	blueswir1	break;
3907	e9ebed4d	blueswir1	case 0x069: /* VIS I fandnot1s */
3908	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3909	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3910	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3911	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnots);
3912	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3913	e9ebed4d	blueswir1	break;
3914	e9ebed4d	blueswir1	case 0x06a: /* VIS I fnot1 */
3915	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3916	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3917	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3918	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3919	e9ebed4d	blueswir1	break;
3920	e9ebed4d	blueswir1	case 0x06b: /* VIS I fnot1s */
3921	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3922	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
3923	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3924	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3925	e9ebed4d	blueswir1	break;
3926	e9ebed4d	blueswir1	case 0x06c: /* VIS I fxor */
3927	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3928	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3929	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3930	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxor);
3931	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3932	e9ebed4d	blueswir1	break;
3933	e9ebed4d	blueswir1	case 0x06d: /* VIS I fxors */
3934	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3935	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3936	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3937	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxors);
3938	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3939	e9ebed4d	blueswir1	break;
3940	e9ebed4d	blueswir1	case 0x06e: /* VIS I fnand */
3941	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3942	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3943	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3944	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnand);
3945	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3946	e9ebed4d	blueswir1	break;
3947	e9ebed4d	blueswir1	case 0x06f: /* VIS I fnands */
3948	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3949	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3950	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3951	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnands);
3952	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3953	e9ebed4d	blueswir1	break;
3954	e9ebed4d	blueswir1	case 0x070: /* VIS I fand */
3955	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3956	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3957	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3958	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fand);
3959	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3960	e9ebed4d	blueswir1	break;
3961	e9ebed4d	blueswir1	case 0x071: /* VIS I fands */
3962	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3963	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3964	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3965	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fands);
3966	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3967	e9ebed4d	blueswir1	break;
3968	e9ebed4d	blueswir1	case 0x072: /* VIS I fxnor */
3969	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3970	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3971	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3972	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxnor);
3973	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3974	e9ebed4d	blueswir1	break;
3975	e9ebed4d	blueswir1	case 0x073: /* VIS I fxnors */
3976	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3977	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3978	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3979	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxnors);
3980	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3981	e9ebed4d	blueswir1	break;
3982	3299908c	blueswir1	case 0x074: /* VIS I fsrc1 */
3983	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3984	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3985	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3986	3299908c	blueswir1	break;
3987	3299908c	blueswir1	case 0x075: /* VIS I fsrc1s */
3988	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3989	3299908c	blueswir1	gen_op_load_fpr_FT0(rs1);
3990	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
3991	3299908c	blueswir1	break;
3992	e9ebed4d	blueswir1	case 0x076: /* VIS I fornot2 */
3993	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3994	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3995	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
3996	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornot);
3997	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3998	e9ebed4d	blueswir1	break;
3999	e9ebed4d	blueswir1	case 0x077: /* VIS I fornot2s */
4000	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4001	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
4002	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs2);
4003	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornots);
4004	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4005	e9ebed4d	blueswir1	break;
4006	3299908c	blueswir1	case 0x078: /* VIS I fsrc2 */
4007	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4008	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
4009	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4010	3299908c	blueswir1	break;
4011	3299908c	blueswir1	case 0x079: /* VIS I fsrc2s */
4012	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4013	3299908c	blueswir1	gen_op_load_fpr_FT0(rs2);
4014	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
4015	3299908c	blueswir1	break;
4016	e9ebed4d	blueswir1	case 0x07a: /* VIS I fornot1 */
4017	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4018	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
4019	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
4020	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornot);
4021	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4022	e9ebed4d	blueswir1	break;
4023	e9ebed4d	blueswir1	case 0x07b: /* VIS I fornot1s */
4024	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4025	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
4026	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
4027	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornots);
4028	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4029	e9ebed4d	blueswir1	break;
4030	e9ebed4d	blueswir1	case 0x07c: /* VIS I for */
4031	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4032	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
4033	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
4034	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_for);
4035	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4036	e9ebed4d	blueswir1	break;
4037	e9ebed4d	blueswir1	case 0x07d: /* VIS I fors */
4038	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4039	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
4040	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
4041	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fors);
4042	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4043	e9ebed4d	blueswir1	break;
4044	3299908c	blueswir1	case 0x07e: /* VIS I fone */
4045	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4046	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_DT0_1);
4047	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4048	3299908c	blueswir1	break;
4049	3299908c	blueswir1	case 0x07f: /* VIS I fones */
4050	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4051	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_FT0_1);
4052	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
4053	3299908c	blueswir1	break;
4054	e9ebed4d	blueswir1	case 0x080: /* VIS I shutdown */
4055	e9ebed4d	blueswir1	case 0x081: /* VIS II siam */
4056	e9ebed4d	blueswir1	// XXX
4057	e9ebed4d	blueswir1	goto illegal_insn;
4058	3299908c	blueswir1	default:
4059	3299908c	blueswir1	goto illegal_insn;
4060	3299908c	blueswir1	}
4061	3299908c	blueswir1	#else
4062	0f8a249a	blueswir1	goto ncp_insn;
4063	3299908c	blueswir1	#endif
4064	3299908c	blueswir1	} else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4065	fcc72045	blueswir1	#ifdef TARGET_SPARC64
4066	0f8a249a	blueswir1	goto illegal_insn;
4067	fcc72045	blueswir1	#else
4068	0f8a249a	blueswir1	goto ncp_insn;
4069	fcc72045	blueswir1	#endif
4070	3475187d	bellard	#ifdef TARGET_SPARC64
4071	0f8a249a	blueswir1	} else if (xop == 0x39) { /* V9 return */
4072	2ea815ca	blueswir1	TCGv r_const;
4073	2ea815ca	blueswir1
4074	6ae20372	blueswir1	save_state(dc, cpu_cond);
4075	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4076	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
4077	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4078	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4079	0f8a249a	blueswir1	} else { /* register */
4080	3475187d	bellard	rs2 = GET_FIELD(insn, 27, 31);
4081	0f8a249a	blueswir1	if (rs2) {
4082	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4083	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4084	6f551262	blueswir1	} else
4085	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
4086	3475187d	bellard	}
4087	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restore);
4088	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4089	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4090	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4091	2ea815ca	blueswir1	tcg_temp_free(r_const);
4092	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4093	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4094	0f8a249a	blueswir1	goto jmp_insn;
4095	3475187d	bellard	#endif
4096	0f8a249a	blueswir1	} else {
4097	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4098	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
4099	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4100	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4101	0f8a249a	blueswir1	} else { /* register */
4102	e80cfcfc	bellard	rs2 = GET_FIELD(insn, 27, 31);
4103	0f8a249a	blueswir1	if (rs2) {
4104	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4105	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4106	6f551262	blueswir1	} else
4107	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
4108	cf495bcf	bellard	}
4109	0f8a249a	blueswir1	switch (xop) {
4110	0f8a249a	blueswir1	case 0x38: /* jmpl */
4111	0f8a249a	blueswir1	{
4112	2ea815ca	blueswir1	TCGv r_const;
4113	2ea815ca	blueswir1
4114	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
4115	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
4116	2ea815ca	blueswir1	tcg_temp_free(r_const);
4117	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4118	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4119	77f193da	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4120	2ea815ca	blueswir1	r_const);
4121	2ea815ca	blueswir1	tcg_temp_free(r_const);
4122	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4123	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4124	0f8a249a	blueswir1	}
4125	0f8a249a	blueswir1	goto jmp_insn;
4126	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4127	0f8a249a	blueswir1	case 0x39: /* rett, V9 return */
4128	0f8a249a	blueswir1	{
4129	2ea815ca	blueswir1	TCGv r_const;
4130	2ea815ca	blueswir1
4131	0f8a249a	blueswir1	if (!supervisor(dc))
4132	0f8a249a	blueswir1	goto priv_insn;
4133	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4134	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4135	77f193da	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4136	2ea815ca	blueswir1	r_const);
4137	2ea815ca	blueswir1	tcg_temp_free(r_const);
4138	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4139	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4140	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_rett);
4141	0f8a249a	blueswir1	}
4142	0f8a249a	blueswir1	goto jmp_insn;
4143	0f8a249a	blueswir1	#endif
4144	0f8a249a	blueswir1	case 0x3b: /* flush */
4145	5578ceab	blueswir1	if (!((dc)->def->features & CPU_FEATURE_FLUSH))
4146	64a88d5d	blueswir1	goto unimp_flush;
4147	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_flush, cpu_dst);
4148	0f8a249a	blueswir1	break;
4149	0f8a249a	blueswir1	case 0x3c: /* save */
4150	6ae20372	blueswir1	save_state(dc, cpu_cond);
4151	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_save);
4152	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
4153	0f8a249a	blueswir1	break;
4154	0f8a249a	blueswir1	case 0x3d: /* restore */
4155	6ae20372	blueswir1	save_state(dc, cpu_cond);
4156	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restore);
4157	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
4158	0f8a249a	blueswir1	break;
4159	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4160	0f8a249a	blueswir1	case 0x3e: /* V9 done/retry */
4161	0f8a249a	blueswir1	{
4162	0f8a249a	blueswir1	switch (rd) {
4163	0f8a249a	blueswir1	case 0:
4164	0f8a249a	blueswir1	if (!supervisor(dc))
4165	0f8a249a	blueswir1	goto priv_insn;
4166	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4167	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4168	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_done);
4169	0f8a249a	blueswir1	goto jmp_insn;
4170	0f8a249a	blueswir1	case 1:
4171	0f8a249a	blueswir1	if (!supervisor(dc))
4172	0f8a249a	blueswir1	goto priv_insn;
4173	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4174	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4175	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_retry);
4176	0f8a249a	blueswir1	goto jmp_insn;
4177	0f8a249a	blueswir1	default:
4178	0f8a249a	blueswir1	goto illegal_insn;
4179	0f8a249a	blueswir1	}
4180	0f8a249a	blueswir1	}
4181	0f8a249a	blueswir1	break;
4182	0f8a249a	blueswir1	#endif
4183	0f8a249a	blueswir1	default:
4184	0f8a249a	blueswir1	goto illegal_insn;
4185	0f8a249a	blueswir1	}
4186	cf495bcf	bellard	}
4187	0f8a249a	blueswir1	break;
4188	0f8a249a	blueswir1	}
4189	0f8a249a	blueswir1	break;
4190	0f8a249a	blueswir1	case 3: /* load/store instructions */
4191	0f8a249a	blueswir1	{
4192	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 12);
4193	9322a4bf	blueswir1
4194	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4195	71817e48	blueswir1	if (xop == 0x3c \|\| xop == 0x3e) { // V9 casa/casxa
4196	81ad8ba2	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
4197	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4198	71817e48	blueswir1	tcg_gen_mov_tl(cpu_addr, cpu_src1);
4199	71817e48	blueswir1	} else if (IS_IMM) { /* immediate */
4200	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4201	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4202	0f8a249a	blueswir1	} else { /* register */
4203	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
4204	0f8a249a	blueswir1	if (rs2 != 0) {
4205	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4206	6ae20372	blueswir1	tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4207	6f551262	blueswir1	} else
4208	6f551262	blueswir1	tcg_gen_mov_tl(cpu_addr, cpu_src1);
4209	0f8a249a	blueswir1	}
4210	2f2ecb83	blueswir1	if (xop < 4 \|\| (xop > 7 && xop < 0x14 && xop != 0x0e) \|\|
4211	2f2ecb83	blueswir1	(xop > 0x17 && xop <= 0x1d ) \|\|
4212	2f2ecb83	blueswir1	(xop > 0x2c && xop <= 0x33) \|\| xop == 0x1f \|\| xop == 0x3d) {
4213	0f8a249a	blueswir1	switch (xop) {
4214	1a2fb1c0	blueswir1	case 0x0: /* load unsigned word */
4215	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4216	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4217	0f8a249a	blueswir1	break;
4218	0f8a249a	blueswir1	case 0x1: /* load unsigned byte */
4219	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4220	6ae20372	blueswir1	tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4221	0f8a249a	blueswir1	break;
4222	0f8a249a	blueswir1	case 0x2: /* load unsigned halfword */
4223	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4224	6ae20372	blueswir1	tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4225	0f8a249a	blueswir1	break;
4226	0f8a249a	blueswir1	case 0x3: /* load double word */
4227	0f8a249a	blueswir1	if (rd & 1)
4228	d4218d99	blueswir1	goto illegal_insn;
4229	1a2fb1c0	blueswir1	else {
4230	2ea815ca	blueswir1	TCGv r_const;
4231	2ea815ca	blueswir1
4232	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4233	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4234	d987963a	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4235	2ea815ca	blueswir1	r_const); // XXX remove
4236	2ea815ca	blueswir1	tcg_temp_free(r_const);
4237	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4238	6ae20372	blueswir1	tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4239	32b6c812	blueswir1	tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4240	32b6c812	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4241	32b6c812	blueswir1	gen_movl_TN_reg(rd + 1, cpu_tmp0);
4242	8911f501	blueswir1	tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4243	6ae20372	blueswir1	tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4244	6ae20372	blueswir1	tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4245	1a2fb1c0	blueswir1	}
4246	0f8a249a	blueswir1	break;
4247	0f8a249a	blueswir1	case 0x9: /* load signed byte */
4248	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4249	6ae20372	blueswir1	tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4250	0f8a249a	blueswir1	break;
4251	0f8a249a	blueswir1	case 0xa: /* load signed halfword */
4252	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4253	6ae20372	blueswir1	tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4254	0f8a249a	blueswir1	break;
4255	0f8a249a	blueswir1	case 0xd: /* ldstub -- XXX: should be atomically */
4256	2ea815ca	blueswir1	{
4257	2ea815ca	blueswir1	TCGv r_const;
4258	2ea815ca	blueswir1
4259	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4260	2ea815ca	blueswir1	tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4261	2ea815ca	blueswir1	r_const = tcg_const_tl(0xff);
4262	2ea815ca	blueswir1	tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4263	2ea815ca	blueswir1	tcg_temp_free(r_const);
4264	2ea815ca	blueswir1	}
4265	0f8a249a	blueswir1	break;
4266	77f193da	blueswir1	case 0x0f: /* swap register with memory. Also
4267	77f193da	blueswir1	atomically */
4268	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, SWAP);
4269	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4270	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4271	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4272	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4273	6ae20372	blueswir1	tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4274	0f8a249a	blueswir1	break;
4275	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4276	0f8a249a	blueswir1	case 0x10: /* load word alternate */
4277	3475187d	bellard	#ifndef TARGET_SPARC64
4278	0f8a249a	blueswir1	if (IS_IMM)
4279	0f8a249a	blueswir1	goto illegal_insn;
4280	0f8a249a	blueswir1	if (!supervisor(dc))
4281	0f8a249a	blueswir1	goto priv_insn;
4282	6ea4a6c8	blueswir1	#endif
4283	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4284	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4285	0f8a249a	blueswir1	break;
4286	0f8a249a	blueswir1	case 0x11: /* load unsigned byte alternate */
4287	3475187d	bellard	#ifndef TARGET_SPARC64
4288	0f8a249a	blueswir1	if (IS_IMM)
4289	0f8a249a	blueswir1	goto illegal_insn;
4290	0f8a249a	blueswir1	if (!supervisor(dc))
4291	0f8a249a	blueswir1	goto priv_insn;
4292	0f8a249a	blueswir1	#endif
4293	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4294	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4295	0f8a249a	blueswir1	break;
4296	0f8a249a	blueswir1	case 0x12: /* load unsigned halfword alternate */
4297	3475187d	bellard	#ifndef TARGET_SPARC64
4298	0f8a249a	blueswir1	if (IS_IMM)
4299	0f8a249a	blueswir1	goto illegal_insn;
4300	0f8a249a	blueswir1	if (!supervisor(dc))
4301	0f8a249a	blueswir1	goto priv_insn;
4302	6ea4a6c8	blueswir1	#endif
4303	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4304	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4305	0f8a249a	blueswir1	break;
4306	0f8a249a	blueswir1	case 0x13: /* load double word alternate */
4307	3475187d	bellard	#ifndef TARGET_SPARC64
4308	0f8a249a	blueswir1	if (IS_IMM)
4309	0f8a249a	blueswir1	goto illegal_insn;
4310	0f8a249a	blueswir1	if (!supervisor(dc))
4311	0f8a249a	blueswir1	goto priv_insn;
4312	3475187d	bellard	#endif
4313	0f8a249a	blueswir1	if (rd & 1)
4314	d4218d99	blueswir1	goto illegal_insn;
4315	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4316	db166940	blueswir1	gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4317	db166940	blueswir1	goto skip_move;
4318	0f8a249a	blueswir1	case 0x19: /* load signed byte alternate */
4319	3475187d	bellard	#ifndef TARGET_SPARC64
4320	0f8a249a	blueswir1	if (IS_IMM)
4321	0f8a249a	blueswir1	goto illegal_insn;
4322	0f8a249a	blueswir1	if (!supervisor(dc))
4323	0f8a249a	blueswir1	goto priv_insn;
4324	0f8a249a	blueswir1	#endif
4325	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4326	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4327	0f8a249a	blueswir1	break;
4328	0f8a249a	blueswir1	case 0x1a: /* load signed halfword alternate */
4329	3475187d	bellard	#ifndef TARGET_SPARC64
4330	0f8a249a	blueswir1	if (IS_IMM)
4331	0f8a249a	blueswir1	goto illegal_insn;
4332	0f8a249a	blueswir1	if (!supervisor(dc))
4333	0f8a249a	blueswir1	goto priv_insn;
4334	6ea4a6c8	blueswir1	#endif
4335	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4336	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4337	0f8a249a	blueswir1	break;
4338	0f8a249a	blueswir1	case 0x1d: /* ldstuba -- XXX: should be atomically */
4339	3475187d	bellard	#ifndef TARGET_SPARC64
4340	0f8a249a	blueswir1	if (IS_IMM)
4341	0f8a249a	blueswir1	goto illegal_insn;
4342	0f8a249a	blueswir1	if (!supervisor(dc))
4343	0f8a249a	blueswir1	goto priv_insn;
4344	0f8a249a	blueswir1	#endif
4345	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4346	6ae20372	blueswir1	gen_ldstub_asi(cpu_val, cpu_addr, insn);
4347	0f8a249a	blueswir1	break;
4348	77f193da	blueswir1	case 0x1f: /* swap reg with alt. memory. Also
4349	77f193da	blueswir1	atomically */
4350	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, SWAP);
4351	3475187d	bellard	#ifndef TARGET_SPARC64
4352	0f8a249a	blueswir1	if (IS_IMM)
4353	0f8a249a	blueswir1	goto illegal_insn;
4354	0f8a249a	blueswir1	if (!supervisor(dc))
4355	0f8a249a	blueswir1	goto priv_insn;
4356	6ea4a6c8	blueswir1	#endif
4357	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4358	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4359	6ae20372	blueswir1	gen_swap_asi(cpu_val, cpu_addr, insn);
4360	0f8a249a	blueswir1	break;
4361	3475187d	bellard
4362	3475187d	bellard	#ifndef TARGET_SPARC64
4363	0f8a249a	blueswir1	case 0x30: /* ldc */
4364	0f8a249a	blueswir1	case 0x31: /* ldcsr */
4365	0f8a249a	blueswir1	case 0x33: /* lddc */
4366	0f8a249a	blueswir1	goto ncp_insn;
4367	3475187d	bellard	#endif
4368	3475187d	bellard	#endif
4369	3475187d	bellard	#ifdef TARGET_SPARC64
4370	0f8a249a	blueswir1	case 0x08: /* V9 ldsw */
4371	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4372	6ae20372	blueswir1	tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4373	0f8a249a	blueswir1	break;
4374	0f8a249a	blueswir1	case 0x0b: /* V9 ldx */
4375	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4376	6ae20372	blueswir1	tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4377	0f8a249a	blueswir1	break;
4378	0f8a249a	blueswir1	case 0x18: /* V9 ldswa */
4379	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4380	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4381	0f8a249a	blueswir1	break;
4382	0f8a249a	blueswir1	case 0x1b: /* V9 ldxa */
4383	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4384	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4385	0f8a249a	blueswir1	break;
4386	0f8a249a	blueswir1	case 0x2d: /* V9 prefetch, no effect */
4387	0f8a249a	blueswir1	goto skip_move;
4388	0f8a249a	blueswir1	case 0x30: /* V9 ldfa */
4389	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4390	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 4, rd);
4391	81ad8ba2	blueswir1	goto skip_move;
4392	0f8a249a	blueswir1	case 0x33: /* V9 lddfa */
4393	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4394	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4395	81ad8ba2	blueswir1	goto skip_move;
4396	0f8a249a	blueswir1	case 0x3d: /* V9 prefetcha, no effect */
4397	0f8a249a	blueswir1	goto skip_move;
4398	0f8a249a	blueswir1	case 0x32: /* V9 ldqfa */
4399	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4400	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4401	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4402	1f587329	blueswir1	goto skip_move;
4403	1f587329	blueswir1	#endif
4404	0f8a249a	blueswir1	default:
4405	0f8a249a	blueswir1	goto illegal_insn;
4406	0f8a249a	blueswir1	}
4407	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4408	db166940	blueswir1	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4409	0f8a249a	blueswir1	skip_move: ;
4410	3475187d	bellard	#endif
4411	0f8a249a	blueswir1	} else if (xop >= 0x20 && xop < 0x24) {
4412	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4413	a80dde08	bellard	goto jmp_insn;
4414	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4415	0f8a249a	blueswir1	switch (xop) {
4416	0f8a249a	blueswir1	case 0x20: /* load fpreg */
4417	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4418	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4419	ce8536e2	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
4420	ce8536e2	blueswir1	offsetof(CPUState, fpr[rd]));
4421	0f8a249a	blueswir1	break;
4422	0f8a249a	blueswir1	case 0x21: /* load fsr */
4423	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4424	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4425	ce8536e2	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
4426	ce8536e2	blueswir1	offsetof(CPUState, ft0));
4427	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_ldfsr);
4428	0f8a249a	blueswir1	break;
4429	0f8a249a	blueswir1	case 0x22: /* load quad fpreg */
4430	2ea815ca	blueswir1	{
4431	2ea815ca	blueswir1	TCGv r_const;
4432	2ea815ca	blueswir1
4433	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4434	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4435	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4436	2ea815ca	blueswir1	tcg_temp_free(r_const);
4437	2ea815ca	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
4438	2ea815ca	blueswir1	}
4439	1f587329	blueswir1	break;
4440	0f8a249a	blueswir1	case 0x23: /* load double fpreg */
4441	2ea815ca	blueswir1	{
4442	2ea815ca	blueswir1	TCGv r_const;
4443	2ea815ca	blueswir1
4444	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4445	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4446	2ea815ca	blueswir1	tcg_temp_free(r_const);
4447	2ea815ca	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4448	2ea815ca	blueswir1	}
4449	0f8a249a	blueswir1	break;
4450	0f8a249a	blueswir1	default:
4451	0f8a249a	blueswir1	goto illegal_insn;
4452	0f8a249a	blueswir1	}
4453	0f8a249a	blueswir1	} else if (xop < 8 \|\| (xop >= 0x14 && xop < 0x18) \|\| \
4454	0f8a249a	blueswir1	xop == 0xe \|\| xop == 0x1e) {
4455	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4456	0f8a249a	blueswir1	switch (xop) {
4457	1a2fb1c0	blueswir1	case 0x4: /* store word */
4458	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4459	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4460	0f8a249a	blueswir1	break;
4461	1a2fb1c0	blueswir1	case 0x5: /* store byte */
4462	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4463	6ae20372	blueswir1	tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4464	0f8a249a	blueswir1	break;
4465	1a2fb1c0	blueswir1	case 0x6: /* store halfword */
4466	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4467	6ae20372	blueswir1	tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4468	0f8a249a	blueswir1	break;
4469	1a2fb1c0	blueswir1	case 0x7: /* store double word */
4470	0f8a249a	blueswir1	if (rd & 1)
4471	d4218d99	blueswir1	goto illegal_insn;
4472	1a2fb1c0	blueswir1	else {
4473	2ea815ca	blueswir1	TCGv r_low, r_const;
4474	1a2fb1c0	blueswir1
4475	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4476	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4477	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4478	c2bc0e38	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4479	2ea815ca	blueswir1	r_const); // XXX remove
4480	2ea815ca	blueswir1	tcg_temp_free(r_const);
4481	8d96d209	blueswir1	r_low = tcg_temp_new(TCG_TYPE_TL);
4482	1a2fb1c0	blueswir1	gen_movl_reg_TN(rd + 1, r_low);
4483	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4484	1a2fb1c0	blueswir1	r_low);
4485	2ea815ca	blueswir1	tcg_temp_free(r_low);
4486	6ae20372	blueswir1	tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4487	7fa76c0b	blueswir1	}
4488	0f8a249a	blueswir1	break;
4489	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4490	1a2fb1c0	blueswir1	case 0x14: /* store word alternate */
4491	3475187d	bellard	#ifndef TARGET_SPARC64
4492	0f8a249a	blueswir1	if (IS_IMM)
4493	0f8a249a	blueswir1	goto illegal_insn;
4494	0f8a249a	blueswir1	if (!supervisor(dc))
4495	0f8a249a	blueswir1	goto priv_insn;
4496	3475187d	bellard	#endif
4497	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4498	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 4);
4499	d39c0b99	bellard	break;
4500	1a2fb1c0	blueswir1	case 0x15: /* store byte alternate */
4501	3475187d	bellard	#ifndef TARGET_SPARC64
4502	0f8a249a	blueswir1	if (IS_IMM)
4503	0f8a249a	blueswir1	goto illegal_insn;
4504	0f8a249a	blueswir1	if (!supervisor(dc))
4505	0f8a249a	blueswir1	goto priv_insn;
4506	3475187d	bellard	#endif
4507	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4508	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 1);
4509	d39c0b99	bellard	break;
4510	1a2fb1c0	blueswir1	case 0x16: /* store halfword alternate */
4511	3475187d	bellard	#ifndef TARGET_SPARC64
4512	0f8a249a	blueswir1	if (IS_IMM)
4513	0f8a249a	blueswir1	goto illegal_insn;
4514	0f8a249a	blueswir1	if (!supervisor(dc))
4515	0f8a249a	blueswir1	goto priv_insn;
4516	3475187d	bellard	#endif
4517	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4518	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 2);
4519	d39c0b99	bellard	break;
4520	1a2fb1c0	blueswir1	case 0x17: /* store double word alternate */
4521	3475187d	bellard	#ifndef TARGET_SPARC64
4522	0f8a249a	blueswir1	if (IS_IMM)
4523	0f8a249a	blueswir1	goto illegal_insn;
4524	0f8a249a	blueswir1	if (!supervisor(dc))
4525	0f8a249a	blueswir1	goto priv_insn;
4526	3475187d	bellard	#endif
4527	0f8a249a	blueswir1	if (rd & 1)
4528	d4218d99	blueswir1	goto illegal_insn;
4529	1a2fb1c0	blueswir1	else {
4530	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4531	6ae20372	blueswir1	gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4532	1a2fb1c0	blueswir1	}
4533	d39c0b99	bellard	break;
4534	e80cfcfc	bellard	#endif
4535	3475187d	bellard	#ifdef TARGET_SPARC64
4536	0f8a249a	blueswir1	case 0x0e: /* V9 stx */
4537	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4538	6ae20372	blueswir1	tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4539	0f8a249a	blueswir1	break;
4540	0f8a249a	blueswir1	case 0x1e: /* V9 stxa */
4541	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4542	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 8);
4543	0f8a249a	blueswir1	break;
4544	3475187d	bellard	#endif
4545	0f8a249a	blueswir1	default:
4546	0f8a249a	blueswir1	goto illegal_insn;
4547	0f8a249a	blueswir1	}
4548	0f8a249a	blueswir1	} else if (xop > 0x23 && xop < 0x28) {
4549	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4550	a80dde08	bellard	goto jmp_insn;
4551	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4552	0f8a249a	blueswir1	switch (xop) {
4553	ce8536e2	blueswir1	case 0x24: /* store fpreg */
4554	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4555	ce8536e2	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4556	ce8536e2	blueswir1	offsetof(CPUState, fpr[rd]));
4557	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4558	0f8a249a	blueswir1	break;
4559	0f8a249a	blueswir1	case 0x25: /* stfsr, V9 stxfsr */
4560	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4561	bb5529bb	blueswir1	tcg_gen_helper_0_0(helper_stfsr);
4562	ce8536e2	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4563	ce8536e2	blueswir1	offsetof(CPUState, ft0));
4564	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4565	0f8a249a	blueswir1	break;
4566	1f587329	blueswir1	case 0x26:
4567	1f587329	blueswir1	#ifdef TARGET_SPARC64
4568	1f587329	blueswir1	/* V9 stqf, store quad fpreg */
4569	2ea815ca	blueswir1	{
4570	2ea815ca	blueswir1	TCGv r_const;
4571	2ea815ca	blueswir1
4572	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4573	2ea815ca	blueswir1	gen_op_load_fpr_QT0(QFPREG(rd));
4574	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4575	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4576	2ea815ca	blueswir1	tcg_temp_free(r_const);
4577	2ea815ca	blueswir1	}
4578	1f587329	blueswir1	break;
4579	1f587329	blueswir1	#else /* !TARGET_SPARC64 */
4580	1f587329	blueswir1	/* stdfq, store floating point queue */
4581	1f587329	blueswir1	#if defined(CONFIG_USER_ONLY)
4582	1f587329	blueswir1	goto illegal_insn;
4583	1f587329	blueswir1	#else
4584	0f8a249a	blueswir1	if (!supervisor(dc))
4585	0f8a249a	blueswir1	goto priv_insn;
4586	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4587	0f8a249a	blueswir1	goto jmp_insn;
4588	0f8a249a	blueswir1	goto nfq_insn;
4589	0f8a249a	blueswir1	#endif
4590	1f587329	blueswir1	#endif
4591	7fa76c0b	blueswir1	case 0x27: /* store double fpreg */
4592	2ea815ca	blueswir1	{
4593	2ea815ca	blueswir1	TCGv r_const;
4594	2ea815ca	blueswir1
4595	2ea815ca	blueswir1	gen_op_load_fpr_DT0(DFPREG(rd));
4596	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4597	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4598	2ea815ca	blueswir1	tcg_temp_free(r_const);
4599	2ea815ca	blueswir1	}
4600	0f8a249a	blueswir1	break;
4601	0f8a249a	blueswir1	default:
4602	0f8a249a	blueswir1	goto illegal_insn;
4603	0f8a249a	blueswir1	}
4604	0f8a249a	blueswir1	} else if (xop > 0x33 && xop < 0x3f) {
4605	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4606	0f8a249a	blueswir1	switch (xop) {
4607	a4d17f19	blueswir1	#ifdef TARGET_SPARC64
4608	0f8a249a	blueswir1	case 0x34: /* V9 stfa */
4609	3391c818	blueswir1	gen_op_load_fpr_FT0(rd);
4610	6ae20372	blueswir1	gen_stf_asi(cpu_addr, insn, 4, rd);
4611	0f8a249a	blueswir1	break;
4612	1f587329	blueswir1	case 0x36: /* V9 stqfa */
4613	2ea815ca	blueswir1	{
4614	2ea815ca	blueswir1	TCGv r_const;
4615	2ea815ca	blueswir1
4616	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4617	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4618	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4619	2ea815ca	blueswir1	r_const);
4620	2ea815ca	blueswir1	tcg_temp_free(r_const);
4621	2ea815ca	blueswir1	gen_op_load_fpr_QT0(QFPREG(rd));
4622	2ea815ca	blueswir1	gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4623	2ea815ca	blueswir1	}
4624	1f587329	blueswir1	break;
4625	0f8a249a	blueswir1	case 0x37: /* V9 stdfa */
4626	3391c818	blueswir1	gen_op_load_fpr_DT0(DFPREG(rd));
4627	6ae20372	blueswir1	gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4628	0f8a249a	blueswir1	break;
4629	0f8a249a	blueswir1	case 0x3c: /* V9 casa */
4630	71817e48	blueswir1	gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4631	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4632	0f8a249a	blueswir1	break;
4633	0f8a249a	blueswir1	case 0x3e: /* V9 casxa */
4634	71817e48	blueswir1	gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4635	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4636	0f8a249a	blueswir1	break;
4637	a4d17f19	blueswir1	#else
4638	0f8a249a	blueswir1	case 0x34: /* stc */
4639	0f8a249a	blueswir1	case 0x35: /* stcsr */
4640	0f8a249a	blueswir1	case 0x36: /* stdcq */
4641	0f8a249a	blueswir1	case 0x37: /* stdc */
4642	0f8a249a	blueswir1	goto ncp_insn;
4643	0f8a249a	blueswir1	#endif
4644	0f8a249a	blueswir1	default:
4645	0f8a249a	blueswir1	goto illegal_insn;
4646	0f8a249a	blueswir1	}
4647	e8af50a3	bellard	}
4648	0f8a249a	blueswir1	else
4649	0f8a249a	blueswir1	goto illegal_insn;
4650	0f8a249a	blueswir1	}
4651	0f8a249a	blueswir1	break;
4652	cf495bcf	bellard	}
4653	cf495bcf	bellard	/* default case for non jump instructions */
4654	72cbca10	bellard	if (dc->npc == DYNAMIC_PC) {
4655	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4656	0f8a249a	blueswir1	gen_op_next_insn();
4657	72cbca10	bellard	} else if (dc->npc == JUMP_PC) {
4658	72cbca10	bellard	/* we can do a static jump */
4659	6ae20372	blueswir1	gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4660	72cbca10	bellard	dc->is_br = 1;
4661	72cbca10	bellard	} else {
4662	0f8a249a	blueswir1	dc->pc = dc->npc;
4663	0f8a249a	blueswir1	dc->npc = dc->npc + 4;
4664	cf495bcf	bellard	}
4665	e80cfcfc	bellard	jmp_insn:
4666	cf495bcf	bellard	return;
4667	cf495bcf	bellard	illegal_insn:
4668	2ea815ca	blueswir1	{
4669	2ea815ca	blueswir1	TCGv r_const;
4670	2ea815ca	blueswir1
4671	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4672	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_ILL_INSN);
4673	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4674	2ea815ca	blueswir1	tcg_temp_free(r_const);
4675	2ea815ca	blueswir1	dc->is_br = 1;
4676	2ea815ca	blueswir1	}
4677	e8af50a3	bellard	return;
4678	64a88d5d	blueswir1	unimp_flush:
4679	2ea815ca	blueswir1	{
4680	2ea815ca	blueswir1	TCGv r_const;
4681	2ea815ca	blueswir1
4682	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4683	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4684	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4685	2ea815ca	blueswir1	tcg_temp_free(r_const);
4686	2ea815ca	blueswir1	dc->is_br = 1;
4687	2ea815ca	blueswir1	}
4688	64a88d5d	blueswir1	return;
4689	e80cfcfc	bellard	#if !defined(CONFIG_USER_ONLY)
4690	e8af50a3	bellard	priv_insn:
4691	2ea815ca	blueswir1	{
4692	2ea815ca	blueswir1	TCGv r_const;
4693	2ea815ca	blueswir1
4694	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4695	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_PRIV_INSN);
4696	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4697	2ea815ca	blueswir1	tcg_temp_free(r_const);
4698	2ea815ca	blueswir1	dc->is_br = 1;
4699	2ea815ca	blueswir1	}
4700	e80cfcfc	bellard	return;
4701	64a88d5d	blueswir1	#endif
4702	e80cfcfc	bellard	nfpu_insn:
4703	6ae20372	blueswir1	save_state(dc, cpu_cond);
4704	e80cfcfc	bellard	gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4705	e80cfcfc	bellard	dc->is_br = 1;
4706	fcc72045	blueswir1	return;
4707	64a88d5d	blueswir1	#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4708	9143e598	blueswir1	nfq_insn:
4709	6ae20372	blueswir1	save_state(dc, cpu_cond);
4710	9143e598	blueswir1	gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4711	9143e598	blueswir1	dc->is_br = 1;
4712	9143e598	blueswir1	return;
4713	9143e598	blueswir1	#endif
4714	fcc72045	blueswir1	#ifndef TARGET_SPARC64
4715	fcc72045	blueswir1	ncp_insn:
4716	2ea815ca	blueswir1	{
4717	2ea815ca	blueswir1	TCGv r_const;
4718	2ea815ca	blueswir1
4719	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4720	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_NCP_INSN);
4721	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4722	2ea815ca	blueswir1	tcg_temp_free(r_const);
4723	2ea815ca	blueswir1	dc->is_br = 1;
4724	2ea815ca	blueswir1	}
4725	fcc72045	blueswir1	return;
4726	fcc72045	blueswir1	#endif
4727	7a3f1944	bellard	}
4728	7a3f1944	bellard
4729	2cfc5f17	ths	static inline void gen_intermediate_code_internal(TranslationBlock * tb,
4730	2cfc5f17	ths	int spc, CPUSPARCState *env)
4731	7a3f1944	bellard	{
4732	72cbca10	bellard	target_ulong pc_start, last_pc;
4733	cf495bcf	bellard	uint16_t *gen_opc_end;
4734	cf495bcf	bellard	DisasContext dc1, *dc = &dc1;
4735	e8af50a3	bellard	int j, lj = -1;
4736	2e70f6ef	pbrook	int num_insns;
4737	2e70f6ef	pbrook	int max_insns;
4738	cf495bcf	bellard
4739	cf495bcf	bellard	memset(dc, 0, sizeof(DisasContext));
4740	cf495bcf	bellard	dc->tb = tb;
4741	72cbca10	bellard	pc_start = tb->pc;
4742	cf495bcf	bellard	dc->pc = pc_start;
4743	e80cfcfc	bellard	last_pc = dc->pc;
4744	72cbca10	bellard	dc->npc = (target_ulong) tb->cs_base;
4745	6f27aba6	blueswir1	dc->mem_idx = cpu_mmu_index(env);
4746	5578ceab	blueswir1	dc->def = env->def;
4747	5578ceab	blueswir1	if ((dc->def->features & CPU_FEATURE_FLOAT))
4748	64a88d5d	blueswir1	dc->fpu_enabled = cpu_fpu_enabled(env);
4749	5578ceab	blueswir1	else
4750	64a88d5d	blueswir1	dc->fpu_enabled = 0;
4751	2cade6a3	blueswir1	#ifdef TARGET_SPARC64
4752	2cade6a3	blueswir1	dc->address_mask_32bit = env->pstate & PS_AM;
4753	2cade6a3	blueswir1	#endif
4754	cf495bcf	bellard	gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4755	cf495bcf	bellard
4756	1a2fb1c0	blueswir1	cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4757	8911f501	blueswir1	cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4758	8911f501	blueswir1	cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4759	d987963a	blueswir1
4760	d987963a	blueswir1	cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4761	d987963a	blueswir1
4762	d987963a	blueswir1	// loads and stores
4763	3f0436fe	blueswir1	cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4764	d987963a	blueswir1	cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4765	1a2fb1c0	blueswir1
4766	2e70f6ef	pbrook	num_insns = 0;
4767	2e70f6ef	pbrook	max_insns = tb->cflags & CF_COUNT_MASK;
4768	2e70f6ef	pbrook	if (max_insns == 0)
4769	2e70f6ef	pbrook	max_insns = CF_COUNT_MASK;
4770	2e70f6ef	pbrook	gen_icount_start();
4771	cf495bcf	bellard	do {
4772	e8af50a3	bellard	if (env->nb_breakpoints > 0) {
4773	e8af50a3	bellard	for(j = 0; j < env->nb_breakpoints; j++) {
4774	e8af50a3	bellard	if (env->breakpoints[j] == dc->pc) {
4775	0f8a249a	blueswir1	if (dc->pc != pc_start)
4776	6ae20372	blueswir1	save_state(dc, cpu_cond);
4777	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_debug);
4778	57fec1fe	bellard	tcg_gen_exit_tb(0);
4779	0f8a249a	blueswir1	dc->is_br = 1;
4780	e80cfcfc	bellard	goto exit_gen_loop;
4781	e8af50a3	bellard	}
4782	e8af50a3	bellard	}
4783	e8af50a3	bellard	}
4784	e8af50a3	bellard	if (spc) {
4785	e8af50a3	bellard	if (loglevel > 0)
4786	e8af50a3	bellard	fprintf(logfile, "Search PC...\n");
4787	e8af50a3	bellard	j = gen_opc_ptr - gen_opc_buf;
4788	e8af50a3	bellard	if (lj < j) {
4789	e8af50a3	bellard	lj++;
4790	e8af50a3	bellard	while (lj < j)
4791	e8af50a3	bellard	gen_opc_instr_start[lj++] = 0;
4792	e8af50a3	bellard	gen_opc_pc[lj] = dc->pc;
4793	e8af50a3	bellard	gen_opc_npc[lj] = dc->npc;
4794	e8af50a3	bellard	gen_opc_instr_start[lj] = 1;
4795	2e70f6ef	pbrook	gen_opc_icount[lj] = num_insns;
4796	e8af50a3	bellard	}
4797	e8af50a3	bellard	}
4798	2e70f6ef	pbrook	if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4799	2e70f6ef	pbrook	gen_io_start();
4800	0f8a249a	blueswir1	last_pc = dc->pc;
4801	0f8a249a	blueswir1	disas_sparc_insn(dc);
4802	2e70f6ef	pbrook	num_insns++;
4803	0f8a249a	blueswir1
4804	0f8a249a	blueswir1	if (dc->is_br)
4805	0f8a249a	blueswir1	break;
4806	0f8a249a	blueswir1	/* if the next PC is different, we abort now */
4807	0f8a249a	blueswir1	if (dc->pc != (last_pc + 4))
4808	0f8a249a	blueswir1	break;
4809	d39c0b99	bellard	/* if we reach a page boundary, we stop generation so that the
4810	d39c0b99	bellard	PC of a TT_TFAULT exception is always in the right page */
4811	d39c0b99	bellard	if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4812	d39c0b99	bellard	break;
4813	e80cfcfc	bellard	/* if single step mode, we generate only one instruction and
4814	e80cfcfc	bellard	generate an exception */
4815	e80cfcfc	bellard	if (env->singlestep_enabled) {
4816	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
4817	57fec1fe	bellard	tcg_gen_exit_tb(0);
4818	e80cfcfc	bellard	break;
4819	e80cfcfc	bellard	}
4820	cf495bcf	bellard	} while ((gen_opc_ptr < gen_opc_end) &&
4821	2e70f6ef	pbrook	(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4822	2e70f6ef	pbrook	num_insns < max_insns);
4823	e80cfcfc	bellard
4824	e80cfcfc	bellard	exit_gen_loop:
4825	d987963a	blueswir1	tcg_temp_free(cpu_addr);
4826	3f0436fe	blueswir1	tcg_temp_free(cpu_val);
4827	d987963a	blueswir1	tcg_temp_free(cpu_dst);
4828	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp64);
4829	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp32);
4830	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp0);
4831	2e70f6ef	pbrook	if (tb->cflags & CF_LAST_IO)
4832	2e70f6ef	pbrook	gen_io_end();
4833	72cbca10	bellard	if (!dc->is_br) {
4834	5fafdf24	ths	if (dc->pc != DYNAMIC_PC &&
4835	72cbca10	bellard	(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4836	72cbca10	bellard	/* static PC and NPC: we can use direct chaining */
4837	2f5680ee	blueswir1	gen_goto_tb(dc, 0, dc->pc, dc->npc);
4838	72cbca10	bellard	} else {
4839	72cbca10	bellard	if (dc->pc != DYNAMIC_PC)
4840	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
4841	6ae20372	blueswir1	save_npc(dc, cpu_cond);
4842	57fec1fe	bellard	tcg_gen_exit_tb(0);
4843	72cbca10	bellard	}
4844	72cbca10	bellard	}
4845	2e70f6ef	pbrook	gen_icount_end(tb, num_insns);
4846	cf495bcf	bellard	*gen_opc_ptr = INDEX_op_end;
4847	e8af50a3	bellard	if (spc) {
4848	e8af50a3	bellard	j = gen_opc_ptr - gen_opc_buf;
4849	e8af50a3	bellard	lj++;
4850	e8af50a3	bellard	while (lj <= j)
4851	e8af50a3	bellard	gen_opc_instr_start[lj++] = 0;
4852	e8af50a3	bellard	#if 0
4853	e8af50a3	bellard	if (loglevel > 0) {
4854	e8af50a3	bellard	page_dump(logfile);
4855	e8af50a3	bellard	}
4856	e8af50a3	bellard	#endif
4857	c3278b7b	bellard	gen_opc_jump_pc[0] = dc->jump_pc[0];
4858	c3278b7b	bellard	gen_opc_jump_pc[1] = dc->jump_pc[1];
4859	e8af50a3	bellard	} else {
4860	e80cfcfc	bellard	tb->size = last_pc + 4 - pc_start;
4861	2e70f6ef	pbrook	tb->icount = num_insns;
4862	e8af50a3	bellard	}
4863	7a3f1944	bellard	#ifdef DEBUG_DISAS
4864	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
4865	0f8a249a	blueswir1	fprintf(logfile, "--------------\n");
4866	0f8a249a	blueswir1	fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4867	0f8a249a	blueswir1	target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4868	0f8a249a	blueswir1	fprintf(logfile, "\n");
4869	cf495bcf	bellard	}
4870	7a3f1944	bellard	#endif
4871	7a3f1944	bellard	}
4872	7a3f1944	bellard
4873	2cfc5f17	ths	void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4874	7a3f1944	bellard	{
4875	2cfc5f17	ths	gen_intermediate_code_internal(tb, 0, env);
4876	7a3f1944	bellard	}
4877	7a3f1944	bellard
4878	2cfc5f17	ths	void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4879	7a3f1944	bellard	{
4880	2cfc5f17	ths	gen_intermediate_code_internal(tb, 1, env);
4881	7a3f1944	bellard	}
4882	7a3f1944	bellard
4883	c48fcb47	blueswir1	void gen_intermediate_code_init(CPUSPARCState *env)
4884	e80cfcfc	bellard	{
4885	f5069b26	blueswir1	unsigned int i;
4886	c48fcb47	blueswir1	static int inited;
4887	f5069b26	blueswir1	static const char * const gregnames[8] = {
4888	f5069b26	blueswir1	NULL, // g0 not used
4889	f5069b26	blueswir1	"g1",
4890	f5069b26	blueswir1	"g2",
4891	f5069b26	blueswir1	"g3",
4892	f5069b26	blueswir1	"g4",
4893	f5069b26	blueswir1	"g5",
4894	f5069b26	blueswir1	"g6",
4895	f5069b26	blueswir1	"g7",
4896	f5069b26	blueswir1	};
4897	aaed909a	bellard
4898	1a2fb1c0	blueswir1	/* init various static tables */
4899	1a2fb1c0	blueswir1	if (!inited) {
4900	1a2fb1c0	blueswir1	inited = 1;
4901	1a2fb1c0	blueswir1
4902	1a2fb1c0	blueswir1	cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4903	db4a4ea4	blueswir1	cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4904	db4a4ea4	blueswir1	offsetof(CPUState, regwptr),
4905	db4a4ea4	blueswir1	"regwptr");
4906	1a2fb1c0	blueswir1	#ifdef TARGET_SPARC64
4907	dc99a3f2	blueswir1	cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4908	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, xcc),
4909	dc99a3f2	blueswir1	"xcc");
4910	1a2fb1c0	blueswir1	#endif
4911	7c60cc4b	bellard	cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4912	77f193da	blueswir1	TCG_AREG0, offsetof(CPUState, cond),
4913	77f193da	blueswir1	"cond");
4914	dc99a3f2	blueswir1	cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4915	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, cc_src),
4916	dc99a3f2	blueswir1	"cc_src");
4917	d9bdab86	blueswir1	cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4918	d9bdab86	blueswir1	offsetof(CPUState, cc_src2),
4919	d9bdab86	blueswir1	"cc_src2");
4920	dc99a3f2	blueswir1	cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4921	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, cc_dst),
4922	dc99a3f2	blueswir1	"cc_dst");
4923	dc99a3f2	blueswir1	cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4924	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, psr),
4925	dc99a3f2	blueswir1	"psr");
4926	87e92502	blueswir1	cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4927	87e92502	blueswir1	TCG_AREG0, offsetof(CPUState, fsr),
4928	87e92502	blueswir1	"fsr");
4929	48d5c82b	blueswir1	cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4930	48d5c82b	blueswir1	TCG_AREG0, offsetof(CPUState, pc),
4931	48d5c82b	blueswir1	"pc");
4932	48d5c82b	blueswir1	cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4933	48d5c82b	blueswir1	TCG_AREG0, offsetof(CPUState, npc),
4934	48d5c82b	blueswir1	"npc");
4935	f5069b26	blueswir1	for (i = 1; i < 8; i++)
4936	f5069b26	blueswir1	cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4937	f5069b26	blueswir1	offsetof(CPUState, gregs[i]),
4938	f5069b26	blueswir1	gregnames[i]);
4939	c9e03d8f	blueswir1	/* register helpers */
4940	c9e03d8f	blueswir1
4941	c9e03d8f	blueswir1	#undef DEF_HELPER
4942	c9e03d8f	blueswir1	#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4943	c9e03d8f	blueswir1	#include "helper.h"
4944	1a2fb1c0	blueswir1	}
4945	658138bc	bellard	}
4946	d2856f1a	aurel32
4947	d2856f1a	aurel32	void gen_pc_load(CPUState env, TranslationBlock tb,
4948	d2856f1a	aurel32	unsigned long searched_pc, int pc_pos, void *puc)
4949	d2856f1a	aurel32	{
4950	d2856f1a	aurel32	target_ulong npc;
4951	d2856f1a	aurel32	env->pc = gen_opc_pc[pc_pos];
4952	d2856f1a	aurel32	npc = gen_opc_npc[pc_pos];
4953	d2856f1a	aurel32	if (npc == 1) {
4954	d2856f1a	aurel32	/* dynamic NPC: already stored */
4955	d2856f1a	aurel32	} else if (npc == 2) {
4956	d2856f1a	aurel32	target_ulong t2 = (target_ulong)(unsigned long)puc;
4957	d2856f1a	aurel32	/* jump PC: use T2 and the jump targets of the translation */
4958	d2856f1a	aurel32	if (t2)
4959	d2856f1a	aurel32	env->npc = gen_opc_jump_pc[0];
4960	d2856f1a	aurel32	else
4961	d2856f1a	aurel32	env->npc = gen_opc_jump_pc[1];
4962	d2856f1a	aurel32	} else {
4963	d2856f1a	aurel32	env->npc = npc;
4964	d2856f1a	aurel32	}
4965	d2856f1a	aurel32	}

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