Revision ed396e2b
| b/hw/openrisc/pic_cpu.c | ||
|---|---|---|
| 26 | 26 |
{
|
| 27 | 27 |
OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; |
| 28 | 28 |
CPUState *cs = CPU(cpu); |
| 29 |
int i; |
|
| 30 | 29 |
uint32_t irq_bit = 1 << irq; |
| 31 | 30 |
|
| 32 | 31 |
if (irq > 31 || irq < 0) {
|
| ... | ... | |
| 39 | 38 |
cpu->env.picsr &= ~irq_bit; |
| 40 | 39 |
} |
| 41 | 40 |
|
| 42 |
for (i = 0; i < 32; i++) {
|
|
| 43 |
if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) {
|
|
| 44 |
cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
|
| 45 |
} else {
|
|
| 46 |
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
|
| 47 |
cpu->env.picsr &= ~(1 << i); |
|
| 48 |
} |
|
| 41 |
if (cpu->env.picsr & cpu->env.picmr) {
|
|
| 42 |
cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
|
| 43 |
} else {
|
|
| 44 |
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
|
| 45 |
cpu->env.picsr = 0; |
|
| 49 | 46 |
} |
| 50 | 47 |
} |
| 51 | 48 |
|
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