Revision ed6ec679 target-arm/translate-a64.c

b/target-arm/translate-a64.c
1644 1644
    }
1645 1645
}
1646 1646

  
1647
/* Move wide (immediate) */
1647
/*
1648
 * C3.4.5 Move wide (immediate)
1649
 *
1650
 *  31 30 29 28         23 22 21 20             5 4    0
1651
 * +--+-----+-------------+-----+----------------+------+
1652
 * |sf| opc | 1 0 0 1 0 1 |  hw |  imm16         |  Rd  |
1653
 * +--+-----+-------------+-----+----------------+------+
1654
 *
1655
 * sf: 0 -> 32 bit, 1 -> 64 bit
1656
 * opc: 00 -> N, 10 -> Z, 11 -> K
1657
 * hw: shift/16 (0,16, and sf only 32, 48)
1658
 */
1648 1659
static void disas_movw_imm(DisasContext *s, uint32_t insn)
1649 1660
{
1650
    unsupported_encoding(s, insn);
1661
    int rd = extract32(insn, 0, 5);
1662
    uint64_t imm = extract32(insn, 5, 16);
1663
    int sf = extract32(insn, 31, 1);
1664
    int opc = extract32(insn, 29, 2);
1665
    int pos = extract32(insn, 21, 2) << 4;
1666
    TCGv_i64 tcg_rd = cpu_reg(s, rd);
1667
    TCGv_i64 tcg_imm;
1668

  
1669
    if (!sf && (pos >= 32)) {
1670
        unallocated_encoding(s);
1671
        return;
1672
    }
1673

  
1674
    switch (opc) {
1675
    case 0: /* MOVN */
1676
    case 2: /* MOVZ */
1677
        imm <<= pos;
1678
        if (opc == 0) {
1679
            imm = ~imm;
1680
        }
1681
        if (!sf) {
1682
            imm &= 0xffffffffu;
1683
        }
1684
        tcg_gen_movi_i64(tcg_rd, imm);
1685
        break;
1686
    case 3: /* MOVK */
1687
        tcg_imm = tcg_const_i64(imm);
1688
        tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
1689
        tcg_temp_free_i64(tcg_imm);
1690
        if (!sf) {
1691
            tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
1692
        }
1693
        break;
1694
    default:
1695
        unallocated_encoding(s);
1696
        break;
1697
    }
1651 1698
}
1652 1699

  
1653 1700
/* C3.4.2 Bitfield

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