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1 | 7d13299d | bellard | /*
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2 | 7d13299d | bellard | * i386 emulator main execution loop
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3 | 7d13299d | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 7d13299d | bellard | *
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6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 7d13299d | bellard | *
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11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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15 | 7d13299d | bellard | *
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16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 7d13299d | bellard | */
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20 | e4533c7a | bellard | #include "config.h" |
21 | 93ac68bc | bellard | #include "exec.h" |
22 | 956034d7 | bellard | #include "disas.h" |
23 | 7d13299d | bellard | |
24 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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25 | fbf9eeb3 | bellard | #undef EAX
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26 | fbf9eeb3 | bellard | #undef ECX
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27 | fbf9eeb3 | bellard | #undef EDX
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28 | fbf9eeb3 | bellard | #undef EBX
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29 | fbf9eeb3 | bellard | #undef ESP
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30 | fbf9eeb3 | bellard | #undef EBP
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31 | fbf9eeb3 | bellard | #undef ESI
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32 | fbf9eeb3 | bellard | #undef EDI
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33 | fbf9eeb3 | bellard | #undef EIP
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34 | fbf9eeb3 | bellard | #include <signal.h> |
35 | fbf9eeb3 | bellard | #include <sys/ucontext.h> |
36 | fbf9eeb3 | bellard | #endif
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37 | fbf9eeb3 | bellard | |
38 | 36bdbe54 | bellard | int tb_invalidated_flag;
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39 | 36bdbe54 | bellard | |
40 | dc99065b | bellard | //#define DEBUG_EXEC
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41 | 9de5e440 | bellard | //#define DEBUG_SIGNAL
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42 | 7d13299d | bellard | |
43 | 93ac68bc | bellard | #if defined(TARGET_ARM) || defined(TARGET_SPARC)
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44 | e4533c7a | bellard | /* XXX: unify with i386 target */
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45 | e4533c7a | bellard | void cpu_loop_exit(void) |
46 | e4533c7a | bellard | { |
47 | e4533c7a | bellard | longjmp(env->jmp_env, 1);
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48 | e4533c7a | bellard | } |
49 | e4533c7a | bellard | #endif
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50 | 3475187d | bellard | #ifndef TARGET_SPARC
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51 | 3475187d | bellard | #define reg_T2
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52 | 3475187d | bellard | #endif
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53 | e4533c7a | bellard | |
54 | fbf9eeb3 | bellard | /* exit the current TB from a signal handler. The host registers are
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55 | fbf9eeb3 | bellard | restored in a state compatible with the CPU emulator
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56 | fbf9eeb3 | bellard | */
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57 | fbf9eeb3 | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc) |
58 | fbf9eeb3 | bellard | { |
59 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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60 | fbf9eeb3 | bellard | struct ucontext *uc = puc;
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61 | fbf9eeb3 | bellard | #endif
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62 | fbf9eeb3 | bellard | |
63 | fbf9eeb3 | bellard | env = env1; |
64 | fbf9eeb3 | bellard | |
65 | fbf9eeb3 | bellard | /* XXX: restore cpu registers saved in host registers */
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66 | fbf9eeb3 | bellard | |
67 | fbf9eeb3 | bellard | #if !defined(CONFIG_SOFTMMU)
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68 | fbf9eeb3 | bellard | if (puc) {
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69 | fbf9eeb3 | bellard | /* XXX: use siglongjmp ? */
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70 | fbf9eeb3 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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71 | fbf9eeb3 | bellard | } |
72 | fbf9eeb3 | bellard | #endif
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73 | fbf9eeb3 | bellard | longjmp(env->jmp_env, 1);
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74 | fbf9eeb3 | bellard | } |
75 | fbf9eeb3 | bellard | |
76 | 8a40a180 | bellard | |
77 | 8a40a180 | bellard | static TranslationBlock *tb_find_slow(target_ulong pc,
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78 | 8a40a180 | bellard | target_ulong cs_base, |
79 | 8a40a180 | bellard | unsigned int flags) |
80 | 8a40a180 | bellard | { |
81 | 8a40a180 | bellard | TranslationBlock *tb, **ptb1; |
82 | 8a40a180 | bellard | int code_gen_size;
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83 | 8a40a180 | bellard | unsigned int h; |
84 | 8a40a180 | bellard | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
85 | 8a40a180 | bellard | uint8_t *tc_ptr; |
86 | 8a40a180 | bellard | |
87 | 8a40a180 | bellard | spin_lock(&tb_lock); |
88 | 8a40a180 | bellard | |
89 | 8a40a180 | bellard | tb_invalidated_flag = 0;
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90 | 8a40a180 | bellard | |
91 | 8a40a180 | bellard | regs_to_env(); /* XXX: do it just before cpu_gen_code() */
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92 | 8a40a180 | bellard | |
93 | 8a40a180 | bellard | /* find translated block using physical mappings */
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94 | 8a40a180 | bellard | phys_pc = get_phys_addr_code(env, pc); |
95 | 8a40a180 | bellard | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
96 | 8a40a180 | bellard | phys_page2 = -1;
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97 | 8a40a180 | bellard | h = tb_phys_hash_func(phys_pc); |
98 | 8a40a180 | bellard | ptb1 = &tb_phys_hash[h]; |
99 | 8a40a180 | bellard | for(;;) {
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100 | 8a40a180 | bellard | tb = *ptb1; |
101 | 8a40a180 | bellard | if (!tb)
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102 | 8a40a180 | bellard | goto not_found;
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103 | 8a40a180 | bellard | if (tb->pc == pc &&
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104 | 8a40a180 | bellard | tb->page_addr[0] == phys_page1 &&
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105 | 8a40a180 | bellard | tb->cs_base == cs_base && |
106 | 8a40a180 | bellard | tb->flags == flags) { |
107 | 8a40a180 | bellard | /* check next page if needed */
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108 | 8a40a180 | bellard | if (tb->page_addr[1] != -1) { |
109 | 8a40a180 | bellard | virt_page2 = (pc & TARGET_PAGE_MASK) + |
110 | 8a40a180 | bellard | TARGET_PAGE_SIZE; |
111 | 8a40a180 | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
112 | 8a40a180 | bellard | if (tb->page_addr[1] == phys_page2) |
113 | 8a40a180 | bellard | goto found;
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114 | 8a40a180 | bellard | } else {
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115 | 8a40a180 | bellard | goto found;
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116 | 8a40a180 | bellard | } |
117 | 8a40a180 | bellard | } |
118 | 8a40a180 | bellard | ptb1 = &tb->phys_hash_next; |
119 | 8a40a180 | bellard | } |
120 | 8a40a180 | bellard | not_found:
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121 | 8a40a180 | bellard | /* if no translated code available, then translate it now */
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122 | 8a40a180 | bellard | tb = tb_alloc(pc); |
123 | 8a40a180 | bellard | if (!tb) {
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124 | 8a40a180 | bellard | /* flush must be done */
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125 | 8a40a180 | bellard | tb_flush(env); |
126 | 8a40a180 | bellard | /* cannot fail at this point */
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127 | 8a40a180 | bellard | tb = tb_alloc(pc); |
128 | 8a40a180 | bellard | /* don't forget to invalidate previous TB info */
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129 | 15388002 | bellard | tb_invalidated_flag = 1;
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130 | 8a40a180 | bellard | } |
131 | 8a40a180 | bellard | tc_ptr = code_gen_ptr; |
132 | 8a40a180 | bellard | tb->tc_ptr = tc_ptr; |
133 | 8a40a180 | bellard | tb->cs_base = cs_base; |
134 | 8a40a180 | bellard | tb->flags = flags; |
135 | 8a40a180 | bellard | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
136 | 8a40a180 | bellard | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
137 | 8a40a180 | bellard | |
138 | 8a40a180 | bellard | /* check next page if needed */
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139 | 8a40a180 | bellard | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
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140 | 8a40a180 | bellard | phys_page2 = -1;
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141 | 8a40a180 | bellard | if ((pc & TARGET_PAGE_MASK) != virt_page2) {
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142 | 8a40a180 | bellard | phys_page2 = get_phys_addr_code(env, virt_page2); |
143 | 8a40a180 | bellard | } |
144 | 8a40a180 | bellard | tb_link_phys(tb, phys_pc, phys_page2); |
145 | 8a40a180 | bellard | |
146 | 8a40a180 | bellard | found:
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147 | 8a40a180 | bellard | /* we add the TB in the virtual pc hash table */
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148 | 8a40a180 | bellard | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; |
149 | 8a40a180 | bellard | spin_unlock(&tb_lock); |
150 | 8a40a180 | bellard | return tb;
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151 | 8a40a180 | bellard | } |
152 | 8a40a180 | bellard | |
153 | 8a40a180 | bellard | static inline TranslationBlock *tb_find_fast(void) |
154 | 8a40a180 | bellard | { |
155 | 8a40a180 | bellard | TranslationBlock *tb; |
156 | 8a40a180 | bellard | target_ulong cs_base, pc; |
157 | 8a40a180 | bellard | unsigned int flags; |
158 | 8a40a180 | bellard | |
159 | 8a40a180 | bellard | /* we record a subset of the CPU state. It will
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160 | 8a40a180 | bellard | always be the same before a given translated block
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161 | 8a40a180 | bellard | is executed. */
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162 | 8a40a180 | bellard | #if defined(TARGET_I386)
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163 | 8a40a180 | bellard | flags = env->hflags; |
164 | 8a40a180 | bellard | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
165 | 8a40a180 | bellard | cs_base = env->segs[R_CS].base; |
166 | 8a40a180 | bellard | pc = cs_base + env->eip; |
167 | 8a40a180 | bellard | #elif defined(TARGET_ARM)
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168 | 8a40a180 | bellard | flags = env->thumb | (env->vfp.vec_len << 1)
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169 | b5ff1b31 | bellard | | (env->vfp.vec_stride << 4);
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170 | b5ff1b31 | bellard | if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
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171 | b5ff1b31 | bellard | flags |= (1 << 6); |
172 | 40f137e1 | pbrook | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) |
173 | 40f137e1 | pbrook | flags |= (1 << 7); |
174 | 8a40a180 | bellard | cs_base = 0;
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175 | 8a40a180 | bellard | pc = env->regs[15];
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176 | 8a40a180 | bellard | #elif defined(TARGET_SPARC)
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177 | 8a40a180 | bellard | #ifdef TARGET_SPARC64
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178 | 8a40a180 | bellard | flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); |
179 | 8a40a180 | bellard | #else
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180 | 8a40a180 | bellard | flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1); |
181 | 8a40a180 | bellard | #endif
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182 | 8a40a180 | bellard | cs_base = env->npc; |
183 | 8a40a180 | bellard | pc = env->pc; |
184 | 8a40a180 | bellard | #elif defined(TARGET_PPC)
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185 | 8a40a180 | bellard | flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | |
186 | 8a40a180 | bellard | (msr_se << MSR_SE) | (msr_le << MSR_LE); |
187 | 8a40a180 | bellard | cs_base = 0;
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188 | 8a40a180 | bellard | pc = env->nip; |
189 | 8a40a180 | bellard | #elif defined(TARGET_MIPS)
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190 | 6810e154 | bellard | flags = env->hflags & (MIPS_HFLAGS_TMASK | MIPS_HFLAG_BMASK); |
191 | cc9442b9 | bellard | cs_base = 0;
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192 | 8a40a180 | bellard | pc = env->PC; |
193 | 8a40a180 | bellard | #else
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194 | 8a40a180 | bellard | #error unsupported CPU
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195 | 8a40a180 | bellard | #endif
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196 | 8a40a180 | bellard | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
197 | 8a40a180 | bellard | if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
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198 | 8a40a180 | bellard | tb->flags != flags, 0)) {
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199 | 8a40a180 | bellard | tb = tb_find_slow(pc, cs_base, flags); |
200 | 15388002 | bellard | /* Note: we do it here to avoid a gcc bug on Mac OS X when
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201 | 15388002 | bellard | doing it in tb_find_slow */
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202 | 15388002 | bellard | if (tb_invalidated_flag) {
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203 | 15388002 | bellard | /* as some TB could have been invalidated because
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204 | 15388002 | bellard | of memory exceptions while generating the code, we
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205 | 15388002 | bellard | must recompute the hash index here */
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206 | 15388002 | bellard | T0 = 0;
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207 | 15388002 | bellard | } |
208 | 8a40a180 | bellard | } |
209 | 8a40a180 | bellard | return tb;
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210 | 8a40a180 | bellard | } |
211 | 8a40a180 | bellard | |
212 | 8a40a180 | bellard | |
213 | 7d13299d | bellard | /* main execution loop */
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214 | 7d13299d | bellard | |
215 | e4533c7a | bellard | int cpu_exec(CPUState *env1)
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216 | 7d13299d | bellard | { |
217 | 3475187d | bellard | int saved_T0, saved_T1;
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218 | 3475187d | bellard | #if defined(reg_T2)
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219 | 3475187d | bellard | int saved_T2;
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220 | 3475187d | bellard | #endif
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221 | e4533c7a | bellard | CPUState *saved_env; |
222 | 3475187d | bellard | #if defined(TARGET_I386)
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223 | 04369ff2 | bellard | #ifdef reg_EAX
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224 | 04369ff2 | bellard | int saved_EAX;
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225 | 04369ff2 | bellard | #endif
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226 | 04369ff2 | bellard | #ifdef reg_ECX
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227 | 04369ff2 | bellard | int saved_ECX;
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228 | 04369ff2 | bellard | #endif
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229 | 04369ff2 | bellard | #ifdef reg_EDX
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230 | 04369ff2 | bellard | int saved_EDX;
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231 | 04369ff2 | bellard | #endif
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232 | 04369ff2 | bellard | #ifdef reg_EBX
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233 | 04369ff2 | bellard | int saved_EBX;
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234 | 04369ff2 | bellard | #endif
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235 | 04369ff2 | bellard | #ifdef reg_ESP
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236 | 04369ff2 | bellard | int saved_ESP;
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237 | 04369ff2 | bellard | #endif
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238 | 04369ff2 | bellard | #ifdef reg_EBP
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239 | 04369ff2 | bellard | int saved_EBP;
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240 | 04369ff2 | bellard | #endif
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241 | 04369ff2 | bellard | #ifdef reg_ESI
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242 | 04369ff2 | bellard | int saved_ESI;
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243 | 04369ff2 | bellard | #endif
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244 | 04369ff2 | bellard | #ifdef reg_EDI
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245 | 04369ff2 | bellard | int saved_EDI;
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246 | 04369ff2 | bellard | #endif
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247 | 3475187d | bellard | #elif defined(TARGET_SPARC)
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248 | 3475187d | bellard | #if defined(reg_REGWPTR)
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249 | 3475187d | bellard | uint32_t *saved_regwptr; |
250 | 3475187d | bellard | #endif
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251 | 3475187d | bellard | #endif
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252 | 8c6939c0 | bellard | #ifdef __sparc__
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253 | 8c6939c0 | bellard | int saved_i7, tmp_T0;
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254 | 8c6939c0 | bellard | #endif
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255 | 8a40a180 | bellard | int ret, interrupt_request;
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256 | 7d13299d | bellard | void (*gen_func)(void); |
257 | 8a40a180 | bellard | TranslationBlock *tb; |
258 | c27004ec | bellard | uint8_t *tc_ptr; |
259 | 8c6939c0 | bellard | |
260 | 5a1e3cfc | bellard | #if defined(TARGET_I386)
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261 | 5a1e3cfc | bellard | /* handle exit of HALTED state */
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262 | 5a1e3cfc | bellard | if (env1->hflags & HF_HALTED_MASK) {
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263 | 5a1e3cfc | bellard | /* disable halt condition */
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264 | 5a1e3cfc | bellard | if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
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265 | 5a1e3cfc | bellard | (env1->eflags & IF_MASK)) { |
266 | 5a1e3cfc | bellard | env1->hflags &= ~HF_HALTED_MASK; |
267 | 5a1e3cfc | bellard | } else {
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268 | 5a1e3cfc | bellard | return EXCP_HALTED;
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269 | e80e1cc4 | bellard | } |
270 | e80e1cc4 | bellard | } |
271 | e80e1cc4 | bellard | #elif defined(TARGET_PPC)
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272 | 50443c98 | bellard | if (env1->halted) {
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273 | e80e1cc4 | bellard | if (env1->msr[MSR_EE] &&
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274 | e80e1cc4 | bellard | (env1->interrupt_request & |
275 | e80e1cc4 | bellard | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) { |
276 | 50443c98 | bellard | env1->halted = 0;
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277 | e80e1cc4 | bellard | } else {
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278 | e80e1cc4 | bellard | return EXCP_HALTED;
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279 | 5a1e3cfc | bellard | } |
280 | 5a1e3cfc | bellard | } |
281 | ba3c64fb | bellard | #elif defined(TARGET_SPARC)
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282 | ba3c64fb | bellard | if (env1->halted) {
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283 | ba3c64fb | bellard | if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
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284 | ba3c64fb | bellard | (env1->psret != 0)) {
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285 | ba3c64fb | bellard | env1->halted = 0;
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286 | ba3c64fb | bellard | } else {
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287 | ba3c64fb | bellard | return EXCP_HALTED;
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288 | ba3c64fb | bellard | } |
289 | ba3c64fb | bellard | } |
290 | 9332f9da | bellard | #elif defined(TARGET_ARM)
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291 | 9332f9da | bellard | if (env1->halted) {
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292 | 9332f9da | bellard | /* An interrupt wakes the CPU even if the I and F CPSR bits are
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293 | 9332f9da | bellard | set. */
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294 | 9332f9da | bellard | if (env1->interrupt_request
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295 | 9332f9da | bellard | & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) { |
296 | 9332f9da | bellard | env1->halted = 0;
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297 | 9332f9da | bellard | } else {
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298 | 9332f9da | bellard | return EXCP_HALTED;
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299 | 9332f9da | bellard | } |
300 | 9332f9da | bellard | } |
301 | 6810e154 | bellard | #elif defined(TARGET_MIPS)
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302 | 6810e154 | bellard | if (env1->halted) {
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303 | 6810e154 | bellard | if (env1->interrupt_request &
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304 | 6810e154 | bellard | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { |
305 | 6810e154 | bellard | env1->halted = 0;
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306 | 6810e154 | bellard | } else {
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307 | 6810e154 | bellard | return EXCP_HALTED;
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308 | 6810e154 | bellard | } |
309 | 6810e154 | bellard | } |
310 | 5a1e3cfc | bellard | #endif
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311 | 5a1e3cfc | bellard | |
312 | 6a00d601 | bellard | cpu_single_env = env1; |
313 | 6a00d601 | bellard | |
314 | 7d13299d | bellard | /* first we save global registers */
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315 | c27004ec | bellard | saved_env = env; |
316 | c27004ec | bellard | env = env1; |
317 | 7d13299d | bellard | saved_T0 = T0; |
318 | 7d13299d | bellard | saved_T1 = T1; |
319 | 3475187d | bellard | #if defined(reg_T2)
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320 | e4533c7a | bellard | saved_T2 = T2; |
321 | 3475187d | bellard | #endif
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322 | e4533c7a | bellard | #ifdef __sparc__
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323 | e4533c7a | bellard | /* we also save i7 because longjmp may not restore it */
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324 | e4533c7a | bellard | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
325 | e4533c7a | bellard | #endif
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326 | e4533c7a | bellard | |
327 | e4533c7a | bellard | #if defined(TARGET_I386)
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328 | 04369ff2 | bellard | #ifdef reg_EAX
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329 | 04369ff2 | bellard | saved_EAX = EAX; |
330 | 04369ff2 | bellard | #endif
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331 | 04369ff2 | bellard | #ifdef reg_ECX
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332 | 04369ff2 | bellard | saved_ECX = ECX; |
333 | 04369ff2 | bellard | #endif
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334 | 04369ff2 | bellard | #ifdef reg_EDX
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335 | 04369ff2 | bellard | saved_EDX = EDX; |
336 | 04369ff2 | bellard | #endif
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337 | 04369ff2 | bellard | #ifdef reg_EBX
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338 | 04369ff2 | bellard | saved_EBX = EBX; |
339 | 04369ff2 | bellard | #endif
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340 | 04369ff2 | bellard | #ifdef reg_ESP
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341 | 04369ff2 | bellard | saved_ESP = ESP; |
342 | 04369ff2 | bellard | #endif
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343 | 04369ff2 | bellard | #ifdef reg_EBP
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344 | 04369ff2 | bellard | saved_EBP = EBP; |
345 | 04369ff2 | bellard | #endif
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346 | 04369ff2 | bellard | #ifdef reg_ESI
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347 | 04369ff2 | bellard | saved_ESI = ESI; |
348 | 04369ff2 | bellard | #endif
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349 | 04369ff2 | bellard | #ifdef reg_EDI
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350 | 04369ff2 | bellard | saved_EDI = EDI; |
351 | 04369ff2 | bellard | #endif
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352 | 0d1a29f9 | bellard | |
353 | 0d1a29f9 | bellard | env_to_regs(); |
354 | 9de5e440 | bellard | /* put eflags in CPU temporary format */
|
355 | fc2b4c48 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
356 | fc2b4c48 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
357 | 9de5e440 | bellard | CC_OP = CC_OP_EFLAGS; |
358 | fc2b4c48 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
359 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
360 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
361 | 3475187d | bellard | #if defined(reg_REGWPTR)
|
362 | 3475187d | bellard | saved_regwptr = REGWPTR; |
363 | 3475187d | bellard | #endif
|
364 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
365 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
366 | e4533c7a | bellard | #else
|
367 | e4533c7a | bellard | #error unsupported target CPU
|
368 | e4533c7a | bellard | #endif
|
369 | 3fb2ded1 | bellard | env->exception_index = -1;
|
370 | 9d27abd9 | bellard | |
371 | 7d13299d | bellard | /* prepare setjmp context for exception handling */
|
372 | 3fb2ded1 | bellard | for(;;) {
|
373 | 3fb2ded1 | bellard | if (setjmp(env->jmp_env) == 0) { |
374 | ee8b7021 | bellard | env->current_tb = NULL;
|
375 | 3fb2ded1 | bellard | /* if an exception is pending, we execute it here */
|
376 | 3fb2ded1 | bellard | if (env->exception_index >= 0) { |
377 | 3fb2ded1 | bellard | if (env->exception_index >= EXCP_INTERRUPT) {
|
378 | 3fb2ded1 | bellard | /* exit request from the cpu execution loop */
|
379 | 3fb2ded1 | bellard | ret = env->exception_index; |
380 | 3fb2ded1 | bellard | break;
|
381 | 3fb2ded1 | bellard | } else if (env->user_mode_only) { |
382 | 3fb2ded1 | bellard | /* if user mode only, we simulate a fake exception
|
383 | 3fb2ded1 | bellard | which will be hanlded outside the cpu execution
|
384 | 3fb2ded1 | bellard | loop */
|
385 | 83479e77 | bellard | #if defined(TARGET_I386)
|
386 | 3fb2ded1 | bellard | do_interrupt_user(env->exception_index, |
387 | 3fb2ded1 | bellard | env->exception_is_int, |
388 | 3fb2ded1 | bellard | env->error_code, |
389 | 3fb2ded1 | bellard | env->exception_next_eip); |
390 | 83479e77 | bellard | #endif
|
391 | 3fb2ded1 | bellard | ret = env->exception_index; |
392 | 3fb2ded1 | bellard | break;
|
393 | 3fb2ded1 | bellard | } else {
|
394 | 83479e77 | bellard | #if defined(TARGET_I386)
|
395 | 3fb2ded1 | bellard | /* simulate a real cpu exception. On i386, it can
|
396 | 3fb2ded1 | bellard | trigger new exceptions, but we do not handle
|
397 | 3fb2ded1 | bellard | double or triple faults yet. */
|
398 | 3fb2ded1 | bellard | do_interrupt(env->exception_index, |
399 | 3fb2ded1 | bellard | env->exception_is_int, |
400 | 3fb2ded1 | bellard | env->error_code, |
401 | d05e66d2 | bellard | env->exception_next_eip, 0);
|
402 | ce09776b | bellard | #elif defined(TARGET_PPC)
|
403 | ce09776b | bellard | do_interrupt(env); |
404 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
405 | 6af0bf9c | bellard | do_interrupt(env); |
406 | e95c8d51 | bellard | #elif defined(TARGET_SPARC)
|
407 | 1a0c3292 | bellard | do_interrupt(env->exception_index); |
408 | b5ff1b31 | bellard | #elif defined(TARGET_ARM)
|
409 | b5ff1b31 | bellard | do_interrupt(env); |
410 | 83479e77 | bellard | #endif
|
411 | 3fb2ded1 | bellard | } |
412 | 3fb2ded1 | bellard | env->exception_index = -1;
|
413 | 9df217a3 | bellard | } |
414 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
415 | 9df217a3 | bellard | if (kqemu_is_ok(env) && env->interrupt_request == 0) { |
416 | 9df217a3 | bellard | int ret;
|
417 | 9df217a3 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
418 | 9df217a3 | bellard | ret = kqemu_cpu_exec(env); |
419 | 9df217a3 | bellard | /* put eflags in CPU temporary format */
|
420 | 9df217a3 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
421 | 9df217a3 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
422 | 9df217a3 | bellard | CC_OP = CC_OP_EFLAGS; |
423 | 9df217a3 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
424 | 9df217a3 | bellard | if (ret == 1) { |
425 | 9df217a3 | bellard | /* exception */
|
426 | 9df217a3 | bellard | longjmp(env->jmp_env, 1);
|
427 | 9df217a3 | bellard | } else if (ret == 2) { |
428 | 9df217a3 | bellard | /* softmmu execution needed */
|
429 | 9df217a3 | bellard | } else {
|
430 | 9df217a3 | bellard | if (env->interrupt_request != 0) { |
431 | 9df217a3 | bellard | /* hardware interrupt will be executed just after */
|
432 | 9df217a3 | bellard | } else {
|
433 | 9df217a3 | bellard | /* otherwise, we restart */
|
434 | 9df217a3 | bellard | longjmp(env->jmp_env, 1);
|
435 | 9df217a3 | bellard | } |
436 | 9df217a3 | bellard | } |
437 | 3fb2ded1 | bellard | } |
438 | 9df217a3 | bellard | #endif
|
439 | 9df217a3 | bellard | |
440 | 3fb2ded1 | bellard | T0 = 0; /* force lookup of first TB */ |
441 | 3fb2ded1 | bellard | for(;;) {
|
442 | 8c6939c0 | bellard | #ifdef __sparc__
|
443 | 3fb2ded1 | bellard | /* g1 can be modified by some libc? functions */
|
444 | 3fb2ded1 | bellard | tmp_T0 = T0; |
445 | 8c6939c0 | bellard | #endif
|
446 | 68a79315 | bellard | interrupt_request = env->interrupt_request; |
447 | 2e255c6b | bellard | if (__builtin_expect(interrupt_request, 0)) { |
448 | 68a79315 | bellard | #if defined(TARGET_I386)
|
449 | 68a79315 | bellard | /* if hardware interrupt pending, we execute it */
|
450 | 68a79315 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
451 | 3f337316 | bellard | (env->eflags & IF_MASK) && |
452 | 3f337316 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
453 | 68a79315 | bellard | int intno;
|
454 | fbf9eeb3 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
455 | a541f297 | bellard | intno = cpu_get_pic_interrupt(env); |
456 | f193c797 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
457 | 68a79315 | bellard | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
|
458 | 68a79315 | bellard | } |
459 | d05e66d2 | bellard | do_interrupt(intno, 0, 0, 0, 1); |
460 | 907a5b26 | bellard | /* ensure that no TB jump will be modified as
|
461 | 907a5b26 | bellard | the program flow was changed */
|
462 | 907a5b26 | bellard | #ifdef __sparc__
|
463 | 907a5b26 | bellard | tmp_T0 = 0;
|
464 | 907a5b26 | bellard | #else
|
465 | 907a5b26 | bellard | T0 = 0;
|
466 | 907a5b26 | bellard | #endif
|
467 | 68a79315 | bellard | } |
468 | ce09776b | bellard | #elif defined(TARGET_PPC)
|
469 | 9fddaa0c | bellard | #if 0
|
470 | 9fddaa0c | bellard | if ((interrupt_request & CPU_INTERRUPT_RESET)) {
|
471 | 9fddaa0c | bellard | cpu_ppc_reset(env);
|
472 | 9fddaa0c | bellard | }
|
473 | 9fddaa0c | bellard | #endif
|
474 | 9fddaa0c | bellard | if (msr_ee != 0) { |
475 | 8a40a180 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD)) {
|
476 | 9fddaa0c | bellard | /* Raise it */
|
477 | 9fddaa0c | bellard | env->exception_index = EXCP_EXTERNAL; |
478 | 9fddaa0c | bellard | env->error_code = 0;
|
479 | ce09776b | bellard | do_interrupt(env); |
480 | 8a40a180 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
481 | 8a40a180 | bellard | #ifdef __sparc__
|
482 | 8a40a180 | bellard | tmp_T0 = 0;
|
483 | 8a40a180 | bellard | #else
|
484 | 8a40a180 | bellard | T0 = 0;
|
485 | 8a40a180 | bellard | #endif
|
486 | 8a40a180 | bellard | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
487 | 8a40a180 | bellard | /* Raise it */
|
488 | 8a40a180 | bellard | env->exception_index = EXCP_DECR; |
489 | 8a40a180 | bellard | env->error_code = 0;
|
490 | 8a40a180 | bellard | do_interrupt(env); |
491 | 9fddaa0c | bellard | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
492 | 8a40a180 | bellard | #ifdef __sparc__
|
493 | 8a40a180 | bellard | tmp_T0 = 0;
|
494 | 8a40a180 | bellard | #else
|
495 | 8a40a180 | bellard | T0 = 0;
|
496 | 8a40a180 | bellard | #endif
|
497 | 8a40a180 | bellard | } |
498 | ce09776b | bellard | } |
499 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
500 | 6af0bf9c | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
501 | 6af0bf9c | bellard | (env->CP0_Status & (1 << CP0St_IE)) &&
|
502 | 7ebab699 | bellard | (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
|
503 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_EXL) && |
504 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_ERL) && |
505 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_DM)) { |
506 | 6af0bf9c | bellard | /* Raise it */
|
507 | 6af0bf9c | bellard | env->exception_index = EXCP_EXT_INTERRUPT; |
508 | 6af0bf9c | bellard | env->error_code = 0;
|
509 | 6af0bf9c | bellard | do_interrupt(env); |
510 | 6af0bf9c | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
511 | 8a40a180 | bellard | #ifdef __sparc__
|
512 | 8a40a180 | bellard | tmp_T0 = 0;
|
513 | 8a40a180 | bellard | #else
|
514 | 8a40a180 | bellard | T0 = 0;
|
515 | 8a40a180 | bellard | #endif
|
516 | 6af0bf9c | bellard | } |
517 | e95c8d51 | bellard | #elif defined(TARGET_SPARC)
|
518 | 66321a11 | bellard | if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
519 | 66321a11 | bellard | (env->psret != 0)) {
|
520 | 66321a11 | bellard | int pil = env->interrupt_index & 15; |
521 | 66321a11 | bellard | int type = env->interrupt_index & 0xf0; |
522 | 66321a11 | bellard | |
523 | 66321a11 | bellard | if (((type == TT_EXTINT) &&
|
524 | 66321a11 | bellard | (pil == 15 || pil > env->psrpil)) ||
|
525 | 66321a11 | bellard | type != TT_EXTINT) { |
526 | 66321a11 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
527 | 66321a11 | bellard | do_interrupt(env->interrupt_index); |
528 | 66321a11 | bellard | env->interrupt_index = 0;
|
529 | 8a40a180 | bellard | #ifdef __sparc__
|
530 | 8a40a180 | bellard | tmp_T0 = 0;
|
531 | 8a40a180 | bellard | #else
|
532 | 8a40a180 | bellard | T0 = 0;
|
533 | 8a40a180 | bellard | #endif
|
534 | 66321a11 | bellard | } |
535 | e95c8d51 | bellard | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
536 | e95c8d51 | bellard | //do_interrupt(0, 0, 0, 0, 0);
|
537 | e95c8d51 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
538 | ba3c64fb | bellard | } else if (interrupt_request & CPU_INTERRUPT_HALT) { |
539 | ba3c64fb | bellard | env1->halted = 1;
|
540 | ba3c64fb | bellard | return EXCP_HALTED;
|
541 | ba3c64fb | bellard | } |
542 | b5ff1b31 | bellard | #elif defined(TARGET_ARM)
|
543 | b5ff1b31 | bellard | if (interrupt_request & CPU_INTERRUPT_FIQ
|
544 | b5ff1b31 | bellard | && !(env->uncached_cpsr & CPSR_F)) { |
545 | b5ff1b31 | bellard | env->exception_index = EXCP_FIQ; |
546 | b5ff1b31 | bellard | do_interrupt(env); |
547 | b5ff1b31 | bellard | } |
548 | b5ff1b31 | bellard | if (interrupt_request & CPU_INTERRUPT_HARD
|
549 | b5ff1b31 | bellard | && !(env->uncached_cpsr & CPSR_I)) { |
550 | b5ff1b31 | bellard | env->exception_index = EXCP_IRQ; |
551 | b5ff1b31 | bellard | do_interrupt(env); |
552 | b5ff1b31 | bellard | } |
553 | 68a79315 | bellard | #endif
|
554 | b5ff1b31 | bellard | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
|
555 | bf3e8bf1 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
556 | bf3e8bf1 | bellard | /* ensure that no TB jump will be modified as
|
557 | bf3e8bf1 | bellard | the program flow was changed */
|
558 | bf3e8bf1 | bellard | #ifdef __sparc__
|
559 | bf3e8bf1 | bellard | tmp_T0 = 0;
|
560 | bf3e8bf1 | bellard | #else
|
561 | bf3e8bf1 | bellard | T0 = 0;
|
562 | bf3e8bf1 | bellard | #endif
|
563 | bf3e8bf1 | bellard | } |
564 | 68a79315 | bellard | if (interrupt_request & CPU_INTERRUPT_EXIT) {
|
565 | 68a79315 | bellard | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
566 | 68a79315 | bellard | env->exception_index = EXCP_INTERRUPT; |
567 | 68a79315 | bellard | cpu_loop_exit(); |
568 | 68a79315 | bellard | } |
569 | 3fb2ded1 | bellard | } |
570 | 7d13299d | bellard | #ifdef DEBUG_EXEC
|
571 | b5ff1b31 | bellard | if ((loglevel & CPU_LOG_TB_CPU)) {
|
572 | e4533c7a | bellard | #if defined(TARGET_I386)
|
573 | 3fb2ded1 | bellard | /* restore flags in standard format */
|
574 | fc9f715d | bellard | #ifdef reg_EAX
|
575 | 3fb2ded1 | bellard | env->regs[R_EAX] = EAX; |
576 | fc9f715d | bellard | #endif
|
577 | fc9f715d | bellard | #ifdef reg_EBX
|
578 | 3fb2ded1 | bellard | env->regs[R_EBX] = EBX; |
579 | fc9f715d | bellard | #endif
|
580 | fc9f715d | bellard | #ifdef reg_ECX
|
581 | 3fb2ded1 | bellard | env->regs[R_ECX] = ECX; |
582 | fc9f715d | bellard | #endif
|
583 | fc9f715d | bellard | #ifdef reg_EDX
|
584 | 3fb2ded1 | bellard | env->regs[R_EDX] = EDX; |
585 | fc9f715d | bellard | #endif
|
586 | fc9f715d | bellard | #ifdef reg_ESI
|
587 | 3fb2ded1 | bellard | env->regs[R_ESI] = ESI; |
588 | fc9f715d | bellard | #endif
|
589 | fc9f715d | bellard | #ifdef reg_EDI
|
590 | 3fb2ded1 | bellard | env->regs[R_EDI] = EDI; |
591 | fc9f715d | bellard | #endif
|
592 | fc9f715d | bellard | #ifdef reg_EBP
|
593 | 3fb2ded1 | bellard | env->regs[R_EBP] = EBP; |
594 | fc9f715d | bellard | #endif
|
595 | fc9f715d | bellard | #ifdef reg_ESP
|
596 | 3fb2ded1 | bellard | env->regs[R_ESP] = ESP; |
597 | fc9f715d | bellard | #endif
|
598 | 3fb2ded1 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
599 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
600 | 3fb2ded1 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
601 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
602 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
603 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
604 | 3475187d | bellard | REGWPTR = env->regbase + (env->cwp * 16);
|
605 | 3475187d | bellard | env->regwptr = REGWPTR; |
606 | 3475187d | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
607 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
608 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
609 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
610 | 6af0bf9c | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
611 | e4533c7a | bellard | #else
|
612 | e4533c7a | bellard | #error unsupported target CPU
|
613 | e4533c7a | bellard | #endif
|
614 | 3fb2ded1 | bellard | } |
615 | 7d13299d | bellard | #endif
|
616 | 8a40a180 | bellard | tb = tb_find_fast(); |
617 | 9d27abd9 | bellard | #ifdef DEBUG_EXEC
|
618 | c1135f61 | bellard | if ((loglevel & CPU_LOG_EXEC)) {
|
619 | c27004ec | bellard | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
620 | c27004ec | bellard | (long)tb->tc_ptr, tb->pc,
|
621 | c27004ec | bellard | lookup_symbol(tb->pc)); |
622 | 3fb2ded1 | bellard | } |
623 | 9d27abd9 | bellard | #endif
|
624 | 8c6939c0 | bellard | #ifdef __sparc__
|
625 | 3fb2ded1 | bellard | T0 = tmp_T0; |
626 | 8c6939c0 | bellard | #endif
|
627 | 8a40a180 | bellard | /* see if we can patch the calling TB. When the TB
|
628 | 8a40a180 | bellard | spans two pages, we cannot safely do a direct
|
629 | 8a40a180 | bellard | jump. */
|
630 | c27004ec | bellard | { |
631 | 8a40a180 | bellard | if (T0 != 0 && |
632 | f32fc648 | bellard | #if USE_KQEMU
|
633 | f32fc648 | bellard | (env->kqemu_enabled != 2) &&
|
634 | f32fc648 | bellard | #endif
|
635 | 8a40a180 | bellard | tb->page_addr[1] == -1 |
636 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
637 | bf3e8bf1 | bellard | && (tb->cflags & CF_CODE_COPY) == |
638 | bf3e8bf1 | bellard | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
639 | bf3e8bf1 | bellard | #endif
|
640 | bf3e8bf1 | bellard | ) { |
641 | 3fb2ded1 | bellard | spin_lock(&tb_lock); |
642 | c27004ec | bellard | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
643 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
644 | 97eb5b14 | bellard | /* propagates the FP use info */
|
645 | 97eb5b14 | bellard | ((TranslationBlock *)(T0 & ~3))->cflags |=
|
646 | 97eb5b14 | bellard | (tb->cflags & CF_FP_USED); |
647 | 97eb5b14 | bellard | #endif
|
648 | 3fb2ded1 | bellard | spin_unlock(&tb_lock); |
649 | 3fb2ded1 | bellard | } |
650 | c27004ec | bellard | } |
651 | 3fb2ded1 | bellard | tc_ptr = tb->tc_ptr; |
652 | 83479e77 | bellard | env->current_tb = tb; |
653 | 3fb2ded1 | bellard | /* execute the generated code */
|
654 | 3fb2ded1 | bellard | gen_func = (void *)tc_ptr;
|
655 | 8c6939c0 | bellard | #if defined(__sparc__)
|
656 | 3fb2ded1 | bellard | __asm__ __volatile__("call %0\n\t"
|
657 | 3fb2ded1 | bellard | "mov %%o7,%%i0"
|
658 | 3fb2ded1 | bellard | : /* no outputs */
|
659 | 3fb2ded1 | bellard | : "r" (gen_func)
|
660 | 3fb2ded1 | bellard | : "i0", "i1", "i2", "i3", "i4", "i5"); |
661 | 8c6939c0 | bellard | #elif defined(__arm__)
|
662 | 3fb2ded1 | bellard | asm volatile ("mov pc, %0\n\t" |
663 | 3fb2ded1 | bellard | ".global exec_loop\n\t"
|
664 | 3fb2ded1 | bellard | "exec_loop:\n\t"
|
665 | 3fb2ded1 | bellard | : /* no outputs */
|
666 | 3fb2ded1 | bellard | : "r" (gen_func)
|
667 | 3fb2ded1 | bellard | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
668 | bf3e8bf1 | bellard | #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
669 | bf3e8bf1 | bellard | { |
670 | bf3e8bf1 | bellard | if (!(tb->cflags & CF_CODE_COPY)) {
|
671 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
672 | 97eb5b14 | bellard | save_native_fp_state(env); |
673 | 97eb5b14 | bellard | } |
674 | bf3e8bf1 | bellard | gen_func(); |
675 | bf3e8bf1 | bellard | } else {
|
676 | 97eb5b14 | bellard | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
677 | 97eb5b14 | bellard | restore_native_fp_state(env); |
678 | 97eb5b14 | bellard | } |
679 | bf3e8bf1 | bellard | /* we work with native eflags */
|
680 | bf3e8bf1 | bellard | CC_SRC = cc_table[CC_OP].compute_all(); |
681 | bf3e8bf1 | bellard | CC_OP = CC_OP_EFLAGS; |
682 | bf3e8bf1 | bellard | asm(".globl exec_loop\n" |
683 | bf3e8bf1 | bellard | "\n"
|
684 | bf3e8bf1 | bellard | "debug1:\n"
|
685 | bf3e8bf1 | bellard | " pushl %%ebp\n"
|
686 | bf3e8bf1 | bellard | " fs movl %10, %9\n"
|
687 | bf3e8bf1 | bellard | " fs movl %11, %%eax\n"
|
688 | bf3e8bf1 | bellard | " andl $0x400, %%eax\n"
|
689 | bf3e8bf1 | bellard | " fs orl %8, %%eax\n"
|
690 | bf3e8bf1 | bellard | " pushl %%eax\n"
|
691 | bf3e8bf1 | bellard | " popf\n"
|
692 | bf3e8bf1 | bellard | " fs movl %%esp, %12\n"
|
693 | bf3e8bf1 | bellard | " fs movl %0, %%eax\n"
|
694 | bf3e8bf1 | bellard | " fs movl %1, %%ecx\n"
|
695 | bf3e8bf1 | bellard | " fs movl %2, %%edx\n"
|
696 | bf3e8bf1 | bellard | " fs movl %3, %%ebx\n"
|
697 | bf3e8bf1 | bellard | " fs movl %4, %%esp\n"
|
698 | bf3e8bf1 | bellard | " fs movl %5, %%ebp\n"
|
699 | bf3e8bf1 | bellard | " fs movl %6, %%esi\n"
|
700 | bf3e8bf1 | bellard | " fs movl %7, %%edi\n"
|
701 | bf3e8bf1 | bellard | " fs jmp *%9\n"
|
702 | bf3e8bf1 | bellard | "exec_loop:\n"
|
703 | bf3e8bf1 | bellard | " fs movl %%esp, %4\n"
|
704 | bf3e8bf1 | bellard | " fs movl %12, %%esp\n"
|
705 | bf3e8bf1 | bellard | " fs movl %%eax, %0\n"
|
706 | bf3e8bf1 | bellard | " fs movl %%ecx, %1\n"
|
707 | bf3e8bf1 | bellard | " fs movl %%edx, %2\n"
|
708 | bf3e8bf1 | bellard | " fs movl %%ebx, %3\n"
|
709 | bf3e8bf1 | bellard | " fs movl %%ebp, %5\n"
|
710 | bf3e8bf1 | bellard | " fs movl %%esi, %6\n"
|
711 | bf3e8bf1 | bellard | " fs movl %%edi, %7\n"
|
712 | bf3e8bf1 | bellard | " pushf\n"
|
713 | bf3e8bf1 | bellard | " popl %%eax\n"
|
714 | bf3e8bf1 | bellard | " movl %%eax, %%ecx\n"
|
715 | bf3e8bf1 | bellard | " andl $0x400, %%ecx\n"
|
716 | bf3e8bf1 | bellard | " shrl $9, %%ecx\n"
|
717 | bf3e8bf1 | bellard | " andl $0x8d5, %%eax\n"
|
718 | bf3e8bf1 | bellard | " fs movl %%eax, %8\n"
|
719 | bf3e8bf1 | bellard | " movl $1, %%eax\n"
|
720 | bf3e8bf1 | bellard | " subl %%ecx, %%eax\n"
|
721 | bf3e8bf1 | bellard | " fs movl %%eax, %11\n"
|
722 | bf3e8bf1 | bellard | " fs movl %9, %%ebx\n" /* get T0 value */ |
723 | bf3e8bf1 | bellard | " popl %%ebp\n"
|
724 | bf3e8bf1 | bellard | : |
725 | bf3e8bf1 | bellard | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
726 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
727 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
728 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
729 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
730 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
731 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
732 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
733 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
734 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
735 | bf3e8bf1 | bellard | "a" (gen_func),
|
736 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, df)),
|
737 | bf3e8bf1 | bellard | "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
738 | bf3e8bf1 | bellard | : "%ecx", "%edx" |
739 | bf3e8bf1 | bellard | ); |
740 | bf3e8bf1 | bellard | } |
741 | bf3e8bf1 | bellard | } |
742 | b8076a74 | bellard | #elif defined(__ia64)
|
743 | b8076a74 | bellard | struct fptr {
|
744 | b8076a74 | bellard | void *ip;
|
745 | b8076a74 | bellard | void *gp;
|
746 | b8076a74 | bellard | } fp; |
747 | b8076a74 | bellard | |
748 | b8076a74 | bellard | fp.ip = tc_ptr; |
749 | b8076a74 | bellard | fp.gp = code_gen_buffer + 2 * (1 << 20); |
750 | b8076a74 | bellard | (*(void (*)(void)) &fp)(); |
751 | ae228531 | bellard | #else
|
752 | 3fb2ded1 | bellard | gen_func(); |
753 | ae228531 | bellard | #endif
|
754 | 83479e77 | bellard | env->current_tb = NULL;
|
755 | 4cbf74b6 | bellard | /* reset soft MMU for next block (it can currently
|
756 | 4cbf74b6 | bellard | only be set by a memory fault) */
|
757 | 4cbf74b6 | bellard | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
758 | 3f337316 | bellard | if (env->hflags & HF_SOFTMMU_MASK) {
|
759 | 3f337316 | bellard | env->hflags &= ~HF_SOFTMMU_MASK; |
760 | 4cbf74b6 | bellard | /* do not allow linking to another block */
|
761 | 4cbf74b6 | bellard | T0 = 0;
|
762 | 4cbf74b6 | bellard | } |
763 | 4cbf74b6 | bellard | #endif
|
764 | f32fc648 | bellard | #if defined(USE_KQEMU)
|
765 | f32fc648 | bellard | #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000) |
766 | f32fc648 | bellard | if (kqemu_is_ok(env) &&
|
767 | f32fc648 | bellard | (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) { |
768 | f32fc648 | bellard | cpu_loop_exit(); |
769 | f32fc648 | bellard | } |
770 | f32fc648 | bellard | #endif
|
771 | 3fb2ded1 | bellard | } |
772 | 3fb2ded1 | bellard | } else {
|
773 | 0d1a29f9 | bellard | env_to_regs(); |
774 | 7d13299d | bellard | } |
775 | 3fb2ded1 | bellard | } /* for(;;) */
|
776 | 3fb2ded1 | bellard | |
777 | 7d13299d | bellard | |
778 | e4533c7a | bellard | #if defined(TARGET_I386)
|
779 | 97eb5b14 | bellard | #if defined(USE_CODE_COPY)
|
780 | 97eb5b14 | bellard | if (env->native_fp_regs) {
|
781 | 97eb5b14 | bellard | save_native_fp_state(env); |
782 | 97eb5b14 | bellard | } |
783 | 97eb5b14 | bellard | #endif
|
784 | 9de5e440 | bellard | /* restore flags in standard format */
|
785 | fc2b4c48 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
786 | 9de5e440 | bellard | |
787 | 7d13299d | bellard | /* restore global registers */
|
788 | 04369ff2 | bellard | #ifdef reg_EAX
|
789 | 04369ff2 | bellard | EAX = saved_EAX; |
790 | 04369ff2 | bellard | #endif
|
791 | 04369ff2 | bellard | #ifdef reg_ECX
|
792 | 04369ff2 | bellard | ECX = saved_ECX; |
793 | 04369ff2 | bellard | #endif
|
794 | 04369ff2 | bellard | #ifdef reg_EDX
|
795 | 04369ff2 | bellard | EDX = saved_EDX; |
796 | 04369ff2 | bellard | #endif
|
797 | 04369ff2 | bellard | #ifdef reg_EBX
|
798 | 04369ff2 | bellard | EBX = saved_EBX; |
799 | 04369ff2 | bellard | #endif
|
800 | 04369ff2 | bellard | #ifdef reg_ESP
|
801 | 04369ff2 | bellard | ESP = saved_ESP; |
802 | 04369ff2 | bellard | #endif
|
803 | 04369ff2 | bellard | #ifdef reg_EBP
|
804 | 04369ff2 | bellard | EBP = saved_EBP; |
805 | 04369ff2 | bellard | #endif
|
806 | 04369ff2 | bellard | #ifdef reg_ESI
|
807 | 04369ff2 | bellard | ESI = saved_ESI; |
808 | 04369ff2 | bellard | #endif
|
809 | 04369ff2 | bellard | #ifdef reg_EDI
|
810 | 04369ff2 | bellard | EDI = saved_EDI; |
811 | 04369ff2 | bellard | #endif
|
812 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
813 | b7bcbe95 | bellard | /* XXX: Save/restore host fpu exception state?. */
|
814 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
815 | 3475187d | bellard | #if defined(reg_REGWPTR)
|
816 | 3475187d | bellard | REGWPTR = saved_regwptr; |
817 | 3475187d | bellard | #endif
|
818 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
819 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
820 | e4533c7a | bellard | #else
|
821 | e4533c7a | bellard | #error unsupported target CPU
|
822 | e4533c7a | bellard | #endif
|
823 | 8c6939c0 | bellard | #ifdef __sparc__
|
824 | 8c6939c0 | bellard | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
825 | 8c6939c0 | bellard | #endif
|
826 | 7d13299d | bellard | T0 = saved_T0; |
827 | 7d13299d | bellard | T1 = saved_T1; |
828 | 3475187d | bellard | #if defined(reg_T2)
|
829 | e4533c7a | bellard | T2 = saved_T2; |
830 | 3475187d | bellard | #endif
|
831 | 7d13299d | bellard | env = saved_env; |
832 | 6a00d601 | bellard | /* fail safe : never use cpu_single_env outside cpu_exec() */
|
833 | 6a00d601 | bellard | cpu_single_env = NULL;
|
834 | 7d13299d | bellard | return ret;
|
835 | 7d13299d | bellard | } |
836 | 6dbad63e | bellard | |
837 | fbf9eeb3 | bellard | /* must only be called from the generated code as an exception can be
|
838 | fbf9eeb3 | bellard | generated */
|
839 | fbf9eeb3 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
840 | fbf9eeb3 | bellard | { |
841 | dc5d0b3d | bellard | /* XXX: cannot enable it yet because it yields to MMU exception
|
842 | dc5d0b3d | bellard | where NIP != read address on PowerPC */
|
843 | dc5d0b3d | bellard | #if 0
|
844 | fbf9eeb3 | bellard | target_ulong phys_addr;
|
845 | fbf9eeb3 | bellard | phys_addr = get_phys_addr_code(env, start);
|
846 | fbf9eeb3 | bellard | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
847 | dc5d0b3d | bellard | #endif
|
848 | fbf9eeb3 | bellard | } |
849 | fbf9eeb3 | bellard | |
850 | 1a18c71b | bellard | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
851 | e4533c7a | bellard | |
852 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
853 | 6dbad63e | bellard | { |
854 | 6dbad63e | bellard | CPUX86State *saved_env; |
855 | 6dbad63e | bellard | |
856 | 6dbad63e | bellard | saved_env = env; |
857 | 6dbad63e | bellard | env = s; |
858 | a412ac57 | bellard | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
859 | a513fe19 | bellard | selector &= 0xffff;
|
860 | 2e255c6b | bellard | cpu_x86_load_seg_cache(env, seg_reg, selector, |
861 | c27004ec | bellard | (selector << 4), 0xffff, 0); |
862 | a513fe19 | bellard | } else {
|
863 | b453b70b | bellard | load_seg(seg_reg, selector); |
864 | a513fe19 | bellard | } |
865 | 6dbad63e | bellard | env = saved_env; |
866 | 6dbad63e | bellard | } |
867 | 9de5e440 | bellard | |
868 | d0a1ffc9 | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
869 | d0a1ffc9 | bellard | { |
870 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
871 | d0a1ffc9 | bellard | |
872 | d0a1ffc9 | bellard | saved_env = env; |
873 | d0a1ffc9 | bellard | env = s; |
874 | d0a1ffc9 | bellard | |
875 | c27004ec | bellard | helper_fsave((target_ulong)ptr, data32); |
876 | d0a1ffc9 | bellard | |
877 | d0a1ffc9 | bellard | env = saved_env; |
878 | d0a1ffc9 | bellard | } |
879 | d0a1ffc9 | bellard | |
880 | d0a1ffc9 | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
881 | d0a1ffc9 | bellard | { |
882 | d0a1ffc9 | bellard | CPUX86State *saved_env; |
883 | d0a1ffc9 | bellard | |
884 | d0a1ffc9 | bellard | saved_env = env; |
885 | d0a1ffc9 | bellard | env = s; |
886 | d0a1ffc9 | bellard | |
887 | c27004ec | bellard | helper_frstor((target_ulong)ptr, data32); |
888 | d0a1ffc9 | bellard | |
889 | d0a1ffc9 | bellard | env = saved_env; |
890 | d0a1ffc9 | bellard | } |
891 | d0a1ffc9 | bellard | |
892 | e4533c7a | bellard | #endif /* TARGET_I386 */ |
893 | e4533c7a | bellard | |
894 | 67b915a5 | bellard | #if !defined(CONFIG_SOFTMMU)
|
895 | 67b915a5 | bellard | |
896 | 3fb2ded1 | bellard | #if defined(TARGET_I386)
|
897 | 3fb2ded1 | bellard | |
898 | b56dad1c | bellard | /* 'pc' is the host PC at which the exception was raised. 'address' is
|
899 | fd6ce8f6 | bellard | the effective address of the memory exception. 'is_write' is 1 if a
|
900 | fd6ce8f6 | bellard | write caused the exception and otherwise 0'. 'old_set' is the
|
901 | fd6ce8f6 | bellard | signal set which should be restored */
|
902 | 2b413144 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
903 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
904 | bf3e8bf1 | bellard | void *puc)
|
905 | 9de5e440 | bellard | { |
906 | a513fe19 | bellard | TranslationBlock *tb; |
907 | a513fe19 | bellard | int ret;
|
908 | 68a79315 | bellard | |
909 | 83479e77 | bellard | if (cpu_single_env)
|
910 | 83479e77 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
911 | fd6ce8f6 | bellard | #if defined(DEBUG_SIGNAL)
|
912 | bf3e8bf1 | bellard | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
913 | bf3e8bf1 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
914 | 9de5e440 | bellard | #endif
|
915 | 25eb4484 | bellard | /* XXX: locking issue */
|
916 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
917 | fd6ce8f6 | bellard | return 1; |
918 | fd6ce8f6 | bellard | } |
919 | fbf9eeb3 | bellard | |
920 | 3fb2ded1 | bellard | /* see if it is an MMU fault */
|
921 | 93a40ea9 | bellard | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
922 | 93a40ea9 | bellard | ((env->hflags & HF_CPL_MASK) == 3), 0); |
923 | 3fb2ded1 | bellard | if (ret < 0) |
924 | 3fb2ded1 | bellard | return 0; /* not an MMU fault */ |
925 | 3fb2ded1 | bellard | if (ret == 0) |
926 | 3fb2ded1 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
927 | 3fb2ded1 | bellard | /* now we have a real cpu fault */
|
928 | a513fe19 | bellard | tb = tb_find_pc(pc); |
929 | a513fe19 | bellard | if (tb) {
|
930 | 9de5e440 | bellard | /* the PC is inside the translated code. It means that we have
|
931 | 9de5e440 | bellard | a virtual CPU fault */
|
932 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
933 | 3fb2ded1 | bellard | } |
934 | 4cbf74b6 | bellard | if (ret == 1) { |
935 | 3fb2ded1 | bellard | #if 0
|
936 | 4cbf74b6 | bellard | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
937 | 4cbf74b6 | bellard | env->eip, env->cr[2], env->error_code);
|
938 | 3fb2ded1 | bellard | #endif
|
939 | 4cbf74b6 | bellard | /* we restore the process signal mask as the sigreturn should
|
940 | 4cbf74b6 | bellard | do it (XXX: use sigsetjmp) */
|
941 | 4cbf74b6 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
942 | 54ca9095 | bellard | raise_exception_err(env->exception_index, env->error_code); |
943 | 4cbf74b6 | bellard | } else {
|
944 | 4cbf74b6 | bellard | /* activate soft MMU for this block */
|
945 | 3f337316 | bellard | env->hflags |= HF_SOFTMMU_MASK; |
946 | fbf9eeb3 | bellard | cpu_resume_from_signal(env, puc); |
947 | 4cbf74b6 | bellard | } |
948 | 3fb2ded1 | bellard | /* never comes here */
|
949 | 3fb2ded1 | bellard | return 1; |
950 | 3fb2ded1 | bellard | } |
951 | 3fb2ded1 | bellard | |
952 | e4533c7a | bellard | #elif defined(TARGET_ARM)
|
953 | 3fb2ded1 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
954 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
955 | bf3e8bf1 | bellard | void *puc)
|
956 | 3fb2ded1 | bellard | { |
957 | 68016c62 | bellard | TranslationBlock *tb; |
958 | 68016c62 | bellard | int ret;
|
959 | 68016c62 | bellard | |
960 | 68016c62 | bellard | if (cpu_single_env)
|
961 | 68016c62 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
962 | 68016c62 | bellard | #if defined(DEBUG_SIGNAL)
|
963 | 68016c62 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
964 | 68016c62 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
965 | 68016c62 | bellard | #endif
|
966 | 9f0777ed | bellard | /* XXX: locking issue */
|
967 | 9f0777ed | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
968 | 9f0777ed | bellard | return 1; |
969 | 9f0777ed | bellard | } |
970 | 68016c62 | bellard | /* see if it is an MMU fault */
|
971 | 68016c62 | bellard | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); |
972 | 68016c62 | bellard | if (ret < 0) |
973 | 68016c62 | bellard | return 0; /* not an MMU fault */ |
974 | 68016c62 | bellard | if (ret == 0) |
975 | 68016c62 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
976 | 68016c62 | bellard | /* now we have a real cpu fault */
|
977 | 68016c62 | bellard | tb = tb_find_pc(pc); |
978 | 68016c62 | bellard | if (tb) {
|
979 | 68016c62 | bellard | /* the PC is inside the translated code. It means that we have
|
980 | 68016c62 | bellard | a virtual CPU fault */
|
981 | 68016c62 | bellard | cpu_restore_state(tb, env, pc, puc); |
982 | 68016c62 | bellard | } |
983 | 68016c62 | bellard | /* we restore the process signal mask as the sigreturn should
|
984 | 68016c62 | bellard | do it (XXX: use sigsetjmp) */
|
985 | 68016c62 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
986 | 68016c62 | bellard | cpu_loop_exit(); |
987 | 3fb2ded1 | bellard | } |
988 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
989 | 93ac68bc | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
990 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
991 | bf3e8bf1 | bellard | void *puc)
|
992 | 93ac68bc | bellard | { |
993 | 68016c62 | bellard | TranslationBlock *tb; |
994 | 68016c62 | bellard | int ret;
|
995 | 68016c62 | bellard | |
996 | 68016c62 | bellard | if (cpu_single_env)
|
997 | 68016c62 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
998 | 68016c62 | bellard | #if defined(DEBUG_SIGNAL)
|
999 | 68016c62 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
1000 | 68016c62 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
1001 | 68016c62 | bellard | #endif
|
1002 | b453b70b | bellard | /* XXX: locking issue */
|
1003 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
1004 | b453b70b | bellard | return 1; |
1005 | b453b70b | bellard | } |
1006 | 68016c62 | bellard | /* see if it is an MMU fault */
|
1007 | 68016c62 | bellard | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); |
1008 | 68016c62 | bellard | if (ret < 0) |
1009 | 68016c62 | bellard | return 0; /* not an MMU fault */ |
1010 | 68016c62 | bellard | if (ret == 0) |
1011 | 68016c62 | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
1012 | 68016c62 | bellard | /* now we have a real cpu fault */
|
1013 | 68016c62 | bellard | tb = tb_find_pc(pc); |
1014 | 68016c62 | bellard | if (tb) {
|
1015 | 68016c62 | bellard | /* the PC is inside the translated code. It means that we have
|
1016 | 68016c62 | bellard | a virtual CPU fault */
|
1017 | 68016c62 | bellard | cpu_restore_state(tb, env, pc, puc); |
1018 | 68016c62 | bellard | } |
1019 | 68016c62 | bellard | /* we restore the process signal mask as the sigreturn should
|
1020 | 68016c62 | bellard | do it (XXX: use sigsetjmp) */
|
1021 | 68016c62 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
1022 | 68016c62 | bellard | cpu_loop_exit(); |
1023 | 93ac68bc | bellard | } |
1024 | 67867308 | bellard | #elif defined (TARGET_PPC)
|
1025 | 67867308 | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
1026 | bf3e8bf1 | bellard | int is_write, sigset_t *old_set,
|
1027 | bf3e8bf1 | bellard | void *puc)
|
1028 | 67867308 | bellard | { |
1029 | 67867308 | bellard | TranslationBlock *tb; |
1030 | ce09776b | bellard | int ret;
|
1031 | 67867308 | bellard | |
1032 | 67867308 | bellard | if (cpu_single_env)
|
1033 | 67867308 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
1034 | 67867308 | bellard | #if defined(DEBUG_SIGNAL)
|
1035 | 67867308 | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
1036 | 67867308 | bellard | pc, address, is_write, *(unsigned long *)old_set); |
1037 | 67867308 | bellard | #endif
|
1038 | 67867308 | bellard | /* XXX: locking issue */
|
1039 | fbf9eeb3 | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
1040 | 67867308 | bellard | return 1; |
1041 | 67867308 | bellard | } |
1042 | 67867308 | bellard | |
1043 | ce09776b | bellard | /* see if it is an MMU fault */
|
1044 | 7f957d28 | bellard | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
1045 | ce09776b | bellard | if (ret < 0) |
1046 | ce09776b | bellard | return 0; /* not an MMU fault */ |
1047 | ce09776b | bellard | if (ret == 0) |
1048 | ce09776b | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
1049 | ce09776b | bellard | |
1050 | 67867308 | bellard | /* now we have a real cpu fault */
|
1051 | 67867308 | bellard | tb = tb_find_pc(pc); |
1052 | 67867308 | bellard | if (tb) {
|
1053 | 67867308 | bellard | /* the PC is inside the translated code. It means that we have
|
1054 | 67867308 | bellard | a virtual CPU fault */
|
1055 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, puc); |
1056 | 67867308 | bellard | } |
1057 | ce09776b | bellard | if (ret == 1) { |
1058 | 67867308 | bellard | #if 0
|
1059 | ce09776b | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
1060 | ce09776b | bellard | env->nip, env->error_code, tb);
|
1061 | 67867308 | bellard | #endif
|
1062 | 67867308 | bellard | /* we restore the process signal mask as the sigreturn should
|
1063 | 67867308 | bellard | do it (XXX: use sigsetjmp) */
|
1064 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
1065 | 9fddaa0c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
1066 | ce09776b | bellard | } else {
|
1067 | ce09776b | bellard | /* activate soft MMU for this block */
|
1068 | fbf9eeb3 | bellard | cpu_resume_from_signal(env, puc); |
1069 | ce09776b | bellard | } |
1070 | 67867308 | bellard | /* never comes here */
|
1071 | 67867308 | bellard | return 1; |
1072 | 67867308 | bellard | } |
1073 | 6af0bf9c | bellard | |
1074 | 6af0bf9c | bellard | #elif defined (TARGET_MIPS)
|
1075 | 6af0bf9c | bellard | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
1076 | 6af0bf9c | bellard | int is_write, sigset_t *old_set,
|
1077 | 6af0bf9c | bellard | void *puc)
|
1078 | 6af0bf9c | bellard | { |
1079 | 6af0bf9c | bellard | TranslationBlock *tb; |
1080 | 6af0bf9c | bellard | int ret;
|
1081 | 6af0bf9c | bellard | |
1082 | 6af0bf9c | bellard | if (cpu_single_env)
|
1083 | 6af0bf9c | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
1084 | 6af0bf9c | bellard | #if defined(DEBUG_SIGNAL)
|
1085 | 6af0bf9c | bellard | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
1086 | 6af0bf9c | bellard | pc, address, is_write, *(unsigned long *)old_set); |
1087 | 6af0bf9c | bellard | #endif
|
1088 | 6af0bf9c | bellard | /* XXX: locking issue */
|
1089 | 6af0bf9c | bellard | if (is_write && page_unprotect(address, pc, puc)) {
|
1090 | 6af0bf9c | bellard | return 1; |
1091 | 6af0bf9c | bellard | } |
1092 | 6af0bf9c | bellard | |
1093 | 6af0bf9c | bellard | /* see if it is an MMU fault */
|
1094 | cc9442b9 | bellard | ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0); |
1095 | 6af0bf9c | bellard | if (ret < 0) |
1096 | 6af0bf9c | bellard | return 0; /* not an MMU fault */ |
1097 | 6af0bf9c | bellard | if (ret == 0) |
1098 | 6af0bf9c | bellard | return 1; /* the MMU fault was handled without causing real CPU fault */ |
1099 | 6af0bf9c | bellard | |
1100 | 6af0bf9c | bellard | /* now we have a real cpu fault */
|
1101 | 6af0bf9c | bellard | tb = tb_find_pc(pc); |
1102 | 6af0bf9c | bellard | if (tb) {
|
1103 | 6af0bf9c | bellard | /* the PC is inside the translated code. It means that we have
|
1104 | 6af0bf9c | bellard | a virtual CPU fault */
|
1105 | 6af0bf9c | bellard | cpu_restore_state(tb, env, pc, puc); |
1106 | 6af0bf9c | bellard | } |
1107 | 6af0bf9c | bellard | if (ret == 1) { |
1108 | 6af0bf9c | bellard | #if 0
|
1109 | 6af0bf9c | bellard | printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
1110 | 6af0bf9c | bellard | env->nip, env->error_code, tb);
|
1111 | 6af0bf9c | bellard | #endif
|
1112 | 6af0bf9c | bellard | /* we restore the process signal mask as the sigreturn should
|
1113 | 6af0bf9c | bellard | do it (XXX: use sigsetjmp) */
|
1114 | 6af0bf9c | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
1115 | 6af0bf9c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
1116 | 6af0bf9c | bellard | } else {
|
1117 | 6af0bf9c | bellard | /* activate soft MMU for this block */
|
1118 | 6af0bf9c | bellard | cpu_resume_from_signal(env, puc); |
1119 | 6af0bf9c | bellard | } |
1120 | 6af0bf9c | bellard | /* never comes here */
|
1121 | 6af0bf9c | bellard | return 1; |
1122 | 6af0bf9c | bellard | } |
1123 | 6af0bf9c | bellard | |
1124 | e4533c7a | bellard | #else
|
1125 | e4533c7a | bellard | #error unsupported target CPU
|
1126 | e4533c7a | bellard | #endif
|
1127 | 9de5e440 | bellard | |
1128 | 2b413144 | bellard | #if defined(__i386__)
|
1129 | 2b413144 | bellard | |
1130 | bf3e8bf1 | bellard | #if defined(USE_CODE_COPY)
|
1131 | bf3e8bf1 | bellard | static void cpu_send_trap(unsigned long pc, int trap, |
1132 | bf3e8bf1 | bellard | struct ucontext *uc)
|
1133 | bf3e8bf1 | bellard | { |
1134 | bf3e8bf1 | bellard | TranslationBlock *tb; |
1135 | bf3e8bf1 | bellard | |
1136 | bf3e8bf1 | bellard | if (cpu_single_env)
|
1137 | bf3e8bf1 | bellard | env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
1138 | bf3e8bf1 | bellard | /* now we have a real cpu fault */
|
1139 | bf3e8bf1 | bellard | tb = tb_find_pc(pc); |
1140 | bf3e8bf1 | bellard | if (tb) {
|
1141 | bf3e8bf1 | bellard | /* the PC is inside the translated code. It means that we have
|
1142 | bf3e8bf1 | bellard | a virtual CPU fault */
|
1143 | bf3e8bf1 | bellard | cpu_restore_state(tb, env, pc, uc); |
1144 | bf3e8bf1 | bellard | } |
1145 | bf3e8bf1 | bellard | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
1146 | bf3e8bf1 | bellard | raise_exception_err(trap, env->error_code); |
1147 | bf3e8bf1 | bellard | } |
1148 | bf3e8bf1 | bellard | #endif
|
1149 | bf3e8bf1 | bellard | |
1150 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1151 | e4533c7a | bellard | void *puc)
|
1152 | 9de5e440 | bellard | { |
1153 | 9de5e440 | bellard | struct ucontext *uc = puc;
|
1154 | 9de5e440 | bellard | unsigned long pc; |
1155 | bf3e8bf1 | bellard | int trapno;
|
1156 | 97eb5b14 | bellard | |
1157 | d691f669 | bellard | #ifndef REG_EIP
|
1158 | d691f669 | bellard | /* for glibc 2.1 */
|
1159 | fd6ce8f6 | bellard | #define REG_EIP EIP
|
1160 | fd6ce8f6 | bellard | #define REG_ERR ERR
|
1161 | fd6ce8f6 | bellard | #define REG_TRAPNO TRAPNO
|
1162 | d691f669 | bellard | #endif
|
1163 | fc2b4c48 | bellard | pc = uc->uc_mcontext.gregs[REG_EIP]; |
1164 | bf3e8bf1 | bellard | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
1165 | bf3e8bf1 | bellard | #if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
1166 | bf3e8bf1 | bellard | if (trapno == 0x00 || trapno == 0x05) { |
1167 | bf3e8bf1 | bellard | /* send division by zero or bound exception */
|
1168 | bf3e8bf1 | bellard | cpu_send_trap(pc, trapno, uc); |
1169 | bf3e8bf1 | bellard | return 1; |
1170 | bf3e8bf1 | bellard | } else
|
1171 | bf3e8bf1 | bellard | #endif
|
1172 | bf3e8bf1 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1173 | bf3e8bf1 | bellard | trapno == 0xe ?
|
1174 | bf3e8bf1 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
1175 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
1176 | 2b413144 | bellard | } |
1177 | 2b413144 | bellard | |
1178 | bc51c5c9 | bellard | #elif defined(__x86_64__)
|
1179 | bc51c5c9 | bellard | |
1180 | bc51c5c9 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1181 | bc51c5c9 | bellard | void *puc)
|
1182 | bc51c5c9 | bellard | { |
1183 | bc51c5c9 | bellard | struct ucontext *uc = puc;
|
1184 | bc51c5c9 | bellard | unsigned long pc; |
1185 | bc51c5c9 | bellard | |
1186 | bc51c5c9 | bellard | pc = uc->uc_mcontext.gregs[REG_RIP]; |
1187 | bc51c5c9 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1188 | bc51c5c9 | bellard | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
1189 | bc51c5c9 | bellard | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
1190 | bc51c5c9 | bellard | &uc->uc_sigmask, puc); |
1191 | bc51c5c9 | bellard | } |
1192 | bc51c5c9 | bellard | |
1193 | 83fb7adf | bellard | #elif defined(__powerpc__)
|
1194 | 2b413144 | bellard | |
1195 | 83fb7adf | bellard | /***********************************************************************
|
1196 | 83fb7adf | bellard | * signal context platform-specific definitions
|
1197 | 83fb7adf | bellard | * From Wine
|
1198 | 83fb7adf | bellard | */
|
1199 | 83fb7adf | bellard | #ifdef linux
|
1200 | 83fb7adf | bellard | /* All Registers access - only for local access */
|
1201 | 83fb7adf | bellard | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
1202 | 83fb7adf | bellard | /* Gpr Registers access */
|
1203 | 83fb7adf | bellard | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
1204 | 83fb7adf | bellard | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
1205 | 83fb7adf | bellard | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
1206 | 83fb7adf | bellard | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
1207 | 83fb7adf | bellard | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
1208 | 83fb7adf | bellard | # define LR_sig(context) REG_sig(link, context) /* Link register */ |
1209 | 83fb7adf | bellard | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
1210 | 83fb7adf | bellard | /* Float Registers access */
|
1211 | 83fb7adf | bellard | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
1212 | 83fb7adf | bellard | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
1213 | 83fb7adf | bellard | /* Exception Registers access */
|
1214 | 83fb7adf | bellard | # define DAR_sig(context) REG_sig(dar, context)
|
1215 | 83fb7adf | bellard | # define DSISR_sig(context) REG_sig(dsisr, context)
|
1216 | 83fb7adf | bellard | # define TRAP_sig(context) REG_sig(trap, context)
|
1217 | 83fb7adf | bellard | #endif /* linux */ |
1218 | 83fb7adf | bellard | |
1219 | 83fb7adf | bellard | #ifdef __APPLE__
|
1220 | 83fb7adf | bellard | # include <sys/ucontext.h> |
1221 | 83fb7adf | bellard | typedef struct ucontext SIGCONTEXT; |
1222 | 83fb7adf | bellard | /* All Registers access - only for local access */
|
1223 | 83fb7adf | bellard | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
1224 | 83fb7adf | bellard | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
1225 | 83fb7adf | bellard | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
1226 | 83fb7adf | bellard | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
1227 | 83fb7adf | bellard | /* Gpr Registers access */
|
1228 | 83fb7adf | bellard | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
1229 | 83fb7adf | bellard | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
1230 | 83fb7adf | bellard | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
1231 | 83fb7adf | bellard | # define CTR_sig(context) REG_sig(ctr, context)
|
1232 | 83fb7adf | bellard | # define XER_sig(context) REG_sig(xer, context) /* Link register */ |
1233 | 83fb7adf | bellard | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
1234 | 83fb7adf | bellard | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
1235 | 83fb7adf | bellard | /* Float Registers access */
|
1236 | 83fb7adf | bellard | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
1237 | 83fb7adf | bellard | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
1238 | 83fb7adf | bellard | /* Exception Registers access */
|
1239 | 83fb7adf | bellard | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
1240 | 83fb7adf | bellard | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
1241 | 83fb7adf | bellard | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
1242 | 83fb7adf | bellard | #endif /* __APPLE__ */ |
1243 | 83fb7adf | bellard | |
1244 | d1d9f421 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1245 | e4533c7a | bellard | void *puc)
|
1246 | 2b413144 | bellard | { |
1247 | 25eb4484 | bellard | struct ucontext *uc = puc;
|
1248 | 25eb4484 | bellard | unsigned long pc; |
1249 | 25eb4484 | bellard | int is_write;
|
1250 | 25eb4484 | bellard | |
1251 | 83fb7adf | bellard | pc = IAR_sig(uc); |
1252 | 25eb4484 | bellard | is_write = 0;
|
1253 | 25eb4484 | bellard | #if 0
|
1254 | 25eb4484 | bellard | /* ppc 4xx case */
|
1255 | 83fb7adf | bellard | if (DSISR_sig(uc) & 0x00800000)
|
1256 | 25eb4484 | bellard | is_write = 1;
|
1257 | 25eb4484 | bellard | #else
|
1258 | 83fb7adf | bellard | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
1259 | 25eb4484 | bellard | is_write = 1;
|
1260 | 25eb4484 | bellard | #endif
|
1261 | 25eb4484 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1262 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
1263 | 2b413144 | bellard | } |
1264 | 2b413144 | bellard | |
1265 | 2f87c607 | bellard | #elif defined(__alpha__)
|
1266 | 2f87c607 | bellard | |
1267 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1268 | 2f87c607 | bellard | void *puc)
|
1269 | 2f87c607 | bellard | { |
1270 | 2f87c607 | bellard | struct ucontext *uc = puc;
|
1271 | 2f87c607 | bellard | uint32_t *pc = uc->uc_mcontext.sc_pc; |
1272 | 2f87c607 | bellard | uint32_t insn = *pc; |
1273 | 2f87c607 | bellard | int is_write = 0; |
1274 | 2f87c607 | bellard | |
1275 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
1276 | 2f87c607 | bellard | switch (insn >> 26) { |
1277 | 2f87c607 | bellard | case 0x0d: // stw |
1278 | 2f87c607 | bellard | case 0x0e: // stb |
1279 | 2f87c607 | bellard | case 0x0f: // stq_u |
1280 | 2f87c607 | bellard | case 0x24: // stf |
1281 | 2f87c607 | bellard | case 0x25: // stg |
1282 | 2f87c607 | bellard | case 0x26: // sts |
1283 | 2f87c607 | bellard | case 0x27: // stt |
1284 | 2f87c607 | bellard | case 0x2c: // stl |
1285 | 2f87c607 | bellard | case 0x2d: // stq |
1286 | 2f87c607 | bellard | case 0x2e: // stl_c |
1287 | 2f87c607 | bellard | case 0x2f: // stq_c |
1288 | 2f87c607 | bellard | is_write = 1;
|
1289 | 2f87c607 | bellard | } |
1290 | 2f87c607 | bellard | |
1291 | 2f87c607 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1292 | bf3e8bf1 | bellard | is_write, &uc->uc_sigmask, puc); |
1293 | 2f87c607 | bellard | } |
1294 | 8c6939c0 | bellard | #elif defined(__sparc__)
|
1295 | 8c6939c0 | bellard | |
1296 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1297 | e4533c7a | bellard | void *puc)
|
1298 | 8c6939c0 | bellard | { |
1299 | 8c6939c0 | bellard | uint32_t *regs = (uint32_t *)(info + 1);
|
1300 | 8c6939c0 | bellard | void *sigmask = (regs + 20); |
1301 | 8c6939c0 | bellard | unsigned long pc; |
1302 | 8c6939c0 | bellard | int is_write;
|
1303 | 8c6939c0 | bellard | uint32_t insn; |
1304 | 8c6939c0 | bellard | |
1305 | 8c6939c0 | bellard | /* XXX: is there a standard glibc define ? */
|
1306 | 8c6939c0 | bellard | pc = regs[1];
|
1307 | 8c6939c0 | bellard | /* XXX: need kernel patch to get write flag faster */
|
1308 | 8c6939c0 | bellard | is_write = 0;
|
1309 | 8c6939c0 | bellard | insn = *(uint32_t *)pc; |
1310 | 8c6939c0 | bellard | if ((insn >> 30) == 3) { |
1311 | 8c6939c0 | bellard | switch((insn >> 19) & 0x3f) { |
1312 | 8c6939c0 | bellard | case 0x05: // stb |
1313 | 8c6939c0 | bellard | case 0x06: // sth |
1314 | 8c6939c0 | bellard | case 0x04: // st |
1315 | 8c6939c0 | bellard | case 0x07: // std |
1316 | 8c6939c0 | bellard | case 0x24: // stf |
1317 | 8c6939c0 | bellard | case 0x27: // stdf |
1318 | 8c6939c0 | bellard | case 0x25: // stfsr |
1319 | 8c6939c0 | bellard | is_write = 1;
|
1320 | 8c6939c0 | bellard | break;
|
1321 | 8c6939c0 | bellard | } |
1322 | 8c6939c0 | bellard | } |
1323 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1324 | bf3e8bf1 | bellard | is_write, sigmask, NULL);
|
1325 | 8c6939c0 | bellard | } |
1326 | 8c6939c0 | bellard | |
1327 | 8c6939c0 | bellard | #elif defined(__arm__)
|
1328 | 8c6939c0 | bellard | |
1329 | e4533c7a | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1330 | e4533c7a | bellard | void *puc)
|
1331 | 8c6939c0 | bellard | { |
1332 | 8c6939c0 | bellard | struct ucontext *uc = puc;
|
1333 | 8c6939c0 | bellard | unsigned long pc; |
1334 | 8c6939c0 | bellard | int is_write;
|
1335 | 8c6939c0 | bellard | |
1336 | 8c6939c0 | bellard | pc = uc->uc_mcontext.gregs[R15]; |
1337 | 8c6939c0 | bellard | /* XXX: compute is_write */
|
1338 | 8c6939c0 | bellard | is_write = 0;
|
1339 | 8c6939c0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1340 | 8c6939c0 | bellard | is_write, |
1341 | 8c6939c0 | bellard | &uc->uc_sigmask); |
1342 | 8c6939c0 | bellard | } |
1343 | 8c6939c0 | bellard | |
1344 | 38e584a0 | bellard | #elif defined(__mc68000)
|
1345 | 38e584a0 | bellard | |
1346 | 38e584a0 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1347 | 38e584a0 | bellard | void *puc)
|
1348 | 38e584a0 | bellard | { |
1349 | 38e584a0 | bellard | struct ucontext *uc = puc;
|
1350 | 38e584a0 | bellard | unsigned long pc; |
1351 | 38e584a0 | bellard | int is_write;
|
1352 | 38e584a0 | bellard | |
1353 | 38e584a0 | bellard | pc = uc->uc_mcontext.gregs[16];
|
1354 | 38e584a0 | bellard | /* XXX: compute is_write */
|
1355 | 38e584a0 | bellard | is_write = 0;
|
1356 | 38e584a0 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1357 | 38e584a0 | bellard | is_write, |
1358 | bf3e8bf1 | bellard | &uc->uc_sigmask, puc); |
1359 | 38e584a0 | bellard | } |
1360 | 38e584a0 | bellard | |
1361 | b8076a74 | bellard | #elif defined(__ia64)
|
1362 | b8076a74 | bellard | |
1363 | b8076a74 | bellard | #ifndef __ISR_VALID
|
1364 | b8076a74 | bellard | /* This ought to be in <bits/siginfo.h>... */
|
1365 | b8076a74 | bellard | # define __ISR_VALID 1 |
1366 | b8076a74 | bellard | # define si_flags _sifields._sigfault._si_pad0
|
1367 | b8076a74 | bellard | #endif
|
1368 | b8076a74 | bellard | |
1369 | b8076a74 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc) |
1370 | b8076a74 | bellard | { |
1371 | b8076a74 | bellard | struct ucontext *uc = puc;
|
1372 | b8076a74 | bellard | unsigned long ip; |
1373 | b8076a74 | bellard | int is_write = 0; |
1374 | b8076a74 | bellard | |
1375 | b8076a74 | bellard | ip = uc->uc_mcontext.sc_ip; |
1376 | b8076a74 | bellard | switch (host_signum) {
|
1377 | b8076a74 | bellard | case SIGILL:
|
1378 | b8076a74 | bellard | case SIGFPE:
|
1379 | b8076a74 | bellard | case SIGSEGV:
|
1380 | b8076a74 | bellard | case SIGBUS:
|
1381 | b8076a74 | bellard | case SIGTRAP:
|
1382 | b8076a74 | bellard | if (info->si_code && (info->si_flags & __ISR_VALID))
|
1383 | b8076a74 | bellard | /* ISR.W (write-access) is bit 33: */
|
1384 | b8076a74 | bellard | is_write = (info->si_isr >> 33) & 1; |
1385 | b8076a74 | bellard | break;
|
1386 | b8076a74 | bellard | |
1387 | b8076a74 | bellard | default:
|
1388 | b8076a74 | bellard | break;
|
1389 | b8076a74 | bellard | } |
1390 | b8076a74 | bellard | return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
1391 | b8076a74 | bellard | is_write, |
1392 | b8076a74 | bellard | &uc->uc_sigmask, puc); |
1393 | b8076a74 | bellard | } |
1394 | b8076a74 | bellard | |
1395 | 90cb9493 | bellard | #elif defined(__s390__)
|
1396 | 90cb9493 | bellard | |
1397 | 90cb9493 | bellard | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1398 | 90cb9493 | bellard | void *puc)
|
1399 | 90cb9493 | bellard | { |
1400 | 90cb9493 | bellard | struct ucontext *uc = puc;
|
1401 | 90cb9493 | bellard | unsigned long pc; |
1402 | 90cb9493 | bellard | int is_write;
|
1403 | 90cb9493 | bellard | |
1404 | 90cb9493 | bellard | pc = uc->uc_mcontext.psw.addr; |
1405 | 90cb9493 | bellard | /* XXX: compute is_write */
|
1406 | 90cb9493 | bellard | is_write = 0;
|
1407 | 90cb9493 | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1408 | 90cb9493 | bellard | is_write, |
1409 | 90cb9493 | bellard | &uc->uc_sigmask, puc); |
1410 | 90cb9493 | bellard | } |
1411 | 90cb9493 | bellard | |
1412 | 9de5e440 | bellard | #else
|
1413 | 2b413144 | bellard | |
1414 | 3fb2ded1 | bellard | #error host CPU specific signal handler needed
|
1415 | 2b413144 | bellard | |
1416 | 9de5e440 | bellard | #endif
|
1417 | 67b915a5 | bellard | |
1418 | 67b915a5 | bellard | #endif /* !defined(CONFIG_SOFTMMU) */ |