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/*
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* Qemu PowerPC MPC8544DS board emualtion
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*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Yu Liu, <yu.liu@freescale.com>
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*
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* This file is derived from hw/ppc440_bamboo.c,
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* the copyright for that material belongs to the original owners.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <dirent.h> |
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#include "config.h" |
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#include "qemu-common.h" |
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#include "net.h" |
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#include "hw.h" |
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#include "pc.h" |
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#include "pci.h" |
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#include "boards.h" |
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#include "sysemu.h" |
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#include "kvm.h" |
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#include "kvm_ppc.h" |
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#include "device_tree.h" |
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#include "openpic.h" |
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#include "ppce500.h" |
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#include "loader.h" |
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#include "elf.h" |
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#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" |
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#define UIMAGE_LOAD_BASE 0 |
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#define DTB_LOAD_BASE 0x600000 |
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#define INITRD_LOAD_BASE 0x2000000 |
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#define RAM_SIZES_ALIGN (64UL << 20) |
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#define MPC8544_CCSRBAR_BASE 0xE0000000 |
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#define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000) |
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#define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500) |
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#define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600) |
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#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000) |
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#define MPC8544_PCI_REGS_SIZE 0x1000 |
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#define MPC8544_PCI_IO 0xE1000000 |
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#define MPC8544_PCI_IOLEN 0x10000 |
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#ifdef CONFIG_FDT
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static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop) |
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{ |
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uint32_t cell; |
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int ret;
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ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
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if (ret < 0) { |
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fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
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goto out;
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} |
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ret = qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
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prop, cell); |
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if (ret < 0) { |
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fprintf(stderr, "couldn't set guest /cpus/PowerPC,8544@0/%s\n", prop);
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goto out;
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} |
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out:
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return ret;
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} |
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#endif
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static void *mpc8544_load_device_tree(target_phys_addr_t addr, |
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uint32_t ramsize, |
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target_phys_addr_t initrd_base, |
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target_phys_addr_t initrd_size, |
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const char *kernel_cmdline) |
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{ |
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void *fdt = NULL; |
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#ifdef CONFIG_FDT
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uint32_t mem_reg_property[] = {0, ramsize};
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char *filename;
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int fdt_size;
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int ret;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
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if (!filename) {
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goto out;
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} |
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fdt = load_device_tree(filename, &fdt_size); |
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qemu_free(filename); |
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if (fdt == NULL) { |
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goto out;
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} |
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/* Manipulate device tree in memory. */
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ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, |
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sizeof(mem_reg_property));
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if (ret < 0) |
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fprintf(stderr, "couldn't set /memory/reg\n");
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ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
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initrd_base); |
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if (ret < 0) |
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fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
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ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
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(initrd_base + initrd_size)); |
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if (ret < 0) |
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fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
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ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", |
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kernel_cmdline); |
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if (ret < 0) |
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fprintf(stderr, "couldn't set /chosen/bootargs\n");
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if (kvm_enabled()) {
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struct dirent *dirp;
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DIR *dp; |
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char buf[128]; |
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if ((dp = opendir("/proc/device-tree/cpus/")) == NULL) { |
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printf("Can't open directory /proc/device-tree/cpus/\n");
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goto out;
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} |
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buf[0] = '\0'; |
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while ((dirp = readdir(dp)) != NULL) { |
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if (strncmp(dirp->d_name, "PowerPC", 7) == 0) { |
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snprintf(buf, 128, "/cpus/%s", dirp->d_name); |
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break;
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} |
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} |
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closedir(dp); |
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if (buf[0] == '\0') { |
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printf("Unknow host!\n");
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goto out;
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} |
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mpc8544_copy_soc_cell(fdt, buf, "clock-frequency");
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mpc8544_copy_soc_cell(fdt, buf, "timebase-frequency");
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} |
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cpu_physical_memory_write (addr, (void *)fdt, fdt_size);
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out:
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#endif
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return fdt;
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} |
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static void mpc8544ds_init(ram_addr_t ram_size, |
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const char *boot_device, |
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const char *kernel_filename, |
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const char *kernel_cmdline, |
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const char *initrd_filename, |
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const char *cpu_model) |
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{ |
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PCIBus *pci_bus; |
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CPUState *env; |
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uint64_t elf_entry; |
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uint64_t elf_lowaddr; |
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target_phys_addr_t entry=0;
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target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; |
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target_long kernel_size=0;
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target_ulong dt_base=DTB_LOAD_BASE; |
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target_ulong initrd_base=INITRD_LOAD_BASE; |
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target_long initrd_size=0;
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void *fdt;
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int i=0; |
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unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; |
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qemu_irq *irqs, *mpic, *pci_irqs; |
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SerialState * serial[2];
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/* Setup CPU */
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env = cpu_ppc_init("e500v2_v30");
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if (!env) {
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fprintf(stderr, "Unable to initialize CPU!\n");
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exit(1);
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} |
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/* Fixup Memory size on a alignment boundary */
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ram_size &= ~(RAM_SIZES_ALIGN - 1);
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/* Register Memory */
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cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(ram_size));
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/* MPIC */
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irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
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irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT]; |
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irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT]; |
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mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL); |
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/* Serial */
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if (serial_hds[0]) |
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serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
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0, mpic[12+26], 399193, |
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serial_hds[0], 1); |
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if (serial_hds[1]) |
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serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
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0, mpic[12+26], 399193, |
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serial_hds[0], 1); |
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/* PCI */
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pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4); |
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pci_irqs[0] = mpic[pci_irq_nrs[0]]; |
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pci_irqs[1] = mpic[pci_irq_nrs[1]]; |
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pci_irqs[2] = mpic[pci_irq_nrs[2]]; |
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pci_irqs[3] = mpic[pci_irq_nrs[3]]; |
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pci_bus = ppce500_pci_init(pci_irqs, MPC8544_PCI_REGS_BASE); |
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if (!pci_bus)
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printf("couldn't create PCI controller!\n");
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isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); |
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if (pci_bus) {
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/* Register network interfaces. */
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for (i = 0; i < nb_nics; i++) { |
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pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
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} |
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} |
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/* Load kernel. */
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if (kernel_filename) {
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kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
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if (kernel_size < 0) { |
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kernel_size = load_elf(kernel_filename, 0, &elf_entry, &elf_lowaddr,
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NULL, 1, ELF_MACHINE, 0); |
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entry = elf_entry; |
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loadaddr = elf_lowaddr; |
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} |
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/* XXX try again as binary */
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if (kernel_size < 0) { |
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename); |
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exit(1);
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} |
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} |
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/* Load initrd. */
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if (initrd_filename) {
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initrd_size = load_image_targphys(initrd_filename, initrd_base, |
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ram_size - initrd_base); |
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if (initrd_size < 0) { |
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename); |
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exit(1);
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} |
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} |
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/* If we're loading a kernel directly, we must load the device tree too. */
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if (kernel_filename) {
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fdt = mpc8544_load_device_tree(dt_base, ram_size, |
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initrd_base, initrd_size, kernel_cmdline); |
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if (fdt == NULL) { |
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fprintf(stderr, "couldn't load device tree\n");
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exit(1);
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} |
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/* Set initial guest state. */
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env->gpr[1] = (16<<20) - 8; |
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env->gpr[3] = dt_base;
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env->nip = entry; |
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/* XXX we currently depend on KVM to create some initial TLB entries. */
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} |
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if (kvm_enabled())
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kvmppc_init(); |
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return;
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} |
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static QEMUMachine mpc8544ds_machine = {
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.name = "mpc8544ds",
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.desc = "mpc8544ds",
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.init = mpc8544ds_init, |
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}; |
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static void mpc8544ds_machine_init(void) |
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{ |
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qemu_register_machine(&mpc8544ds_machine); |
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} |
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machine_init(mpc8544ds_machine_init); |