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/*
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* VT82C686B south bridge support
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*
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* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
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* Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
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* Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
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* This code is licensed under the GNU GPL v2.
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*/
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#include "hw.h"
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#include "pc.h"
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#include "vt82c686.h"
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#include "i2c.h"
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#include "smbus.h"
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#include "pci.h"
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#include "isa.h"
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#include "sysbus.h"
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#include "mips.h"
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#include "apm.h"
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#include "acpi.h"
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#include "pm_smbus.h"
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#include "sysemu.h"
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#include "qemu-timer.h"
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typedef uint32_t pci_addr_t;
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#include "pci_host.h"
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//#define DEBUG_VT82C686B
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#ifdef DEBUG_VT82C686B
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#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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typedef struct SuperIOConfig
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{
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uint8_t config[0xff];
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uint8_t index;
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uint8_t data;
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} SuperIOConfig;
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typedef struct VT82C686BState {
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PCIDevice dev;
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SuperIOConfig superio_conf;
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} VT82C686BState;
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static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
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{
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int can_write;
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SuperIOConfig *superio_conf = opaque;
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DPRINTF("superio_ioport_writeb address 0x%x val 0x%x \n", addr, data);
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if (addr == 0x3f0) {
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superio_conf->index = data & 0xff;
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} else {
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/* 0x3f1 */
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switch (superio_conf->index) {
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case 0x00 ... 0xdf:
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case 0xe4:
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case 0xe5:
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case 0xe9 ... 0xed:
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case 0xf3:
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case 0xf5:
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case 0xf7:
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case 0xf9 ... 0xfb:
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case 0xfd ... 0xff:
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can_write = 0;
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break;
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default:
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can_write = 1;
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if (can_write) {
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switch (superio_conf->index) {
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case 0xe7:
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if ((data & 0xff) != 0xfe) {
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DPRINTF("chage uart 1 base. unsupported yet \n");
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}
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break;
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case 0xe8:
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if ((data & 0xff) != 0xbe) {
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DPRINTF("chage uart 2 base. unsupported yet \n");
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}
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break;
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default:
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superio_conf->config[superio_conf->index] = data & 0xff;
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}
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}
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}
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superio_conf->config[superio_conf->index] = data & 0xff;
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}
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}
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static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
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{
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SuperIOConfig *superio_conf = opaque;
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DPRINTF("superio_ioport_readb address 0x%x \n", addr);
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return (superio_conf->config[superio_conf->index]);
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}
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static void vt82c686b_reset(void * opaque)
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{
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PCIDevice *d = opaque;
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uint8_t *pci_conf = d->config;
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VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
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pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
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pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
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pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
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pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
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pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
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pci_conf[0x59] = 0x04;
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pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
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pci_conf[0x5f] = 0x04;
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pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
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vt82c->superio_conf.config[0xe0] = 0x3c;
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vt82c->superio_conf.config[0xe2] = 0x03;
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vt82c->superio_conf.config[0xe3] = 0xfc;
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vt82c->superio_conf.config[0xe6] = 0xde;
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vt82c->superio_conf.config[0xe7] = 0xfe;
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vt82c->superio_conf.config[0xe8] = 0xbe;
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}
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/* write config pci function0 registers. PCI-ISA bridge */
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static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
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uint32_t val, int len)
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{
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VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
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DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x \n",
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address, val, len);
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pci_default_write_config(d, address, val, len);
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if (address == 0x85) { /* enable or disable super IO configure */
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if (val & 0x2) {
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/* floppy also uses 0x3f0 and 0x3f1.
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* But we do not emulate flopy,so just set it here. */
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isa_unassign_ioport(0x3f0, 2);
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register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
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&vt686->superio_conf);
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register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
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&vt686->superio_conf);
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} else {
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isa_unassign_ioport(0x3f0, 2);
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}
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}
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}
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#define ACPI_DBG_IO_ADDR 0xb044
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typedef struct VT686PMState {
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PCIDevice dev;
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uint16_t pmsts;
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uint16_t pmen;
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uint16_t pmcntrl;
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APMState apm;
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QEMUTimer *tmr_timer;
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int64_t tmr_overflow_time;
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PMSMBus smb;
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uint32_t smb_io_base;
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} VT686PMState;
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typedef struct VT686AC97State {
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PCIDevice dev;
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} VT686AC97State;
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typedef struct VT686MC97State {
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PCIDevice dev;
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} VT686MC97State;
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define SUS_EN (1 << 13)
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#define ACPI_ENABLE 0xf1
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#define ACPI_DISABLE 0xf0
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static uint32_t get_pmtmr(VT686PMState *s)
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{
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uint32_t d;
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
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return d & 0xffffff;
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}
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static int get_pmsts(VT686PMState *s)
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{
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int64_t d;
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int pmsts;
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pmsts = s->pmsts;
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
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if (d >= s->tmr_overflow_time)
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s->pmsts |= TMROF_EN;
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return pmsts;
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}
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static void pm_update_sci(VT686PMState *s)
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{
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int sci_level, pmsts;
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int64_t expire_time;
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pmsts = get_pmsts(s);
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sci_level = (((pmsts & s->pmen) &
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(RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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qemu_set_irq(s->dev.irq[0], sci_level);
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/* schedule a timer interruption if needed */
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if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_TIMER_FREQUENCY);
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qemu_mod_timer(s->tmr_timer, expire_time);
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} else {
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qemu_del_timer(s->tmr_timer);
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}
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}
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static void pm_tmr_timer(void *opaque)
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{
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VT686PMState *s = opaque;
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pm_update_sci(s);
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}
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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VT686PMState *s = opaque;
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addr &= 0x0f;
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switch (addr) {
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case 0x00:
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{
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int64_t d;
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int pmsts;
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pmsts = get_pmsts(s);
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if (pmsts & val & TMROF_EN) {
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/* if TMRSTS is reset, then compute the new overflow time */
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
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s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
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}
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s->pmsts &= ~val;
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pm_update_sci(s);
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}
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break;
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case 0x02:
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s->pmen = val;
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pm_update_sci(s);
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break;
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case 0x04:
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{
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int sus_typ;
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s->pmcntrl = val & ~(SUS_EN);
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if (val & SUS_EN) {
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/* change suspend type */
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sus_typ = (val >> 10) & 3;
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switch (sus_typ) {
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case 0: /* soft power off */
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qemu_system_shutdown_request();
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break;
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default:
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break;
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}
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}
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}
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break;
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default:
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break;
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}
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DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
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}
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
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{
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VT686PMState *s = opaque;
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uint32_t val;
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addr &= 0x0f;
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switch (addr) {
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case 0x00:
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val = get_pmsts(s);
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break;
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case 0x02:
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val = s->pmen;
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break;
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case 0x04:
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val = s->pmcntrl;
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break;
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default:
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val = 0;
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break;
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}
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DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
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return val;
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}
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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addr &= 0x0f;
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DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
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}
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
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{
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VT686PMState *s = opaque;
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uint32_t val;
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addr &= 0x0f;
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switch (addr) {
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case 0x08:
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val = get_pmtmr(s);
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break;
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default:
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val = 0;
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break;
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}
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DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
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return val;
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}
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static void pm_io_space_update(VT686PMState *s)
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{
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uint32_t pm_io_base;
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326 |
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if (s->dev.config[0x80] & 1) {
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pm_io_base = pci_get_long(s->dev.config + 0x40);
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
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}
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}
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339 |
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340 |
static void pm_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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342 |
{
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343 |
DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x \n",
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address, val, len);
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pci_default_write_config(d, address, val, len);
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346 |
}
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347 |
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348 |
static int vmstate_acpi_post_load(void *opaque, int version_id)
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349 |
{
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350 |
VT686PMState *s = opaque;
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351 |
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352 |
pm_io_space_update(s);
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353 |
return 0;
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354 |
}
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355 |
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356 |
static const VMStateDescription vmstate_acpi = {
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357 |
.name = "vt82c686b_pm",
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.version_id = 1,
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359 |
.minimum_version_id = 1,
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360 |
.minimum_version_id_old = 1,
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361 |
.post_load = vmstate_acpi_post_load,
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362 |
.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(dev, VT686PMState),
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364 |
VMSTATE_UINT16(pmsts, VT686PMState),
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VMSTATE_UINT16(pmen, VT686PMState),
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VMSTATE_UINT16(pmcntrl, VT686PMState),
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VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
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368 |
VMSTATE_TIMER(tmr_timer, VT686PMState),
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VMSTATE_INT64(tmr_overflow_time, VT686PMState),
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VMSTATE_END_OF_LIST()
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}
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372 |
};
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373 |
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374 |
/*
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375 |
* TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
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376 |
* just register a PCI device now, functionalities will be implemented later.
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377 |
*/
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378 |
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379 |
static int vt82c686b_ac97_initfn(PCIDevice *dev)
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|
380 |
{
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381 |
VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
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|
382 |
uint8_t *pci_conf = s->dev.config;
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383 |
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384 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
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385 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_AC97);
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|
386 |
pci_config_set_class(pci_conf, PCI_CLASS_MULTIMEDIA_AUDIO);
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387 |
pci_config_set_revision(pci_conf, 0x50);
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388 |
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|
389 |
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
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|
390 |
PCI_COMMAND_PARITY);
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|
391 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
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|
392 |
PCI_STATUS_DEVSEL_MEDIUM);
|
|
393 |
pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
|
|
394 |
|
|
395 |
return 0;
|
|
396 |
}
|
|
397 |
|
|
398 |
void vt82c686b_ac97_init(PCIBus *bus, int devfn)
|
|
399 |
{
|
|
400 |
PCIDevice *dev;
|
|
401 |
|
|
402 |
dev = pci_create(bus, devfn, "VT82C686B_AC97");
|
|
403 |
qdev_init_nofail(&dev->qdev);
|
|
404 |
}
|
|
405 |
|
|
406 |
static PCIDeviceInfo via_ac97_info = {
|
|
407 |
.qdev.name = "VT82C686B_AC97",
|
|
408 |
.qdev.desc = "AC97",
|
|
409 |
.qdev.size = sizeof(VT686AC97State),
|
|
410 |
.init = vt82c686b_ac97_initfn,
|
|
411 |
};
|
|
412 |
|
|
413 |
static void vt82c686b_ac97_register(void)
|
|
414 |
{
|
|
415 |
pci_qdev_register(&via_ac97_info);
|
|
416 |
}
|
|
417 |
|
|
418 |
device_init(vt82c686b_ac97_register);
|
|
419 |
|
|
420 |
static int vt82c686b_mc97_initfn(PCIDevice *dev)
|
|
421 |
{
|
|
422 |
VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
|
|
423 |
uint8_t *pci_conf = s->dev.config;
|
|
424 |
|
|
425 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
|
|
426 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_MC97);
|
|
427 |
pci_config_set_class(pci_conf, PCI_CLASS_COMMUNICATION_OTHER);
|
|
428 |
pci_config_set_revision(pci_conf, 0x30);
|
|
429 |
|
|
430 |
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
|
|
431 |
PCI_COMMAND_VGA_PALETTE);
|
|
432 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
|
|
433 |
pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
|
|
434 |
|
|
435 |
return 0;
|
|
436 |
}
|
|
437 |
|
|
438 |
void vt82c686b_mc97_init(PCIBus *bus, int devfn)
|
|
439 |
{
|
|
440 |
PCIDevice *dev;
|
|
441 |
|
|
442 |
dev = pci_create(bus, devfn, "VT82C686B_MC97");
|
|
443 |
qdev_init_nofail(&dev->qdev);
|
|
444 |
}
|
|
445 |
|
|
446 |
static PCIDeviceInfo via_mc97_info = {
|
|
447 |
.qdev.name = "VT82C686B_MC97",
|
|
448 |
.qdev.desc = "MC97",
|
|
449 |
.qdev.size = sizeof(VT686MC97State),
|
|
450 |
.init = vt82c686b_mc97_initfn,
|
|
451 |
};
|
|
452 |
|
|
453 |
static void vt82c686b_mc97_register(void)
|
|
454 |
{
|
|
455 |
pci_qdev_register(&via_mc97_info);
|
|
456 |
}
|
|
457 |
|
|
458 |
device_init(vt82c686b_mc97_register);
|
|
459 |
|
|
460 |
/* vt82c686 pm init */
|
|
461 |
static int vt82c686b_pm_initfn(PCIDevice *dev)
|
|
462 |
{
|
|
463 |
VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
|
|
464 |
uint8_t *pci_conf;
|
|
465 |
|
|
466 |
pci_conf = s->dev.config;
|
|
467 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
|
|
468 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ACPI);
|
|
469 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
|
|
470 |
pci_config_set_revision(pci_conf, 0x40);
|
|
471 |
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
|
472 |
|
|
473 |
pci_set_word(pci_conf + PCI_COMMAND, 0);
|
|
474 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
|
|
475 |
PCI_STATUS_DEVSEL_MEDIUM);
|
|
476 |
|
|
477 |
/* 0x48-0x4B is Power Management I/O Base */
|
|
478 |
pci_set_long(pci_conf + 0x48, 0x00000001);
|
|
479 |
|
|
480 |
/* SMB ports:0xeee0~0xeeef */
|
|
481 |
s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
|
|
482 |
pci_conf[0x90] = s->smb_io_base | 1;
|
|
483 |
pci_conf[0x91] = s->smb_io_base >> 8;
|
|
484 |
pci_conf[0xd2] = 0x90;
|
|
485 |
register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb);
|
|
486 |
register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);
|
|
487 |
|
|
488 |
apm_init(&s->apm, NULL, s);
|
|
489 |
|
|
490 |
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
|
|
491 |
|
|
492 |
pm_smbus_init(&s->dev.qdev, &s->smb);
|
|
493 |
|
|
494 |
return 0;
|
|
495 |
}
|
|
496 |
|
|
497 |
i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
|
498 |
qemu_irq sci_irq)
|
|
499 |
{
|
|
500 |
PCIDevice *dev;
|
|
501 |
VT686PMState *s;
|
|
502 |
|
|
503 |
dev = pci_create(bus, devfn, "VT82C686B_PM");
|
|
504 |
qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
|
|
505 |
|
|
506 |
s = DO_UPCAST(VT686PMState, dev, dev);
|
|
507 |
|
|
508 |
qdev_init_nofail(&dev->qdev);
|
|
509 |
|
|
510 |
return s->smb.smbus;
|
|
511 |
}
|
|
512 |
|
|
513 |
static PCIDeviceInfo via_pm_info = {
|
|
514 |
.qdev.name = "VT82C686B_PM",
|
|
515 |
.qdev.desc = "PM",
|
|
516 |
.qdev.size = sizeof(VT686PMState),
|
|
517 |
.qdev.vmsd = &vmstate_acpi,
|
|
518 |
.init = vt82c686b_pm_initfn,
|
|
519 |
.config_write = pm_write_config,
|
|
520 |
.qdev.props = (Property[]) {
|
|
521 |
DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
|
|
522 |
DEFINE_PROP_END_OF_LIST(),
|
|
523 |
}
|
|
524 |
};
|
|
525 |
|
|
526 |
static void vt82c686b_pm_register(void)
|
|
527 |
{
|
|
528 |
pci_qdev_register(&via_pm_info);
|
|
529 |
}
|
|
530 |
|
|
531 |
device_init(vt82c686b_pm_register);
|
|
532 |
|
|
533 |
static const VMStateDescription vmstate_via = {
|
|
534 |
.name = "vt82c686b",
|
|
535 |
.version_id = 1,
|
|
536 |
.minimum_version_id = 1,
|
|
537 |
.minimum_version_id_old = 1,
|
|
538 |
.fields = (VMStateField []) {
|
|
539 |
VMSTATE_PCI_DEVICE(dev, VT82C686BState),
|
|
540 |
VMSTATE_END_OF_LIST()
|
|
541 |
}
|
|
542 |
};
|
|
543 |
|
|
544 |
/* init the PCI-to-ISA bridge */
|
|
545 |
static int vt82c686b_initfn(PCIDevice *d)
|
|
546 |
{
|
|
547 |
uint8_t *pci_conf;
|
|
548 |
uint8_t *wmask;
|
|
549 |
int i;
|
|
550 |
|
|
551 |
isa_bus_new(&d->qdev);
|
|
552 |
|
|
553 |
pci_conf = d->config;
|
|
554 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
|
|
555 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ISA_BRIDGE);
|
|
556 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
|
|
557 |
pci_config_set_prog_interface(pci_conf, 0x0);
|
|
558 |
pci_config_set_revision(pci_conf,0x40); /* Revision 4.0 */
|
|
559 |
pci_conf[PCI_HEADER_TYPE] =
|
|
560 |
PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION;
|
|
561 |
|
|
562 |
wmask = d->wmask;
|
|
563 |
for (i = 0x00; i < 0xff; i++) {
|
|
564 |
if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
|
|
565 |
wmask[i] = 0x00;
|
|
566 |
}
|
|
567 |
}
|
|
568 |
|
|
569 |
qemu_register_reset(vt82c686b_reset, d);
|
|
570 |
|
|
571 |
return 0;
|
|
572 |
}
|
|
573 |
|
|
574 |
int vt82c686b_init(PCIBus *bus, int devfn)
|
|
575 |
{
|
|
576 |
PCIDevice *d;
|
|
577 |
|
|
578 |
d = pci_create_simple(bus, devfn, "VT82C686B");
|
|
579 |
|
|
580 |
return d->devfn;
|
|
581 |
}
|
|
582 |
|
|
583 |
static PCIDeviceInfo via_info = {
|
|
584 |
.qdev.name = "VT82C686B",
|
|
585 |
.qdev.desc = "ISA bridge",
|
|
586 |
.qdev.size = sizeof(VT82C686BState),
|
|
587 |
.qdev.vmsd = &vmstate_via,
|
|
588 |
.qdev.no_user = 1,
|
|
589 |
.init = vt82c686b_initfn,
|
|
590 |
.config_write = vt82c686b_write_config,
|
|
591 |
};
|
|
592 |
|
|
593 |
static void vt82c686b_register(void)
|
|
594 |
{
|
|
595 |
pci_qdev_register(&via_info);
|
|
596 |
}
|
|
597 |
device_init(vt82c686b_register);
|