root / hw / cs4231.c @ ee0ea1d0
History | View | Annotate | Download (4.7 kB)
1 | b8174937 | bellard | /*
|
---|---|---|---|
2 | b8174937 | bellard | * QEMU Crystal CS4231 audio chip emulation
|
3 | b8174937 | bellard | *
|
4 | b8174937 | bellard | * Copyright (c) 2006 Fabrice Bellard
|
5 | b8174937 | bellard | *
|
6 | b8174937 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | b8174937 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | b8174937 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | b8174937 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | b8174937 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | b8174937 | bellard | * furnished to do so, subject to the following conditions:
|
12 | b8174937 | bellard | *
|
13 | b8174937 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | b8174937 | bellard | * all copies or substantial portions of the Software.
|
15 | b8174937 | bellard | *
|
16 | b8174937 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | b8174937 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | b8174937 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | b8174937 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | b8174937 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | b8174937 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | b8174937 | bellard | * THE SOFTWARE.
|
23 | b8174937 | bellard | */
|
24 | b8174937 | bellard | #include "vl.h" |
25 | b8174937 | bellard | |
26 | b8174937 | bellard | /* debug CS4231 */
|
27 | b8174937 | bellard | //#define DEBUG_CS
|
28 | b8174937 | bellard | |
29 | b8174937 | bellard | /*
|
30 | b8174937 | bellard | * In addition to Crystal CS4231 there is a DMA controller on Sparc.
|
31 | b8174937 | bellard | */
|
32 | b8174937 | bellard | #define CS_MAXADDR 0x3f |
33 | b8174937 | bellard | #define CS_REGS 16 |
34 | b8174937 | bellard | #define CS_DREGS 32 |
35 | b8174937 | bellard | #define CS_MAXDREG (CS_DREGS - 1) |
36 | b8174937 | bellard | |
37 | b8174937 | bellard | typedef struct CSState { |
38 | b8174937 | bellard | uint32_t regs[CS_REGS]; |
39 | b8174937 | bellard | uint8_t dregs[CS_DREGS]; |
40 | b8174937 | bellard | void *intctl;
|
41 | b8174937 | bellard | } CSState; |
42 | b8174937 | bellard | |
43 | b8174937 | bellard | #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG) |
44 | b8174937 | bellard | #define CS_VER 0xa0 |
45 | b8174937 | bellard | #define CS_CDC_VER 0x8a |
46 | b8174937 | bellard | |
47 | b8174937 | bellard | #ifdef DEBUG_CS
|
48 | b8174937 | bellard | #define DPRINTF(fmt, args...) \
|
49 | b8174937 | bellard | do { printf("CS: " fmt , ##args); } while (0) |
50 | b8174937 | bellard | #define pic_set_irq_new(intctl, irq, level) \
|
51 | b8174937 | bellard | do { printf("CS: set_irq(%d): %d\n", (irq), (level)); \ |
52 | b8174937 | bellard | pic_set_irq_new((intctl), (irq),(level));} while (0) |
53 | b8174937 | bellard | #else
|
54 | b8174937 | bellard | #define DPRINTF(fmt, args...)
|
55 | b8174937 | bellard | #endif
|
56 | b8174937 | bellard | |
57 | b8174937 | bellard | static void cs_reset(void *opaque) |
58 | b8174937 | bellard | { |
59 | b8174937 | bellard | CSState *s = opaque; |
60 | b8174937 | bellard | |
61 | b8174937 | bellard | memset(s->regs, 0, CS_REGS * 4); |
62 | b8174937 | bellard | memset(s->dregs, 0, CS_DREGS);
|
63 | b8174937 | bellard | s->dregs[12] = CS_CDC_VER;
|
64 | b8174937 | bellard | s->dregs[25] = CS_VER;
|
65 | b8174937 | bellard | } |
66 | b8174937 | bellard | |
67 | b8174937 | bellard | static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) |
68 | b8174937 | bellard | { |
69 | b8174937 | bellard | CSState *s = opaque; |
70 | b8174937 | bellard | uint32_t saddr, ret; |
71 | b8174937 | bellard | |
72 | b8174937 | bellard | saddr = (addr & CS_MAXADDR) >> 2;
|
73 | b8174937 | bellard | switch (saddr) {
|
74 | b8174937 | bellard | case 1: |
75 | b8174937 | bellard | switch (CS_RAP(s)) {
|
76 | b8174937 | bellard | case 3: // Write only |
77 | b8174937 | bellard | ret = 0;
|
78 | b8174937 | bellard | break;
|
79 | b8174937 | bellard | default:
|
80 | b8174937 | bellard | ret = s->dregs[CS_RAP(s)]; |
81 | b8174937 | bellard | break;
|
82 | b8174937 | bellard | } |
83 | b8174937 | bellard | DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
|
84 | b8174937 | bellard | break;
|
85 | b8174937 | bellard | default:
|
86 | b8174937 | bellard | ret = s->regs[saddr]; |
87 | b8174937 | bellard | DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
|
88 | b8174937 | bellard | break;
|
89 | b8174937 | bellard | } |
90 | b8174937 | bellard | return ret;
|
91 | b8174937 | bellard | } |
92 | b8174937 | bellard | |
93 | b8174937 | bellard | static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
94 | b8174937 | bellard | { |
95 | b8174937 | bellard | CSState *s = opaque; |
96 | b8174937 | bellard | uint32_t saddr; |
97 | b8174937 | bellard | |
98 | b8174937 | bellard | saddr = (addr & CS_MAXADDR) >> 2;
|
99 | b8174937 | bellard | DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
|
100 | b8174937 | bellard | switch (saddr) {
|
101 | b8174937 | bellard | case 1: |
102 | b8174937 | bellard | DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), s->dregs[CS_RAP(s)], val);
|
103 | b8174937 | bellard | switch(CS_RAP(s)) {
|
104 | b8174937 | bellard | case 11: |
105 | b8174937 | bellard | case 25: // Read only |
106 | b8174937 | bellard | break;
|
107 | b8174937 | bellard | case 12: |
108 | b8174937 | bellard | val &= 0x40;
|
109 | b8174937 | bellard | val |= CS_CDC_VER; // Codec version
|
110 | b8174937 | bellard | s->dregs[CS_RAP(s)] = val; |
111 | b8174937 | bellard | break;
|
112 | b8174937 | bellard | default:
|
113 | b8174937 | bellard | s->dregs[CS_RAP(s)] = val; |
114 | b8174937 | bellard | break;
|
115 | b8174937 | bellard | } |
116 | b8174937 | bellard | break;
|
117 | b8174937 | bellard | case 2: // Read only |
118 | b8174937 | bellard | break;
|
119 | b8174937 | bellard | case 4: |
120 | b8174937 | bellard | if (val & 1) |
121 | b8174937 | bellard | cs_reset(s); |
122 | b8174937 | bellard | val &= 0x7f;
|
123 | b8174937 | bellard | s->regs[saddr] = val; |
124 | b8174937 | bellard | break;
|
125 | b8174937 | bellard | default:
|
126 | b8174937 | bellard | s->regs[saddr] = val; |
127 | b8174937 | bellard | break;
|
128 | b8174937 | bellard | } |
129 | b8174937 | bellard | } |
130 | b8174937 | bellard | |
131 | b8174937 | bellard | static CPUReadMemoryFunc *cs_mem_read[3] = { |
132 | b8174937 | bellard | cs_mem_readl, |
133 | b8174937 | bellard | cs_mem_readl, |
134 | b8174937 | bellard | cs_mem_readl, |
135 | b8174937 | bellard | }; |
136 | b8174937 | bellard | |
137 | b8174937 | bellard | static CPUWriteMemoryFunc *cs_mem_write[3] = { |
138 | b8174937 | bellard | cs_mem_writel, |
139 | b8174937 | bellard | cs_mem_writel, |
140 | b8174937 | bellard | cs_mem_writel, |
141 | b8174937 | bellard | }; |
142 | b8174937 | bellard | |
143 | b8174937 | bellard | static void cs_save(QEMUFile *f, void *opaque) |
144 | b8174937 | bellard | { |
145 | b8174937 | bellard | CSState *s = opaque; |
146 | b8174937 | bellard | unsigned int i; |
147 | b8174937 | bellard | |
148 | b8174937 | bellard | for (i = 0; i < CS_REGS; i++) |
149 | b8174937 | bellard | qemu_put_be32s(f, &s->regs[i]); |
150 | b8174937 | bellard | |
151 | b8174937 | bellard | qemu_put_buffer(f, s->dregs, CS_DREGS); |
152 | b8174937 | bellard | } |
153 | b8174937 | bellard | |
154 | b8174937 | bellard | static int cs_load(QEMUFile *f, void *opaque, int version_id) |
155 | b8174937 | bellard | { |
156 | b8174937 | bellard | CSState *s = opaque; |
157 | b8174937 | bellard | unsigned int i; |
158 | b8174937 | bellard | |
159 | b8174937 | bellard | if (version_id > 1) |
160 | b8174937 | bellard | return -EINVAL;
|
161 | b8174937 | bellard | |
162 | b8174937 | bellard | for (i = 0; i < CS_REGS; i++) |
163 | b8174937 | bellard | qemu_get_be32s(f, &s->regs[i]); |
164 | b8174937 | bellard | |
165 | b8174937 | bellard | qemu_get_buffer(f, s->dregs, CS_DREGS); |
166 | b8174937 | bellard | return 0; |
167 | b8174937 | bellard | } |
168 | b8174937 | bellard | |
169 | b8174937 | bellard | void cs_init(target_phys_addr_t base, int irq, void *intctl) |
170 | b8174937 | bellard | { |
171 | b8174937 | bellard | int cs_io_memory;
|
172 | b8174937 | bellard | CSState *s; |
173 | b8174937 | bellard | |
174 | b8174937 | bellard | s = qemu_mallocz(sizeof(CSState));
|
175 | b8174937 | bellard | if (!s)
|
176 | b8174937 | bellard | return;
|
177 | b8174937 | bellard | |
178 | b8174937 | bellard | cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
|
179 | b8174937 | bellard | cpu_register_physical_memory(base, CS_MAXADDR, cs_io_memory); |
180 | b8174937 | bellard | register_savevm("cs4231", base, 1, cs_save, cs_load, s); |
181 | b8174937 | bellard | qemu_register_reset(cs_reset, s); |
182 | b8174937 | bellard | cs_reset(s); |
183 | b8174937 | bellard | } |