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1 | c1713132 | balrog | /*
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2 | c1713132 | balrog | * Intel XScale PXA255/270 processor support.
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3 | c1713132 | balrog | *
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4 | c1713132 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | c1713132 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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6 | c1713132 | balrog | *
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7 | 3efda49d | balrog | * This code is licenced under the GNU GPL v2.
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8 | c1713132 | balrog | */
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9 | c1713132 | balrog | #ifndef PXA_H
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10 | c1713132 | balrog | # define PXA_H "pxa.h" |
11 | c1713132 | balrog | |
12 | c1713132 | balrog | /* Interrupt numbers */
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13 | c1713132 | balrog | # define PXA2XX_PIC_SSP3 0 |
14 | c1713132 | balrog | # define PXA2XX_PIC_USBH2 2 |
15 | c1713132 | balrog | # define PXA2XX_PIC_USBH1 3 |
16 | 31b87f2e | balrog | # define PXA2XX_PIC_KEYPAD 4 |
17 | c1713132 | balrog | # define PXA2XX_PIC_PWRI2C 6 |
18 | c1713132 | balrog | # define PXA25X_PIC_HWUART 7 |
19 | c1713132 | balrog | # define PXA27X_PIC_OST_4_11 7 |
20 | c1713132 | balrog | # define PXA2XX_PIC_GPIO_0 8 |
21 | c1713132 | balrog | # define PXA2XX_PIC_GPIO_1 9 |
22 | c1713132 | balrog | # define PXA2XX_PIC_GPIO_X 10 |
23 | c1713132 | balrog | # define PXA2XX_PIC_I2S 13 |
24 | c1713132 | balrog | # define PXA26X_PIC_ASSP 15 |
25 | c1713132 | balrog | # define PXA25X_PIC_NSSP 16 |
26 | c1713132 | balrog | # define PXA27X_PIC_SSP2 16 |
27 | c1713132 | balrog | # define PXA2XX_PIC_LCD 17 |
28 | c1713132 | balrog | # define PXA2XX_PIC_I2C 18 |
29 | c1713132 | balrog | # define PXA2XX_PIC_ICP 19 |
30 | c1713132 | balrog | # define PXA2XX_PIC_STUART 20 |
31 | c1713132 | balrog | # define PXA2XX_PIC_BTUART 21 |
32 | c1713132 | balrog | # define PXA2XX_PIC_FFUART 22 |
33 | c1713132 | balrog | # define PXA2XX_PIC_MMC 23 |
34 | c1713132 | balrog | # define PXA2XX_PIC_SSP 24 |
35 | c1713132 | balrog | # define PXA2XX_PIC_DMA 25 |
36 | c1713132 | balrog | # define PXA2XX_PIC_OST_0 26 |
37 | c1713132 | balrog | # define PXA2XX_PIC_RTC1HZ 30 |
38 | c1713132 | balrog | # define PXA2XX_PIC_RTCALARM 31 |
39 | c1713132 | balrog | |
40 | c1713132 | balrog | /* DMA requests */
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41 | c1713132 | balrog | # define PXA2XX_RX_RQ_I2S 2 |
42 | c1713132 | balrog | # define PXA2XX_TX_RQ_I2S 3 |
43 | c1713132 | balrog | # define PXA2XX_RX_RQ_BTUART 4 |
44 | c1713132 | balrog | # define PXA2XX_TX_RQ_BTUART 5 |
45 | c1713132 | balrog | # define PXA2XX_RX_RQ_FFUART 6 |
46 | c1713132 | balrog | # define PXA2XX_TX_RQ_FFUART 7 |
47 | c1713132 | balrog | # define PXA2XX_RX_RQ_SSP1 13 |
48 | c1713132 | balrog | # define PXA2XX_TX_RQ_SSP1 14 |
49 | c1713132 | balrog | # define PXA2XX_RX_RQ_SSP2 15 |
50 | c1713132 | balrog | # define PXA2XX_TX_RQ_SSP2 16 |
51 | c1713132 | balrog | # define PXA2XX_RX_RQ_ICP 17 |
52 | c1713132 | balrog | # define PXA2XX_TX_RQ_ICP 18 |
53 | c1713132 | balrog | # define PXA2XX_RX_RQ_STUART 19 |
54 | c1713132 | balrog | # define PXA2XX_TX_RQ_STUART 20 |
55 | c1713132 | balrog | # define PXA2XX_RX_RQ_MMCI 21 |
56 | c1713132 | balrog | # define PXA2XX_TX_RQ_MMCI 22 |
57 | c1713132 | balrog | # define PXA2XX_USB_RQ(x) ((x) + 24) |
58 | c1713132 | balrog | # define PXA2XX_RX_RQ_SSP3 66 |
59 | c1713132 | balrog | # define PXA2XX_TX_RQ_SSP3 67 |
60 | c1713132 | balrog | |
61 | d95b2f8d | balrog | # define PXA2XX_SDRAM_BASE 0xa0000000 |
62 | d95b2f8d | balrog | # define PXA2XX_INTERNAL_BASE 0x5c000000 |
63 | a07dec22 | balrog | # define PXA2XX_INTERNAL_SIZE 0x40000 |
64 | c1713132 | balrog | |
65 | c1713132 | balrog | /* pxa2xx_pic.c */
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66 | e1f8c729 | Dmitry Eremin-Solenikov | DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env); |
67 | c1713132 | balrog | |
68 | c1713132 | balrog | /* pxa2xx_gpio.c */
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69 | 0bb53337 | Dmitry Eremin-Solenikov | DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, |
70 | e1f8c729 | Dmitry Eremin-Solenikov | CPUState *env, DeviceState *pic, int lines);
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71 | 0bb53337 | Dmitry Eremin-Solenikov | void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
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72 | c1713132 | balrog | |
73 | c1713132 | balrog | /* pxa2xx_dma.c */
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74 | bc24a225 | Paul Brook | typedef struct PXA2xxDMAState PXA2xxDMAState; |
75 | c227f099 | Anthony Liguori | PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, |
76 | c1713132 | balrog | qemu_irq irq); |
77 | c227f099 | Anthony Liguori | PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, |
78 | c1713132 | balrog | qemu_irq irq); |
79 | bc24a225 | Paul Brook | void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on); |
80 | c1713132 | balrog | |
81 | a171fe39 | balrog | /* pxa2xx_lcd.c */
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82 | bc24a225 | Paul Brook | typedef struct PXA2xxLCDState PXA2xxLCDState; |
83 | c227f099 | Anthony Liguori | PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, |
84 | 3023f332 | aliguori | qemu_irq irq); |
85 | bc24a225 | Paul Brook | void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
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86 | a171fe39 | balrog | void pxa2xx_lcdc_oritentation(void *opaque, int angle); |
87 | a171fe39 | balrog | |
88 | a171fe39 | balrog | /* pxa2xx_mmci.c */
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89 | bc24a225 | Paul Brook | typedef struct PXA2xxMMCIState PXA2xxMMCIState; |
90 | c227f099 | Anthony Liguori | PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, |
91 | 87ecb68b | pbrook | BlockDriverState *bd, qemu_irq irq, void *dma);
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92 | bc24a225 | Paul Brook | void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
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93 | 02ce600c | balrog | qemu_irq coverswitch); |
94 | a171fe39 | balrog | |
95 | a171fe39 | balrog | /* pxa2xx_pcmcia.c */
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96 | bc24a225 | Paul Brook | typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState; |
97 | c227f099 | Anthony Liguori | PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base); |
98 | bc24a225 | Paul Brook | int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); |
99 | a171fe39 | balrog | int pxa2xx_pcmcia_dettach(void *opaque); |
100 | a171fe39 | balrog | void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); |
101 | a171fe39 | balrog | |
102 | 31b87f2e | balrog | /* pxa2xx_keypad.c */
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103 | 31b87f2e | balrog | struct keymap {
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104 | 31b87f2e | balrog | int column;
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105 | 31b87f2e | balrog | int row;
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106 | 31b87f2e | balrog | }; |
107 | bc24a225 | Paul Brook | typedef struct PXA2xxKeyPadState PXA2xxKeyPadState; |
108 | c227f099 | Anthony Liguori | PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base, |
109 | 31b87f2e | balrog | qemu_irq irq); |
110 | bc24a225 | Paul Brook | void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map, |
111 | 31b87f2e | balrog | int size);
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112 | 31b87f2e | balrog | |
113 | c1713132 | balrog | /* pxa2xx.c */
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114 | bc24a225 | Paul Brook | typedef struct PXA2xxI2CState PXA2xxI2CState; |
115 | c227f099 | Anthony Liguori | PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base, |
116 | 2a163929 | balrog | qemu_irq irq, uint32_t page_size); |
117 | bc24a225 | Paul Brook | i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s); |
118 | 3f582262 | balrog | |
119 | bc24a225 | Paul Brook | typedef struct PXA2xxI2SState PXA2xxI2SState; |
120 | bc24a225 | Paul Brook | typedef struct PXA2xxFIrState PXA2xxFIrState; |
121 | c1713132 | balrog | |
122 | bc24a225 | Paul Brook | typedef struct { |
123 | c1713132 | balrog | CPUState *env; |
124 | e1f8c729 | Dmitry Eremin-Solenikov | DeviceState *pic; |
125 | 38641a52 | balrog | qemu_irq reset; |
126 | bc24a225 | Paul Brook | PXA2xxDMAState *dma; |
127 | 0bb53337 | Dmitry Eremin-Solenikov | DeviceState *gpio; |
128 | bc24a225 | Paul Brook | PXA2xxLCDState *lcd; |
129 | a984a69e | Paul Brook | SSIBus **ssp; |
130 | bc24a225 | Paul Brook | PXA2xxI2CState *i2c[2];
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131 | bc24a225 | Paul Brook | PXA2xxMMCIState *mmc; |
132 | bc24a225 | Paul Brook | PXA2xxPCMCIAState *pcmcia[2];
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133 | bc24a225 | Paul Brook | PXA2xxI2SState *i2s; |
134 | bc24a225 | Paul Brook | PXA2xxFIrState *fir; |
135 | bc24a225 | Paul Brook | PXA2xxKeyPadState *kp; |
136 | c1713132 | balrog | |
137 | c1713132 | balrog | /* Power management */
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138 | c227f099 | Anthony Liguori | target_phys_addr_t pm_base; |
139 | c1713132 | balrog | uint32_t pm_regs[0x40];
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140 | c1713132 | balrog | |
141 | c1713132 | balrog | /* Clock management */
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142 | c227f099 | Anthony Liguori | target_phys_addr_t cm_base; |
143 | c1713132 | balrog | uint32_t cm_regs[4];
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144 | c1713132 | balrog | uint32_t clkcfg; |
145 | c1713132 | balrog | |
146 | c1713132 | balrog | /* Memory management */
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147 | c227f099 | Anthony Liguori | target_phys_addr_t mm_base; |
148 | c1713132 | balrog | uint32_t mm_regs[0x1a];
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149 | c1713132 | balrog | |
150 | c1713132 | balrog | /* Performance monitoring */
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151 | c1713132 | balrog | uint32_t pmnc; |
152 | c1713132 | balrog | |
153 | c1713132 | balrog | /* Real-Time clock */
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154 | c227f099 | Anthony Liguori | target_phys_addr_t rtc_base; |
155 | c1713132 | balrog | uint32_t rttr; |
156 | c1713132 | balrog | uint32_t rtsr; |
157 | c1713132 | balrog | uint32_t rtar; |
158 | c1713132 | balrog | uint32_t rdar1; |
159 | c1713132 | balrog | uint32_t rdar2; |
160 | c1713132 | balrog | uint32_t ryar1; |
161 | c1713132 | balrog | uint32_t ryar2; |
162 | c1713132 | balrog | uint32_t swar1; |
163 | c1713132 | balrog | uint32_t swar2; |
164 | c1713132 | balrog | uint32_t piar; |
165 | c1713132 | balrog | uint32_t last_rcnr; |
166 | c1713132 | balrog | uint32_t last_rdcr; |
167 | c1713132 | balrog | uint32_t last_rycr; |
168 | c1713132 | balrog | uint32_t last_swcr; |
169 | c1713132 | balrog | uint32_t last_rtcpicr; |
170 | c1713132 | balrog | int64_t last_hz; |
171 | c1713132 | balrog | int64_t last_sw; |
172 | c1713132 | balrog | int64_t last_pi; |
173 | c1713132 | balrog | QEMUTimer *rtc_hz; |
174 | c1713132 | balrog | QEMUTimer *rtc_rdal1; |
175 | c1713132 | balrog | QEMUTimer *rtc_rdal2; |
176 | c1713132 | balrog | QEMUTimer *rtc_swal1; |
177 | c1713132 | balrog | QEMUTimer *rtc_swal2; |
178 | c1713132 | balrog | QEMUTimer *rtc_pi; |
179 | e1f8c729 | Dmitry Eremin-Solenikov | qemu_irq rtc_irq; |
180 | bc24a225 | Paul Brook | } PXA2xxState; |
181 | c1713132 | balrog | |
182 | bc24a225 | Paul Brook | struct PXA2xxI2SState {
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183 | c1713132 | balrog | qemu_irq irq; |
184 | bc24a225 | Paul Brook | PXA2xxDMAState *dma; |
185 | c1713132 | balrog | void (*data_req)(void *, int, int); |
186 | c1713132 | balrog | |
187 | c1713132 | balrog | uint32_t control[2];
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188 | c1713132 | balrog | uint32_t status; |
189 | c1713132 | balrog | uint32_t mask; |
190 | c1713132 | balrog | uint32_t clk; |
191 | c1713132 | balrog | |
192 | c1713132 | balrog | int enable;
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193 | c1713132 | balrog | int rx_len;
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194 | c1713132 | balrog | int tx_len;
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195 | c1713132 | balrog | void (*codec_out)(void *, uint32_t); |
196 | c1713132 | balrog | uint32_t (*codec_in)(void *);
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197 | c1713132 | balrog | void *opaque;
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198 | c1713132 | balrog | |
199 | c1713132 | balrog | int fifo_len;
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200 | c1713132 | balrog | uint32_t fifo[16];
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201 | c1713132 | balrog | }; |
202 | c1713132 | balrog | |
203 | c1713132 | balrog | # define PA_FMT "0x%08lx" |
204 | 444ce241 | bellard | # define REG_FMT "0x" TARGET_FMT_plx |
205 | c1713132 | balrog | |
206 | bc24a225 | Paul Brook | PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision); |
207 | bc24a225 | Paul Brook | PXA2xxState *pxa255_init(unsigned int sdram_size); |
208 | c1713132 | balrog | |
209 | c1713132 | balrog | #endif /* PXA_H */ |