Revision ee6c0b51

b/target-sparc/translate.c
956 956
		    int cc;
957 957

  
958 958
		    target = GET_FIELD_SP(insn, 0, 18);
959
		    target <<= 2;
960 959
		    target = sign_extend(target, 18);
960
		    target <<= 2;
961 961
		    cc = GET_FIELD_SP(insn, 20, 21);
962 962
		    if (cc == 0)
963 963
			do_branch(dc, target, insn, 0);
......
971 971
		{
972 972
		    target = GET_FIELD_SP(insn, 0, 13) | 
973 973
			(GET_FIELD_SP(insn, 20, 21) >> 7);
974
		    target <<= 2;
975 974
		    target = sign_extend(target, 16);
975
		    target <<= 2;
976 976
		    rs1 = GET_FIELD(insn, 13, 17);
977 977
		    gen_movl_reg_T0(rs1);
978 978
		    do_branch_reg(dc, target, insn);
......
986 986
		    gen_op_trap_ifnofpu();
987 987
#endif
988 988
		    target = GET_FIELD_SP(insn, 0, 18);
989
		    target <<= 2;
990 989
		    target = sign_extend(target, 19);
990
		    target <<= 2;
991 991
		    do_fbranch(dc, target, insn, cc);
992 992
		    goto jmp_insn;
993 993
		}
......
995 995
	    case 0x2:		/* BN+x */
996 996
		{
997 997
		    target = GET_FIELD(insn, 10, 31);
998
		    target <<= 2;
999 998
		    target = sign_extend(target, 22);
999
		    target <<= 2;
1000 1000
		    do_branch(dc, target, insn, 0);
1001 1001
		    goto jmp_insn;
1002 1002
		}
......
1007 1007
		    gen_op_trap_ifnofpu();
1008 1008
#endif
1009 1009
		    target = GET_FIELD(insn, 10, 31);
1010
		    target <<= 2;
1011 1010
		    target = sign_extend(target, 22);
1011
		    target <<= 2;
1012 1012
		    do_fbranch(dc, target, insn, 0);
1013 1013
		    goto jmp_insn;
1014 1014
		}

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