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/*
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* QEMU model of Xilinx AXI-Ethernet.
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*
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* Copyright (c) 2011 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h" |
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#include "qemu/log.h" |
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#include "net/net.h" |
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#include "net/checksum.h" |
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#include "qapi/qmp/qerror.h" |
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#include "hw/stream.h" |
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#define DPHY(x)
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#define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" |
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#define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream" |
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#define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream" |
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|
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#define XILINX_AXI_ENET(obj) \
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OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET) |
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|
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#define XILINX_AXI_ENET_DATA_STREAM(obj) \
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OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ |
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TYPE_XILINX_AXI_ENET_DATA_STREAM) |
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|
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#define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
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OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\ |
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TYPE_XILINX_AXI_ENET_CONTROL_STREAM) |
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|
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/* Advertisement control register. */
|
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ |
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ |
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ |
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ |
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|
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#define CONTROL_PAYLOAD_WORDS 5 |
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#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) |
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|
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struct PHY {
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uint32_t regs[32];
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|
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int link;
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|
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unsigned int (*read)(struct PHY *phy, unsigned int req); |
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void (*write)(struct PHY *phy, unsigned int req, |
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unsigned int data); |
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}; |
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|
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static unsigned int tdk_read(struct PHY *phy, unsigned int req) |
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{
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int regnum;
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unsigned r = 0; |
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regnum = req & 0x1f;
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switch (regnum) {
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case 1: |
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if (!phy->link) {
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break;
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} |
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/* MR1. */
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/* Speeds and modes. */
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r |= (1 << 13) | (1 << 14); |
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r |= (1 << 11) | (1 << 12); |
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r |= (1 << 5); /* Autoneg complete. */ |
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r |= (1 << 3); /* Autoneg able. */ |
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r |= (1 << 2); /* link. */ |
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r |= (1 << 1); /* link. */ |
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break;
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case 5: |
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/* Link partner ability.
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We are kind; always agree with whatever best mode
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the guest advertises. */
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r = 1 << 14; /* Success. */ |
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/* Copy advertised modes. */
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r |= phy->regs[4] & (15 << 5); |
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/* Autoneg support. */
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r |= 1;
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break;
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case 17: |
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/* Marvel PHY on many xilinx boards. */
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r = 0x8000; /* 1000Mb */ |
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break;
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case 18: |
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{
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/* Diagnostics reg. */
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int duplex = 0; |
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int speed_100 = 0; |
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|
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if (!phy->link) {
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break;
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} |
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/* Are we advertising 100 half or 100 duplex ? */
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speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
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speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
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/* Are we advertising 10 duplex or 100 duplex ? */
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duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
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duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
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r = (speed_100 << 10) | (duplex << 11); |
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} |
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break;
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default:
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r = phy->regs[regnum]; |
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break;
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} |
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DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
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return r;
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} |
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static void |
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tdk_write(struct PHY *phy, unsigned int req, unsigned int data) |
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{
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int regnum;
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regnum = req & 0x1f;
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DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
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switch (regnum) {
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default:
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phy->regs[regnum] = data; |
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break;
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} |
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} |
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static void |
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tdk_init(struct PHY *phy)
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{
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phy->regs[0] = 0x3100; |
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/* PHY Id. */
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phy->regs[2] = 0x0300; |
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phy->regs[3] = 0xe400; |
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/* Autonegotiation advertisement reg. */
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phy->regs[4] = 0x01E1; |
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phy->link = 1;
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phy->read = tdk_read; |
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phy->write = tdk_write; |
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} |
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struct MDIOBus {
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/* bus. */
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int mdc;
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int mdio;
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/* decoder. */
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enum {
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PREAMBLE, |
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SOF, |
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OPC, |
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ADDR, |
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REQ, |
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TURNAROUND, |
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DATA |
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} state; |
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unsigned int drive; |
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|
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unsigned int cnt; |
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unsigned int addr; |
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unsigned int opc; |
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unsigned int req; |
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unsigned int data; |
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|
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struct PHY *devs[32]; |
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}; |
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static void |
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mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) |
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{
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bus->devs[addr & 0x1f] = phy;
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} |
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#ifdef USE_THIS_DEAD_CODE
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static void |
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mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) |
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{
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bus->devs[addr & 0x1f] = NULL; |
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} |
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#endif
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static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, |
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unsigned int reg) |
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{
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struct PHY *phy;
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uint16_t data; |
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phy = bus->devs[addr]; |
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if (phy && phy->read) {
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data = phy->read(phy, reg); |
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} else {
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data = 0xffff;
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} |
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DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
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return data;
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} |
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static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, |
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unsigned int reg, uint16_t data) |
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{
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struct PHY *phy;
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DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
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phy = bus->devs[addr]; |
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if (phy && phy->write) {
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phy->write(phy, reg, data); |
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} |
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} |
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#define DENET(x)
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|
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#define R_RAF (0x000 / 4) |
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enum {
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RAF_MCAST_REJ = (1 << 1), |
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RAF_BCAST_REJ = (1 << 2), |
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RAF_EMCF_EN = (1 << 12), |
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RAF_NEWFUNC_EN = (1 << 11) |
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}; |
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#define R_IS (0x00C / 4) |
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enum {
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IS_HARD_ACCESS_COMPLETE = 1,
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IS_AUTONEG = (1 << 1), |
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IS_RX_COMPLETE = (1 << 2), |
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IS_RX_REJECT = (1 << 3), |
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IS_TX_COMPLETE = (1 << 5), |
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IS_RX_DCM_LOCK = (1 << 6), |
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IS_MGM_RDY = (1 << 7), |
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IS_PHY_RST_DONE = (1 << 8), |
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}; |
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|
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#define R_IP (0x010 / 4) |
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#define R_IE (0x014 / 4) |
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#define R_UAWL (0x020 / 4) |
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#define R_UAWU (0x024 / 4) |
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#define R_PPST (0x030 / 4) |
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enum {
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PPST_LINKSTATUS = (1 << 0), |
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PPST_PHY_LINKSTATUS = (1 << 7), |
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}; |
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|
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#define R_STATS_RX_BYTESL (0x200 / 4) |
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#define R_STATS_RX_BYTESH (0x204 / 4) |
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#define R_STATS_TX_BYTESL (0x208 / 4) |
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#define R_STATS_TX_BYTESH (0x20C / 4) |
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#define R_STATS_RXL (0x290 / 4) |
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#define R_STATS_RXH (0x294 / 4) |
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#define R_STATS_RX_BCASTL (0x2a0 / 4) |
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#define R_STATS_RX_BCASTH (0x2a4 / 4) |
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#define R_STATS_RX_MCASTL (0x2a8 / 4) |
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#define R_STATS_RX_MCASTH (0x2ac / 4) |
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|
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#define R_RCW0 (0x400 / 4) |
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#define R_RCW1 (0x404 / 4) |
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enum {
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RCW1_VLAN = (1 << 27), |
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RCW1_RX = (1 << 28), |
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RCW1_FCS = (1 << 29), |
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RCW1_JUM = (1 << 30), |
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RCW1_RST = (1 << 31), |
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}; |
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|
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#define R_TC (0x408 / 4) |
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enum {
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TC_VLAN = (1 << 27), |
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TC_TX = (1 << 28), |
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TC_FCS = (1 << 29), |
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TC_JUM = (1 << 30), |
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TC_RST = (1 << 31), |
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}; |
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|
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#define R_EMMC (0x410 / 4) |
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enum {
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EMMC_LINKSPEED_10MB = (0 << 30), |
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EMMC_LINKSPEED_100MB = (1 << 30), |
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EMMC_LINKSPEED_1000MB = (2 << 30), |
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}; |
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|
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#define R_PHYC (0x414 / 4) |
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|
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#define R_MC (0x500 / 4) |
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#define MC_EN (1 << 6) |
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|
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#define R_MCR (0x504 / 4) |
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#define R_MWD (0x508 / 4) |
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#define R_MRD (0x50c / 4) |
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#define R_MIS (0x600 / 4) |
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#define R_MIP (0x620 / 4) |
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#define R_MIE (0x640 / 4) |
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#define R_MIC (0x640 / 4) |
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|
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#define R_UAW0 (0x700 / 4) |
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#define R_UAW1 (0x704 / 4) |
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#define R_FMI (0x708 / 4) |
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#define R_AF0 (0x710 / 4) |
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#define R_AF1 (0x714 / 4) |
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#define R_MAX (0x34 / 4) |
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|
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/* Indirect registers. */
|
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struct TEMAC {
|
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struct MDIOBus mdio_bus;
|
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struct PHY phy;
|
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|
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void *parent;
|
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}; |
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|
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typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave; |
| 328 |
typedef struct XilinxAXIEnet XilinxAXIEnet; |
| 329 |
|
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struct XilinxAXIEnetStreamSlave {
|
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Object parent; |
| 332 |
|
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struct XilinxAXIEnet *enet;
|
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} ; |
| 335 |
|
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struct XilinxAXIEnet {
|
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SysBusDevice busdev; |
| 338 |
MemoryRegion iomem; |
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qemu_irq irq; |
| 340 |
StreamSlave *tx_data_dev; |
| 341 |
StreamSlave *tx_control_dev; |
| 342 |
XilinxAXIEnetStreamSlave rx_data_dev; |
| 343 |
XilinxAXIEnetStreamSlave rx_control_dev; |
| 344 |
NICState *nic; |
| 345 |
NICConf conf; |
| 346 |
|
| 347 |
|
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uint32_t c_rxmem; |
| 349 |
uint32_t c_txmem; |
| 350 |
uint32_t c_phyaddr; |
| 351 |
|
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struct TEMAC TEMAC;
|
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|
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/* MII regs. */
|
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union {
|
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uint32_t regs[4];
|
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struct {
|
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uint32_t mc; |
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uint32_t mcr; |
| 360 |
uint32_t mwd; |
| 361 |
uint32_t mrd; |
| 362 |
}; |
| 363 |
} mii; |
| 364 |
|
| 365 |
struct {
|
| 366 |
uint64_t rx_bytes; |
| 367 |
uint64_t tx_bytes; |
| 368 |
|
| 369 |
uint64_t rx; |
| 370 |
uint64_t rx_bcast; |
| 371 |
uint64_t rx_mcast; |
| 372 |
} stats; |
| 373 |
|
| 374 |
/* Receive configuration words. */
|
| 375 |
uint32_t rcw[2];
|
| 376 |
/* Transmit config. */
|
| 377 |
uint32_t tc; |
| 378 |
uint32_t emmc; |
| 379 |
uint32_t phyc; |
| 380 |
|
| 381 |
/* Unicast Address Word. */
|
| 382 |
uint32_t uaw[2];
|
| 383 |
/* Unicast address filter used with extended mcast. */
|
| 384 |
uint32_t ext_uaw[2];
|
| 385 |
uint32_t fmi; |
| 386 |
|
| 387 |
uint32_t regs[R_MAX]; |
| 388 |
|
| 389 |
/* Multicast filter addrs. */
|
| 390 |
uint32_t maddr[4][2]; |
| 391 |
/* 32K x 1 lookup filter. */
|
| 392 |
uint32_t ext_mtable[1024];
|
| 393 |
|
| 394 |
uint32_t hdr[CONTROL_PAYLOAD_WORDS]; |
| 395 |
|
| 396 |
uint8_t *rxmem; |
| 397 |
uint32_t rxsize; |
| 398 |
uint32_t rxpos; |
| 399 |
|
| 400 |
uint8_t rxapp[CONTROL_PAYLOAD_SIZE]; |
| 401 |
uint32_t rxappsize; |
| 402 |
}; |
| 403 |
|
| 404 |
static void axienet_rx_reset(XilinxAXIEnet *s) |
| 405 |
{
|
| 406 |
s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
|
| 407 |
} |
| 408 |
|
| 409 |
static void axienet_tx_reset(XilinxAXIEnet *s) |
| 410 |
{
|
| 411 |
s->tc = TC_JUM | TC_TX | TC_VLAN; |
| 412 |
} |
| 413 |
|
| 414 |
static inline int axienet_rx_resetting(XilinxAXIEnet *s) |
| 415 |
{
|
| 416 |
return s->rcw[1] & RCW1_RST; |
| 417 |
} |
| 418 |
|
| 419 |
static inline int axienet_rx_enabled(XilinxAXIEnet *s) |
| 420 |
{
|
| 421 |
return s->rcw[1] & RCW1_RX; |
| 422 |
} |
| 423 |
|
| 424 |
static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) |
| 425 |
{
|
| 426 |
return !!(s->regs[R_RAF] & RAF_EMCF_EN);
|
| 427 |
} |
| 428 |
|
| 429 |
static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) |
| 430 |
{
|
| 431 |
return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
|
| 432 |
} |
| 433 |
|
| 434 |
static void xilinx_axienet_reset(DeviceState *d) |
| 435 |
{
|
| 436 |
XilinxAXIEnet *s = XILINX_AXI_ENET(d); |
| 437 |
|
| 438 |
axienet_rx_reset(s); |
| 439 |
axienet_tx_reset(s); |
| 440 |
|
| 441 |
s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; |
| 442 |
s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; |
| 443 |
|
| 444 |
s->emmc = EMMC_LINKSPEED_100MB; |
| 445 |
} |
| 446 |
|
| 447 |
static void enet_update_irq(XilinxAXIEnet *s) |
| 448 |
{
|
| 449 |
s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; |
| 450 |
qemu_set_irq(s->irq, !!s->regs[R_IP]); |
| 451 |
} |
| 452 |
|
| 453 |
static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) |
| 454 |
{
|
| 455 |
XilinxAXIEnet *s = opaque; |
| 456 |
uint32_t r = 0;
|
| 457 |
addr >>= 2;
|
| 458 |
|
| 459 |
switch (addr) {
|
| 460 |
case R_RCW0:
|
| 461 |
case R_RCW1:
|
| 462 |
r = s->rcw[addr & 1];
|
| 463 |
break;
|
| 464 |
|
| 465 |
case R_TC:
|
| 466 |
r = s->tc; |
| 467 |
break;
|
| 468 |
|
| 469 |
case R_EMMC:
|
| 470 |
r = s->emmc; |
| 471 |
break;
|
| 472 |
|
| 473 |
case R_PHYC:
|
| 474 |
r = s->phyc; |
| 475 |
break;
|
| 476 |
|
| 477 |
case R_MCR:
|
| 478 |
r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ |
| 479 |
break;
|
| 480 |
|
| 481 |
case R_STATS_RX_BYTESL:
|
| 482 |
case R_STATS_RX_BYTESH:
|
| 483 |
r = s->stats.rx_bytes >> (32 * (addr & 1)); |
| 484 |
break;
|
| 485 |
|
| 486 |
case R_STATS_TX_BYTESL:
|
| 487 |
case R_STATS_TX_BYTESH:
|
| 488 |
r = s->stats.tx_bytes >> (32 * (addr & 1)); |
| 489 |
break;
|
| 490 |
|
| 491 |
case R_STATS_RXL:
|
| 492 |
case R_STATS_RXH:
|
| 493 |
r = s->stats.rx >> (32 * (addr & 1)); |
| 494 |
break;
|
| 495 |
case R_STATS_RX_BCASTL:
|
| 496 |
case R_STATS_RX_BCASTH:
|
| 497 |
r = s->stats.rx_bcast >> (32 * (addr & 1)); |
| 498 |
break;
|
| 499 |
case R_STATS_RX_MCASTL:
|
| 500 |
case R_STATS_RX_MCASTH:
|
| 501 |
r = s->stats.rx_mcast >> (32 * (addr & 1)); |
| 502 |
break;
|
| 503 |
|
| 504 |
case R_MC:
|
| 505 |
case R_MWD:
|
| 506 |
case R_MRD:
|
| 507 |
r = s->mii.regs[addr & 3];
|
| 508 |
break;
|
| 509 |
|
| 510 |
case R_UAW0:
|
| 511 |
case R_UAW1:
|
| 512 |
r = s->uaw[addr & 1];
|
| 513 |
break;
|
| 514 |
|
| 515 |
case R_UAWU:
|
| 516 |
case R_UAWL:
|
| 517 |
r = s->ext_uaw[addr & 1];
|
| 518 |
break;
|
| 519 |
|
| 520 |
case R_FMI:
|
| 521 |
r = s->fmi; |
| 522 |
break;
|
| 523 |
|
| 524 |
case R_AF0:
|
| 525 |
case R_AF1:
|
| 526 |
r = s->maddr[s->fmi & 3][addr & 1]; |
| 527 |
break;
|
| 528 |
|
| 529 |
case 0x8000 ... 0x83ff: |
| 530 |
r = s->ext_mtable[addr - 0x8000];
|
| 531 |
break;
|
| 532 |
|
| 533 |
default:
|
| 534 |
if (addr < ARRAY_SIZE(s->regs)) {
|
| 535 |
r = s->regs[addr]; |
| 536 |
} |
| 537 |
DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", |
| 538 |
__func__, addr * 4, r));
|
| 539 |
break;
|
| 540 |
} |
| 541 |
return r;
|
| 542 |
} |
| 543 |
|
| 544 |
static void enet_write(void *opaque, hwaddr addr, |
| 545 |
uint64_t value, unsigned size)
|
| 546 |
{
|
| 547 |
XilinxAXIEnet *s = opaque; |
| 548 |
struct TEMAC *t = &s->TEMAC;
|
| 549 |
|
| 550 |
addr >>= 2;
|
| 551 |
switch (addr) {
|
| 552 |
case R_RCW0:
|
| 553 |
case R_RCW1:
|
| 554 |
s->rcw[addr & 1] = value;
|
| 555 |
if ((addr & 1) && value & RCW1_RST) { |
| 556 |
axienet_rx_reset(s); |
| 557 |
} else {
|
| 558 |
qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
| 559 |
} |
| 560 |
break;
|
| 561 |
|
| 562 |
case R_TC:
|
| 563 |
s->tc = value; |
| 564 |
if (value & TC_RST) {
|
| 565 |
axienet_tx_reset(s); |
| 566 |
} |
| 567 |
break;
|
| 568 |
|
| 569 |
case R_EMMC:
|
| 570 |
s->emmc = value; |
| 571 |
break;
|
| 572 |
|
| 573 |
case R_PHYC:
|
| 574 |
s->phyc = value; |
| 575 |
break;
|
| 576 |
|
| 577 |
case R_MC:
|
| 578 |
value &= ((1 << 7) - 1); |
| 579 |
|
| 580 |
/* Enable the MII. */
|
| 581 |
if (value & MC_EN) {
|
| 582 |
unsigned int miiclkdiv = value & ((1 << 6) - 1); |
| 583 |
if (!miiclkdiv) {
|
| 584 |
qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
|
| 585 |
} |
| 586 |
} |
| 587 |
s->mii.mc = value; |
| 588 |
break;
|
| 589 |
|
| 590 |
case R_MCR: {
|
| 591 |
unsigned int phyaddr = (value >> 24) & 0x1f; |
| 592 |
unsigned int regaddr = (value >> 16) & 0x1f; |
| 593 |
unsigned int op = (value >> 14) & 3; |
| 594 |
unsigned int initiate = (value >> 11) & 1; |
| 595 |
|
| 596 |
if (initiate) {
|
| 597 |
if (op == 1) { |
| 598 |
mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); |
| 599 |
} else if (op == 2) { |
| 600 |
s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); |
| 601 |
} else {
|
| 602 |
qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
|
| 603 |
} |
| 604 |
} |
| 605 |
s->mii.mcr = value; |
| 606 |
break;
|
| 607 |
} |
| 608 |
|
| 609 |
case R_MWD:
|
| 610 |
case R_MRD:
|
| 611 |
s->mii.regs[addr & 3] = value;
|
| 612 |
break;
|
| 613 |
|
| 614 |
|
| 615 |
case R_UAW0:
|
| 616 |
case R_UAW1:
|
| 617 |
s->uaw[addr & 1] = value;
|
| 618 |
break;
|
| 619 |
|
| 620 |
case R_UAWL:
|
| 621 |
case R_UAWU:
|
| 622 |
s->ext_uaw[addr & 1] = value;
|
| 623 |
break;
|
| 624 |
|
| 625 |
case R_FMI:
|
| 626 |
s->fmi = value; |
| 627 |
break;
|
| 628 |
|
| 629 |
case R_AF0:
|
| 630 |
case R_AF1:
|
| 631 |
s->maddr[s->fmi & 3][addr & 1] = value; |
| 632 |
break;
|
| 633 |
|
| 634 |
case R_IS:
|
| 635 |
s->regs[addr] &= ~value; |
| 636 |
break;
|
| 637 |
|
| 638 |
case 0x8000 ... 0x83ff: |
| 639 |
s->ext_mtable[addr - 0x8000] = value;
|
| 640 |
break;
|
| 641 |
|
| 642 |
default:
|
| 643 |
DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", |
| 644 |
__func__, addr * 4, (unsigned)value)); |
| 645 |
if (addr < ARRAY_SIZE(s->regs)) {
|
| 646 |
s->regs[addr] = value; |
| 647 |
} |
| 648 |
break;
|
| 649 |
} |
| 650 |
enet_update_irq(s); |
| 651 |
} |
| 652 |
|
| 653 |
static const MemoryRegionOps enet_ops = { |
| 654 |
.read = enet_read, |
| 655 |
.write = enet_write, |
| 656 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 657 |
}; |
| 658 |
|
| 659 |
static int eth_can_rx(NetClientState *nc) |
| 660 |
{
|
| 661 |
XilinxAXIEnet *s = qemu_get_nic_opaque(nc); |
| 662 |
|
| 663 |
/* RX enabled? */
|
| 664 |
return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s);
|
| 665 |
} |
| 666 |
|
| 667 |
static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) |
| 668 |
{
|
| 669 |
int match = 1; |
| 670 |
|
| 671 |
if (memcmp(buf, &f0, 4)) { |
| 672 |
match = 0;
|
| 673 |
} |
| 674 |
|
| 675 |
if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { |
| 676 |
match = 0;
|
| 677 |
} |
| 678 |
|
| 679 |
return match;
|
| 680 |
} |
| 681 |
|
| 682 |
static void axienet_eth_rx_notify(void *opaque) |
| 683 |
{
|
| 684 |
XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); |
| 685 |
|
| 686 |
while (s->rxappsize && stream_can_push(s->tx_control_dev,
|
| 687 |
axienet_eth_rx_notify, s)) {
|
| 688 |
size_t ret = stream_push(s->tx_control_dev, |
| 689 |
(void *)s->rxapp + CONTROL_PAYLOAD_SIZE
|
| 690 |
- s->rxappsize, s->rxappsize); |
| 691 |
s->rxappsize -= ret; |
| 692 |
} |
| 693 |
|
| 694 |
while (s->rxsize && stream_can_push(s->tx_data_dev,
|
| 695 |
axienet_eth_rx_notify, s)) {
|
| 696 |
size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos,
|
| 697 |
s->rxsize); |
| 698 |
s->rxsize -= ret; |
| 699 |
s->rxpos += ret; |
| 700 |
if (!s->rxsize) {
|
| 701 |
s->regs[R_IS] |= IS_RX_COMPLETE; |
| 702 |
} |
| 703 |
} |
| 704 |
enet_update_irq(s); |
| 705 |
} |
| 706 |
|
| 707 |
static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) |
| 708 |
{
|
| 709 |
XilinxAXIEnet *s = qemu_get_nic_opaque(nc); |
| 710 |
static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, |
| 711 |
0xff, 0xff, 0xff}; |
| 712 |
static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; |
| 713 |
uint32_t app[CONTROL_PAYLOAD_WORDS] = {0};
|
| 714 |
int promisc = s->fmi & (1 << 31); |
| 715 |
int unicast, broadcast, multicast, ip_multicast = 0; |
| 716 |
uint32_t csum32; |
| 717 |
uint16_t csum16; |
| 718 |
int i;
|
| 719 |
|
| 720 |
DENET(qemu_log("%s: %zd bytes\n", __func__, size));
|
| 721 |
|
| 722 |
unicast = ~buf[0] & 0x1; |
| 723 |
broadcast = memcmp(buf, sa_bcast, 6) == 0; |
| 724 |
multicast = !unicast && !broadcast; |
| 725 |
if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { |
| 726 |
ip_multicast = 1;
|
| 727 |
} |
| 728 |
|
| 729 |
/* Jumbo or vlan sizes ? */
|
| 730 |
if (!(s->rcw[1] & RCW1_JUM)) { |
| 731 |
if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { |
| 732 |
return size;
|
| 733 |
} |
| 734 |
} |
| 735 |
|
| 736 |
/* Basic Address filters. If you want to use the extended filters
|
| 737 |
you'll generally have to place the ethernet mac into promiscuous mode
|
| 738 |
to avoid the basic filtering from dropping most frames. */
|
| 739 |
if (!promisc) {
|
| 740 |
if (unicast) {
|
| 741 |
if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { |
| 742 |
return size;
|
| 743 |
} |
| 744 |
} else {
|
| 745 |
if (broadcast) {
|
| 746 |
/* Broadcast. */
|
| 747 |
if (s->regs[R_RAF] & RAF_BCAST_REJ) {
|
| 748 |
return size;
|
| 749 |
} |
| 750 |
} else {
|
| 751 |
int drop = 1; |
| 752 |
|
| 753 |
/* Multicast. */
|
| 754 |
if (s->regs[R_RAF] & RAF_MCAST_REJ) {
|
| 755 |
return size;
|
| 756 |
} |
| 757 |
|
| 758 |
for (i = 0; i < 4; i++) { |
| 759 |
if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { |
| 760 |
drop = 0;
|
| 761 |
break;
|
| 762 |
} |
| 763 |
} |
| 764 |
|
| 765 |
if (drop) {
|
| 766 |
return size;
|
| 767 |
} |
| 768 |
} |
| 769 |
} |
| 770 |
} |
| 771 |
|
| 772 |
/* Extended mcast filtering enabled? */
|
| 773 |
if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
|
| 774 |
if (unicast) {
|
| 775 |
if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { |
| 776 |
return size;
|
| 777 |
} |
| 778 |
} else {
|
| 779 |
if (broadcast) {
|
| 780 |
/* Broadcast. ??? */
|
| 781 |
if (s->regs[R_RAF] & RAF_BCAST_REJ) {
|
| 782 |
return size;
|
| 783 |
} |
| 784 |
} else {
|
| 785 |
int idx, bit;
|
| 786 |
|
| 787 |
/* Multicast. */
|
| 788 |
if (!memcmp(buf, sa_ipmcast, 3)) { |
| 789 |
return size;
|
| 790 |
} |
| 791 |
|
| 792 |
idx = (buf[4] & 0x7f) << 8; |
| 793 |
idx |= buf[5];
|
| 794 |
|
| 795 |
bit = 1 << (idx & 0x1f); |
| 796 |
idx >>= 5;
|
| 797 |
|
| 798 |
if (!(s->ext_mtable[idx] & bit)) {
|
| 799 |
return size;
|
| 800 |
} |
| 801 |
} |
| 802 |
} |
| 803 |
} |
| 804 |
|
| 805 |
if (size < 12) { |
| 806 |
s->regs[R_IS] |= IS_RX_REJECT; |
| 807 |
enet_update_irq(s); |
| 808 |
return -1; |
| 809 |
} |
| 810 |
|
| 811 |
if (size > (s->c_rxmem - 4)) { |
| 812 |
size = s->c_rxmem - 4;
|
| 813 |
} |
| 814 |
|
| 815 |
memcpy(s->rxmem, buf, size); |
| 816 |
memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ |
| 817 |
|
| 818 |
if (s->rcw[1] & RCW1_FCS) { |
| 819 |
size += 4; /* fcs is inband. */ |
| 820 |
} |
| 821 |
|
| 822 |
app[0] = 5 << 28; |
| 823 |
csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); |
| 824 |
/* Fold it once. */
|
| 825 |
csum32 = (csum32 & 0xffff) + (csum32 >> 16); |
| 826 |
/* And twice to get rid of possible carries. */
|
| 827 |
csum16 = (csum32 & 0xffff) + (csum32 >> 16); |
| 828 |
app[3] = csum16;
|
| 829 |
app[4] = size & 0xffff; |
| 830 |
|
| 831 |
s->stats.rx_bytes += size; |
| 832 |
s->stats.rx++; |
| 833 |
if (multicast) {
|
| 834 |
s->stats.rx_mcast++; |
| 835 |
app[2] |= 1 | (ip_multicast << 1); |
| 836 |
} else if (broadcast) { |
| 837 |
s->stats.rx_bcast++; |
| 838 |
app[2] |= 1 << 3; |
| 839 |
} |
| 840 |
|
| 841 |
/* Good frame. */
|
| 842 |
app[2] |= 1 << 6; |
| 843 |
|
| 844 |
s->rxsize = size; |
| 845 |
s->rxpos = 0;
|
| 846 |
for (i = 0; i < ARRAY_SIZE(app); ++i) { |
| 847 |
app[i] = cpu_to_le32(app[i]); |
| 848 |
} |
| 849 |
s->rxappsize = CONTROL_PAYLOAD_SIZE; |
| 850 |
memcpy(s->rxapp, app, s->rxappsize); |
| 851 |
axienet_eth_rx_notify(s); |
| 852 |
|
| 853 |
enet_update_irq(s); |
| 854 |
return size;
|
| 855 |
} |
| 856 |
|
| 857 |
static void eth_cleanup(NetClientState *nc) |
| 858 |
{
|
| 859 |
/* FIXME. */
|
| 860 |
XilinxAXIEnet *s = qemu_get_nic_opaque(nc); |
| 861 |
g_free(s->rxmem); |
| 862 |
g_free(s); |
| 863 |
} |
| 864 |
|
| 865 |
static size_t
|
| 866 |
xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len) |
| 867 |
{
|
| 868 |
int i;
|
| 869 |
XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); |
| 870 |
XilinxAXIEnet *s = cs->enet; |
| 871 |
|
| 872 |
if (len != CONTROL_PAYLOAD_SIZE) {
|
| 873 |
hw_error("AXI Enet requires %d byte control stream payload\n",
|
| 874 |
(int)CONTROL_PAYLOAD_SIZE);
|
| 875 |
} |
| 876 |
|
| 877 |
memcpy(s->hdr, buf, len); |
| 878 |
|
| 879 |
for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { |
| 880 |
s->hdr[i] = le32_to_cpu(s->hdr[i]); |
| 881 |
} |
| 882 |
return len;
|
| 883 |
} |
| 884 |
|
| 885 |
static size_t
|
| 886 |
xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size) |
| 887 |
{
|
| 888 |
XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); |
| 889 |
XilinxAXIEnet *s = ds->enet; |
| 890 |
|
| 891 |
/* TX enable ? */
|
| 892 |
if (!(s->tc & TC_TX)) {
|
| 893 |
return size;
|
| 894 |
} |
| 895 |
|
| 896 |
/* Jumbo or vlan sizes ? */
|
| 897 |
if (!(s->tc & TC_JUM)) {
|
| 898 |
if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) { |
| 899 |
return size;
|
| 900 |
} |
| 901 |
} |
| 902 |
|
| 903 |
if (s->hdr[0] & 1) { |
| 904 |
unsigned int start_off = s->hdr[1] >> 16; |
| 905 |
unsigned int write_off = s->hdr[1] & 0xffff; |
| 906 |
uint32_t tmp_csum; |
| 907 |
uint16_t csum; |
| 908 |
|
| 909 |
tmp_csum = net_checksum_add(size - start_off, |
| 910 |
(uint8_t *)buf + start_off); |
| 911 |
/* Accumulate the seed. */
|
| 912 |
tmp_csum += s->hdr[2] & 0xffff; |
| 913 |
|
| 914 |
/* Fold the 32bit partial checksum. */
|
| 915 |
csum = net_checksum_finish(tmp_csum); |
| 916 |
|
| 917 |
/* Writeback. */
|
| 918 |
buf[write_off] = csum >> 8;
|
| 919 |
buf[write_off + 1] = csum & 0xff; |
| 920 |
} |
| 921 |
|
| 922 |
qemu_send_packet(qemu_get_queue(s->nic), buf, size); |
| 923 |
|
| 924 |
s->stats.tx_bytes += size; |
| 925 |
s->regs[R_IS] |= IS_TX_COMPLETE; |
| 926 |
enet_update_irq(s); |
| 927 |
|
| 928 |
return size;
|
| 929 |
} |
| 930 |
|
| 931 |
static NetClientInfo net_xilinx_enet_info = {
|
| 932 |
.type = NET_CLIENT_OPTIONS_KIND_NIC, |
| 933 |
.size = sizeof(NICState),
|
| 934 |
.can_receive = eth_can_rx, |
| 935 |
.receive = eth_rx, |
| 936 |
.cleanup = eth_cleanup, |
| 937 |
}; |
| 938 |
|
| 939 |
static void xilinx_enet_realize(DeviceState *dev, Error **errp) |
| 940 |
{
|
| 941 |
XilinxAXIEnet *s = XILINX_AXI_ENET(dev); |
| 942 |
XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); |
| 943 |
XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM( |
| 944 |
&s->rx_control_dev); |
| 945 |
Error *local_errp = NULL;
|
| 946 |
|
| 947 |
object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", |
| 948 |
(Object **) &ds->enet, &local_errp); |
| 949 |
object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", |
| 950 |
(Object **) &cs->enet, &local_errp); |
| 951 |
if (local_errp) {
|
| 952 |
goto xilinx_enet_realize_fail;
|
| 953 |
} |
| 954 |
object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_errp);
|
| 955 |
object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_errp);
|
| 956 |
if (local_errp) {
|
| 957 |
goto xilinx_enet_realize_fail;
|
| 958 |
} |
| 959 |
|
| 960 |
qemu_macaddr_default_if_unset(&s->conf.macaddr); |
| 961 |
s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, |
| 962 |
object_get_typename(OBJECT(dev)), dev->id, s); |
| 963 |
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
| 964 |
|
| 965 |
tdk_init(&s->TEMAC.phy); |
| 966 |
mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); |
| 967 |
|
| 968 |
s->TEMAC.parent = s; |
| 969 |
|
| 970 |
s->rxmem = g_malloc(s->c_rxmem); |
| 971 |
return;
|
| 972 |
|
| 973 |
xilinx_enet_realize_fail:
|
| 974 |
if (!*errp) {
|
| 975 |
*errp = local_errp; |
| 976 |
} |
| 977 |
} |
| 978 |
|
| 979 |
static void xilinx_enet_init(Object *obj) |
| 980 |
{
|
| 981 |
XilinxAXIEnet *s = XILINX_AXI_ENET(obj); |
| 982 |
SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 983 |
Error *errp = NULL;
|
| 984 |
|
| 985 |
object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
|
| 986 |
(Object **) &s->tx_data_dev, &errp); |
| 987 |
assert_no_error(errp); |
| 988 |
object_property_add_link(obj, "axistream-control-connected",
|
| 989 |
TYPE_STREAM_SLAVE, |
| 990 |
(Object **) &s->tx_control_dev, &errp); |
| 991 |
assert_no_error(errp); |
| 992 |
|
| 993 |
object_initialize(&s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM); |
| 994 |
object_initialize(&s->rx_control_dev, TYPE_XILINX_AXI_ENET_CONTROL_STREAM); |
| 995 |
object_property_add_child(OBJECT(s), "axistream-connected-target",
|
| 996 |
(Object *)&s->rx_data_dev, &errp); |
| 997 |
assert_no_error(errp); |
| 998 |
object_property_add_child(OBJECT(s), "axistream-control-connected-target",
|
| 999 |
(Object *)&s->rx_control_dev, &errp); |
| 1000 |
assert_no_error(errp); |
| 1001 |
|
| 1002 |
sysbus_init_irq(sbd, &s->irq); |
| 1003 |
|
| 1004 |
memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); |
| 1005 |
sysbus_init_mmio(sbd, &s->iomem); |
| 1006 |
} |
| 1007 |
|
| 1008 |
static Property xilinx_enet_properties[] = {
|
| 1009 |
DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), |
| 1010 |
DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), |
| 1011 |
DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), |
| 1012 |
DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), |
| 1013 |
DEFINE_PROP_END_OF_LIST(), |
| 1014 |
}; |
| 1015 |
|
| 1016 |
static void xilinx_enet_class_init(ObjectClass *klass, void *data) |
| 1017 |
{
|
| 1018 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 1019 |
|
| 1020 |
dc->realize = xilinx_enet_realize; |
| 1021 |
dc->props = xilinx_enet_properties; |
| 1022 |
dc->reset = xilinx_axienet_reset; |
| 1023 |
} |
| 1024 |
|
| 1025 |
static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data) |
| 1026 |
{
|
| 1027 |
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); |
| 1028 |
|
| 1029 |
ssc->push = data; |
| 1030 |
} |
| 1031 |
|
| 1032 |
static const TypeInfo xilinx_enet_info = { |
| 1033 |
.name = TYPE_XILINX_AXI_ENET, |
| 1034 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 1035 |
.instance_size = sizeof(XilinxAXIEnet),
|
| 1036 |
.class_init = xilinx_enet_class_init, |
| 1037 |
.instance_init = xilinx_enet_init, |
| 1038 |
}; |
| 1039 |
|
| 1040 |
static const TypeInfo xilinx_enet_data_stream_info = { |
| 1041 |
.name = TYPE_XILINX_AXI_ENET_DATA_STREAM, |
| 1042 |
.parent = TYPE_OBJECT, |
| 1043 |
.instance_size = sizeof(struct XilinxAXIEnetStreamSlave), |
| 1044 |
.class_init = xilinx_enet_stream_class_init, |
| 1045 |
.class_data = xilinx_axienet_data_stream_push, |
| 1046 |
.interfaces = (InterfaceInfo[]) {
|
| 1047 |
{ TYPE_STREAM_SLAVE },
|
| 1048 |
{ }
|
| 1049 |
} |
| 1050 |
}; |
| 1051 |
|
| 1052 |
static const TypeInfo xilinx_enet_control_stream_info = { |
| 1053 |
.name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, |
| 1054 |
.parent = TYPE_OBJECT, |
| 1055 |
.instance_size = sizeof(struct XilinxAXIEnetStreamSlave), |
| 1056 |
.class_init = xilinx_enet_stream_class_init, |
| 1057 |
.class_data = xilinx_axienet_control_stream_push, |
| 1058 |
.interfaces = (InterfaceInfo[]) {
|
| 1059 |
{ TYPE_STREAM_SLAVE },
|
| 1060 |
{ }
|
| 1061 |
} |
| 1062 |
}; |
| 1063 |
|
| 1064 |
static void xilinx_enet_register_types(void) |
| 1065 |
{
|
| 1066 |
type_register_static(&xilinx_enet_info); |
| 1067 |
type_register_static(&xilinx_enet_data_stream_info); |
| 1068 |
type_register_static(&xilinx_enet_control_stream_info); |
| 1069 |
} |
| 1070 |
|
| 1071 |
type_init(xilinx_enet_register_types) |