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Revision ef04a846

IDef04a8467eae31bc93b9458ad3d30a6ad1303327

Added by Max Filippov over 11 years ago

target-xtensa: implement coprocessor context option

In case Coprocessor Context option is enabled CPENABLE SR bits control
whether access to coprocessors is allowed or would rise one of
CoprocessorXDisabled exceptions.

See ISA, 4.4.5 for more details.

FP is coprocessor 0.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>

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