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/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "pci.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "i2c.h" |
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#include "smbus.h" |
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#include "kvm.h" |
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//#define DEBUG
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/* i82731AB (PIIX4) compatible power management function */
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#define PM_FREQ 3579545 |
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|
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#define ACPI_DBG_IO_ADDR 0xb044 |
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typedef struct PIIX4PMState { |
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PCIDevice dev; |
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uint16_t pmsts; |
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uint16_t pmen; |
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uint16_t pmcntrl; |
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uint8_t apmc; |
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uint8_t apms; |
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QEMUTimer *tmr_timer; |
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int64_t tmr_overflow_time; |
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i2c_bus *smbus; |
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uint8_t smb_stat; |
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uint8_t smb_ctl; |
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uint8_t smb_cmd; |
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uint8_t smb_addr; |
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uint8_t smb_data0; |
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uint8_t smb_data1; |
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uint8_t smb_data[32];
|
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uint8_t smb_index; |
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qemu_irq irq; |
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} PIIX4PMState; |
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#define RSM_STS (1 << 15) |
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#define PWRBTN_STS (1 << 8) |
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#define RTC_EN (1 << 10) |
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#define PWRBTN_EN (1 << 8) |
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#define GBL_EN (1 << 5) |
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#define TMROF_EN (1 << 0) |
61 |
|
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#define SCI_EN (1 << 0) |
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#define SUS_EN (1 << 13) |
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#define ACPI_ENABLE 0xf1 |
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#define ACPI_DISABLE 0xf0 |
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#define SMBHSTSTS 0x00 |
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#define SMBHSTCNT 0x02 |
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#define SMBHSTCMD 0x03 |
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#define SMBHSTADD 0x04 |
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#define SMBHSTDAT0 0x05 |
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#define SMBHSTDAT1 0x06 |
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#define SMBBLKDAT 0x07 |
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static PIIX4PMState *pm_state;
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|
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{ |
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uint32_t d; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec()); |
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return d & 0xffffff; |
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} |
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|
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static int get_pmsts(PIIX4PMState *s) |
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{ |
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int64_t d; |
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int pmsts;
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pmsts = s->pmsts; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec()); |
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if (d >= s->tmr_overflow_time)
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s->pmsts |= TMROF_EN; |
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return s->pmsts;
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} |
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static void pm_update_sci(PIIX4PMState *s) |
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{ |
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int sci_level, pmsts;
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int64_t expire_time; |
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pmsts = get_pmsts(s); |
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sci_level = (((pmsts & s->pmen) & |
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(RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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qemu_set_irq(s->irq, sci_level); |
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/* schedule a timer interruption if needed */
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if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_FREQ); |
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qemu_mod_timer(s->tmr_timer, expire_time); |
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} else {
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qemu_del_timer(s->tmr_timer); |
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} |
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} |
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static void pm_tmr_timer(void *opaque) |
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{ |
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PIIX4PMState *s = opaque; |
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pm_update_sci(s); |
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} |
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|
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 0x3f;
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switch(addr) {
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case 0x00: |
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{ |
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int64_t d; |
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int pmsts;
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pmsts = get_pmsts(s); |
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if (pmsts & val & TMROF_EN) {
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/* if TMRSTS is reset, then compute the new overflow time */
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, |
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get_ticks_per_sec()); |
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s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
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} |
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s->pmsts &= ~val; |
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pm_update_sci(s); |
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} |
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break;
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case 0x02: |
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s->pmen = val; |
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pm_update_sci(s); |
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break;
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case 0x04: |
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{ |
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int sus_typ;
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s->pmcntrl = val & ~(SUS_EN); |
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if (val & SUS_EN) {
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/* change suspend type */
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sus_typ = (val >> 10) & 7; |
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switch(sus_typ) {
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case 0: /* soft power off */ |
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qemu_system_shutdown_request(); |
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break;
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case 1: |
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/* RSM_STS should be set on resume. Pretend that resume
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was caused by power button */
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s->pmsts |= (RSM_STS | PWRBTN_STS); |
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qemu_system_reset_request(); |
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#if defined(TARGET_I386)
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cmos_set_s3_resume(); |
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#endif
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default:
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break;
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} |
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} |
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} |
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break;
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default:
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break;
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} |
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#ifdef DEBUG
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printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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#endif
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} |
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x3f;
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switch(addr) {
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case 0x00: |
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val = get_pmsts(s); |
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break;
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case 0x02: |
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val = s->pmen; |
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break;
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case 0x04: |
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val = s->pmcntrl; |
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break;
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default:
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val = 0;
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break;
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} |
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#ifdef DEBUG
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printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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#endif
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return val;
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} |
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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// PIIX4PMState *s = opaque;
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addr &= 0x3f;
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#ifdef DEBUG
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printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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#endif
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} |
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
217 |
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addr &= 0x3f;
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switch(addr) {
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case 0x08: |
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val = get_pmtmr(s); |
222 |
break;
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default:
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val = 0;
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break;
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} |
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#ifdef DEBUG
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printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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#endif
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return val;
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} |
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static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 1;
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#ifdef DEBUG
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printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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if (addr == 0) { |
241 |
s->apmc = val; |
242 |
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/* ACPI specs 3.0, 4.7.2.5 */
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if (val == ACPI_ENABLE) {
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s->pmcntrl |= SCI_EN; |
246 |
} else if (val == ACPI_DISABLE) { |
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s->pmcntrl &= ~SCI_EN; |
248 |
} |
249 |
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if (s->dev.config[0x5b] & (1 << 1)) { |
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cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); |
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} |
253 |
} else {
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s->apms = val; |
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} |
256 |
} |
257 |
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static uint32_t pm_smi_readb(void *opaque, uint32_t addr) |
259 |
{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
262 |
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addr &= 1;
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if (addr == 0) { |
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val = s->apmc; |
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} else {
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val = s->apms; |
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} |
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#ifdef DEBUG
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printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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return val;
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} |
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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#if defined(DEBUG)
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printf("ACPI: DBG: 0x%08x\n", val);
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#endif
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} |
281 |
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static void smb_transaction(PIIX4PMState *s) |
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{ |
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uint8_t prot = (s->smb_ctl >> 2) & 0x07; |
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uint8_t read = s->smb_addr & 0x01;
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uint8_t cmd = s->smb_cmd; |
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uint8_t addr = s->smb_addr >> 1;
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i2c_bus *bus = s->smbus; |
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#ifdef DEBUG
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printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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#endif
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switch(prot) {
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case 0x0: |
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smbus_quick_command(bus, addr, read); |
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break;
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case 0x1: |
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if (read) {
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s->smb_data0 = smbus_receive_byte(bus, addr); |
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} else {
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smbus_send_byte(bus, addr, cmd); |
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} |
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break;
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case 0x2: |
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if (read) {
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s->smb_data0 = smbus_read_byte(bus, addr, cmd); |
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} else {
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smbus_write_byte(bus, addr, cmd, s->smb_data0); |
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} |
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break;
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case 0x3: |
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if (read) {
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uint16_t val; |
314 |
val = smbus_read_word(bus, addr, cmd); |
315 |
s->smb_data0 = val; |
316 |
s->smb_data1 = val >> 8;
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} else {
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smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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} |
320 |
break;
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case 0x5: |
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if (read) {
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s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data); |
324 |
} else {
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smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0); |
326 |
} |
327 |
break;
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default:
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goto error;
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} |
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return;
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error:
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s->smb_stat |= 0x04;
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} |
336 |
|
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static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
338 |
{ |
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PIIX4PMState *s = opaque; |
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addr &= 0x3f;
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#ifdef DEBUG
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printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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case SMBHSTSTS:
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s->smb_stat = 0;
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347 |
s->smb_index = 0;
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break;
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349 |
case SMBHSTCNT:
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350 |
s->smb_ctl = val; |
351 |
if (val & 0x40) |
352 |
smb_transaction(s); |
353 |
break;
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354 |
case SMBHSTCMD:
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355 |
s->smb_cmd = val; |
356 |
break;
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357 |
case SMBHSTADD:
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358 |
s->smb_addr = val; |
359 |
break;
|
360 |
case SMBHSTDAT0:
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361 |
s->smb_data0 = val; |
362 |
break;
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363 |
case SMBHSTDAT1:
|
364 |
s->smb_data1 = val; |
365 |
break;
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366 |
case SMBBLKDAT:
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367 |
s->smb_data[s->smb_index++] = val; |
368 |
if (s->smb_index > 31) |
369 |
s->smb_index = 0;
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370 |
break;
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371 |
default:
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372 |
break;
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373 |
} |
374 |
} |
375 |
|
376 |
static uint32_t smb_ioport_readb(void *opaque, uint32_t addr) |
377 |
{ |
378 |
PIIX4PMState *s = opaque; |
379 |
uint32_t val; |
380 |
|
381 |
addr &= 0x3f;
|
382 |
switch(addr) {
|
383 |
case SMBHSTSTS:
|
384 |
val = s->smb_stat; |
385 |
break;
|
386 |
case SMBHSTCNT:
|
387 |
s->smb_index = 0;
|
388 |
val = s->smb_ctl & 0x1f;
|
389 |
break;
|
390 |
case SMBHSTCMD:
|
391 |
val = s->smb_cmd; |
392 |
break;
|
393 |
case SMBHSTADD:
|
394 |
val = s->smb_addr; |
395 |
break;
|
396 |
case SMBHSTDAT0:
|
397 |
val = s->smb_data0; |
398 |
break;
|
399 |
case SMBHSTDAT1:
|
400 |
val = s->smb_data1; |
401 |
break;
|
402 |
case SMBBLKDAT:
|
403 |
val = s->smb_data[s->smb_index++]; |
404 |
if (s->smb_index > 31) |
405 |
s->smb_index = 0;
|
406 |
break;
|
407 |
default:
|
408 |
val = 0;
|
409 |
break;
|
410 |
} |
411 |
#ifdef DEBUG
|
412 |
printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
|
413 |
#endif
|
414 |
return val;
|
415 |
} |
416 |
|
417 |
static void pm_io_space_update(PIIX4PMState *s) |
418 |
{ |
419 |
uint32_t pm_io_base; |
420 |
|
421 |
if (s->dev.config[0x80] & 1) { |
422 |
pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
|
423 |
pm_io_base &= 0xffc0;
|
424 |
|
425 |
/* XXX: need to improve memory and ioport allocation */
|
426 |
#if defined(DEBUG)
|
427 |
printf("PM: mapping to 0x%x\n", pm_io_base);
|
428 |
#endif
|
429 |
register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
430 |
register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
431 |
register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
432 |
register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
433 |
} |
434 |
} |
435 |
|
436 |
static void pm_write_config(PCIDevice *d, |
437 |
uint32_t address, uint32_t val, int len)
|
438 |
{ |
439 |
pci_default_write_config(d, address, val, len); |
440 |
if (address == 0x80) |
441 |
pm_io_space_update((PIIX4PMState *)d); |
442 |
} |
443 |
|
444 |
static int vmstate_acpi_post_load(void *opaque, int version_id) |
445 |
{ |
446 |
PIIX4PMState *s = opaque; |
447 |
|
448 |
pm_io_space_update(s); |
449 |
return 0; |
450 |
} |
451 |
|
452 |
static const VMStateDescription vmstate_acpi = { |
453 |
.name = "piix4_pm",
|
454 |
.version_id = 1,
|
455 |
.minimum_version_id = 1,
|
456 |
.minimum_version_id_old = 1,
|
457 |
.post_load = vmstate_acpi_post_load, |
458 |
.fields = (VMStateField []) { |
459 |
VMSTATE_PCI_DEVICE(dev, PIIX4PMState), |
460 |
VMSTATE_UINT16(pmsts, PIIX4PMState), |
461 |
VMSTATE_UINT16(pmen, PIIX4PMState), |
462 |
VMSTATE_UINT16(pmcntrl, PIIX4PMState), |
463 |
VMSTATE_UINT8(apmc, PIIX4PMState), |
464 |
VMSTATE_UINT8(apms, PIIX4PMState), |
465 |
VMSTATE_TIMER(tmr_timer, PIIX4PMState), |
466 |
VMSTATE_INT64(tmr_overflow_time, PIIX4PMState), |
467 |
VMSTATE_END_OF_LIST() |
468 |
} |
469 |
}; |
470 |
|
471 |
static void piix4_reset(void *opaque) |
472 |
{ |
473 |
PIIX4PMState *s = opaque; |
474 |
uint8_t *pci_conf = s->dev.config; |
475 |
|
476 |
pci_conf[0x58] = 0; |
477 |
pci_conf[0x59] = 0; |
478 |
pci_conf[0x5a] = 0; |
479 |
pci_conf[0x5b] = 0; |
480 |
|
481 |
if (kvm_enabled()) {
|
482 |
/* Mark SMM as already inited (until KVM supports SMM). */
|
483 |
pci_conf[0x5B] = 0x02; |
484 |
} |
485 |
} |
486 |
|
487 |
static void piix4_powerdown(void *opaque, int irq, int power_failing) |
488 |
{ |
489 |
#if defined(TARGET_I386)
|
490 |
PIIX4PMState *s = opaque; |
491 |
|
492 |
if (!s) {
|
493 |
qemu_system_shutdown_request(); |
494 |
} else if (s->pmen & PWRBTN_EN) { |
495 |
s->pmsts |= PWRBTN_EN; |
496 |
pm_update_sci(s); |
497 |
} |
498 |
#endif
|
499 |
} |
500 |
|
501 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
502 |
qemu_irq sci_irq) |
503 |
{ |
504 |
PIIX4PMState *s; |
505 |
uint8_t *pci_conf; |
506 |
|
507 |
s = (PIIX4PMState *)pci_register_device(bus, |
508 |
"PM", sizeof(PIIX4PMState), |
509 |
devfn, NULL, pm_write_config);
|
510 |
pm_state = s; |
511 |
pci_conf = s->dev.config; |
512 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
513 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3); |
514 |
pci_conf[0x06] = 0x80; |
515 |
pci_conf[0x07] = 0x02; |
516 |
pci_conf[0x08] = 0x03; // revision number |
517 |
pci_conf[0x09] = 0x00; |
518 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); |
519 |
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
520 |
pci_conf[0x3d] = 0x01; // interrupt pin 1 |
521 |
|
522 |
pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
523 |
|
524 |
register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s); |
525 |
register_ioport_read(0xb2, 2, 1, pm_smi_readb, s); |
526 |
|
527 |
register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
528 |
|
529 |
if (kvm_enabled()) {
|
530 |
/* Mark SMM as already inited to prevent SMM from running. KVM does not
|
531 |
* support SMM mode. */
|
532 |
pci_conf[0x5B] = 0x02; |
533 |
} |
534 |
|
535 |
/* XXX: which specification is used ? The i82731AB has different
|
536 |
mappings */
|
537 |
pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
538 |
pci_conf[0x63] = 0x60; |
539 |
pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
540 |
(serial_hds[1] != NULL ? 0x90 : 0); |
541 |
|
542 |
pci_conf[0x90] = smb_io_base | 1; |
543 |
pci_conf[0x91] = smb_io_base >> 8; |
544 |
pci_conf[0xd2] = 0x09; |
545 |
register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s); |
546 |
register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s); |
547 |
|
548 |
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
549 |
|
550 |
qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
|
551 |
|
552 |
vmstate_register(0, &vmstate_acpi, s);
|
553 |
|
554 |
s->smbus = i2c_init_bus(NULL, "i2c"); |
555 |
s->irq = sci_irq; |
556 |
qemu_register_reset(piix4_reset, s); |
557 |
|
558 |
return s->smbus;
|
559 |
} |
560 |
|
561 |
#define GPE_BASE 0xafe0 |
562 |
#define PCI_BASE 0xae00 |
563 |
#define PCI_EJ_BASE 0xae08 |
564 |
|
565 |
struct gpe_regs {
|
566 |
uint16_t sts; /* status */
|
567 |
uint16_t en; /* enabled */
|
568 |
}; |
569 |
|
570 |
struct pci_status {
|
571 |
uint32_t up; |
572 |
uint32_t down; |
573 |
}; |
574 |
|
575 |
static struct gpe_regs gpe; |
576 |
static struct pci_status pci0_status; |
577 |
|
578 |
static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
|
579 |
{ |
580 |
if (addr & 1) |
581 |
return (val >> 8) & 0xff; |
582 |
return val & 0xff; |
583 |
} |
584 |
|
585 |
static uint32_t gpe_readb(void *opaque, uint32_t addr) |
586 |
{ |
587 |
uint32_t val = 0;
|
588 |
struct gpe_regs *g = opaque;
|
589 |
switch (addr) {
|
590 |
case GPE_BASE:
|
591 |
case GPE_BASE + 1: |
592 |
val = gpe_read_val(g->sts, addr); |
593 |
break;
|
594 |
case GPE_BASE + 2: |
595 |
case GPE_BASE + 3: |
596 |
val = gpe_read_val(g->en, addr); |
597 |
break;
|
598 |
default:
|
599 |
break;
|
600 |
} |
601 |
|
602 |
#if defined(DEBUG)
|
603 |
printf("gpe read %x == %x\n", addr, val);
|
604 |
#endif
|
605 |
return val;
|
606 |
} |
607 |
|
608 |
static void gpe_write_val(uint16_t *cur, int addr, uint32_t val) |
609 |
{ |
610 |
if (addr & 1) |
611 |
*cur = (*cur & 0xff) | (val << 8); |
612 |
else
|
613 |
*cur = (*cur & 0xff00) | (val & 0xff); |
614 |
} |
615 |
|
616 |
static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val) |
617 |
{ |
618 |
uint16_t x1, x0 = val & 0xff;
|
619 |
int shift = (addr & 1) ? 8 : 0; |
620 |
|
621 |
x1 = (*cur >> shift) & 0xff;
|
622 |
|
623 |
x1 = x1 & ~x0; |
624 |
|
625 |
*cur = (*cur & (0xff << (8 - shift))) | (x1 << shift); |
626 |
} |
627 |
|
628 |
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
629 |
{ |
630 |
struct gpe_regs *g = opaque;
|
631 |
switch (addr) {
|
632 |
case GPE_BASE:
|
633 |
case GPE_BASE + 1: |
634 |
gpe_reset_val(&g->sts, addr, val); |
635 |
break;
|
636 |
case GPE_BASE + 2: |
637 |
case GPE_BASE + 3: |
638 |
gpe_write_val(&g->en, addr, val); |
639 |
break;
|
640 |
default:
|
641 |
break;
|
642 |
} |
643 |
|
644 |
#if defined(DEBUG)
|
645 |
printf("gpe write %x <== %d\n", addr, val);
|
646 |
#endif
|
647 |
} |
648 |
|
649 |
static uint32_t pcihotplug_read(void *opaque, uint32_t addr) |
650 |
{ |
651 |
uint32_t val = 0;
|
652 |
struct pci_status *g = opaque;
|
653 |
switch (addr) {
|
654 |
case PCI_BASE:
|
655 |
val = g->up; |
656 |
break;
|
657 |
case PCI_BASE + 4: |
658 |
val = g->down; |
659 |
break;
|
660 |
default:
|
661 |
break;
|
662 |
} |
663 |
|
664 |
#if defined(DEBUG)
|
665 |
printf("pcihotplug read %x == %x\n", addr, val);
|
666 |
#endif
|
667 |
return val;
|
668 |
} |
669 |
|
670 |
static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) |
671 |
{ |
672 |
struct pci_status *g = opaque;
|
673 |
switch (addr) {
|
674 |
case PCI_BASE:
|
675 |
g->up = val; |
676 |
break;
|
677 |
case PCI_BASE + 4: |
678 |
g->down = val; |
679 |
break;
|
680 |
} |
681 |
|
682 |
#if defined(DEBUG)
|
683 |
printf("pcihotplug write %x <== %d\n", addr, val);
|
684 |
#endif
|
685 |
} |
686 |
|
687 |
static uint32_t pciej_read(void *opaque, uint32_t addr) |
688 |
{ |
689 |
#if defined(DEBUG)
|
690 |
printf("pciej read %x\n", addr);
|
691 |
#endif
|
692 |
return 0; |
693 |
} |
694 |
|
695 |
static void pciej_write(void *opaque, uint32_t addr, uint32_t val) |
696 |
{ |
697 |
#if defined (TARGET_I386)
|
698 |
int slot = ffs(val) - 1; |
699 |
|
700 |
pci_device_hot_remove_success(0, slot);
|
701 |
#endif
|
702 |
|
703 |
#if defined(DEBUG)
|
704 |
printf("pciej write %x <== %d\n", addr, val);
|
705 |
#endif
|
706 |
} |
707 |
|
708 |
static void piix4_device_hot_add(int bus, int slot, int state); |
709 |
|
710 |
void piix4_acpi_system_hot_add_init(void) |
711 |
{ |
712 |
register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe); |
713 |
register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe); |
714 |
|
715 |
register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status); |
716 |
register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status); |
717 |
|
718 |
register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL); |
719 |
register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, NULL); |
720 |
|
721 |
qemu_system_device_hot_add_register(piix4_device_hot_add); |
722 |
} |
723 |
|
724 |
static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot) |
725 |
{ |
726 |
g->sts |= 2;
|
727 |
p->up |= (1 << slot);
|
728 |
} |
729 |
|
730 |
static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot) |
731 |
{ |
732 |
g->sts |= 2;
|
733 |
p->down |= (1 << slot);
|
734 |
} |
735 |
|
736 |
static void piix4_device_hot_add(int bus, int slot, int state) |
737 |
{ |
738 |
pci0_status.up = 0;
|
739 |
pci0_status.down = 0;
|
740 |
if (state)
|
741 |
enable_device(&pci0_status, &gpe, slot); |
742 |
else
|
743 |
disable_device(&pci0_status, &gpe, slot); |
744 |
if (gpe.en & 2) { |
745 |
qemu_set_irq(pm_state->irq, 1);
|
746 |
qemu_set_irq(pm_state->irq, 0);
|
747 |
} |
748 |
} |
749 |
|
750 |
static qemu_system_device_hot_add_t device_hot_add_callback;
|
751 |
void qemu_system_device_hot_add_register(qemu_system_device_hot_add_t callback)
|
752 |
{ |
753 |
device_hot_add_callback = callback; |
754 |
} |
755 |
|
756 |
void qemu_system_device_hot_add(int pcibus, int slot, int state) |
757 |
{ |
758 |
if (device_hot_add_callback)
|
759 |
device_hot_add_callback(pcibus, slot, state); |
760 |
} |
761 |
|
762 |
struct acpi_table_header
|
763 |
{ |
764 |
char signature [4]; /* ACPI signature (4 ASCII characters) */ |
765 |
uint32_t length; /* Length of table, in bytes, including header */
|
766 |
uint8_t revision; /* ACPI Specification minor version # */
|
767 |
uint8_t checksum; /* To make sum of entire table == 0 */
|
768 |
char oem_id [6]; /* OEM identification */ |
769 |
char oem_table_id [8]; /* OEM table identification */ |
770 |
uint32_t oem_revision; /* OEM revision number */
|
771 |
char asl_compiler_id [4]; /* ASL compiler vendor ID */ |
772 |
uint32_t asl_compiler_revision; /* ASL compiler revision number */
|
773 |
} __attribute__((packed)); |
774 |
|
775 |
char *acpi_tables;
|
776 |
size_t acpi_tables_len; |
777 |
|
778 |
static int acpi_checksum(const uint8_t *data, int len) |
779 |
{ |
780 |
int sum, i;
|
781 |
sum = 0;
|
782 |
for(i = 0; i < len; i++) |
783 |
sum += data[i]; |
784 |
return (-sum) & 0xff; |
785 |
} |
786 |
|
787 |
int acpi_table_add(const char *t) |
788 |
{ |
789 |
static const char *dfl_id = "QEMUQEMU"; |
790 |
char buf[1024], *p, *f; |
791 |
struct acpi_table_header acpi_hdr;
|
792 |
unsigned long val; |
793 |
size_t off; |
794 |
|
795 |
memset(&acpi_hdr, 0, sizeof(acpi_hdr)); |
796 |
|
797 |
if (get_param_value(buf, sizeof(buf), "sig", t)) { |
798 |
strncpy(acpi_hdr.signature, buf, 4);
|
799 |
} else {
|
800 |
strncpy(acpi_hdr.signature, dfl_id, 4);
|
801 |
} |
802 |
if (get_param_value(buf, sizeof(buf), "rev", t)) { |
803 |
val = strtoul(buf, &p, 10);
|
804 |
if (val > 255 || *p != '\0') |
805 |
goto out;
|
806 |
} else {
|
807 |
val = 1;
|
808 |
} |
809 |
acpi_hdr.revision = (int8_t)val; |
810 |
|
811 |
if (get_param_value(buf, sizeof(buf), "oem_id", t)) { |
812 |
strncpy(acpi_hdr.oem_id, buf, 6);
|
813 |
} else {
|
814 |
strncpy(acpi_hdr.oem_id, dfl_id, 6);
|
815 |
} |
816 |
|
817 |
if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) { |
818 |
strncpy(acpi_hdr.oem_table_id, buf, 8);
|
819 |
} else {
|
820 |
strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
|
821 |
} |
822 |
|
823 |
if (get_param_value(buf, sizeof(buf), "oem_rev", t)) { |
824 |
val = strtol(buf, &p, 10);
|
825 |
if(*p != '\0') |
826 |
goto out;
|
827 |
} else {
|
828 |
val = 1;
|
829 |
} |
830 |
acpi_hdr.oem_revision = cpu_to_le32(val); |
831 |
|
832 |
if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) { |
833 |
strncpy(acpi_hdr.asl_compiler_id, buf, 4);
|
834 |
} else {
|
835 |
strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
|
836 |
} |
837 |
|
838 |
if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) { |
839 |
val = strtol(buf, &p, 10);
|
840 |
if(*p != '\0') |
841 |
goto out;
|
842 |
} else {
|
843 |
val = 1;
|
844 |
} |
845 |
acpi_hdr.asl_compiler_revision = cpu_to_le32(val); |
846 |
|
847 |
if (!get_param_value(buf, sizeof(buf), "data", t)) { |
848 |
buf[0] = '\0'; |
849 |
} |
850 |
|
851 |
acpi_hdr.length = sizeof(acpi_hdr);
|
852 |
|
853 |
f = buf; |
854 |
while (buf[0]) { |
855 |
struct stat s;
|
856 |
char *n = strchr(f, ':'); |
857 |
if (n)
|
858 |
*n = '\0';
|
859 |
if(stat(f, &s) < 0) { |
860 |
fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
|
861 |
goto out;
|
862 |
} |
863 |
acpi_hdr.length += s.st_size; |
864 |
if (!n)
|
865 |
break;
|
866 |
*n = ':';
|
867 |
f = n + 1;
|
868 |
} |
869 |
|
870 |
if (!acpi_tables) {
|
871 |
acpi_tables_len = sizeof(uint16_t);
|
872 |
acpi_tables = qemu_mallocz(acpi_tables_len); |
873 |
} |
874 |
p = acpi_tables + acpi_tables_len; |
875 |
acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
|
876 |
acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len); |
877 |
|
878 |
acpi_hdr.length = cpu_to_le32(acpi_hdr.length); |
879 |
*(uint16_t*)p = acpi_hdr.length; |
880 |
p += sizeof(uint16_t);
|
881 |
memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
|
882 |
off = sizeof(acpi_hdr);
|
883 |
|
884 |
f = buf; |
885 |
while (buf[0]) { |
886 |
struct stat s;
|
887 |
int fd;
|
888 |
char *n = strchr(f, ':'); |
889 |
if (n)
|
890 |
*n = '\0';
|
891 |
fd = open(f, O_RDONLY); |
892 |
|
893 |
if(fd < 0) |
894 |
goto out;
|
895 |
if(fstat(fd, &s) < 0) { |
896 |
close(fd); |
897 |
goto out;
|
898 |
} |
899 |
|
900 |
do {
|
901 |
int r;
|
902 |
r = read(fd, p + off, s.st_size); |
903 |
if (r > 0) { |
904 |
off += r; |
905 |
s.st_size -= r; |
906 |
} else if ((r < 0 && errno != EINTR) || r == 0) { |
907 |
close(fd); |
908 |
goto out;
|
909 |
} |
910 |
} while(s.st_size);
|
911 |
|
912 |
close(fd); |
913 |
if (!n)
|
914 |
break;
|
915 |
f = n + 1;
|
916 |
} |
917 |
|
918 |
((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
|
919 |
/* increase number of tables */
|
920 |
(*(uint16_t*)acpi_tables) = |
921 |
cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
|
922 |
return 0; |
923 |
out:
|
924 |
if (acpi_tables) {
|
925 |
free(acpi_tables); |
926 |
acpi_tables = NULL;
|
927 |
} |
928 |
return -1; |
929 |
} |