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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU 8253/8254 interval timer emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pc.h" |
26 | 87ecb68b | pbrook | #include "isa.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | 80cabfad | bellard | |
29 | b0a21b53 | bellard | //#define DEBUG_PIT
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30 | b0a21b53 | bellard | |
31 | ec844b96 | bellard | #define RW_STATE_LSB 1 |
32 | ec844b96 | bellard | #define RW_STATE_MSB 2 |
33 | ec844b96 | bellard | #define RW_STATE_WORD0 3 |
34 | ec844b96 | bellard | #define RW_STATE_WORD1 4 |
35 | 80cabfad | bellard | |
36 | ec844b96 | bellard | typedef struct PITChannelState { |
37 | ec844b96 | bellard | int count; /* can be 65536 */ |
38 | ec844b96 | bellard | uint16_t latched_count; |
39 | ec844b96 | bellard | uint8_t count_latched; |
40 | ec844b96 | bellard | uint8_t status_latched; |
41 | ec844b96 | bellard | uint8_t status; |
42 | ec844b96 | bellard | uint8_t read_state; |
43 | ec844b96 | bellard | uint8_t write_state; |
44 | ec844b96 | bellard | uint8_t write_latch; |
45 | ec844b96 | bellard | uint8_t rw_mode; |
46 | ec844b96 | bellard | uint8_t mode; |
47 | ec844b96 | bellard | uint8_t bcd; /* not supported */
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48 | ec844b96 | bellard | uint8_t gate; /* timer start */
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49 | ec844b96 | bellard | int64_t count_load_time; |
50 | ec844b96 | bellard | /* irq handling */
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51 | ec844b96 | bellard | int64_t next_transition_time; |
52 | ec844b96 | bellard | QEMUTimer *irq_timer; |
53 | d537cf6c | pbrook | qemu_irq irq; |
54 | ec844b96 | bellard | } PITChannelState; |
55 | ec844b96 | bellard | |
56 | ec844b96 | bellard | struct PITState {
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57 | ec844b96 | bellard | PITChannelState channels[3];
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58 | ec844b96 | bellard | }; |
59 | ec844b96 | bellard | |
60 | ec844b96 | bellard | static PITState pit_state;
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61 | 80cabfad | bellard | |
62 | b0a21b53 | bellard | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
63 | b0a21b53 | bellard | |
64 | 80cabfad | bellard | static int pit_get_count(PITChannelState *s) |
65 | 80cabfad | bellard | { |
66 | 80cabfad | bellard | uint64_t d; |
67 | 80cabfad | bellard | int counter;
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68 | 80cabfad | bellard | |
69 | 6ee093c9 | Juan Quintela | d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, |
70 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
71 | 80cabfad | bellard | switch(s->mode) {
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72 | 80cabfad | bellard | case 0: |
73 | 80cabfad | bellard | case 1: |
74 | 80cabfad | bellard | case 4: |
75 | 80cabfad | bellard | case 5: |
76 | 80cabfad | bellard | counter = (s->count - d) & 0xffff;
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77 | 80cabfad | bellard | break;
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78 | 80cabfad | bellard | case 3: |
79 | 80cabfad | bellard | /* XXX: may be incorrect for odd counts */
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80 | 80cabfad | bellard | counter = s->count - ((2 * d) % s->count);
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81 | 80cabfad | bellard | break;
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82 | 80cabfad | bellard | default:
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83 | 80cabfad | bellard | counter = s->count - (d % s->count); |
84 | 80cabfad | bellard | break;
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85 | 80cabfad | bellard | } |
86 | 80cabfad | bellard | return counter;
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87 | 80cabfad | bellard | } |
88 | 80cabfad | bellard | |
89 | 80cabfad | bellard | /* get pit output bit */
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90 | ec844b96 | bellard | static int pit_get_out1(PITChannelState *s, int64_t current_time) |
91 | 80cabfad | bellard | { |
92 | 80cabfad | bellard | uint64_t d; |
93 | 80cabfad | bellard | int out;
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94 | 80cabfad | bellard | |
95 | 6ee093c9 | Juan Quintela | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
96 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
97 | 80cabfad | bellard | switch(s->mode) {
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98 | 80cabfad | bellard | default:
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99 | 80cabfad | bellard | case 0: |
100 | 80cabfad | bellard | out = (d >= s->count); |
101 | 80cabfad | bellard | break;
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102 | 80cabfad | bellard | case 1: |
103 | 80cabfad | bellard | out = (d < s->count); |
104 | 80cabfad | bellard | break;
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105 | 80cabfad | bellard | case 2: |
106 | 80cabfad | bellard | if ((d % s->count) == 0 && d != 0) |
107 | 80cabfad | bellard | out = 1;
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108 | 80cabfad | bellard | else
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109 | 80cabfad | bellard | out = 0;
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110 | 80cabfad | bellard | break;
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111 | 80cabfad | bellard | case 3: |
112 | 80cabfad | bellard | out = (d % s->count) < ((s->count + 1) >> 1); |
113 | 80cabfad | bellard | break;
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114 | 80cabfad | bellard | case 4: |
115 | 80cabfad | bellard | case 5: |
116 | 80cabfad | bellard | out = (d == s->count); |
117 | 80cabfad | bellard | break;
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118 | 80cabfad | bellard | } |
119 | 80cabfad | bellard | return out;
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120 | 80cabfad | bellard | } |
121 | 80cabfad | bellard | |
122 | ec844b96 | bellard | int pit_get_out(PITState *pit, int channel, int64_t current_time) |
123 | ec844b96 | bellard | { |
124 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
125 | ec844b96 | bellard | return pit_get_out1(s, current_time);
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126 | ec844b96 | bellard | } |
127 | ec844b96 | bellard | |
128 | b0a21b53 | bellard | /* return -1 if no transition will occur. */
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129 | 5fafdf24 | ths | static int64_t pit_get_next_transition_time(PITChannelState *s,
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130 | b0a21b53 | bellard | int64_t current_time) |
131 | 80cabfad | bellard | { |
132 | b0a21b53 | bellard | uint64_t d, next_time, base; |
133 | b0a21b53 | bellard | int period2;
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134 | 80cabfad | bellard | |
135 | 6ee093c9 | Juan Quintela | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
136 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
137 | 80cabfad | bellard | switch(s->mode) {
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138 | 80cabfad | bellard | default:
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139 | 80cabfad | bellard | case 0: |
140 | 80cabfad | bellard | case 1: |
141 | b0a21b53 | bellard | if (d < s->count)
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142 | b0a21b53 | bellard | next_time = s->count; |
143 | b0a21b53 | bellard | else
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144 | b0a21b53 | bellard | return -1; |
145 | 80cabfad | bellard | break;
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146 | 80cabfad | bellard | case 2: |
147 | b0a21b53 | bellard | base = (d / s->count) * s->count; |
148 | b0a21b53 | bellard | if ((d - base) == 0 && d != 0) |
149 | b0a21b53 | bellard | next_time = base + s->count; |
150 | b0a21b53 | bellard | else
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151 | b0a21b53 | bellard | next_time = base + s->count + 1;
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152 | 80cabfad | bellard | break;
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153 | 80cabfad | bellard | case 3: |
154 | b0a21b53 | bellard | base = (d / s->count) * s->count; |
155 | b0a21b53 | bellard | period2 = ((s->count + 1) >> 1); |
156 | 5fafdf24 | ths | if ((d - base) < period2)
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157 | b0a21b53 | bellard | next_time = base + period2; |
158 | b0a21b53 | bellard | else
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159 | b0a21b53 | bellard | next_time = base + s->count; |
160 | 80cabfad | bellard | break;
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161 | 80cabfad | bellard | case 4: |
162 | 80cabfad | bellard | case 5: |
163 | b0a21b53 | bellard | if (d < s->count)
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164 | b0a21b53 | bellard | next_time = s->count; |
165 | b0a21b53 | bellard | else if (d == s->count) |
166 | b0a21b53 | bellard | next_time = s->count + 1;
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167 | 80cabfad | bellard | else
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168 | b0a21b53 | bellard | return -1; |
169 | 80cabfad | bellard | break;
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170 | 80cabfad | bellard | } |
171 | b0a21b53 | bellard | /* convert to timer units */
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172 | 6ee093c9 | Juan Quintela | next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(), |
173 | 6ee093c9 | Juan Quintela | PIT_FREQ); |
174 | 1154e441 | bellard | /* fix potential rounding problems */
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175 | 1154e441 | bellard | /* XXX: better solution: use a clock at PIT_FREQ Hz */
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176 | 1154e441 | bellard | if (next_time <= current_time)
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177 | 1154e441 | bellard | next_time = current_time + 1;
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178 | b0a21b53 | bellard | return next_time;
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179 | 80cabfad | bellard | } |
180 | 80cabfad | bellard | |
181 | 80cabfad | bellard | /* val must be 0 or 1 */
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182 | ec844b96 | bellard | void pit_set_gate(PITState *pit, int channel, int val) |
183 | 80cabfad | bellard | { |
184 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
185 | ec844b96 | bellard | |
186 | 80cabfad | bellard | switch(s->mode) {
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187 | 80cabfad | bellard | default:
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188 | 80cabfad | bellard | case 0: |
189 | 80cabfad | bellard | case 4: |
190 | 80cabfad | bellard | /* XXX: just disable/enable counting */
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191 | 80cabfad | bellard | break;
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192 | 80cabfad | bellard | case 1: |
193 | 80cabfad | bellard | case 5: |
194 | 80cabfad | bellard | if (s->gate < val) {
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195 | 80cabfad | bellard | /* restart counting on rising edge */
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196 | b0a21b53 | bellard | s->count_load_time = qemu_get_clock(vm_clock); |
197 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
198 | 80cabfad | bellard | } |
199 | 80cabfad | bellard | break;
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200 | 80cabfad | bellard | case 2: |
201 | 80cabfad | bellard | case 3: |
202 | 80cabfad | bellard | if (s->gate < val) {
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203 | 80cabfad | bellard | /* restart counting on rising edge */
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204 | b0a21b53 | bellard | s->count_load_time = qemu_get_clock(vm_clock); |
205 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
206 | 80cabfad | bellard | } |
207 | 80cabfad | bellard | /* XXX: disable/enable counting */
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208 | 80cabfad | bellard | break;
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209 | 80cabfad | bellard | } |
210 | 80cabfad | bellard | s->gate = val; |
211 | 80cabfad | bellard | } |
212 | 80cabfad | bellard | |
213 | ec844b96 | bellard | int pit_get_gate(PITState *pit, int channel) |
214 | ec844b96 | bellard | { |
215 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
216 | ec844b96 | bellard | return s->gate;
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217 | ec844b96 | bellard | } |
218 | ec844b96 | bellard | |
219 | fd06c375 | bellard | int pit_get_initial_count(PITState *pit, int channel) |
220 | fd06c375 | bellard | { |
221 | fd06c375 | bellard | PITChannelState *s = &pit->channels[channel]; |
222 | fd06c375 | bellard | return s->count;
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223 | fd06c375 | bellard | } |
224 | fd06c375 | bellard | |
225 | fd06c375 | bellard | int pit_get_mode(PITState *pit, int channel) |
226 | fd06c375 | bellard | { |
227 | fd06c375 | bellard | PITChannelState *s = &pit->channels[channel]; |
228 | fd06c375 | bellard | return s->mode;
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229 | fd06c375 | bellard | } |
230 | fd06c375 | bellard | |
231 | 80cabfad | bellard | static inline void pit_load_count(PITChannelState *s, int val) |
232 | 80cabfad | bellard | { |
233 | 80cabfad | bellard | if (val == 0) |
234 | 80cabfad | bellard | val = 0x10000;
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235 | b0a21b53 | bellard | s->count_load_time = qemu_get_clock(vm_clock); |
236 | 80cabfad | bellard | s->count = val; |
237 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
238 | 80cabfad | bellard | } |
239 | 80cabfad | bellard | |
240 | ec844b96 | bellard | /* if already latched, do not latch again */
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241 | ec844b96 | bellard | static void pit_latch_count(PITChannelState *s) |
242 | ec844b96 | bellard | { |
243 | ec844b96 | bellard | if (!s->count_latched) {
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244 | ec844b96 | bellard | s->latched_count = pit_get_count(s); |
245 | ec844b96 | bellard | s->count_latched = s->rw_mode; |
246 | ec844b96 | bellard | } |
247 | ec844b96 | bellard | } |
248 | ec844b96 | bellard | |
249 | b41a2cd1 | bellard | static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
250 | 80cabfad | bellard | { |
251 | ec844b96 | bellard | PITState *pit = opaque; |
252 | 80cabfad | bellard | int channel, access;
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253 | 80cabfad | bellard | PITChannelState *s; |
254 | 80cabfad | bellard | |
255 | 80cabfad | bellard | addr &= 3;
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256 | 80cabfad | bellard | if (addr == 3) { |
257 | 80cabfad | bellard | channel = val >> 6;
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258 | ec844b96 | bellard | if (channel == 3) { |
259 | ec844b96 | bellard | /* read back command */
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260 | ec844b96 | bellard | for(channel = 0; channel < 3; channel++) { |
261 | ec844b96 | bellard | s = &pit->channels[channel]; |
262 | ec844b96 | bellard | if (val & (2 << channel)) { |
263 | ec844b96 | bellard | if (!(val & 0x20)) { |
264 | ec844b96 | bellard | pit_latch_count(s); |
265 | ec844b96 | bellard | } |
266 | ec844b96 | bellard | if (!(val & 0x10) && !s->status_latched) { |
267 | ec844b96 | bellard | /* status latch */
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268 | ec844b96 | bellard | /* XXX: add BCD and null count */
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269 | ec844b96 | bellard | s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
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270 | ec844b96 | bellard | (s->rw_mode << 4) |
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271 | ec844b96 | bellard | (s->mode << 1) |
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272 | ec844b96 | bellard | s->bcd; |
273 | ec844b96 | bellard | s->status_latched = 1;
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274 | ec844b96 | bellard | } |
275 | ec844b96 | bellard | } |
276 | ec844b96 | bellard | } |
277 | ec844b96 | bellard | } else {
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278 | ec844b96 | bellard | s = &pit->channels[channel]; |
279 | ec844b96 | bellard | access = (val >> 4) & 3; |
280 | ec844b96 | bellard | if (access == 0) { |
281 | ec844b96 | bellard | pit_latch_count(s); |
282 | ec844b96 | bellard | } else {
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283 | ec844b96 | bellard | s->rw_mode = access; |
284 | ec844b96 | bellard | s->read_state = access; |
285 | ec844b96 | bellard | s->write_state = access; |
286 | ec844b96 | bellard | |
287 | ec844b96 | bellard | s->mode = (val >> 1) & 7; |
288 | ec844b96 | bellard | s->bcd = val & 1;
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289 | ec844b96 | bellard | /* XXX: update irq timer ? */
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290 | ec844b96 | bellard | } |
291 | 80cabfad | bellard | } |
292 | 80cabfad | bellard | } else {
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293 | ec844b96 | bellard | s = &pit->channels[addr]; |
294 | ec844b96 | bellard | switch(s->write_state) {
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295 | ec844b96 | bellard | default:
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296 | 80cabfad | bellard | case RW_STATE_LSB:
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297 | 80cabfad | bellard | pit_load_count(s, val); |
298 | 80cabfad | bellard | break;
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299 | 80cabfad | bellard | case RW_STATE_MSB:
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300 | 80cabfad | bellard | pit_load_count(s, val << 8);
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301 | 80cabfad | bellard | break;
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302 | 80cabfad | bellard | case RW_STATE_WORD0:
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303 | ec844b96 | bellard | s->write_latch = val; |
304 | ec844b96 | bellard | s->write_state = RW_STATE_WORD1; |
305 | ec844b96 | bellard | break;
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306 | 80cabfad | bellard | case RW_STATE_WORD1:
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307 | ec844b96 | bellard | pit_load_count(s, s->write_latch | (val << 8));
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308 | ec844b96 | bellard | s->write_state = RW_STATE_WORD0; |
309 | 80cabfad | bellard | break;
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310 | 80cabfad | bellard | } |
311 | 80cabfad | bellard | } |
312 | 80cabfad | bellard | } |
313 | 80cabfad | bellard | |
314 | b41a2cd1 | bellard | static uint32_t pit_ioport_read(void *opaque, uint32_t addr) |
315 | 80cabfad | bellard | { |
316 | ec844b96 | bellard | PITState *pit = opaque; |
317 | 80cabfad | bellard | int ret, count;
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318 | 80cabfad | bellard | PITChannelState *s; |
319 | 3b46e624 | ths | |
320 | 80cabfad | bellard | addr &= 3;
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321 | ec844b96 | bellard | s = &pit->channels[addr]; |
322 | ec844b96 | bellard | if (s->status_latched) {
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323 | ec844b96 | bellard | s->status_latched = 0;
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324 | ec844b96 | bellard | ret = s->status; |
325 | ec844b96 | bellard | } else if (s->count_latched) { |
326 | ec844b96 | bellard | switch(s->count_latched) {
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327 | ec844b96 | bellard | default:
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328 | ec844b96 | bellard | case RW_STATE_LSB:
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329 | ec844b96 | bellard | ret = s->latched_count & 0xff;
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330 | ec844b96 | bellard | s->count_latched = 0;
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331 | ec844b96 | bellard | break;
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332 | ec844b96 | bellard | case RW_STATE_MSB:
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333 | 80cabfad | bellard | ret = s->latched_count >> 8;
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334 | ec844b96 | bellard | s->count_latched = 0;
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335 | ec844b96 | bellard | break;
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336 | ec844b96 | bellard | case RW_STATE_WORD0:
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337 | 80cabfad | bellard | ret = s->latched_count & 0xff;
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338 | ec844b96 | bellard | s->count_latched = RW_STATE_MSB; |
339 | ec844b96 | bellard | break;
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340 | ec844b96 | bellard | } |
341 | ec844b96 | bellard | } else {
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342 | ec844b96 | bellard | switch(s->read_state) {
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343 | ec844b96 | bellard | default:
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344 | ec844b96 | bellard | case RW_STATE_LSB:
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345 | ec844b96 | bellard | count = pit_get_count(s); |
346 | ec844b96 | bellard | ret = count & 0xff;
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347 | ec844b96 | bellard | break;
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348 | ec844b96 | bellard | case RW_STATE_MSB:
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349 | ec844b96 | bellard | count = pit_get_count(s); |
350 | ec844b96 | bellard | ret = (count >> 8) & 0xff; |
351 | ec844b96 | bellard | break;
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352 | ec844b96 | bellard | case RW_STATE_WORD0:
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353 | ec844b96 | bellard | count = pit_get_count(s); |
354 | ec844b96 | bellard | ret = count & 0xff;
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355 | ec844b96 | bellard | s->read_state = RW_STATE_WORD1; |
356 | ec844b96 | bellard | break;
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357 | ec844b96 | bellard | case RW_STATE_WORD1:
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358 | ec844b96 | bellard | count = pit_get_count(s); |
359 | ec844b96 | bellard | ret = (count >> 8) & 0xff; |
360 | ec844b96 | bellard | s->read_state = RW_STATE_WORD0; |
361 | ec844b96 | bellard | break;
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362 | ec844b96 | bellard | } |
363 | 80cabfad | bellard | } |
364 | 80cabfad | bellard | return ret;
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365 | 80cabfad | bellard | } |
366 | 80cabfad | bellard | |
367 | b0a21b53 | bellard | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
368 | b0a21b53 | bellard | { |
369 | b0a21b53 | bellard | int64_t expire_time; |
370 | b0a21b53 | bellard | int irq_level;
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371 | b0a21b53 | bellard | |
372 | b0a21b53 | bellard | if (!s->irq_timer)
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373 | b0a21b53 | bellard | return;
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374 | b0a21b53 | bellard | expire_time = pit_get_next_transition_time(s, current_time); |
375 | ec844b96 | bellard | irq_level = pit_get_out1(s, current_time); |
376 | d537cf6c | pbrook | qemu_set_irq(s->irq, irq_level); |
377 | b0a21b53 | bellard | #ifdef DEBUG_PIT
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378 | b0a21b53 | bellard | printf("irq_level=%d next_delay=%f\n",
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379 | 5fafdf24 | ths | irq_level, |
380 | 6ee093c9 | Juan Quintela | (double)(expire_time - current_time) / get_ticks_per_sec());
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381 | b0a21b53 | bellard | #endif
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382 | b0a21b53 | bellard | s->next_transition_time = expire_time; |
383 | b0a21b53 | bellard | if (expire_time != -1) |
384 | b0a21b53 | bellard | qemu_mod_timer(s->irq_timer, expire_time); |
385 | b0a21b53 | bellard | else
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386 | b0a21b53 | bellard | qemu_del_timer(s->irq_timer); |
387 | b0a21b53 | bellard | } |
388 | b0a21b53 | bellard | |
389 | b0a21b53 | bellard | static void pit_irq_timer(void *opaque) |
390 | b0a21b53 | bellard | { |
391 | b0a21b53 | bellard | PITChannelState *s = opaque; |
392 | b0a21b53 | bellard | |
393 | b0a21b53 | bellard | pit_irq_timer_update(s, s->next_transition_time); |
394 | b0a21b53 | bellard | } |
395 | b0a21b53 | bellard | |
396 | 5122b431 | Juan Quintela | static const VMStateDescription vmstate_pit_channel = { |
397 | 5122b431 | Juan Quintela | .name = "pit channel",
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398 | 5122b431 | Juan Quintela | .version_id = 2,
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399 | 5122b431 | Juan Quintela | .minimum_version_id = 2,
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400 | 5122b431 | Juan Quintela | .minimum_version_id_old = 2,
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401 | 5122b431 | Juan Quintela | .fields = (VMStateField []) { |
402 | 5122b431 | Juan Quintela | VMSTATE_INT32(count, PITChannelState), |
403 | 5122b431 | Juan Quintela | VMSTATE_UINT16(latched_count, PITChannelState), |
404 | 5122b431 | Juan Quintela | VMSTATE_UINT8(count_latched, PITChannelState), |
405 | 5122b431 | Juan Quintela | VMSTATE_UINT8(status_latched, PITChannelState), |
406 | 5122b431 | Juan Quintela | VMSTATE_UINT8(status, PITChannelState), |
407 | 5122b431 | Juan Quintela | VMSTATE_UINT8(read_state, PITChannelState), |
408 | 5122b431 | Juan Quintela | VMSTATE_UINT8(write_state, PITChannelState), |
409 | 5122b431 | Juan Quintela | VMSTATE_UINT8(write_latch, PITChannelState), |
410 | 5122b431 | Juan Quintela | VMSTATE_UINT8(rw_mode, PITChannelState), |
411 | 5122b431 | Juan Quintela | VMSTATE_UINT8(mode, PITChannelState), |
412 | 5122b431 | Juan Quintela | VMSTATE_UINT8(bcd, PITChannelState), |
413 | 5122b431 | Juan Quintela | VMSTATE_UINT8(gate, PITChannelState), |
414 | 5122b431 | Juan Quintela | VMSTATE_INT64(count_load_time, PITChannelState), |
415 | 5122b431 | Juan Quintela | VMSTATE_INT64(next_transition_time, PITChannelState), |
416 | 5122b431 | Juan Quintela | VMSTATE_END_OF_LIST() |
417 | b0a21b53 | bellard | } |
418 | 5122b431 | Juan Quintela | }; |
419 | b0a21b53 | bellard | |
420 | 5122b431 | Juan Quintela | static int pit_load_old(QEMUFile *f, void *opaque, int version_id) |
421 | b0a21b53 | bellard | { |
422 | ec844b96 | bellard | PITState *pit = opaque; |
423 | b0a21b53 | bellard | PITChannelState *s; |
424 | b0a21b53 | bellard | int i;
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425 | 3b46e624 | ths | |
426 | b0a21b53 | bellard | if (version_id != 1) |
427 | b0a21b53 | bellard | return -EINVAL;
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428 | b0a21b53 | bellard | |
429 | b0a21b53 | bellard | for(i = 0; i < 3; i++) { |
430 | ec844b96 | bellard | s = &pit->channels[i]; |
431 | bee8d684 | ths | s->count=qemu_get_be32(f); |
432 | b0a21b53 | bellard | qemu_get_be16s(f, &s->latched_count); |
433 | ec844b96 | bellard | qemu_get_8s(f, &s->count_latched); |
434 | ec844b96 | bellard | qemu_get_8s(f, &s->status_latched); |
435 | ec844b96 | bellard | qemu_get_8s(f, &s->status); |
436 | ec844b96 | bellard | qemu_get_8s(f, &s->read_state); |
437 | ec844b96 | bellard | qemu_get_8s(f, &s->write_state); |
438 | ec844b96 | bellard | qemu_get_8s(f, &s->write_latch); |
439 | ec844b96 | bellard | qemu_get_8s(f, &s->rw_mode); |
440 | b0a21b53 | bellard | qemu_get_8s(f, &s->mode); |
441 | b0a21b53 | bellard | qemu_get_8s(f, &s->bcd); |
442 | b0a21b53 | bellard | qemu_get_8s(f, &s->gate); |
443 | bee8d684 | ths | s->count_load_time=qemu_get_be64(f); |
444 | b0a21b53 | bellard | if (s->irq_timer) {
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445 | bee8d684 | ths | s->next_transition_time=qemu_get_be64(f); |
446 | b0a21b53 | bellard | qemu_get_timer(f, s->irq_timer); |
447 | b0a21b53 | bellard | } |
448 | b0a21b53 | bellard | } |
449 | b0a21b53 | bellard | return 0; |
450 | b0a21b53 | bellard | } |
451 | b0a21b53 | bellard | |
452 | 5122b431 | Juan Quintela | static const VMStateDescription vmstate_pit = { |
453 | 5122b431 | Juan Quintela | .name = "i8254",
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454 | 5122b431 | Juan Quintela | .version_id = 2,
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455 | 5122b431 | Juan Quintela | .minimum_version_id = 2,
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456 | 5122b431 | Juan Quintela | .minimum_version_id_old = 1,
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457 | 5122b431 | Juan Quintela | .load_state_old = pit_load_old, |
458 | 5122b431 | Juan Quintela | .fields = (VMStateField []) { |
459 | 5122b431 | Juan Quintela | VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState), |
460 | 5122b431 | Juan Quintela | VMSTATE_TIMER(channels[0].irq_timer, PITState),
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461 | 5122b431 | Juan Quintela | VMSTATE_END_OF_LIST() |
462 | 5122b431 | Juan Quintela | } |
463 | 5122b431 | Juan Quintela | }; |
464 | 5122b431 | Juan Quintela | |
465 | d7d02e3c | bellard | static void pit_reset(void *opaque) |
466 | 80cabfad | bellard | { |
467 | d7d02e3c | bellard | PITState *pit = opaque; |
468 | 80cabfad | bellard | PITChannelState *s; |
469 | 80cabfad | bellard | int i;
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470 | 80cabfad | bellard | |
471 | 80cabfad | bellard | for(i = 0;i < 3; i++) { |
472 | ec844b96 | bellard | s = &pit->channels[i]; |
473 | 80cabfad | bellard | s->mode = 3;
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474 | 80cabfad | bellard | s->gate = (i != 2);
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475 | 80cabfad | bellard | pit_load_count(s, 0);
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476 | 80cabfad | bellard | } |
477 | d7d02e3c | bellard | } |
478 | d7d02e3c | bellard | |
479 | 16b29ae1 | aliguori | /* When HPET is operating in legacy mode, i8254 timer0 is disabled */
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480 | 16b29ae1 | aliguori | void hpet_pit_disable(void) { |
481 | 16b29ae1 | aliguori | PITChannelState *s; |
482 | 16b29ae1 | aliguori | s = &pit_state.channels[0];
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483 | e0dd114c | aliguori | if (s->irq_timer)
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484 | e0dd114c | aliguori | qemu_del_timer(s->irq_timer); |
485 | 16b29ae1 | aliguori | } |
486 | 16b29ae1 | aliguori | |
487 | c50c2d68 | aurel32 | /* When HPET is reset or leaving legacy mode, it must reenable i8254
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488 | 16b29ae1 | aliguori | * timer 0
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489 | 16b29ae1 | aliguori | */
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490 | 16b29ae1 | aliguori | |
491 | 16b29ae1 | aliguori | void hpet_pit_enable(void) |
492 | 16b29ae1 | aliguori | { |
493 | 16b29ae1 | aliguori | PITState *pit = &pit_state; |
494 | 16b29ae1 | aliguori | PITChannelState *s; |
495 | 16b29ae1 | aliguori | s = &pit->channels[0];
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496 | 16b29ae1 | aliguori | s->mode = 3;
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497 | 16b29ae1 | aliguori | s->gate = 1;
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498 | 16b29ae1 | aliguori | pit_load_count(s, 0);
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499 | 16b29ae1 | aliguori | } |
500 | 16b29ae1 | aliguori | |
501 | d537cf6c | pbrook | PITState *pit_init(int base, qemu_irq irq)
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502 | d7d02e3c | bellard | { |
503 | d7d02e3c | bellard | PITState *pit = &pit_state; |
504 | d7d02e3c | bellard | PITChannelState *s; |
505 | d7d02e3c | bellard | |
506 | d7d02e3c | bellard | s = &pit->channels[0];
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507 | d7d02e3c | bellard | /* the timer 0 is connected to an IRQ */
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508 | d7d02e3c | bellard | s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s); |
509 | d7d02e3c | bellard | s->irq = irq; |
510 | 80cabfad | bellard | |
511 | 5122b431 | Juan Quintela | vmstate_register(base, &vmstate_pit, pit); |
512 | a08d4367 | Jan Kiszka | qemu_register_reset(pit_reset, pit); |
513 | ec844b96 | bellard | register_ioport_write(base, 4, 1, pit_ioport_write, pit); |
514 | ec844b96 | bellard | register_ioport_read(base, 3, 1, pit_ioport_read, pit); |
515 | d7d02e3c | bellard | |
516 | d7d02e3c | bellard | pit_reset(pit); |
517 | d7d02e3c | bellard | |
518 | ec844b96 | bellard | return pit;
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519 | 80cabfad | bellard | } |