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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC translation
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
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6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 7a3f1944 | bellard | Lesser General Public License for more details.
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16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 7a3f1944 | bellard | */
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20 | 7a3f1944 | bellard | |
21 | 7a3f1944 | bellard | #include <stdarg.h> |
22 | 7a3f1944 | bellard | #include <stdlib.h> |
23 | 7a3f1944 | bellard | #include <stdio.h> |
24 | 7a3f1944 | bellard | #include <string.h> |
25 | 7a3f1944 | bellard | #include <inttypes.h> |
26 | 7a3f1944 | bellard | |
27 | 7a3f1944 | bellard | #include "cpu.h" |
28 | 7a3f1944 | bellard | #include "disas.h" |
29 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
30 | 57fec1fe | bellard | #include "tcg-op.h" |
31 | 7a3f1944 | bellard | |
32 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
33 | a7812ae4 | pbrook | #include "helper.h" |
34 | a7812ae4 | pbrook | |
35 | 7a3f1944 | bellard | #define DEBUG_DISAS
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36 | 7a3f1944 | bellard | |
37 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
38 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
39 | 72cbca10 | bellard | according to jump_pc[T2] */
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40 | 72cbca10 | bellard | |
41 | 1a2fb1c0 | blueswir1 | /* global register indexes */
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42 | a7812ae4 | pbrook | static TCGv_ptr cpu_env, cpu_regwptr;
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43 | 25517f99 | Paul Brook | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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44 | 25517f99 | Paul Brook | static TCGv_i32 cpu_cc_op;
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45 | a7812ae4 | pbrook | static TCGv_i32 cpu_psr;
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46 | a7812ae4 | pbrook | static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
47 | 255e1fcb | blueswir1 | static TCGv cpu_y;
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48 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
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49 | 255e1fcb | blueswir1 | static TCGv cpu_tbr;
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50 | 255e1fcb | blueswir1 | #endif
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51 | 5793f2a4 | Richard Henderson | static TCGv cpu_cond;
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52 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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53 | a7812ae4 | pbrook | static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
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54 | a7812ae4 | pbrook | static TCGv cpu_gsr;
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55 | 255e1fcb | blueswir1 | static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
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56 | a7812ae4 | pbrook | static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
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57 | a7812ae4 | pbrook | static TCGv_i32 cpu_softint;
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58 | 255e1fcb | blueswir1 | #else
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59 | 255e1fcb | blueswir1 | static TCGv cpu_wim;
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60 | dc99a3f2 | blueswir1 | #endif
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61 | 714547bb | blueswir1 | /* Floating point registers */
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62 | 30038fd8 | Richard Henderson | static TCGv_i64 cpu_fpr[TARGET_DPREGS];
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63 | 1a2fb1c0 | blueswir1 | |
64 | 1a7ff922 | Paolo Bonzini | static target_ulong gen_opc_npc[OPC_BUF_SIZE];
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65 | 1a7ff922 | Paolo Bonzini | static target_ulong gen_opc_jump_pc[2]; |
66 | 1a7ff922 | Paolo Bonzini | |
67 | 2e70f6ef | pbrook | #include "gen-icount.h" |
68 | 2e70f6ef | pbrook | |
69 | 7a3f1944 | bellard | typedef struct DisasContext { |
70 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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71 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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72 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
73 | cf495bcf | bellard | int is_br;
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74 | e8af50a3 | bellard | int mem_idx;
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75 | a80dde08 | bellard | int fpu_enabled;
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76 | 2cade6a3 | blueswir1 | int address_mask_32bit;
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77 | 060718c1 | Richard Henderson | int singlestep;
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78 | 8393617c | Blue Swirl | uint32_t cc_op; /* current CC operation */
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79 | cf495bcf | bellard | struct TranslationBlock *tb;
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80 | 5578ceab | blueswir1 | sparc_def_t *def; |
81 | 30038fd8 | Richard Henderson | TCGv_i32 t32[3];
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82 | 88023616 | Richard Henderson | TCGv ttl[5];
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83 | 30038fd8 | Richard Henderson | int n_t32;
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84 | 88023616 | Richard Henderson | int n_ttl;
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85 | 7a3f1944 | bellard | } DisasContext; |
86 | 7a3f1944 | bellard | |
87 | 416fcaea | Richard Henderson | typedef struct { |
88 | 416fcaea | Richard Henderson | TCGCond cond; |
89 | 416fcaea | Richard Henderson | bool is_bool;
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90 | 416fcaea | Richard Henderson | bool g1, g2;
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91 | 416fcaea | Richard Henderson | TCGv c1, c2; |
92 | 416fcaea | Richard Henderson | } DisasCompare; |
93 | 416fcaea | Richard Henderson | |
94 | 3475187d | bellard | // This function uses non-native bit order
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95 | dc1a6971 | Blue Swirl | #define GET_FIELD(X, FROM, TO) \
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96 | dc1a6971 | Blue Swirl | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
97 | 7a3f1944 | bellard | |
98 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
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99 | dc1a6971 | Blue Swirl | #define GET_FIELD_SP(X, FROM, TO) \
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100 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
101 | 3475187d | bellard | |
102 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
103 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
104 | 3475187d | bellard | |
105 | 3475187d | bellard | #ifdef TARGET_SPARC64
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106 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
107 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
108 | 3475187d | bellard | #else
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109 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
110 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
111 | 3475187d | bellard | #endif
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112 | 3475187d | bellard | |
113 | b158a785 | blueswir1 | #define UA2005_HTRAP_MASK 0xff |
114 | b158a785 | blueswir1 | #define V8_TRAP_MASK 0x7f |
115 | b158a785 | blueswir1 | |
116 | 3475187d | bellard | static int sign_extend(int x, int len) |
117 | 3475187d | bellard | { |
118 | 3475187d | bellard | len = 32 - len;
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119 | 3475187d | bellard | return (x << len) >> len;
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120 | 3475187d | bellard | } |
121 | 3475187d | bellard | |
122 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
123 | 7a3f1944 | bellard | |
124 | 2ae23e17 | Richard Henderson | static inline TCGv_i32 get_temp_i32(DisasContext *dc) |
125 | 2ae23e17 | Richard Henderson | { |
126 | 2ae23e17 | Richard Henderson | TCGv_i32 t; |
127 | 2ae23e17 | Richard Henderson | assert(dc->n_t32 < ARRAY_SIZE(dc->t32)); |
128 | 2ae23e17 | Richard Henderson | dc->t32[dc->n_t32++] = t = tcg_temp_new_i32(); |
129 | 2ae23e17 | Richard Henderson | return t;
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130 | 2ae23e17 | Richard Henderson | } |
131 | 2ae23e17 | Richard Henderson | |
132 | 2ae23e17 | Richard Henderson | static inline TCGv get_temp_tl(DisasContext *dc) |
133 | 2ae23e17 | Richard Henderson | { |
134 | 2ae23e17 | Richard Henderson | TCGv t; |
135 | 2ae23e17 | Richard Henderson | assert(dc->n_ttl < ARRAY_SIZE(dc->ttl)); |
136 | 2ae23e17 | Richard Henderson | dc->ttl[dc->n_ttl++] = t = tcg_temp_new(); |
137 | 2ae23e17 | Richard Henderson | return t;
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138 | 2ae23e17 | Richard Henderson | } |
139 | 2ae23e17 | Richard Henderson | |
140 | 141ae5c1 | Richard Henderson | static inline void gen_update_fprs_dirty(int rd) |
141 | 141ae5c1 | Richard Henderson | { |
142 | 141ae5c1 | Richard Henderson | #if defined(TARGET_SPARC64)
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143 | 141ae5c1 | Richard Henderson | tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2); |
144 | 141ae5c1 | Richard Henderson | #endif
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145 | 141ae5c1 | Richard Henderson | } |
146 | 141ae5c1 | Richard Henderson | |
147 | ff07ec83 | blueswir1 | /* floating point registers moves */
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148 | 208ae657 | Richard Henderson | static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) |
149 | 208ae657 | Richard Henderson | { |
150 | 30038fd8 | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 |
151 | 30038fd8 | Richard Henderson | if (src & 1) { |
152 | 30038fd8 | Richard Henderson | return TCGV_LOW(cpu_fpr[src / 2]); |
153 | 30038fd8 | Richard Henderson | } else {
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154 | 30038fd8 | Richard Henderson | return TCGV_HIGH(cpu_fpr[src / 2]); |
155 | 30038fd8 | Richard Henderson | } |
156 | 30038fd8 | Richard Henderson | #else
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157 | 30038fd8 | Richard Henderson | if (src & 1) { |
158 | 30038fd8 | Richard Henderson | return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2])); |
159 | 30038fd8 | Richard Henderson | } else {
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160 | 2ae23e17 | Richard Henderson | TCGv_i32 ret = get_temp_i32(dc); |
161 | 30038fd8 | Richard Henderson | TCGv_i64 t = tcg_temp_new_i64(); |
162 | 30038fd8 | Richard Henderson | |
163 | 30038fd8 | Richard Henderson | tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32); |
164 | 30038fd8 | Richard Henderson | tcg_gen_trunc_i64_i32(ret, t); |
165 | 30038fd8 | Richard Henderson | tcg_temp_free_i64(t); |
166 | 30038fd8 | Richard Henderson | |
167 | 30038fd8 | Richard Henderson | return ret;
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168 | 30038fd8 | Richard Henderson | } |
169 | 30038fd8 | Richard Henderson | #endif
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170 | 208ae657 | Richard Henderson | } |
171 | 208ae657 | Richard Henderson | |
172 | 208ae657 | Richard Henderson | static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) |
173 | 208ae657 | Richard Henderson | { |
174 | 30038fd8 | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 |
175 | 30038fd8 | Richard Henderson | if (dst & 1) { |
176 | 30038fd8 | Richard Henderson | tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
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177 | 30038fd8 | Richard Henderson | } else {
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178 | 30038fd8 | Richard Henderson | tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
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179 | 30038fd8 | Richard Henderson | } |
180 | 30038fd8 | Richard Henderson | #else
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181 | 30038fd8 | Richard Henderson | TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v)); |
182 | 30038fd8 | Richard Henderson | tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t, |
183 | 30038fd8 | Richard Henderson | (dst & 1 ? 0 : 32), 32); |
184 | 30038fd8 | Richard Henderson | #endif
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185 | 141ae5c1 | Richard Henderson | gen_update_fprs_dirty(dst); |
186 | 208ae657 | Richard Henderson | } |
187 | 208ae657 | Richard Henderson | |
188 | ba5f5179 | Richard Henderson | static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
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189 | 208ae657 | Richard Henderson | { |
190 | ba5f5179 | Richard Henderson | return get_temp_i32(dc);
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191 | 208ae657 | Richard Henderson | } |
192 | 208ae657 | Richard Henderson | |
193 | 96eda024 | Richard Henderson | static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) |
194 | 96eda024 | Richard Henderson | { |
195 | 96eda024 | Richard Henderson | src = DFPREG(src); |
196 | 30038fd8 | Richard Henderson | return cpu_fpr[src / 2]; |
197 | 96eda024 | Richard Henderson | } |
198 | 96eda024 | Richard Henderson | |
199 | 96eda024 | Richard Henderson | static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v) |
200 | 96eda024 | Richard Henderson | { |
201 | 96eda024 | Richard Henderson | dst = DFPREG(dst); |
202 | 30038fd8 | Richard Henderson | tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
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203 | 96eda024 | Richard Henderson | gen_update_fprs_dirty(dst); |
204 | 96eda024 | Richard Henderson | } |
205 | 96eda024 | Richard Henderson | |
206 | 3886b8a3 | Richard Henderson | static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst) |
207 | 96eda024 | Richard Henderson | { |
208 | 3886b8a3 | Richard Henderson | return cpu_fpr[DFPREG(dst) / 2]; |
209 | 96eda024 | Richard Henderson | } |
210 | 96eda024 | Richard Henderson | |
211 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT0(unsigned int src) |
212 | ff07ec83 | blueswir1 | { |
213 | 30038fd8 | Richard Henderson | tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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214 | 30038fd8 | Richard Henderson | offsetof(CPU_QuadU, ll.upper)); |
215 | 30038fd8 | Richard Henderson | tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) + |
216 | 30038fd8 | Richard Henderson | offsetof(CPU_QuadU, ll.lower)); |
217 | ff07ec83 | blueswir1 | } |
218 | ff07ec83 | blueswir1 | |
219 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT1(unsigned int src) |
220 | ff07ec83 | blueswir1 | { |
221 | 30038fd8 | Richard Henderson | tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
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222 | 30038fd8 | Richard Henderson | offsetof(CPU_QuadU, ll.upper)); |
223 | 30038fd8 | Richard Henderson | tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) + |
224 | 30038fd8 | Richard Henderson | offsetof(CPU_QuadU, ll.lower)); |
225 | ff07ec83 | blueswir1 | } |
226 | ff07ec83 | blueswir1 | |
227 | ff07ec83 | blueswir1 | static void gen_op_store_QT0_fpr(unsigned int dst) |
228 | ff07ec83 | blueswir1 | { |
229 | 30038fd8 | Richard Henderson | tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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230 | 30038fd8 | Richard Henderson | offsetof(CPU_QuadU, ll.upper)); |
231 | 30038fd8 | Richard Henderson | tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) + |
232 | 30038fd8 | Richard Henderson | offsetof(CPU_QuadU, ll.lower)); |
233 | ff07ec83 | blueswir1 | } |
234 | 1f587329 | blueswir1 | |
235 | ac11f776 | Richard Henderson | #ifdef TARGET_SPARC64
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236 | 30038fd8 | Richard Henderson | static void gen_move_Q(unsigned int rd, unsigned int rs) |
237 | ac11f776 | Richard Henderson | { |
238 | ac11f776 | Richard Henderson | rd = QFPREG(rd); |
239 | ac11f776 | Richard Henderson | rs = QFPREG(rs); |
240 | ac11f776 | Richard Henderson | |
241 | 30038fd8 | Richard Henderson | tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]); |
242 | 30038fd8 | Richard Henderson | tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]); |
243 | ac11f776 | Richard Henderson | gen_update_fprs_dirty(rd); |
244 | ac11f776 | Richard Henderson | } |
245 | ac11f776 | Richard Henderson | #endif
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246 | ac11f776 | Richard Henderson | |
247 | 81ad8ba2 | blueswir1 | /* moves */
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248 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
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249 | 3475187d | bellard | #define supervisor(dc) 0 |
250 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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251 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
252 | 81ad8ba2 | blueswir1 | #endif
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253 | 3475187d | bellard | #else
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254 | 2aae2b8e | Igor V. Kovalenko | #define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
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255 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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256 | 2aae2b8e | Igor V. Kovalenko | #define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
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257 | 6f27aba6 | blueswir1 | #else
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258 | 3475187d | bellard | #endif
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259 | 81ad8ba2 | blueswir1 | #endif
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260 | 81ad8ba2 | blueswir1 | |
261 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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262 | 2cade6a3 | blueswir1 | #ifndef TARGET_ABI32
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263 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) ((dc)->address_mask_32bit)
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264 | 1a2fb1c0 | blueswir1 | #else
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265 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) (1) |
266 | 2cade6a3 | blueswir1 | #endif
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267 | 1a2fb1c0 | blueswir1 | #endif
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268 | 3391c818 | blueswir1 | |
269 | 2cade6a3 | blueswir1 | static inline void gen_address_mask(DisasContext *dc, TCGv addr) |
270 | 2cade6a3 | blueswir1 | { |
271 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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272 | 2cade6a3 | blueswir1 | if (AM_CHECK(dc))
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273 | 2cade6a3 | blueswir1 | tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
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274 | 2cade6a3 | blueswir1 | #endif
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275 | 2cade6a3 | blueswir1 | } |
276 | 2cade6a3 | blueswir1 | |
277 | 88023616 | Richard Henderson | static inline TCGv gen_load_gpr(DisasContext *dc, int reg) |
278 | 88023616 | Richard Henderson | { |
279 | 88023616 | Richard Henderson | if (reg == 0 || reg >= 8) { |
280 | 88023616 | Richard Henderson | TCGv t = get_temp_tl(dc); |
281 | 88023616 | Richard Henderson | if (reg == 0) { |
282 | 88023616 | Richard Henderson | tcg_gen_movi_tl(t, 0);
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283 | 88023616 | Richard Henderson | } else {
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284 | 88023616 | Richard Henderson | tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
285 | 88023616 | Richard Henderson | } |
286 | 88023616 | Richard Henderson | return t;
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287 | 88023616 | Richard Henderson | } else {
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288 | 88023616 | Richard Henderson | return cpu_gregs[reg];
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289 | 88023616 | Richard Henderson | } |
290 | 88023616 | Richard Henderson | } |
291 | 88023616 | Richard Henderson | |
292 | 88023616 | Richard Henderson | static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v) |
293 | 88023616 | Richard Henderson | { |
294 | 88023616 | Richard Henderson | if (reg > 0) { |
295 | 88023616 | Richard Henderson | if (reg < 8) { |
296 | 88023616 | Richard Henderson | tcg_gen_mov_tl(cpu_gregs[reg], v); |
297 | 88023616 | Richard Henderson | } else {
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298 | 88023616 | Richard Henderson | tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
299 | 88023616 | Richard Henderson | } |
300 | 88023616 | Richard Henderson | } |
301 | 88023616 | Richard Henderson | } |
302 | 88023616 | Richard Henderson | |
303 | 88023616 | Richard Henderson | static inline TCGv gen_dest_gpr(DisasContext *dc, int reg) |
304 | 88023616 | Richard Henderson | { |
305 | 88023616 | Richard Henderson | if (reg == 0 || reg >= 8) { |
306 | 88023616 | Richard Henderson | return get_temp_tl(dc);
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307 | 88023616 | Richard Henderson | } else {
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308 | 88023616 | Richard Henderson | return cpu_gregs[reg];
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309 | 88023616 | Richard Henderson | } |
310 | 88023616 | Richard Henderson | } |
311 | 88023616 | Richard Henderson | |
312 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
313 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
314 | 6e256c93 | bellard | { |
315 | 6e256c93 | bellard | TranslationBlock *tb; |
316 | 6e256c93 | bellard | |
317 | 6e256c93 | bellard | tb = s->tb; |
318 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
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319 | 060718c1 | Richard Henderson | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && |
320 | 060718c1 | Richard Henderson | !s->singlestep) { |
321 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
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322 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
323 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
324 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
325 | 4b4a72e5 | Stefan Weil | tcg_gen_exit_tb((tcg_target_long)tb + tb_num); |
326 | 6e256c93 | bellard | } else {
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327 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
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328 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
329 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
330 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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331 | 6e256c93 | bellard | } |
332 | 6e256c93 | bellard | } |
333 | 6e256c93 | bellard | |
334 | 19f329ad | blueswir1 | // XXX suboptimal
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335 | a7812ae4 | pbrook | static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src) |
336 | 19f329ad | blueswir1 | { |
337 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
338 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
339 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
340 | 19f329ad | blueswir1 | } |
341 | 19f329ad | blueswir1 | |
342 | a7812ae4 | pbrook | static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) |
343 | 19f329ad | blueswir1 | { |
344 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
345 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
346 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
347 | 19f329ad | blueswir1 | } |
348 | 19f329ad | blueswir1 | |
349 | a7812ae4 | pbrook | static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src) |
350 | 19f329ad | blueswir1 | { |
351 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
352 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
353 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
354 | 19f329ad | blueswir1 | } |
355 | 19f329ad | blueswir1 | |
356 | a7812ae4 | pbrook | static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) |
357 | 19f329ad | blueswir1 | { |
358 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
359 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
360 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
361 | 19f329ad | blueswir1 | } |
362 | 19f329ad | blueswir1 | |
363 | 41d72852 | Blue Swirl | static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2) |
364 | 41d72852 | Blue Swirl | { |
365 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
366 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
367 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2); |
368 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
369 | 41d72852 | Blue Swirl | } |
370 | 41d72852 | Blue Swirl | |
371 | 4af984a7 | blueswir1 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
372 | dc99a3f2 | blueswir1 | { |
373 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
374 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
375 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
376 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
377 | 41d72852 | Blue Swirl | } |
378 | 41d72852 | Blue Swirl | |
379 | 70c48285 | Richard Henderson | static TCGv_i32 gen_add32_carry32(void) |
380 | dc99a3f2 | blueswir1 | { |
381 | 70c48285 | Richard Henderson | TCGv_i32 carry_32, cc_src1_32, cc_src2_32; |
382 | 70c48285 | Richard Henderson | |
383 | 70c48285 | Richard Henderson | /* Carry is computed from a previous add: (dst < src) */
|
384 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
385 | 70c48285 | Richard Henderson | cc_src1_32 = tcg_temp_new_i32(); |
386 | 70c48285 | Richard Henderson | cc_src2_32 = tcg_temp_new_i32(); |
387 | 70c48285 | Richard Henderson | tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_dst); |
388 | 70c48285 | Richard Henderson | tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src); |
389 | 70c48285 | Richard Henderson | #else
|
390 | 70c48285 | Richard Henderson | cc_src1_32 = cpu_cc_dst; |
391 | 70c48285 | Richard Henderson | cc_src2_32 = cpu_cc_src; |
392 | 70c48285 | Richard Henderson | #endif
|
393 | 70c48285 | Richard Henderson | |
394 | 70c48285 | Richard Henderson | carry_32 = tcg_temp_new_i32(); |
395 | 70c48285 | Richard Henderson | tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); |
396 | 70c48285 | Richard Henderson | |
397 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
398 | 70c48285 | Richard Henderson | tcg_temp_free_i32(cc_src1_32); |
399 | 70c48285 | Richard Henderson | tcg_temp_free_i32(cc_src2_32); |
400 | 70c48285 | Richard Henderson | #endif
|
401 | 70c48285 | Richard Henderson | |
402 | 70c48285 | Richard Henderson | return carry_32;
|
403 | 41d72852 | Blue Swirl | } |
404 | 41d72852 | Blue Swirl | |
405 | 70c48285 | Richard Henderson | static TCGv_i32 gen_sub32_carry32(void) |
406 | 41d72852 | Blue Swirl | { |
407 | 70c48285 | Richard Henderson | TCGv_i32 carry_32, cc_src1_32, cc_src2_32; |
408 | 70c48285 | Richard Henderson | |
409 | 70c48285 | Richard Henderson | /* Carry is computed from a previous borrow: (src1 < src2) */
|
410 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
411 | 70c48285 | Richard Henderson | cc_src1_32 = tcg_temp_new_i32(); |
412 | 70c48285 | Richard Henderson | cc_src2_32 = tcg_temp_new_i32(); |
413 | 70c48285 | Richard Henderson | tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_src); |
414 | 70c48285 | Richard Henderson | tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src2); |
415 | 70c48285 | Richard Henderson | #else
|
416 | 70c48285 | Richard Henderson | cc_src1_32 = cpu_cc_src; |
417 | 70c48285 | Richard Henderson | cc_src2_32 = cpu_cc_src2; |
418 | 70c48285 | Richard Henderson | #endif
|
419 | 70c48285 | Richard Henderson | |
420 | 70c48285 | Richard Henderson | carry_32 = tcg_temp_new_i32(); |
421 | 70c48285 | Richard Henderson | tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); |
422 | 70c48285 | Richard Henderson | |
423 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
424 | 70c48285 | Richard Henderson | tcg_temp_free_i32(cc_src1_32); |
425 | 70c48285 | Richard Henderson | tcg_temp_free_i32(cc_src2_32); |
426 | 70c48285 | Richard Henderson | #endif
|
427 | 70c48285 | Richard Henderson | |
428 | 70c48285 | Richard Henderson | return carry_32;
|
429 | 70c48285 | Richard Henderson | } |
430 | 70c48285 | Richard Henderson | |
431 | 70c48285 | Richard Henderson | static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1, |
432 | 70c48285 | Richard Henderson | TCGv src2, int update_cc)
|
433 | 70c48285 | Richard Henderson | { |
434 | 70c48285 | Richard Henderson | TCGv_i32 carry_32; |
435 | 70c48285 | Richard Henderson | TCGv carry; |
436 | 70c48285 | Richard Henderson | |
437 | 70c48285 | Richard Henderson | switch (dc->cc_op) {
|
438 | 70c48285 | Richard Henderson | case CC_OP_DIV:
|
439 | 70c48285 | Richard Henderson | case CC_OP_LOGIC:
|
440 | 70c48285 | Richard Henderson | /* Carry is known to be zero. Fall back to plain ADD. */
|
441 | 70c48285 | Richard Henderson | if (update_cc) {
|
442 | 70c48285 | Richard Henderson | gen_op_add_cc(dst, src1, src2); |
443 | 70c48285 | Richard Henderson | } else {
|
444 | 70c48285 | Richard Henderson | tcg_gen_add_tl(dst, src1, src2); |
445 | 70c48285 | Richard Henderson | } |
446 | 70c48285 | Richard Henderson | return;
|
447 | 70c48285 | Richard Henderson | |
448 | 70c48285 | Richard Henderson | case CC_OP_ADD:
|
449 | 70c48285 | Richard Henderson | case CC_OP_TADD:
|
450 | 70c48285 | Richard Henderson | case CC_OP_TADDTV:
|
451 | 70c48285 | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32 |
452 | 70c48285 | Richard Henderson | { |
453 | 70c48285 | Richard Henderson | /* For 32-bit hosts, we can re-use the host's hardware carry
|
454 | 70c48285 | Richard Henderson | generation by using an ADD2 opcode. We discard the low
|
455 | 70c48285 | Richard Henderson | part of the output. Ideally we'd combine this operation
|
456 | 70c48285 | Richard Henderson | with the add that generated the carry in the first place. */
|
457 | 70c48285 | Richard Henderson | TCGv dst_low = tcg_temp_new(); |
458 | 70c48285 | Richard Henderson | tcg_gen_op6_i32(INDEX_op_add2_i32, dst_low, dst, |
459 | 70c48285 | Richard Henderson | cpu_cc_src, src1, cpu_cc_src2, src2); |
460 | 70c48285 | Richard Henderson | tcg_temp_free(dst_low); |
461 | 70c48285 | Richard Henderson | goto add_done;
|
462 | 70c48285 | Richard Henderson | } |
463 | 70c48285 | Richard Henderson | #endif
|
464 | 70c48285 | Richard Henderson | carry_32 = gen_add32_carry32(); |
465 | 70c48285 | Richard Henderson | break;
|
466 | 70c48285 | Richard Henderson | |
467 | 70c48285 | Richard Henderson | case CC_OP_SUB:
|
468 | 70c48285 | Richard Henderson | case CC_OP_TSUB:
|
469 | 70c48285 | Richard Henderson | case CC_OP_TSUBTV:
|
470 | 70c48285 | Richard Henderson | carry_32 = gen_sub32_carry32(); |
471 | 70c48285 | Richard Henderson | break;
|
472 | 70c48285 | Richard Henderson | |
473 | 70c48285 | Richard Henderson | default:
|
474 | 70c48285 | Richard Henderson | /* We need external help to produce the carry. */
|
475 | 70c48285 | Richard Henderson | carry_32 = tcg_temp_new_i32(); |
476 | 2ffd9176 | Blue Swirl | gen_helper_compute_C_icc(carry_32, cpu_env); |
477 | 70c48285 | Richard Henderson | break;
|
478 | 70c48285 | Richard Henderson | } |
479 | 70c48285 | Richard Henderson | |
480 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
481 | 70c48285 | Richard Henderson | carry = tcg_temp_new(); |
482 | 70c48285 | Richard Henderson | tcg_gen_extu_i32_i64(carry, carry_32); |
483 | 70c48285 | Richard Henderson | #else
|
484 | 70c48285 | Richard Henderson | carry = carry_32; |
485 | 70c48285 | Richard Henderson | #endif
|
486 | 70c48285 | Richard Henderson | |
487 | 70c48285 | Richard Henderson | tcg_gen_add_tl(dst, src1, src2); |
488 | 70c48285 | Richard Henderson | tcg_gen_add_tl(dst, dst, carry); |
489 | 70c48285 | Richard Henderson | |
490 | 70c48285 | Richard Henderson | tcg_temp_free_i32(carry_32); |
491 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
492 | 70c48285 | Richard Henderson | tcg_temp_free(carry); |
493 | 70c48285 | Richard Henderson | #endif
|
494 | 70c48285 | Richard Henderson | |
495 | 70c48285 | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32 |
496 | 70c48285 | Richard Henderson | add_done:
|
497 | 70c48285 | Richard Henderson | #endif
|
498 | 70c48285 | Richard Henderson | if (update_cc) {
|
499 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_src, src1); |
500 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_src2, src2); |
501 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_dst, dst); |
502 | 70c48285 | Richard Henderson | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); |
503 | 70c48285 | Richard Henderson | dc->cc_op = CC_OP_ADDX; |
504 | 70c48285 | Richard Henderson | } |
505 | dc99a3f2 | blueswir1 | } |
506 | dc99a3f2 | blueswir1 | |
507 | d4b0d468 | Blue Swirl | static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc) |
508 | 41d72852 | Blue Swirl | { |
509 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
510 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
511 | 719f66a7 | Blue Swirl | if (src2 == 0) { |
512 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, src1); |
513 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
514 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
515 | 719f66a7 | Blue Swirl | } else {
|
516 | 719f66a7 | Blue Swirl | tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2); |
517 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
518 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_SUB; |
519 | 719f66a7 | Blue Swirl | } |
520 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
521 | 41d72852 | Blue Swirl | } |
522 | 41d72852 | Blue Swirl | |
523 | 41d72852 | Blue Swirl | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
524 | dc99a3f2 | blueswir1 | { |
525 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
526 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
527 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
528 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
529 | 41d72852 | Blue Swirl | } |
530 | 41d72852 | Blue Swirl | |
531 | 70c48285 | Richard Henderson | static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1, |
532 | 70c48285 | Richard Henderson | TCGv src2, int update_cc)
|
533 | 41d72852 | Blue Swirl | { |
534 | 70c48285 | Richard Henderson | TCGv_i32 carry_32; |
535 | 70c48285 | Richard Henderson | TCGv carry; |
536 | 41d72852 | Blue Swirl | |
537 | 70c48285 | Richard Henderson | switch (dc->cc_op) {
|
538 | 70c48285 | Richard Henderson | case CC_OP_DIV:
|
539 | 70c48285 | Richard Henderson | case CC_OP_LOGIC:
|
540 | 70c48285 | Richard Henderson | /* Carry is known to be zero. Fall back to plain SUB. */
|
541 | 70c48285 | Richard Henderson | if (update_cc) {
|
542 | 70c48285 | Richard Henderson | gen_op_sub_cc(dst, src1, src2); |
543 | 70c48285 | Richard Henderson | } else {
|
544 | 70c48285 | Richard Henderson | tcg_gen_sub_tl(dst, src1, src2); |
545 | 70c48285 | Richard Henderson | } |
546 | 70c48285 | Richard Henderson | return;
|
547 | 70c48285 | Richard Henderson | |
548 | 70c48285 | Richard Henderson | case CC_OP_ADD:
|
549 | 70c48285 | Richard Henderson | case CC_OP_TADD:
|
550 | 70c48285 | Richard Henderson | case CC_OP_TADDTV:
|
551 | 70c48285 | Richard Henderson | carry_32 = gen_add32_carry32(); |
552 | 70c48285 | Richard Henderson | break;
|
553 | 70c48285 | Richard Henderson | |
554 | 70c48285 | Richard Henderson | case CC_OP_SUB:
|
555 | 70c48285 | Richard Henderson | case CC_OP_TSUB:
|
556 | 70c48285 | Richard Henderson | case CC_OP_TSUBTV:
|
557 | 70c48285 | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32 |
558 | 70c48285 | Richard Henderson | { |
559 | 70c48285 | Richard Henderson | /* For 32-bit hosts, we can re-use the host's hardware carry
|
560 | 70c48285 | Richard Henderson | generation by using a SUB2 opcode. We discard the low
|
561 | 70c48285 | Richard Henderson | part of the output. Ideally we'd combine this operation
|
562 | 70c48285 | Richard Henderson | with the add that generated the carry in the first place. */
|
563 | 70c48285 | Richard Henderson | TCGv dst_low = tcg_temp_new(); |
564 | 70c48285 | Richard Henderson | tcg_gen_op6_i32(INDEX_op_sub2_i32, dst_low, dst, |
565 | 70c48285 | Richard Henderson | cpu_cc_src, src1, cpu_cc_src2, src2); |
566 | 70c48285 | Richard Henderson | tcg_temp_free(dst_low); |
567 | 70c48285 | Richard Henderson | goto sub_done;
|
568 | 70c48285 | Richard Henderson | } |
569 | 70c48285 | Richard Henderson | #endif
|
570 | 70c48285 | Richard Henderson | carry_32 = gen_sub32_carry32(); |
571 | 70c48285 | Richard Henderson | break;
|
572 | 70c48285 | Richard Henderson | |
573 | 70c48285 | Richard Henderson | default:
|
574 | 70c48285 | Richard Henderson | /* We need external help to produce the carry. */
|
575 | 70c48285 | Richard Henderson | carry_32 = tcg_temp_new_i32(); |
576 | 2ffd9176 | Blue Swirl | gen_helper_compute_C_icc(carry_32, cpu_env); |
577 | 70c48285 | Richard Henderson | break;
|
578 | 70c48285 | Richard Henderson | } |
579 | 70c48285 | Richard Henderson | |
580 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
581 | 70c48285 | Richard Henderson | carry = tcg_temp_new(); |
582 | 70c48285 | Richard Henderson | tcg_gen_extu_i32_i64(carry, carry_32); |
583 | 70c48285 | Richard Henderson | #else
|
584 | 70c48285 | Richard Henderson | carry = carry_32; |
585 | 70c48285 | Richard Henderson | #endif
|
586 | 70c48285 | Richard Henderson | |
587 | 70c48285 | Richard Henderson | tcg_gen_sub_tl(dst, src1, src2); |
588 | 70c48285 | Richard Henderson | tcg_gen_sub_tl(dst, dst, carry); |
589 | 70c48285 | Richard Henderson | |
590 | 70c48285 | Richard Henderson | tcg_temp_free_i32(carry_32); |
591 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
592 | 70c48285 | Richard Henderson | tcg_temp_free(carry); |
593 | 70c48285 | Richard Henderson | #endif
|
594 | 70c48285 | Richard Henderson | |
595 | 70c48285 | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32 |
596 | 70c48285 | Richard Henderson | sub_done:
|
597 | 70c48285 | Richard Henderson | #endif
|
598 | 70c48285 | Richard Henderson | if (update_cc) {
|
599 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_src, src1); |
600 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_src2, src2); |
601 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_dst, dst); |
602 | 70c48285 | Richard Henderson | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); |
603 | 70c48285 | Richard Henderson | dc->cc_op = CC_OP_SUBX; |
604 | 70c48285 | Richard Henderson | } |
605 | dc99a3f2 | blueswir1 | } |
606 | dc99a3f2 | blueswir1 | |
607 | 4af984a7 | blueswir1 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
608 | d9bdab86 | blueswir1 | { |
609 | de9e9d9f | Richard Henderson | TCGv r_temp, zero, t0; |
610 | d9bdab86 | blueswir1 | |
611 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
612 | de9e9d9f | Richard Henderson | t0 = tcg_temp_new(); |
613 | d9bdab86 | blueswir1 | |
614 | d9bdab86 | blueswir1 | /* old op:
|
615 | d9bdab86 | blueswir1 | if (!(env->y & 1))
|
616 | d9bdab86 | blueswir1 | T1 = 0;
|
617 | d9bdab86 | blueswir1 | */
|
618 | 6cb675b0 | Richard Henderson | zero = tcg_const_tl(0);
|
619 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
|
620 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
|
621 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
|
622 | 6cb675b0 | Richard Henderson | tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero, |
623 | 6cb675b0 | Richard Henderson | zero, cpu_cc_src2); |
624 | 6cb675b0 | Richard Henderson | tcg_temp_free(zero); |
625 | d9bdab86 | blueswir1 | |
626 | d9bdab86 | blueswir1 | // b2 = T0 & 1;
|
627 | d9bdab86 | blueswir1 | // env->y = (b2 << 31) | (env->y >> 1);
|
628 | 105a1f04 | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
|
629 | 105a1f04 | blueswir1 | tcg_gen_shli_tl(r_temp, r_temp, 31);
|
630 | de9e9d9f | Richard Henderson | tcg_gen_shri_tl(t0, cpu_y, 1);
|
631 | de9e9d9f | Richard Henderson | tcg_gen_andi_tl(t0, t0, 0x7fffffff);
|
632 | de9e9d9f | Richard Henderson | tcg_gen_or_tl(t0, t0, r_temp); |
633 | de9e9d9f | Richard Henderson | tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
|
634 | d9bdab86 | blueswir1 | |
635 | d9bdab86 | blueswir1 | // b1 = N ^ V;
|
636 | de9e9d9f | Richard Henderson | gen_mov_reg_N(t0, cpu_psr); |
637 | d9bdab86 | blueswir1 | gen_mov_reg_V(r_temp, cpu_psr); |
638 | de9e9d9f | Richard Henderson | tcg_gen_xor_tl(t0, t0, r_temp); |
639 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
640 | d9bdab86 | blueswir1 | |
641 | d9bdab86 | blueswir1 | // T0 = (b1 << 31) | (T0 >> 1);
|
642 | d9bdab86 | blueswir1 | // src1 = T0;
|
643 | de9e9d9f | Richard Henderson | tcg_gen_shli_tl(t0, t0, 31);
|
644 | 6f551262 | blueswir1 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
|
645 | de9e9d9f | Richard Henderson | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); |
646 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
647 | d9bdab86 | blueswir1 | |
648 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
649 | d9bdab86 | blueswir1 | |
650 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
651 | d9bdab86 | blueswir1 | } |
652 | d9bdab86 | blueswir1 | |
653 | fb170183 | Igor V. Kovalenko | static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext) |
654 | 8879d139 | blueswir1 | { |
655 | fb170183 | Igor V. Kovalenko | TCGv_i32 r_src1, r_src2; |
656 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
657 | 8879d139 | blueswir1 | |
658 | fb170183 | Igor V. Kovalenko | r_src1 = tcg_temp_new_i32(); |
659 | fb170183 | Igor V. Kovalenko | r_src2 = tcg_temp_new_i32(); |
660 | fb170183 | Igor V. Kovalenko | |
661 | fb170183 | Igor V. Kovalenko | tcg_gen_trunc_tl_i32(r_src1, src1); |
662 | fb170183 | Igor V. Kovalenko | tcg_gen_trunc_tl_i32(r_src2, src2); |
663 | fb170183 | Igor V. Kovalenko | |
664 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
665 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
666 | 8879d139 | blueswir1 | |
667 | fb170183 | Igor V. Kovalenko | if (sign_ext) {
|
668 | fb170183 | Igor V. Kovalenko | tcg_gen_ext_i32_i64(r_temp, r_src2); |
669 | fb170183 | Igor V. Kovalenko | tcg_gen_ext_i32_i64(r_temp2, r_src1); |
670 | fb170183 | Igor V. Kovalenko | } else {
|
671 | fb170183 | Igor V. Kovalenko | tcg_gen_extu_i32_i64(r_temp, r_src2); |
672 | fb170183 | Igor V. Kovalenko | tcg_gen_extu_i32_i64(r_temp2, r_src1); |
673 | fb170183 | Igor V. Kovalenko | } |
674 | fb170183 | Igor V. Kovalenko | |
675 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
676 | 8879d139 | blueswir1 | |
677 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
678 | de9e9d9f | Richard Henderson | tcg_gen_trunc_i64_tl(cpu_y, r_temp); |
679 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
680 | de9e9d9f | Richard Henderson | tcg_gen_andi_tl(cpu_y, cpu_y, 0xffffffff);
|
681 | fb170183 | Igor V. Kovalenko | |
682 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
683 | fb170183 | Igor V. Kovalenko | |
684 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
685 | fb170183 | Igor V. Kovalenko | |
686 | fb170183 | Igor V. Kovalenko | tcg_temp_free_i32(r_src1); |
687 | fb170183 | Igor V. Kovalenko | tcg_temp_free_i32(r_src2); |
688 | 8879d139 | blueswir1 | } |
689 | 8879d139 | blueswir1 | |
690 | fb170183 | Igor V. Kovalenko | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
691 | 8879d139 | blueswir1 | { |
692 | fb170183 | Igor V. Kovalenko | /* zero-extend truncated operands before multiplication */
|
693 | fb170183 | Igor V. Kovalenko | gen_op_multiply(dst, src1, src2, 0);
|
694 | fb170183 | Igor V. Kovalenko | } |
695 | 8879d139 | blueswir1 | |
696 | fb170183 | Igor V. Kovalenko | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
697 | fb170183 | Igor V. Kovalenko | { |
698 | fb170183 | Igor V. Kovalenko | /* sign-extend truncated operands before multiplication */
|
699 | fb170183 | Igor V. Kovalenko | gen_op_multiply(dst, src1, src2, 1);
|
700 | 8879d139 | blueswir1 | } |
701 | 8879d139 | blueswir1 | |
702 | 19f329ad | blueswir1 | // 1
|
703 | 19f329ad | blueswir1 | static inline void gen_op_eval_ba(TCGv dst) |
704 | 19f329ad | blueswir1 | { |
705 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 1);
|
706 | 19f329ad | blueswir1 | } |
707 | 19f329ad | blueswir1 | |
708 | 19f329ad | blueswir1 | // Z
|
709 | a7812ae4 | pbrook | static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src) |
710 | 19f329ad | blueswir1 | { |
711 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
712 | 19f329ad | blueswir1 | } |
713 | 19f329ad | blueswir1 | |
714 | 19f329ad | blueswir1 | // Z | (N ^ V)
|
715 | a7812ae4 | pbrook | static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src) |
716 | 19f329ad | blueswir1 | { |
717 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
718 | de9e9d9f | Richard Henderson | gen_mov_reg_N(t0, src); |
719 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
720 | de9e9d9f | Richard Henderson | tcg_gen_xor_tl(dst, dst, t0); |
721 | de9e9d9f | Richard Henderson | gen_mov_reg_Z(t0, src); |
722 | de9e9d9f | Richard Henderson | tcg_gen_or_tl(dst, dst, t0); |
723 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
724 | 19f329ad | blueswir1 | } |
725 | 19f329ad | blueswir1 | |
726 | 19f329ad | blueswir1 | // N ^ V
|
727 | a7812ae4 | pbrook | static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src) |
728 | 19f329ad | blueswir1 | { |
729 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
730 | de9e9d9f | Richard Henderson | gen_mov_reg_V(t0, src); |
731 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
732 | de9e9d9f | Richard Henderson | tcg_gen_xor_tl(dst, dst, t0); |
733 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
734 | 19f329ad | blueswir1 | } |
735 | 19f329ad | blueswir1 | |
736 | 19f329ad | blueswir1 | // C | Z
|
737 | a7812ae4 | pbrook | static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) |
738 | 19f329ad | blueswir1 | { |
739 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
740 | de9e9d9f | Richard Henderson | gen_mov_reg_Z(t0, src); |
741 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
742 | de9e9d9f | Richard Henderson | tcg_gen_or_tl(dst, dst, t0); |
743 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
744 | 19f329ad | blueswir1 | } |
745 | 19f329ad | blueswir1 | |
746 | 19f329ad | blueswir1 | // C
|
747 | a7812ae4 | pbrook | static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) |
748 | 19f329ad | blueswir1 | { |
749 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
750 | 19f329ad | blueswir1 | } |
751 | 19f329ad | blueswir1 | |
752 | 19f329ad | blueswir1 | // V
|
753 | a7812ae4 | pbrook | static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) |
754 | 19f329ad | blueswir1 | { |
755 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
756 | 19f329ad | blueswir1 | } |
757 | 19f329ad | blueswir1 | |
758 | 19f329ad | blueswir1 | // 0
|
759 | 19f329ad | blueswir1 | static inline void gen_op_eval_bn(TCGv dst) |
760 | 19f329ad | blueswir1 | { |
761 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 0);
|
762 | 19f329ad | blueswir1 | } |
763 | 19f329ad | blueswir1 | |
764 | 19f329ad | blueswir1 | // N
|
765 | a7812ae4 | pbrook | static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) |
766 | 19f329ad | blueswir1 | { |
767 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
768 | 19f329ad | blueswir1 | } |
769 | 19f329ad | blueswir1 | |
770 | 19f329ad | blueswir1 | // !Z
|
771 | a7812ae4 | pbrook | static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src) |
772 | 19f329ad | blueswir1 | { |
773 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
774 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
775 | 19f329ad | blueswir1 | } |
776 | 19f329ad | blueswir1 | |
777 | 19f329ad | blueswir1 | // !(Z | (N ^ V))
|
778 | a7812ae4 | pbrook | static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src) |
779 | 19f329ad | blueswir1 | { |
780 | de9e9d9f | Richard Henderson | gen_op_eval_ble(dst, src); |
781 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
782 | 19f329ad | blueswir1 | } |
783 | 19f329ad | blueswir1 | |
784 | 19f329ad | blueswir1 | // !(N ^ V)
|
785 | a7812ae4 | pbrook | static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src) |
786 | 19f329ad | blueswir1 | { |
787 | de9e9d9f | Richard Henderson | gen_op_eval_bl(dst, src); |
788 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
789 | 19f329ad | blueswir1 | } |
790 | 19f329ad | blueswir1 | |
791 | 19f329ad | blueswir1 | // !(C | Z)
|
792 | a7812ae4 | pbrook | static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) |
793 | 19f329ad | blueswir1 | { |
794 | de9e9d9f | Richard Henderson | gen_op_eval_bleu(dst, src); |
795 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
796 | 19f329ad | blueswir1 | } |
797 | 19f329ad | blueswir1 | |
798 | 19f329ad | blueswir1 | // !C
|
799 | a7812ae4 | pbrook | static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) |
800 | 19f329ad | blueswir1 | { |
801 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
802 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
803 | 19f329ad | blueswir1 | } |
804 | 19f329ad | blueswir1 | |
805 | 19f329ad | blueswir1 | // !N
|
806 | a7812ae4 | pbrook | static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) |
807 | 19f329ad | blueswir1 | { |
808 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
809 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
810 | 19f329ad | blueswir1 | } |
811 | 19f329ad | blueswir1 | |
812 | 19f329ad | blueswir1 | // !V
|
813 | a7812ae4 | pbrook | static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) |
814 | 19f329ad | blueswir1 | { |
815 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
816 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
817 | 19f329ad | blueswir1 | } |
818 | 19f329ad | blueswir1 | |
819 | 19f329ad | blueswir1 | /*
|
820 | 19f329ad | blueswir1 | FPSR bit field FCC1 | FCC0:
|
821 | 19f329ad | blueswir1 | 0 =
|
822 | 19f329ad | blueswir1 | 1 <
|
823 | 19f329ad | blueswir1 | 2 >
|
824 | 19f329ad | blueswir1 | 3 unordered
|
825 | 19f329ad | blueswir1 | */
|
826 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, |
827 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
828 | 19f329ad | blueswir1 | { |
829 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); |
830 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
831 | 19f329ad | blueswir1 | } |
832 | 19f329ad | blueswir1 | |
833 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, |
834 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
835 | 19f329ad | blueswir1 | { |
836 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); |
837 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
838 | 19f329ad | blueswir1 | } |
839 | 19f329ad | blueswir1 | |
840 | 19f329ad | blueswir1 | // !0: FCC0 | FCC1
|
841 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, |
842 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
843 | 19f329ad | blueswir1 | { |
844 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
845 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
846 | de9e9d9f | Richard Henderson | gen_mov_reg_FCC1(t0, src, fcc_offset); |
847 | de9e9d9f | Richard Henderson | tcg_gen_or_tl(dst, dst, t0); |
848 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
849 | 19f329ad | blueswir1 | } |
850 | 19f329ad | blueswir1 | |
851 | 19f329ad | blueswir1 | // 1 or 2: FCC0 ^ FCC1
|
852 | 19f329ad | blueswir1 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, |
853 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
854 | 19f329ad | blueswir1 | { |
855 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
856 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
857 | de9e9d9f | Richard Henderson | gen_mov_reg_FCC1(t0, src, fcc_offset); |
858 | de9e9d9f | Richard Henderson | tcg_gen_xor_tl(dst, dst, t0); |
859 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
860 | 19f329ad | blueswir1 | } |
861 | 19f329ad | blueswir1 | |
862 | 19f329ad | blueswir1 | // 1 or 3: FCC0
|
863 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, |
864 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
865 | 19f329ad | blueswir1 | { |
866 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
867 | 19f329ad | blueswir1 | } |
868 | 19f329ad | blueswir1 | |
869 | 19f329ad | blueswir1 | // 1: FCC0 & !FCC1
|
870 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, |
871 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
872 | 19f329ad | blueswir1 | { |
873 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
874 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
875 | de9e9d9f | Richard Henderson | gen_mov_reg_FCC1(t0, src, fcc_offset); |
876 | de9e9d9f | Richard Henderson | tcg_gen_andc_tl(dst, dst, t0); |
877 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
878 | 19f329ad | blueswir1 | } |
879 | 19f329ad | blueswir1 | |
880 | 19f329ad | blueswir1 | // 2 or 3: FCC1
|
881 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, |
882 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
883 | 19f329ad | blueswir1 | { |
884 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
885 | 19f329ad | blueswir1 | } |
886 | 19f329ad | blueswir1 | |
887 | 19f329ad | blueswir1 | // 2: !FCC0 & FCC1
|
888 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, |
889 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
890 | 19f329ad | blueswir1 | { |
891 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
892 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
893 | de9e9d9f | Richard Henderson | gen_mov_reg_FCC1(t0, src, fcc_offset); |
894 | de9e9d9f | Richard Henderson | tcg_gen_andc_tl(dst, t0, dst); |
895 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
896 | 19f329ad | blueswir1 | } |
897 | 19f329ad | blueswir1 | |
898 | 19f329ad | blueswir1 | // 3: FCC0 & FCC1
|
899 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, |
900 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
901 | 19f329ad | blueswir1 | { |
902 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
903 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
904 | de9e9d9f | Richard Henderson | gen_mov_reg_FCC1(t0, src, fcc_offset); |
905 | de9e9d9f | Richard Henderson | tcg_gen_and_tl(dst, dst, t0); |
906 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
907 | 19f329ad | blueswir1 | } |
908 | 19f329ad | blueswir1 | |
909 | 19f329ad | blueswir1 | // 0: !(FCC0 | FCC1)
|
910 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, |
911 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
912 | 19f329ad | blueswir1 | { |
913 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
914 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
915 | de9e9d9f | Richard Henderson | gen_mov_reg_FCC1(t0, src, fcc_offset); |
916 | de9e9d9f | Richard Henderson | tcg_gen_or_tl(dst, dst, t0); |
917 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
918 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
919 | 19f329ad | blueswir1 | } |
920 | 19f329ad | blueswir1 | |
921 | 19f329ad | blueswir1 | // 0 or 3: !(FCC0 ^ FCC1)
|
922 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, |
923 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
924 | 19f329ad | blueswir1 | { |
925 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
926 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
927 | de9e9d9f | Richard Henderson | gen_mov_reg_FCC1(t0, src, fcc_offset); |
928 | de9e9d9f | Richard Henderson | tcg_gen_xor_tl(dst, dst, t0); |
929 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
930 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
931 | 19f329ad | blueswir1 | } |
932 | 19f329ad | blueswir1 | |
933 | 19f329ad | blueswir1 | // 0 or 2: !FCC0
|
934 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, |
935 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
936 | 19f329ad | blueswir1 | { |
937 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
938 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
939 | 19f329ad | blueswir1 | } |
940 | 19f329ad | blueswir1 | |
941 | 19f329ad | blueswir1 | // !1: !(FCC0 & !FCC1)
|
942 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, |
943 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
944 | 19f329ad | blueswir1 | { |
945 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
946 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
947 | de9e9d9f | Richard Henderson | gen_mov_reg_FCC1(t0, src, fcc_offset); |
948 | de9e9d9f | Richard Henderson | tcg_gen_andc_tl(dst, dst, t0); |
949 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
950 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
951 | 19f329ad | blueswir1 | } |
952 | 19f329ad | blueswir1 | |
953 | 19f329ad | blueswir1 | // 0 or 1: !FCC1
|
954 | 19f329ad | blueswir1 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, |
955 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
956 | 19f329ad | blueswir1 | { |
957 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
958 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
959 | 19f329ad | blueswir1 | } |
960 | 19f329ad | blueswir1 | |
961 | 19f329ad | blueswir1 | // !2: !(!FCC0 & FCC1)
|
962 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, |
963 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
964 | 19f329ad | blueswir1 | { |
965 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
966 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
967 | de9e9d9f | Richard Henderson | gen_mov_reg_FCC1(t0, src, fcc_offset); |
968 | de9e9d9f | Richard Henderson | tcg_gen_andc_tl(dst, t0, dst); |
969 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
970 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
971 | 19f329ad | blueswir1 | } |
972 | 19f329ad | blueswir1 | |
973 | 19f329ad | blueswir1 | // !3: !(FCC0 & FCC1)
|
974 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, |
975 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
976 | 19f329ad | blueswir1 | { |
977 | de9e9d9f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
978 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
979 | de9e9d9f | Richard Henderson | gen_mov_reg_FCC1(t0, src, fcc_offset); |
980 | de9e9d9f | Richard Henderson | tcg_gen_and_tl(dst, dst, t0); |
981 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
982 | de9e9d9f | Richard Henderson | tcg_temp_free(t0); |
983 | 19f329ad | blueswir1 | } |
984 | 19f329ad | blueswir1 | |
985 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
986 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
987 | 83469015 | bellard | { |
988 | 83469015 | bellard | int l1;
|
989 | 83469015 | bellard | |
990 | 83469015 | bellard | l1 = gen_new_label(); |
991 | 83469015 | bellard | |
992 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
993 | 83469015 | bellard | |
994 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
995 | 83469015 | bellard | |
996 | 83469015 | bellard | gen_set_label(l1); |
997 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
998 | 83469015 | bellard | } |
999 | 83469015 | bellard | |
1000 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
1001 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1002 | 83469015 | bellard | { |
1003 | 83469015 | bellard | int l1;
|
1004 | 83469015 | bellard | |
1005 | 83469015 | bellard | l1 = gen_new_label(); |
1006 | 83469015 | bellard | |
1007 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1008 | 83469015 | bellard | |
1009 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
1010 | 83469015 | bellard | |
1011 | 83469015 | bellard | gen_set_label(l1); |
1012 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
1013 | 83469015 | bellard | } |
1014 | 83469015 | bellard | |
1015 | 2e655fe7 | Richard Henderson | static inline void gen_generic_branch(DisasContext *dc) |
1016 | 83469015 | bellard | { |
1017 | 61316742 | Richard Henderson | TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
|
1018 | 61316742 | Richard Henderson | TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
|
1019 | 61316742 | Richard Henderson | TCGv zero = tcg_const_tl(0);
|
1020 | 19f329ad | blueswir1 | |
1021 | 61316742 | Richard Henderson | tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1); |
1022 | 83469015 | bellard | |
1023 | 61316742 | Richard Henderson | tcg_temp_free(npc0); |
1024 | 61316742 | Richard Henderson | tcg_temp_free(npc1); |
1025 | 61316742 | Richard Henderson | tcg_temp_free(zero); |
1026 | 83469015 | bellard | } |
1027 | 83469015 | bellard | |
1028 | 4af984a7 | blueswir1 | /* call this function before using the condition register as it may
|
1029 | 4af984a7 | blueswir1 | have been set for a jump */
|
1030 | dee8913c | Richard Henderson | static inline void flush_cond(DisasContext *dc) |
1031 | 83469015 | bellard | { |
1032 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
1033 | 2e655fe7 | Richard Henderson | gen_generic_branch(dc); |
1034 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
1035 | 83469015 | bellard | } |
1036 | 83469015 | bellard | } |
1037 | 83469015 | bellard | |
1038 | 934da7ee | Richard Henderson | static inline void save_npc(DisasContext *dc) |
1039 | 72cbca10 | bellard | { |
1040 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
1041 | 2e655fe7 | Richard Henderson | gen_generic_branch(dc); |
1042 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
1043 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
1044 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
1045 | 72cbca10 | bellard | } |
1046 | 72cbca10 | bellard | } |
1047 | 72cbca10 | bellard | |
1048 | 20132b96 | Richard Henderson | static inline void update_psr(DisasContext *dc) |
1049 | 72cbca10 | bellard | { |
1050 | cfa90513 | Blue Swirl | if (dc->cc_op != CC_OP_FLAGS) {
|
1051 | cfa90513 | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
1052 | 2ffd9176 | Blue Swirl | gen_helper_compute_psr(cpu_env); |
1053 | cfa90513 | Blue Swirl | } |
1054 | 20132b96 | Richard Henderson | } |
1055 | 20132b96 | Richard Henderson | |
1056 | 20132b96 | Richard Henderson | static inline void save_state(DisasContext *dc) |
1057 | 20132b96 | Richard Henderson | { |
1058 | 20132b96 | Richard Henderson | tcg_gen_movi_tl(cpu_pc, dc->pc); |
1059 | 934da7ee | Richard Henderson | save_npc(dc); |
1060 | 72cbca10 | bellard | } |
1061 | 72cbca10 | bellard | |
1062 | 13a6dd00 | Richard Henderson | static inline void gen_mov_pc_npc(DisasContext *dc) |
1063 | 0bee699e | bellard | { |
1064 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
1065 | 2e655fe7 | Richard Henderson | gen_generic_branch(dc); |
1066 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1067 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1068 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
1069 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1070 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1071 | 0bee699e | bellard | } else {
|
1072 | 0bee699e | bellard | dc->pc = dc->npc; |
1073 | 0bee699e | bellard | } |
1074 | 0bee699e | bellard | } |
1075 | 0bee699e | bellard | |
1076 | 38bc628b | blueswir1 | static inline void gen_op_next_insn(void) |
1077 | 38bc628b | blueswir1 | { |
1078 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1079 | 48d5c82b | blueswir1 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
|
1080 | 38bc628b | blueswir1 | } |
1081 | 38bc628b | blueswir1 | |
1082 | 416fcaea | Richard Henderson | static void free_compare(DisasCompare *cmp) |
1083 | 416fcaea | Richard Henderson | { |
1084 | 416fcaea | Richard Henderson | if (!cmp->g1) {
|
1085 | 416fcaea | Richard Henderson | tcg_temp_free(cmp->c1); |
1086 | 416fcaea | Richard Henderson | } |
1087 | 416fcaea | Richard Henderson | if (!cmp->g2) {
|
1088 | 416fcaea | Richard Henderson | tcg_temp_free(cmp->c2); |
1089 | 416fcaea | Richard Henderson | } |
1090 | 416fcaea | Richard Henderson | } |
1091 | 416fcaea | Richard Henderson | |
1092 | 2a484ecf | Richard Henderson | static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, |
1093 | 416fcaea | Richard Henderson | DisasContext *dc) |
1094 | 19f329ad | blueswir1 | { |
1095 | 2a484ecf | Richard Henderson | static int subcc_cond[16] = { |
1096 | 96b5a3d3 | Richard Henderson | TCG_COND_NEVER, |
1097 | 2a484ecf | Richard Henderson | TCG_COND_EQ, |
1098 | 2a484ecf | Richard Henderson | TCG_COND_LE, |
1099 | 2a484ecf | Richard Henderson | TCG_COND_LT, |
1100 | 2a484ecf | Richard Henderson | TCG_COND_LEU, |
1101 | 2a484ecf | Richard Henderson | TCG_COND_LTU, |
1102 | 2a484ecf | Richard Henderson | -1, /* neg */ |
1103 | 2a484ecf | Richard Henderson | -1, /* overflow */ |
1104 | 96b5a3d3 | Richard Henderson | TCG_COND_ALWAYS, |
1105 | 2a484ecf | Richard Henderson | TCG_COND_NE, |
1106 | 2a484ecf | Richard Henderson | TCG_COND_GT, |
1107 | 2a484ecf | Richard Henderson | TCG_COND_GE, |
1108 | 2a484ecf | Richard Henderson | TCG_COND_GTU, |
1109 | 2a484ecf | Richard Henderson | TCG_COND_GEU, |
1110 | 2a484ecf | Richard Henderson | -1, /* pos */ |
1111 | 2a484ecf | Richard Henderson | -1, /* no overflow */ |
1112 | 2a484ecf | Richard Henderson | }; |
1113 | 2a484ecf | Richard Henderson | |
1114 | 96b5a3d3 | Richard Henderson | static int logic_cond[16] = { |
1115 | 96b5a3d3 | Richard Henderson | TCG_COND_NEVER, |
1116 | 96b5a3d3 | Richard Henderson | TCG_COND_EQ, /* eq: Z */
|
1117 | 96b5a3d3 | Richard Henderson | TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
|
1118 | 96b5a3d3 | Richard Henderson | TCG_COND_LT, /* lt: N ^ V -> N */
|
1119 | 96b5a3d3 | Richard Henderson | TCG_COND_EQ, /* leu: C | Z -> Z */
|
1120 | 96b5a3d3 | Richard Henderson | TCG_COND_NEVER, /* ltu: C -> 0 */
|
1121 | 96b5a3d3 | Richard Henderson | TCG_COND_LT, /* neg: N */
|
1122 | 96b5a3d3 | Richard Henderson | TCG_COND_NEVER, /* vs: V -> 0 */
|
1123 | 96b5a3d3 | Richard Henderson | TCG_COND_ALWAYS, |
1124 | 96b5a3d3 | Richard Henderson | TCG_COND_NE, /* ne: !Z */
|
1125 | 96b5a3d3 | Richard Henderson | TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
|
1126 | 96b5a3d3 | Richard Henderson | TCG_COND_GE, /* ge: !(N ^ V) -> !N */
|
1127 | 96b5a3d3 | Richard Henderson | TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
|
1128 | 96b5a3d3 | Richard Henderson | TCG_COND_ALWAYS, /* geu: !C -> 1 */
|
1129 | 96b5a3d3 | Richard Henderson | TCG_COND_GE, /* pos: !N */
|
1130 | 96b5a3d3 | Richard Henderson | TCG_COND_ALWAYS, /* vc: !V -> 1 */
|
1131 | 96b5a3d3 | Richard Henderson | }; |
1132 | 96b5a3d3 | Richard Henderson | |
1133 | a7812ae4 | pbrook | TCGv_i32 r_src; |
1134 | 416fcaea | Richard Henderson | TCGv r_dst; |
1135 | 416fcaea | Richard Henderson | |
1136 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1137 | 2a484ecf | Richard Henderson | if (xcc) {
|
1138 | dc99a3f2 | blueswir1 | r_src = cpu_xcc; |
1139 | 2a484ecf | Richard Henderson | } else {
|
1140 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1141 | 2a484ecf | Richard Henderson | } |
1142 | 3475187d | bellard | #else
|
1143 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1144 | 3475187d | bellard | #endif
|
1145 | 2a484ecf | Richard Henderson | |
1146 | 8393617c | Blue Swirl | switch (dc->cc_op) {
|
1147 | 96b5a3d3 | Richard Henderson | case CC_OP_LOGIC:
|
1148 | 96b5a3d3 | Richard Henderson | cmp->cond = logic_cond[cond]; |
1149 | 96b5a3d3 | Richard Henderson | do_compare_dst_0:
|
1150 | 96b5a3d3 | Richard Henderson | cmp->is_bool = false;
|
1151 | 96b5a3d3 | Richard Henderson | cmp->g2 = false;
|
1152 | 96b5a3d3 | Richard Henderson | cmp->c2 = tcg_const_tl(0);
|
1153 | 96b5a3d3 | Richard Henderson | #ifdef TARGET_SPARC64
|
1154 | 96b5a3d3 | Richard Henderson | if (!xcc) {
|
1155 | 96b5a3d3 | Richard Henderson | cmp->g1 = false;
|
1156 | 96b5a3d3 | Richard Henderson | cmp->c1 = tcg_temp_new(); |
1157 | 96b5a3d3 | Richard Henderson | tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst); |
1158 | 96b5a3d3 | Richard Henderson | break;
|
1159 | 96b5a3d3 | Richard Henderson | } |
1160 | 96b5a3d3 | Richard Henderson | #endif
|
1161 | 96b5a3d3 | Richard Henderson | cmp->g1 = true;
|
1162 | 96b5a3d3 | Richard Henderson | cmp->c1 = cpu_cc_dst; |
1163 | 96b5a3d3 | Richard Henderson | break;
|
1164 | 96b5a3d3 | Richard Henderson | |
1165 | 2a484ecf | Richard Henderson | case CC_OP_SUB:
|
1166 | 2a484ecf | Richard Henderson | switch (cond) {
|
1167 | 2a484ecf | Richard Henderson | case 6: /* neg */ |
1168 | 2a484ecf | Richard Henderson | case 14: /* pos */ |
1169 | 2a484ecf | Richard Henderson | cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
|
1170 | 96b5a3d3 | Richard Henderson | goto do_compare_dst_0;
|
1171 | 2a484ecf | Richard Henderson | |
1172 | 2a484ecf | Richard Henderson | case 7: /* overflow */ |
1173 | 2a484ecf | Richard Henderson | case 15: /* !overflow */ |
1174 | 2a484ecf | Richard Henderson | goto do_dynamic;
|
1175 | 2a484ecf | Richard Henderson | |
1176 | 2a484ecf | Richard Henderson | default:
|
1177 | 2a484ecf | Richard Henderson | cmp->cond = subcc_cond[cond]; |
1178 | 2a484ecf | Richard Henderson | cmp->is_bool = false;
|
1179 | 2a484ecf | Richard Henderson | #ifdef TARGET_SPARC64
|
1180 | 2a484ecf | Richard Henderson | if (!xcc) {
|
1181 | 2a484ecf | Richard Henderson | /* Note that sign-extension works for unsigned compares as
|
1182 | 2a484ecf | Richard Henderson | long as both operands are sign-extended. */
|
1183 | 2a484ecf | Richard Henderson | cmp->g1 = cmp->g2 = false;
|
1184 | 2a484ecf | Richard Henderson | cmp->c1 = tcg_temp_new(); |
1185 | 2a484ecf | Richard Henderson | cmp->c2 = tcg_temp_new(); |
1186 | 2a484ecf | Richard Henderson | tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src); |
1187 | 2a484ecf | Richard Henderson | tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2); |
1188 | 0fa2a066 | Richard Henderson | break;
|
1189 | 2a484ecf | Richard Henderson | } |
1190 | 2a484ecf | Richard Henderson | #endif
|
1191 | 2a484ecf | Richard Henderson | cmp->g1 = cmp->g2 = true;
|
1192 | 2a484ecf | Richard Henderson | cmp->c1 = cpu_cc_src; |
1193 | 2a484ecf | Richard Henderson | cmp->c2 = cpu_cc_src2; |
1194 | 2a484ecf | Richard Henderson | break;
|
1195 | 2a484ecf | Richard Henderson | } |
1196 | 8393617c | Blue Swirl | break;
|
1197 | 2a484ecf | Richard Henderson | |
1198 | 8393617c | Blue Swirl | default:
|
1199 | 2a484ecf | Richard Henderson | do_dynamic:
|
1200 | 2ffd9176 | Blue Swirl | gen_helper_compute_psr(cpu_env); |
1201 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
1202 | 2a484ecf | Richard Henderson | /* FALLTHRU */
|
1203 | 2a484ecf | Richard Henderson | |
1204 | 2a484ecf | Richard Henderson | case CC_OP_FLAGS:
|
1205 | 2a484ecf | Richard Henderson | /* We're going to generate a boolean result. */
|
1206 | 2a484ecf | Richard Henderson | cmp->cond = TCG_COND_NE; |
1207 | 2a484ecf | Richard Henderson | cmp->is_bool = true;
|
1208 | 2a484ecf | Richard Henderson | cmp->g1 = cmp->g2 = false;
|
1209 | 2a484ecf | Richard Henderson | cmp->c1 = r_dst = tcg_temp_new(); |
1210 | 2a484ecf | Richard Henderson | cmp->c2 = tcg_const_tl(0);
|
1211 | 2a484ecf | Richard Henderson | |
1212 | 2a484ecf | Richard Henderson | switch (cond) {
|
1213 | 2a484ecf | Richard Henderson | case 0x0: |
1214 | 2a484ecf | Richard Henderson | gen_op_eval_bn(r_dst); |
1215 | 2a484ecf | Richard Henderson | break;
|
1216 | 2a484ecf | Richard Henderson | case 0x1: |
1217 | 2a484ecf | Richard Henderson | gen_op_eval_be(r_dst, r_src); |
1218 | 2a484ecf | Richard Henderson | break;
|
1219 | 2a484ecf | Richard Henderson | case 0x2: |
1220 | 2a484ecf | Richard Henderson | gen_op_eval_ble(r_dst, r_src); |
1221 | 2a484ecf | Richard Henderson | break;
|
1222 | 2a484ecf | Richard Henderson | case 0x3: |
1223 | 2a484ecf | Richard Henderson | gen_op_eval_bl(r_dst, r_src); |
1224 | 2a484ecf | Richard Henderson | break;
|
1225 | 2a484ecf | Richard Henderson | case 0x4: |
1226 | 2a484ecf | Richard Henderson | gen_op_eval_bleu(r_dst, r_src); |
1227 | 2a484ecf | Richard Henderson | break;
|
1228 | 2a484ecf | Richard Henderson | case 0x5: |
1229 | 2a484ecf | Richard Henderson | gen_op_eval_bcs(r_dst, r_src); |
1230 | 2a484ecf | Richard Henderson | break;
|
1231 | 2a484ecf | Richard Henderson | case 0x6: |
1232 | 2a484ecf | Richard Henderson | gen_op_eval_bneg(r_dst, r_src); |
1233 | 2a484ecf | Richard Henderson | break;
|
1234 | 2a484ecf | Richard Henderson | case 0x7: |
1235 | 2a484ecf | Richard Henderson | gen_op_eval_bvs(r_dst, r_src); |
1236 | 2a484ecf | Richard Henderson | break;
|
1237 | 2a484ecf | Richard Henderson | case 0x8: |
1238 | 2a484ecf | Richard Henderson | gen_op_eval_ba(r_dst); |
1239 | 2a484ecf | Richard Henderson | break;
|
1240 | 2a484ecf | Richard Henderson | case 0x9: |
1241 | 2a484ecf | Richard Henderson | gen_op_eval_bne(r_dst, r_src); |
1242 | 2a484ecf | Richard Henderson | break;
|
1243 | 2a484ecf | Richard Henderson | case 0xa: |
1244 | 2a484ecf | Richard Henderson | gen_op_eval_bg(r_dst, r_src); |
1245 | 2a484ecf | Richard Henderson | break;
|
1246 | 2a484ecf | Richard Henderson | case 0xb: |
1247 | 2a484ecf | Richard Henderson | gen_op_eval_bge(r_dst, r_src); |
1248 | 2a484ecf | Richard Henderson | break;
|
1249 | 2a484ecf | Richard Henderson | case 0xc: |
1250 | 2a484ecf | Richard Henderson | gen_op_eval_bgu(r_dst, r_src); |
1251 | 2a484ecf | Richard Henderson | break;
|
1252 | 2a484ecf | Richard Henderson | case 0xd: |
1253 | 2a484ecf | Richard Henderson | gen_op_eval_bcc(r_dst, r_src); |
1254 | 2a484ecf | Richard Henderson | break;
|
1255 | 2a484ecf | Richard Henderson | case 0xe: |
1256 | 2a484ecf | Richard Henderson | gen_op_eval_bpos(r_dst, r_src); |
1257 | 2a484ecf | Richard Henderson | break;
|
1258 | 2a484ecf | Richard Henderson | case 0xf: |
1259 | 2a484ecf | Richard Henderson | gen_op_eval_bvc(r_dst, r_src); |
1260 | 2a484ecf | Richard Henderson | break;
|
1261 | 2a484ecf | Richard Henderson | } |
1262 | 19f329ad | blueswir1 | break;
|
1263 | 19f329ad | blueswir1 | } |
1264 | 19f329ad | blueswir1 | } |
1265 | 7a3f1944 | bellard | |
1266 | 416fcaea | Richard Henderson | static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond) |
1267 | e8af50a3 | bellard | { |
1268 | 19f329ad | blueswir1 | unsigned int offset; |
1269 | 416fcaea | Richard Henderson | TCGv r_dst; |
1270 | 416fcaea | Richard Henderson | |
1271 | 416fcaea | Richard Henderson | /* For now we still generate a straight boolean result. */
|
1272 | 416fcaea | Richard Henderson | cmp->cond = TCG_COND_NE; |
1273 | 416fcaea | Richard Henderson | cmp->is_bool = true;
|
1274 | 416fcaea | Richard Henderson | cmp->g1 = cmp->g2 = false;
|
1275 | 416fcaea | Richard Henderson | cmp->c1 = r_dst = tcg_temp_new(); |
1276 | 416fcaea | Richard Henderson | cmp->c2 = tcg_const_tl(0);
|
1277 | 19f329ad | blueswir1 | |
1278 | 19f329ad | blueswir1 | switch (cc) {
|
1279 | 19f329ad | blueswir1 | default:
|
1280 | 19f329ad | blueswir1 | case 0x0: |
1281 | 19f329ad | blueswir1 | offset = 0;
|
1282 | 19f329ad | blueswir1 | break;
|
1283 | 19f329ad | blueswir1 | case 0x1: |
1284 | 19f329ad | blueswir1 | offset = 32 - 10; |
1285 | 19f329ad | blueswir1 | break;
|
1286 | 19f329ad | blueswir1 | case 0x2: |
1287 | 19f329ad | blueswir1 | offset = 34 - 10; |
1288 | 19f329ad | blueswir1 | break;
|
1289 | 19f329ad | blueswir1 | case 0x3: |
1290 | 19f329ad | blueswir1 | offset = 36 - 10; |
1291 | 19f329ad | blueswir1 | break;
|
1292 | 19f329ad | blueswir1 | } |
1293 | 19f329ad | blueswir1 | |
1294 | 19f329ad | blueswir1 | switch (cond) {
|
1295 | 19f329ad | blueswir1 | case 0x0: |
1296 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1297 | 19f329ad | blueswir1 | break;
|
1298 | 19f329ad | blueswir1 | case 0x1: |
1299 | 87e92502 | blueswir1 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
1300 | 19f329ad | blueswir1 | break;
|
1301 | 19f329ad | blueswir1 | case 0x2: |
1302 | 87e92502 | blueswir1 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
1303 | 19f329ad | blueswir1 | break;
|
1304 | 19f329ad | blueswir1 | case 0x3: |
1305 | 87e92502 | blueswir1 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
1306 | 19f329ad | blueswir1 | break;
|
1307 | 19f329ad | blueswir1 | case 0x4: |
1308 | 87e92502 | blueswir1 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
1309 | 19f329ad | blueswir1 | break;
|
1310 | 19f329ad | blueswir1 | case 0x5: |
1311 | 87e92502 | blueswir1 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
1312 | 19f329ad | blueswir1 | break;
|
1313 | 19f329ad | blueswir1 | case 0x6: |
1314 | 87e92502 | blueswir1 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
1315 | 19f329ad | blueswir1 | break;
|
1316 | 19f329ad | blueswir1 | case 0x7: |
1317 | 87e92502 | blueswir1 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
1318 | 19f329ad | blueswir1 | break;
|
1319 | 19f329ad | blueswir1 | case 0x8: |
1320 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1321 | 19f329ad | blueswir1 | break;
|
1322 | 19f329ad | blueswir1 | case 0x9: |
1323 | 87e92502 | blueswir1 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
1324 | 19f329ad | blueswir1 | break;
|
1325 | 19f329ad | blueswir1 | case 0xa: |
1326 | 87e92502 | blueswir1 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
1327 | 19f329ad | blueswir1 | break;
|
1328 | 19f329ad | blueswir1 | case 0xb: |
1329 | 87e92502 | blueswir1 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
1330 | 19f329ad | blueswir1 | break;
|
1331 | 19f329ad | blueswir1 | case 0xc: |
1332 | 87e92502 | blueswir1 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
1333 | 19f329ad | blueswir1 | break;
|
1334 | 19f329ad | blueswir1 | case 0xd: |
1335 | 87e92502 | blueswir1 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
1336 | 19f329ad | blueswir1 | break;
|
1337 | 19f329ad | blueswir1 | case 0xe: |
1338 | 87e92502 | blueswir1 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
1339 | 19f329ad | blueswir1 | break;
|
1340 | 19f329ad | blueswir1 | case 0xf: |
1341 | 87e92502 | blueswir1 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
1342 | 19f329ad | blueswir1 | break;
|
1343 | 19f329ad | blueswir1 | } |
1344 | e8af50a3 | bellard | } |
1345 | 00f219bf | blueswir1 | |
1346 | 416fcaea | Richard Henderson | static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond, |
1347 | 416fcaea | Richard Henderson | DisasContext *dc) |
1348 | 416fcaea | Richard Henderson | { |
1349 | 416fcaea | Richard Henderson | DisasCompare cmp; |
1350 | 416fcaea | Richard Henderson | gen_compare(&cmp, cc, cond, dc); |
1351 | 416fcaea | Richard Henderson | |
1352 | 416fcaea | Richard Henderson | /* The interface is to return a boolean in r_dst. */
|
1353 | 416fcaea | Richard Henderson | if (cmp.is_bool) {
|
1354 | 416fcaea | Richard Henderson | tcg_gen_mov_tl(r_dst, cmp.c1); |
1355 | 416fcaea | Richard Henderson | } else {
|
1356 | 416fcaea | Richard Henderson | tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); |
1357 | 416fcaea | Richard Henderson | } |
1358 | 416fcaea | Richard Henderson | |
1359 | 416fcaea | Richard Henderson | free_compare(&cmp); |
1360 | 416fcaea | Richard Henderson | } |
1361 | 416fcaea | Richard Henderson | |
1362 | 416fcaea | Richard Henderson | static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1363 | 416fcaea | Richard Henderson | { |
1364 | 416fcaea | Richard Henderson | DisasCompare cmp; |
1365 | 416fcaea | Richard Henderson | gen_fcompare(&cmp, cc, cond); |
1366 | 416fcaea | Richard Henderson | |
1367 | 416fcaea | Richard Henderson | /* The interface is to return a boolean in r_dst. */
|
1368 | 416fcaea | Richard Henderson | if (cmp.is_bool) {
|
1369 | 416fcaea | Richard Henderson | tcg_gen_mov_tl(r_dst, cmp.c1); |
1370 | 416fcaea | Richard Henderson | } else {
|
1371 | 416fcaea | Richard Henderson | tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); |
1372 | 416fcaea | Richard Henderson | } |
1373 | 416fcaea | Richard Henderson | |
1374 | 416fcaea | Richard Henderson | free_compare(&cmp); |
1375 | 416fcaea | Richard Henderson | } |
1376 | 416fcaea | Richard Henderson | |
1377 | 19f329ad | blueswir1 | #ifdef TARGET_SPARC64
|
1378 | 00f219bf | blueswir1 | // Inverted logic
|
1379 | 00f219bf | blueswir1 | static const int gen_tcg_cond_reg[8] = { |
1380 | 00f219bf | blueswir1 | -1,
|
1381 | 00f219bf | blueswir1 | TCG_COND_NE, |
1382 | 00f219bf | blueswir1 | TCG_COND_GT, |
1383 | 00f219bf | blueswir1 | TCG_COND_GE, |
1384 | 00f219bf | blueswir1 | -1,
|
1385 | 00f219bf | blueswir1 | TCG_COND_EQ, |
1386 | 00f219bf | blueswir1 | TCG_COND_LE, |
1387 | 00f219bf | blueswir1 | TCG_COND_LT, |
1388 | 00f219bf | blueswir1 | }; |
1389 | 19f329ad | blueswir1 | |
1390 | 416fcaea | Richard Henderson | static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) |
1391 | 416fcaea | Richard Henderson | { |
1392 | 416fcaea | Richard Henderson | cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]); |
1393 | 416fcaea | Richard Henderson | cmp->is_bool = false;
|
1394 | 416fcaea | Richard Henderson | cmp->g1 = true;
|
1395 | 416fcaea | Richard Henderson | cmp->g2 = false;
|
1396 | 416fcaea | Richard Henderson | cmp->c1 = r_src; |
1397 | 416fcaea | Richard Henderson | cmp->c2 = tcg_const_tl(0);
|
1398 | 416fcaea | Richard Henderson | } |
1399 | 416fcaea | Richard Henderson | |
1400 | 4af984a7 | blueswir1 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
1401 | 19f329ad | blueswir1 | { |
1402 | 416fcaea | Richard Henderson | DisasCompare cmp; |
1403 | 416fcaea | Richard Henderson | gen_compare_reg(&cmp, cond, r_src); |
1404 | 19f329ad | blueswir1 | |
1405 | 416fcaea | Richard Henderson | /* The interface is to return a boolean in r_dst. */
|
1406 | 416fcaea | Richard Henderson | tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); |
1407 | 416fcaea | Richard Henderson | |
1408 | 416fcaea | Richard Henderson | free_compare(&cmp); |
1409 | 19f329ad | blueswir1 | } |
1410 | 3475187d | bellard | #endif
|
1411 | cf495bcf | bellard | |
1412 | d4a288ef | Richard Henderson | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) |
1413 | 7a3f1944 | bellard | { |
1414 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1415 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1416 | 5fafdf24 | ths | |
1417 | 22036a49 | Artyom Tarasenko | #ifdef TARGET_SPARC64
|
1418 | 22036a49 | Artyom Tarasenko | if (unlikely(AM_CHECK(dc))) {
|
1419 | 22036a49 | Artyom Tarasenko | target &= 0xffffffffULL;
|
1420 | 22036a49 | Artyom Tarasenko | } |
1421 | 22036a49 | Artyom Tarasenko | #endif
|
1422 | cf495bcf | bellard | if (cond == 0x0) { |
1423 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1424 | 0f8a249a | blueswir1 | if (a) {
|
1425 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1426 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1427 | 0f8a249a | blueswir1 | } else {
|
1428 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1429 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1430 | 0f8a249a | blueswir1 | } |
1431 | cf495bcf | bellard | } else if (cond == 0x8) { |
1432 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1433 | 0f8a249a | blueswir1 | if (a) {
|
1434 | 0f8a249a | blueswir1 | dc->pc = target; |
1435 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1436 | 0f8a249a | blueswir1 | } else {
|
1437 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1438 | 0f8a249a | blueswir1 | dc->npc = target; |
1439 | c27e2752 | Blue Swirl | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1440 | 0f8a249a | blueswir1 | } |
1441 | cf495bcf | bellard | } else {
|
1442 | dee8913c | Richard Henderson | flush_cond(dc); |
1443 | d4a288ef | Richard Henderson | gen_cond(cpu_cond, cc, cond, dc); |
1444 | 0f8a249a | blueswir1 | if (a) {
|
1445 | d4a288ef | Richard Henderson | gen_branch_a(dc, target, dc->npc, cpu_cond); |
1446 | cf495bcf | bellard | dc->is_br = 1;
|
1447 | 0f8a249a | blueswir1 | } else {
|
1448 | cf495bcf | bellard | dc->pc = dc->npc; |
1449 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
1450 | 548f66db | Artyom Tarasenko | if (unlikely(dc->npc == DYNAMIC_PC)) {
|
1451 | 548f66db | Artyom Tarasenko | dc->jump_pc[1] = DYNAMIC_PC;
|
1452 | 548f66db | Artyom Tarasenko | tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
|
1453 | 548f66db | Artyom Tarasenko | } else {
|
1454 | 548f66db | Artyom Tarasenko | dc->jump_pc[1] = dc->npc + 4; |
1455 | 548f66db | Artyom Tarasenko | dc->npc = JUMP_PC; |
1456 | 548f66db | Artyom Tarasenko | } |
1457 | 0f8a249a | blueswir1 | } |
1458 | cf495bcf | bellard | } |
1459 | 7a3f1944 | bellard | } |
1460 | 7a3f1944 | bellard | |
1461 | d4a288ef | Richard Henderson | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) |
1462 | e8af50a3 | bellard | { |
1463 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1464 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1465 | af7bf89b | bellard | |
1466 | 22036a49 | Artyom Tarasenko | #ifdef TARGET_SPARC64
|
1467 | 22036a49 | Artyom Tarasenko | if (unlikely(AM_CHECK(dc))) {
|
1468 | 22036a49 | Artyom Tarasenko | target &= 0xffffffffULL;
|
1469 | 22036a49 | Artyom Tarasenko | } |
1470 | 22036a49 | Artyom Tarasenko | #endif
|
1471 | e8af50a3 | bellard | if (cond == 0x0) { |
1472 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1473 | 0f8a249a | blueswir1 | if (a) {
|
1474 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1475 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1476 | 0f8a249a | blueswir1 | } else {
|
1477 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1478 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1479 | 0f8a249a | blueswir1 | } |
1480 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1481 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1482 | 0f8a249a | blueswir1 | if (a) {
|
1483 | 0f8a249a | blueswir1 | dc->pc = target; |
1484 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1485 | 0f8a249a | blueswir1 | } else {
|
1486 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1487 | 0f8a249a | blueswir1 | dc->npc = target; |
1488 | c27e2752 | Blue Swirl | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1489 | 0f8a249a | blueswir1 | } |
1490 | e8af50a3 | bellard | } else {
|
1491 | dee8913c | Richard Henderson | flush_cond(dc); |
1492 | d4a288ef | Richard Henderson | gen_fcond(cpu_cond, cc, cond); |
1493 | 0f8a249a | blueswir1 | if (a) {
|
1494 | d4a288ef | Richard Henderson | gen_branch_a(dc, target, dc->npc, cpu_cond); |
1495 | e8af50a3 | bellard | dc->is_br = 1;
|
1496 | 0f8a249a | blueswir1 | } else {
|
1497 | e8af50a3 | bellard | dc->pc = dc->npc; |
1498 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1499 | 548f66db | Artyom Tarasenko | if (unlikely(dc->npc == DYNAMIC_PC)) {
|
1500 | 548f66db | Artyom Tarasenko | dc->jump_pc[1] = DYNAMIC_PC;
|
1501 | 548f66db | Artyom Tarasenko | tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
|
1502 | 548f66db | Artyom Tarasenko | } else {
|
1503 | 548f66db | Artyom Tarasenko | dc->jump_pc[1] = dc->npc + 4; |
1504 | 548f66db | Artyom Tarasenko | dc->npc = JUMP_PC; |
1505 | 548f66db | Artyom Tarasenko | } |
1506 | 0f8a249a | blueswir1 | } |
1507 | e8af50a3 | bellard | } |
1508 | e8af50a3 | bellard | } |
1509 | e8af50a3 | bellard | |
1510 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1511 | 4af984a7 | blueswir1 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1512 | d4a288ef | Richard Henderson | TCGv r_reg) |
1513 | 7a3f1944 | bellard | { |
1514 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1515 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1516 | 3475187d | bellard | |
1517 | 22036a49 | Artyom Tarasenko | if (unlikely(AM_CHECK(dc))) {
|
1518 | 22036a49 | Artyom Tarasenko | target &= 0xffffffffULL;
|
1519 | 22036a49 | Artyom Tarasenko | } |
1520 | dee8913c | Richard Henderson | flush_cond(dc); |
1521 | d4a288ef | Richard Henderson | gen_cond_reg(cpu_cond, cond, r_reg); |
1522 | 3475187d | bellard | if (a) {
|
1523 | d4a288ef | Richard Henderson | gen_branch_a(dc, target, dc->npc, cpu_cond); |
1524 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1525 | 3475187d | bellard | } else {
|
1526 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1527 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1528 | 548f66db | Artyom Tarasenko | if (unlikely(dc->npc == DYNAMIC_PC)) {
|
1529 | 548f66db | Artyom Tarasenko | dc->jump_pc[1] = DYNAMIC_PC;
|
1530 | 548f66db | Artyom Tarasenko | tcg_gen_addi_tl(cpu_pc, cpu_npc, 4);
|
1531 | 548f66db | Artyom Tarasenko | } else {
|
1532 | 548f66db | Artyom Tarasenko | dc->jump_pc[1] = dc->npc + 4; |
1533 | 548f66db | Artyom Tarasenko | dc->npc = JUMP_PC; |
1534 | 548f66db | Artyom Tarasenko | } |
1535 | 3475187d | bellard | } |
1536 | 7a3f1944 | bellard | } |
1537 | 7a3f1944 | bellard | |
1538 | a7812ae4 | pbrook | static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1539 | 7e8c2b6c | blueswir1 | { |
1540 | 714547bb | blueswir1 | switch (fccno) {
|
1541 | 714547bb | blueswir1 | case 0: |
1542 | 2e2f4ade | Blue Swirl | gen_helper_fcmps(cpu_env, r_rs1, r_rs2); |
1543 | 714547bb | blueswir1 | break;
|
1544 | 714547bb | blueswir1 | case 1: |
1545 | 2e2f4ade | Blue Swirl | gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2); |
1546 | 714547bb | blueswir1 | break;
|
1547 | 714547bb | blueswir1 | case 2: |
1548 | 2e2f4ade | Blue Swirl | gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2); |
1549 | 714547bb | blueswir1 | break;
|
1550 | 714547bb | blueswir1 | case 3: |
1551 | 2e2f4ade | Blue Swirl | gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2); |
1552 | 714547bb | blueswir1 | break;
|
1553 | 714547bb | blueswir1 | } |
1554 | 7e8c2b6c | blueswir1 | } |
1555 | 7e8c2b6c | blueswir1 | |
1556 | 03fb8cfc | Richard Henderson | static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) |
1557 | 7e8c2b6c | blueswir1 | { |
1558 | a7812ae4 | pbrook | switch (fccno) {
|
1559 | a7812ae4 | pbrook | case 0: |
1560 | 03fb8cfc | Richard Henderson | gen_helper_fcmpd(cpu_env, r_rs1, r_rs2); |
1561 | a7812ae4 | pbrook | break;
|
1562 | a7812ae4 | pbrook | case 1: |
1563 | 03fb8cfc | Richard Henderson | gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2); |
1564 | a7812ae4 | pbrook | break;
|
1565 | a7812ae4 | pbrook | case 2: |
1566 | 03fb8cfc | Richard Henderson | gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2); |
1567 | a7812ae4 | pbrook | break;
|
1568 | a7812ae4 | pbrook | case 3: |
1569 | 03fb8cfc | Richard Henderson | gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2); |
1570 | a7812ae4 | pbrook | break;
|
1571 | a7812ae4 | pbrook | } |
1572 | 7e8c2b6c | blueswir1 | } |
1573 | 7e8c2b6c | blueswir1 | |
1574 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1575 | 7e8c2b6c | blueswir1 | { |
1576 | a7812ae4 | pbrook | switch (fccno) {
|
1577 | a7812ae4 | pbrook | case 0: |
1578 | 2e2f4ade | Blue Swirl | gen_helper_fcmpq(cpu_env); |
1579 | a7812ae4 | pbrook | break;
|
1580 | a7812ae4 | pbrook | case 1: |
1581 | 2e2f4ade | Blue Swirl | gen_helper_fcmpq_fcc1(cpu_env); |
1582 | a7812ae4 | pbrook | break;
|
1583 | a7812ae4 | pbrook | case 2: |
1584 | 2e2f4ade | Blue Swirl | gen_helper_fcmpq_fcc2(cpu_env); |
1585 | a7812ae4 | pbrook | break;
|
1586 | a7812ae4 | pbrook | case 3: |
1587 | 2e2f4ade | Blue Swirl | gen_helper_fcmpq_fcc3(cpu_env); |
1588 | a7812ae4 | pbrook | break;
|
1589 | a7812ae4 | pbrook | } |
1590 | 7e8c2b6c | blueswir1 | } |
1591 | 7e8c2b6c | blueswir1 | |
1592 | a7812ae4 | pbrook | static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1593 | 7e8c2b6c | blueswir1 | { |
1594 | 714547bb | blueswir1 | switch (fccno) {
|
1595 | 714547bb | blueswir1 | case 0: |
1596 | 2e2f4ade | Blue Swirl | gen_helper_fcmpes(cpu_env, r_rs1, r_rs2); |
1597 | 714547bb | blueswir1 | break;
|
1598 | 714547bb | blueswir1 | case 1: |
1599 | 2e2f4ade | Blue Swirl | gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2); |
1600 | 714547bb | blueswir1 | break;
|
1601 | 714547bb | blueswir1 | case 2: |
1602 | 2e2f4ade | Blue Swirl | gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2); |
1603 | 714547bb | blueswir1 | break;
|
1604 | 714547bb | blueswir1 | case 3: |
1605 | 2e2f4ade | Blue Swirl | gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2); |
1606 | 714547bb | blueswir1 | break;
|
1607 | 714547bb | blueswir1 | } |
1608 | 7e8c2b6c | blueswir1 | } |
1609 | 7e8c2b6c | blueswir1 | |
1610 | 03fb8cfc | Richard Henderson | static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) |
1611 | 7e8c2b6c | blueswir1 | { |
1612 | a7812ae4 | pbrook | switch (fccno) {
|
1613 | a7812ae4 | pbrook | case 0: |
1614 | 03fb8cfc | Richard Henderson | gen_helper_fcmped(cpu_env, r_rs1, r_rs2); |
1615 | a7812ae4 | pbrook | break;
|
1616 | a7812ae4 | pbrook | case 1: |
1617 | 03fb8cfc | Richard Henderson | gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2); |
1618 | a7812ae4 | pbrook | break;
|
1619 | a7812ae4 | pbrook | case 2: |
1620 | 03fb8cfc | Richard Henderson | gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2); |
1621 | a7812ae4 | pbrook | break;
|
1622 | a7812ae4 | pbrook | case 3: |
1623 | 03fb8cfc | Richard Henderson | gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2); |
1624 | a7812ae4 | pbrook | break;
|
1625 | a7812ae4 | pbrook | } |
1626 | 7e8c2b6c | blueswir1 | } |
1627 | 7e8c2b6c | blueswir1 | |
1628 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1629 | 7e8c2b6c | blueswir1 | { |
1630 | a7812ae4 | pbrook | switch (fccno) {
|
1631 | a7812ae4 | pbrook | case 0: |
1632 | 2e2f4ade | Blue Swirl | gen_helper_fcmpeq(cpu_env); |
1633 | a7812ae4 | pbrook | break;
|
1634 | a7812ae4 | pbrook | case 1: |
1635 | 2e2f4ade | Blue Swirl | gen_helper_fcmpeq_fcc1(cpu_env); |
1636 | a7812ae4 | pbrook | break;
|
1637 | a7812ae4 | pbrook | case 2: |
1638 | 2e2f4ade | Blue Swirl | gen_helper_fcmpeq_fcc2(cpu_env); |
1639 | a7812ae4 | pbrook | break;
|
1640 | a7812ae4 | pbrook | case 3: |
1641 | 2e2f4ade | Blue Swirl | gen_helper_fcmpeq_fcc3(cpu_env); |
1642 | a7812ae4 | pbrook | break;
|
1643 | a7812ae4 | pbrook | } |
1644 | 7e8c2b6c | blueswir1 | } |
1645 | 7e8c2b6c | blueswir1 | |
1646 | 7e8c2b6c | blueswir1 | #else
|
1647 | 7e8c2b6c | blueswir1 | |
1648 | 714547bb | blueswir1 | static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
1649 | 7e8c2b6c | blueswir1 | { |
1650 | 2e2f4ade | Blue Swirl | gen_helper_fcmps(cpu_env, r_rs1, r_rs2); |
1651 | 7e8c2b6c | blueswir1 | } |
1652 | 7e8c2b6c | blueswir1 | |
1653 | 03fb8cfc | Richard Henderson | static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) |
1654 | 7e8c2b6c | blueswir1 | { |
1655 | 03fb8cfc | Richard Henderson | gen_helper_fcmpd(cpu_env, r_rs1, r_rs2); |
1656 | 7e8c2b6c | blueswir1 | } |
1657 | 7e8c2b6c | blueswir1 | |
1658 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1659 | 7e8c2b6c | blueswir1 | { |
1660 | 2e2f4ade | Blue Swirl | gen_helper_fcmpq(cpu_env); |
1661 | 7e8c2b6c | blueswir1 | } |
1662 | 7e8c2b6c | blueswir1 | |
1663 | 714547bb | blueswir1 | static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) |
1664 | 7e8c2b6c | blueswir1 | { |
1665 | 2e2f4ade | Blue Swirl | gen_helper_fcmpes(cpu_env, r_rs1, r_rs2); |
1666 | 7e8c2b6c | blueswir1 | } |
1667 | 7e8c2b6c | blueswir1 | |
1668 | 03fb8cfc | Richard Henderson | static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) |
1669 | 7e8c2b6c | blueswir1 | { |
1670 | 03fb8cfc | Richard Henderson | gen_helper_fcmped(cpu_env, r_rs1, r_rs2); |
1671 | 7e8c2b6c | blueswir1 | } |
1672 | 7e8c2b6c | blueswir1 | |
1673 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1674 | 7e8c2b6c | blueswir1 | { |
1675 | 2e2f4ade | Blue Swirl | gen_helper_fcmpeq(cpu_env); |
1676 | 7e8c2b6c | blueswir1 | } |
1677 | 7e8c2b6c | blueswir1 | #endif
|
1678 | 7e8c2b6c | blueswir1 | |
1679 | 134d77a1 | blueswir1 | static inline void gen_op_fpexception_im(int fsr_flags) |
1680 | 134d77a1 | blueswir1 | { |
1681 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1682 | 2ea815ca | blueswir1 | |
1683 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); |
1684 | 87e92502 | blueswir1 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
1685 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_FP_EXCP); |
1686 | bc265319 | Blue Swirl | gen_helper_raise_exception(cpu_env, r_const); |
1687 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1688 | 134d77a1 | blueswir1 | } |
1689 | 134d77a1 | blueswir1 | |
1690 | 5b12f1e8 | Richard Henderson | static int gen_trap_ifnofpu(DisasContext *dc) |
1691 | a80dde08 | bellard | { |
1692 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1693 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1694 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1695 | 2ea815ca | blueswir1 | |
1696 | 66442b07 | Richard Henderson | save_state(dc); |
1697 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NFPU_INSN); |
1698 | bc265319 | Blue Swirl | gen_helper_raise_exception(cpu_env, r_const); |
1699 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1700 | a80dde08 | bellard | dc->is_br = 1;
|
1701 | a80dde08 | bellard | return 1; |
1702 | a80dde08 | bellard | } |
1703 | a80dde08 | bellard | #endif
|
1704 | a80dde08 | bellard | return 0; |
1705 | a80dde08 | bellard | } |
1706 | a80dde08 | bellard | |
1707 | 7e8c2b6c | blueswir1 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1708 | 7e8c2b6c | blueswir1 | { |
1709 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); |
1710 | 7e8c2b6c | blueswir1 | } |
1711 | 7e8c2b6c | blueswir1 | |
1712 | 61f17f6e | Richard Henderson | static inline void gen_fop_FF(DisasContext *dc, int rd, int rs, |
1713 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
|
1714 | 61f17f6e | Richard Henderson | { |
1715 | 61f17f6e | Richard Henderson | TCGv_i32 dst, src; |
1716 | 61f17f6e | Richard Henderson | |
1717 | 61f17f6e | Richard Henderson | src = gen_load_fpr_F(dc, rs); |
1718 | ba5f5179 | Richard Henderson | dst = gen_dest_fpr_F(dc); |
1719 | 61f17f6e | Richard Henderson | |
1720 | 61f17f6e | Richard Henderson | gen(dst, cpu_env, src); |
1721 | 61f17f6e | Richard Henderson | |
1722 | 61f17f6e | Richard Henderson | gen_store_fpr_F(dc, rd, dst); |
1723 | 61f17f6e | Richard Henderson | } |
1724 | 61f17f6e | Richard Henderson | |
1725 | 61f17f6e | Richard Henderson | static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs, |
1726 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i32, TCGv_i32))
|
1727 | 61f17f6e | Richard Henderson | { |
1728 | 61f17f6e | Richard Henderson | TCGv_i32 dst, src; |
1729 | 61f17f6e | Richard Henderson | |
1730 | 61f17f6e | Richard Henderson | src = gen_load_fpr_F(dc, rs); |
1731 | ba5f5179 | Richard Henderson | dst = gen_dest_fpr_F(dc); |
1732 | 61f17f6e | Richard Henderson | |
1733 | 61f17f6e | Richard Henderson | gen(dst, src); |
1734 | 61f17f6e | Richard Henderson | |
1735 | 61f17f6e | Richard Henderson | gen_store_fpr_F(dc, rd, dst); |
1736 | 61f17f6e | Richard Henderson | } |
1737 | 61f17f6e | Richard Henderson | |
1738 | 61f17f6e | Richard Henderson | static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, |
1739 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
|
1740 | 61f17f6e | Richard Henderson | { |
1741 | 61f17f6e | Richard Henderson | TCGv_i32 dst, src1, src2; |
1742 | 61f17f6e | Richard Henderson | |
1743 | 61f17f6e | Richard Henderson | src1 = gen_load_fpr_F(dc, rs1); |
1744 | 61f17f6e | Richard Henderson | src2 = gen_load_fpr_F(dc, rs2); |
1745 | ba5f5179 | Richard Henderson | dst = gen_dest_fpr_F(dc); |
1746 | 61f17f6e | Richard Henderson | |
1747 | 61f17f6e | Richard Henderson | gen(dst, cpu_env, src1, src2); |
1748 | 61f17f6e | Richard Henderson | |
1749 | 61f17f6e | Richard Henderson | gen_store_fpr_F(dc, rd, dst); |
1750 | 61f17f6e | Richard Henderson | } |
1751 | 61f17f6e | Richard Henderson | |
1752 | 61f17f6e | Richard Henderson | #ifdef TARGET_SPARC64
|
1753 | 61f17f6e | Richard Henderson | static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, |
1754 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
|
1755 | 61f17f6e | Richard Henderson | { |
1756 | 61f17f6e | Richard Henderson | TCGv_i32 dst, src1, src2; |
1757 | 61f17f6e | Richard Henderson | |
1758 | 61f17f6e | Richard Henderson | src1 = gen_load_fpr_F(dc, rs1); |
1759 | 61f17f6e | Richard Henderson | src2 = gen_load_fpr_F(dc, rs2); |
1760 | ba5f5179 | Richard Henderson | dst = gen_dest_fpr_F(dc); |
1761 | 61f17f6e | Richard Henderson | |
1762 | 61f17f6e | Richard Henderson | gen(dst, src1, src2); |
1763 | 61f17f6e | Richard Henderson | |
1764 | 61f17f6e | Richard Henderson | gen_store_fpr_F(dc, rd, dst); |
1765 | 61f17f6e | Richard Henderson | } |
1766 | 61f17f6e | Richard Henderson | #endif
|
1767 | 61f17f6e | Richard Henderson | |
1768 | 61f17f6e | Richard Henderson | static inline void gen_fop_DD(DisasContext *dc, int rd, int rs, |
1769 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
|
1770 | 61f17f6e | Richard Henderson | { |
1771 | 61f17f6e | Richard Henderson | TCGv_i64 dst, src; |
1772 | 61f17f6e | Richard Henderson | |
1773 | 61f17f6e | Richard Henderson | src = gen_load_fpr_D(dc, rs); |
1774 | 3886b8a3 | Richard Henderson | dst = gen_dest_fpr_D(dc, rd); |
1775 | 61f17f6e | Richard Henderson | |
1776 | 61f17f6e | Richard Henderson | gen(dst, cpu_env, src); |
1777 | 61f17f6e | Richard Henderson | |
1778 | 61f17f6e | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
1779 | 61f17f6e | Richard Henderson | } |
1780 | 61f17f6e | Richard Henderson | |
1781 | 61f17f6e | Richard Henderson | #ifdef TARGET_SPARC64
|
1782 | 61f17f6e | Richard Henderson | static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs, |
1783 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i64, TCGv_i64))
|
1784 | 61f17f6e | Richard Henderson | { |
1785 | 61f17f6e | Richard Henderson | TCGv_i64 dst, src; |
1786 | 61f17f6e | Richard Henderson | |
1787 | 61f17f6e | Richard Henderson | src = gen_load_fpr_D(dc, rs); |
1788 | 3886b8a3 | Richard Henderson | dst = gen_dest_fpr_D(dc, rd); |
1789 | 61f17f6e | Richard Henderson | |
1790 | 61f17f6e | Richard Henderson | gen(dst, src); |
1791 | 61f17f6e | Richard Henderson | |
1792 | 61f17f6e | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
1793 | 61f17f6e | Richard Henderson | } |
1794 | 61f17f6e | Richard Henderson | #endif
|
1795 | 61f17f6e | Richard Henderson | |
1796 | 61f17f6e | Richard Henderson | static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, |
1797 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
|
1798 | 61f17f6e | Richard Henderson | { |
1799 | 61f17f6e | Richard Henderson | TCGv_i64 dst, src1, src2; |
1800 | 61f17f6e | Richard Henderson | |
1801 | 61f17f6e | Richard Henderson | src1 = gen_load_fpr_D(dc, rs1); |
1802 | 61f17f6e | Richard Henderson | src2 = gen_load_fpr_D(dc, rs2); |
1803 | 3886b8a3 | Richard Henderson | dst = gen_dest_fpr_D(dc, rd); |
1804 | 61f17f6e | Richard Henderson | |
1805 | 61f17f6e | Richard Henderson | gen(dst, cpu_env, src1, src2); |
1806 | 61f17f6e | Richard Henderson | |
1807 | 61f17f6e | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
1808 | 61f17f6e | Richard Henderson | } |
1809 | 61f17f6e | Richard Henderson | |
1810 | 61f17f6e | Richard Henderson | #ifdef TARGET_SPARC64
|
1811 | 61f17f6e | Richard Henderson | static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, |
1812 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
|
1813 | 61f17f6e | Richard Henderson | { |
1814 | 61f17f6e | Richard Henderson | TCGv_i64 dst, src1, src2; |
1815 | 61f17f6e | Richard Henderson | |
1816 | 61f17f6e | Richard Henderson | src1 = gen_load_fpr_D(dc, rs1); |
1817 | 61f17f6e | Richard Henderson | src2 = gen_load_fpr_D(dc, rs2); |
1818 | 3886b8a3 | Richard Henderson | dst = gen_dest_fpr_D(dc, rd); |
1819 | 61f17f6e | Richard Henderson | |
1820 | 61f17f6e | Richard Henderson | gen(dst, src1, src2); |
1821 | 61f17f6e | Richard Henderson | |
1822 | 61f17f6e | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
1823 | 61f17f6e | Richard Henderson | } |
1824 | f888300b | Richard Henderson | |
1825 | 2dedf314 | Richard Henderson | static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, |
1826 | 2dedf314 | Richard Henderson | void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
|
1827 | 2dedf314 | Richard Henderson | { |
1828 | 2dedf314 | Richard Henderson | TCGv_i64 dst, src1, src2; |
1829 | 2dedf314 | Richard Henderson | |
1830 | 2dedf314 | Richard Henderson | src1 = gen_load_fpr_D(dc, rs1); |
1831 | 2dedf314 | Richard Henderson | src2 = gen_load_fpr_D(dc, rs2); |
1832 | 3886b8a3 | Richard Henderson | dst = gen_dest_fpr_D(dc, rd); |
1833 | 2dedf314 | Richard Henderson | |
1834 | 2dedf314 | Richard Henderson | gen(dst, cpu_gsr, src1, src2); |
1835 | 2dedf314 | Richard Henderson | |
1836 | 2dedf314 | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
1837 | 2dedf314 | Richard Henderson | } |
1838 | 2dedf314 | Richard Henderson | |
1839 | f888300b | Richard Henderson | static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, |
1840 | f888300b | Richard Henderson | void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
|
1841 | f888300b | Richard Henderson | { |
1842 | f888300b | Richard Henderson | TCGv_i64 dst, src0, src1, src2; |
1843 | f888300b | Richard Henderson | |
1844 | f888300b | Richard Henderson | src1 = gen_load_fpr_D(dc, rs1); |
1845 | f888300b | Richard Henderson | src2 = gen_load_fpr_D(dc, rs2); |
1846 | f888300b | Richard Henderson | src0 = gen_load_fpr_D(dc, rd); |
1847 | 3886b8a3 | Richard Henderson | dst = gen_dest_fpr_D(dc, rd); |
1848 | f888300b | Richard Henderson | |
1849 | f888300b | Richard Henderson | gen(dst, src0, src1, src2); |
1850 | f888300b | Richard Henderson | |
1851 | f888300b | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
1852 | f888300b | Richard Henderson | } |
1853 | 61f17f6e | Richard Henderson | #endif
|
1854 | 61f17f6e | Richard Henderson | |
1855 | 61f17f6e | Richard Henderson | static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs, |
1856 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_ptr))
|
1857 | 61f17f6e | Richard Henderson | { |
1858 | 61f17f6e | Richard Henderson | gen_op_load_fpr_QT1(QFPREG(rs)); |
1859 | 61f17f6e | Richard Henderson | |
1860 | 61f17f6e | Richard Henderson | gen(cpu_env); |
1861 | 61f17f6e | Richard Henderson | |
1862 | 61f17f6e | Richard Henderson | gen_op_store_QT0_fpr(QFPREG(rd)); |
1863 | 61f17f6e | Richard Henderson | gen_update_fprs_dirty(QFPREG(rd)); |
1864 | 61f17f6e | Richard Henderson | } |
1865 | 61f17f6e | Richard Henderson | |
1866 | 61f17f6e | Richard Henderson | #ifdef TARGET_SPARC64
|
1867 | 61f17f6e | Richard Henderson | static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, |
1868 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_ptr))
|
1869 | 61f17f6e | Richard Henderson | { |
1870 | 61f17f6e | Richard Henderson | gen_op_load_fpr_QT1(QFPREG(rs)); |
1871 | 61f17f6e | Richard Henderson | |
1872 | 61f17f6e | Richard Henderson | gen(cpu_env); |
1873 | 61f17f6e | Richard Henderson | |
1874 | 61f17f6e | Richard Henderson | gen_op_store_QT0_fpr(QFPREG(rd)); |
1875 | 61f17f6e | Richard Henderson | gen_update_fprs_dirty(QFPREG(rd)); |
1876 | 61f17f6e | Richard Henderson | } |
1877 | 61f17f6e | Richard Henderson | #endif
|
1878 | 61f17f6e | Richard Henderson | |
1879 | 61f17f6e | Richard Henderson | static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2, |
1880 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_ptr))
|
1881 | 61f17f6e | Richard Henderson | { |
1882 | 61f17f6e | Richard Henderson | gen_op_load_fpr_QT0(QFPREG(rs1)); |
1883 | 61f17f6e | Richard Henderson | gen_op_load_fpr_QT1(QFPREG(rs2)); |
1884 | 61f17f6e | Richard Henderson | |
1885 | 61f17f6e | Richard Henderson | gen(cpu_env); |
1886 | 61f17f6e | Richard Henderson | |
1887 | 61f17f6e | Richard Henderson | gen_op_store_QT0_fpr(QFPREG(rd)); |
1888 | 61f17f6e | Richard Henderson | gen_update_fprs_dirty(QFPREG(rd)); |
1889 | 61f17f6e | Richard Henderson | } |
1890 | 61f17f6e | Richard Henderson | |
1891 | 61f17f6e | Richard Henderson | static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, |
1892 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
|
1893 | 61f17f6e | Richard Henderson | { |
1894 | 61f17f6e | Richard Henderson | TCGv_i64 dst; |
1895 | 61f17f6e | Richard Henderson | TCGv_i32 src1, src2; |
1896 | 61f17f6e | Richard Henderson | |
1897 | 61f17f6e | Richard Henderson | src1 = gen_load_fpr_F(dc, rs1); |
1898 | 61f17f6e | Richard Henderson | src2 = gen_load_fpr_F(dc, rs2); |
1899 | 3886b8a3 | Richard Henderson | dst = gen_dest_fpr_D(dc, rd); |
1900 | 61f17f6e | Richard Henderson | |
1901 | 61f17f6e | Richard Henderson | gen(dst, cpu_env, src1, src2); |
1902 | 61f17f6e | Richard Henderson | |
1903 | 61f17f6e | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
1904 | 61f17f6e | Richard Henderson | } |
1905 | 61f17f6e | Richard Henderson | |
1906 | 61f17f6e | Richard Henderson | static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, |
1907 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
|
1908 | 61f17f6e | Richard Henderson | { |
1909 | 61f17f6e | Richard Henderson | TCGv_i64 src1, src2; |
1910 | 61f17f6e | Richard Henderson | |
1911 | 61f17f6e | Richard Henderson | src1 = gen_load_fpr_D(dc, rs1); |
1912 | 61f17f6e | Richard Henderson | src2 = gen_load_fpr_D(dc, rs2); |
1913 | 61f17f6e | Richard Henderson | |
1914 | 61f17f6e | Richard Henderson | gen(cpu_env, src1, src2); |
1915 | 61f17f6e | Richard Henderson | |
1916 | 61f17f6e | Richard Henderson | gen_op_store_QT0_fpr(QFPREG(rd)); |
1917 | 61f17f6e | Richard Henderson | gen_update_fprs_dirty(QFPREG(rd)); |
1918 | 61f17f6e | Richard Henderson | } |
1919 | 61f17f6e | Richard Henderson | |
1920 | 61f17f6e | Richard Henderson | #ifdef TARGET_SPARC64
|
1921 | 61f17f6e | Richard Henderson | static inline void gen_fop_DF(DisasContext *dc, int rd, int rs, |
1922 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
|
1923 | 61f17f6e | Richard Henderson | { |
1924 | 61f17f6e | Richard Henderson | TCGv_i64 dst; |
1925 | 61f17f6e | Richard Henderson | TCGv_i32 src; |
1926 | 61f17f6e | Richard Henderson | |
1927 | 61f17f6e | Richard Henderson | src = gen_load_fpr_F(dc, rs); |
1928 | 3886b8a3 | Richard Henderson | dst = gen_dest_fpr_D(dc, rd); |
1929 | 61f17f6e | Richard Henderson | |
1930 | 61f17f6e | Richard Henderson | gen(dst, cpu_env, src); |
1931 | 61f17f6e | Richard Henderson | |
1932 | 61f17f6e | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
1933 | 61f17f6e | Richard Henderson | } |
1934 | 61f17f6e | Richard Henderson | #endif
|
1935 | 61f17f6e | Richard Henderson | |
1936 | 61f17f6e | Richard Henderson | static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs, |
1937 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
|
1938 | 61f17f6e | Richard Henderson | { |
1939 | 61f17f6e | Richard Henderson | TCGv_i64 dst; |
1940 | 61f17f6e | Richard Henderson | TCGv_i32 src; |
1941 | 61f17f6e | Richard Henderson | |
1942 | 61f17f6e | Richard Henderson | src = gen_load_fpr_F(dc, rs); |
1943 | 3886b8a3 | Richard Henderson | dst = gen_dest_fpr_D(dc, rd); |
1944 | 61f17f6e | Richard Henderson | |
1945 | 61f17f6e | Richard Henderson | gen(dst, cpu_env, src); |
1946 | 61f17f6e | Richard Henderson | |
1947 | 61f17f6e | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
1948 | 61f17f6e | Richard Henderson | } |
1949 | 61f17f6e | Richard Henderson | |
1950 | 61f17f6e | Richard Henderson | static inline void gen_fop_FD(DisasContext *dc, int rd, int rs, |
1951 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
|
1952 | 61f17f6e | Richard Henderson | { |
1953 | 61f17f6e | Richard Henderson | TCGv_i32 dst; |
1954 | 61f17f6e | Richard Henderson | TCGv_i64 src; |
1955 | 61f17f6e | Richard Henderson | |
1956 | 61f17f6e | Richard Henderson | src = gen_load_fpr_D(dc, rs); |
1957 | ba5f5179 | Richard Henderson | dst = gen_dest_fpr_F(dc); |
1958 | 61f17f6e | Richard Henderson | |
1959 | 61f17f6e | Richard Henderson | gen(dst, cpu_env, src); |
1960 | 61f17f6e | Richard Henderson | |
1961 | 61f17f6e | Richard Henderson | gen_store_fpr_F(dc, rd, dst); |
1962 | 61f17f6e | Richard Henderson | } |
1963 | 61f17f6e | Richard Henderson | |
1964 | 61f17f6e | Richard Henderson | static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs, |
1965 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i32, TCGv_ptr))
|
1966 | 61f17f6e | Richard Henderson | { |
1967 | 61f17f6e | Richard Henderson | TCGv_i32 dst; |
1968 | 61f17f6e | Richard Henderson | |
1969 | 61f17f6e | Richard Henderson | gen_op_load_fpr_QT1(QFPREG(rs)); |
1970 | ba5f5179 | Richard Henderson | dst = gen_dest_fpr_F(dc); |
1971 | 61f17f6e | Richard Henderson | |
1972 | 61f17f6e | Richard Henderson | gen(dst, cpu_env); |
1973 | 61f17f6e | Richard Henderson | |
1974 | 61f17f6e | Richard Henderson | gen_store_fpr_F(dc, rd, dst); |
1975 | 61f17f6e | Richard Henderson | } |
1976 | 61f17f6e | Richard Henderson | |
1977 | 61f17f6e | Richard Henderson | static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs, |
1978 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_i64, TCGv_ptr))
|
1979 | 61f17f6e | Richard Henderson | { |
1980 | 61f17f6e | Richard Henderson | TCGv_i64 dst; |
1981 | 61f17f6e | Richard Henderson | |
1982 | 61f17f6e | Richard Henderson | gen_op_load_fpr_QT1(QFPREG(rs)); |
1983 | 3886b8a3 | Richard Henderson | dst = gen_dest_fpr_D(dc, rd); |
1984 | 61f17f6e | Richard Henderson | |
1985 | 61f17f6e | Richard Henderson | gen(dst, cpu_env); |
1986 | 61f17f6e | Richard Henderson | |
1987 | 61f17f6e | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
1988 | 61f17f6e | Richard Henderson | } |
1989 | 61f17f6e | Richard Henderson | |
1990 | 61f17f6e | Richard Henderson | static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, |
1991 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_ptr, TCGv_i32))
|
1992 | 61f17f6e | Richard Henderson | { |
1993 | 61f17f6e | Richard Henderson | TCGv_i32 src; |
1994 | 61f17f6e | Richard Henderson | |
1995 | 61f17f6e | Richard Henderson | src = gen_load_fpr_F(dc, rs); |
1996 | 61f17f6e | Richard Henderson | |
1997 | 61f17f6e | Richard Henderson | gen(cpu_env, src); |
1998 | 61f17f6e | Richard Henderson | |
1999 | 61f17f6e | Richard Henderson | gen_op_store_QT0_fpr(QFPREG(rd)); |
2000 | 61f17f6e | Richard Henderson | gen_update_fprs_dirty(QFPREG(rd)); |
2001 | 61f17f6e | Richard Henderson | } |
2002 | 61f17f6e | Richard Henderson | |
2003 | 61f17f6e | Richard Henderson | static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, |
2004 | 61f17f6e | Richard Henderson | void (*gen)(TCGv_ptr, TCGv_i64))
|
2005 | 61f17f6e | Richard Henderson | { |
2006 | 61f17f6e | Richard Henderson | TCGv_i64 src; |
2007 | 61f17f6e | Richard Henderson | |
2008 | 61f17f6e | Richard Henderson | src = gen_load_fpr_D(dc, rs); |
2009 | 61f17f6e | Richard Henderson | |
2010 | 61f17f6e | Richard Henderson | gen(cpu_env, src); |
2011 | 61f17f6e | Richard Henderson | |
2012 | 61f17f6e | Richard Henderson | gen_op_store_QT0_fpr(QFPREG(rd)); |
2013 | 61f17f6e | Richard Henderson | gen_update_fprs_dirty(QFPREG(rd)); |
2014 | 61f17f6e | Richard Henderson | } |
2015 | 61f17f6e | Richard Henderson | |
2016 | 1a2fb1c0 | blueswir1 | /* asi moves */
|
2017 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
2018 | a7812ae4 | pbrook | static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr) |
2019 | 1a2fb1c0 | blueswir1 | { |
2020 | 95f9397c | blueswir1 | int asi;
|
2021 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
2022 | 1a2fb1c0 | blueswir1 | |
2023 | 1a2fb1c0 | blueswir1 | if (IS_IMM) {
|
2024 | a7812ae4 | pbrook | r_asi = tcg_temp_new_i32(); |
2025 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(r_asi, cpu_asi); |
2026 | 1a2fb1c0 | blueswir1 | } else {
|
2027 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
2028 | 0425bee5 | blueswir1 | r_asi = tcg_const_i32(asi); |
2029 | 1a2fb1c0 | blueswir1 | } |
2030 | 0425bee5 | blueswir1 | return r_asi;
|
2031 | 0425bee5 | blueswir1 | } |
2032 | 0425bee5 | blueswir1 | |
2033 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
2034 | 77f193da | blueswir1 | int sign)
|
2035 | 0425bee5 | blueswir1 | { |
2036 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
2037 | 0425bee5 | blueswir1 | |
2038 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
2039 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
2040 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
2041 | fe8d8f0f | Blue Swirl | gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign); |
2042 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
2043 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
2044 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
2045 | 1a2fb1c0 | blueswir1 | } |
2046 | 1a2fb1c0 | blueswir1 | |
2047 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
2048 | 1a2fb1c0 | blueswir1 | { |
2049 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
2050 | 1a2fb1c0 | blueswir1 | |
2051 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
2052 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
2053 | fe8d8f0f | Blue Swirl | gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size); |
2054 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
2055 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
2056 | 1a2fb1c0 | blueswir1 | } |
2057 | 1a2fb1c0 | blueswir1 | |
2058 | 4af984a7 | blueswir1 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
2059 | 1a2fb1c0 | blueswir1 | { |
2060 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
2061 | 1a2fb1c0 | blueswir1 | |
2062 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
2063 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
2064 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
2065 | fe8d8f0f | Blue Swirl | gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd); |
2066 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
2067 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
2068 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
2069 | 1a2fb1c0 | blueswir1 | } |
2070 | 1a2fb1c0 | blueswir1 | |
2071 | 4af984a7 | blueswir1 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
2072 | 1a2fb1c0 | blueswir1 | { |
2073 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
2074 | 1a2fb1c0 | blueswir1 | |
2075 | 31741a27 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
2076 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
2077 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
2078 | fe8d8f0f | Blue Swirl | gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd); |
2079 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
2080 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
2081 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
2082 | 1a2fb1c0 | blueswir1 | } |
2083 | 1a2fb1c0 | blueswir1 | |
2084 | 06828032 | Richard Henderson | static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn) |
2085 | 1a2fb1c0 | blueswir1 | { |
2086 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
2087 | 1ec789ab | Richard Henderson | TCGv_i64 t64 = tcg_temp_new_i64(); |
2088 | 1a2fb1c0 | blueswir1 | |
2089 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
2090 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
2091 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
2092 | 1ec789ab | Richard Henderson | gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign); |
2093 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
2094 | 06828032 | Richard Henderson | gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size); |
2095 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
2096 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
2097 | 1ec789ab | Richard Henderson | tcg_gen_trunc_i64_tl(dst, t64); |
2098 | 1ec789ab | Richard Henderson | tcg_temp_free_i64(t64); |
2099 | 1a2fb1c0 | blueswir1 | } |
2100 | 1a2fb1c0 | blueswir1 | |
2101 | c7785e16 | Richard Henderson | static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr, |
2102 | c7785e16 | Richard Henderson | int insn, int rd) |
2103 | 1a2fb1c0 | blueswir1 | { |
2104 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_rd; |
2105 | 1a2fb1c0 | blueswir1 | |
2106 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
2107 | db166940 | blueswir1 | r_rd = tcg_const_i32(rd); |
2108 | fe8d8f0f | Blue Swirl | gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd); |
2109 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
2110 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
2111 | 0425bee5 | blueswir1 | } |
2112 | 0425bee5 | blueswir1 | |
2113 | c7785e16 | Richard Henderson | static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, |
2114 | c7785e16 | Richard Henderson | int insn, int rd) |
2115 | 0425bee5 | blueswir1 | { |
2116 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
2117 | c7785e16 | Richard Henderson | TCGv lo = gen_load_gpr(dc, rd + 1);
|
2118 | 1ec789ab | Richard Henderson | TCGv_i64 t64 = tcg_temp_new_i64(); |
2119 | a7ec4229 | blueswir1 | |
2120 | 1ec789ab | Richard Henderson | tcg_gen_concat_tl_i64(t64, lo, hi); |
2121 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
2122 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
2123 | 1ec789ab | Richard Henderson | gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size); |
2124 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
2125 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
2126 | 1ec789ab | Richard Henderson | tcg_temp_free_i64(t64); |
2127 | 1a2fb1c0 | blueswir1 | } |
2128 | 1a2fb1c0 | blueswir1 | |
2129 | 81634eea | Richard Henderson | static inline void gen_cas_asi(DisasContext *dc, TCGv addr, |
2130 | c7785e16 | Richard Henderson | TCGv val2, int insn, int rd) |
2131 | 1a2fb1c0 | blueswir1 | { |
2132 | 81634eea | Richard Henderson | TCGv val1 = gen_load_gpr(dc, rd); |
2133 | 81634eea | Richard Henderson | TCGv dst = gen_dest_gpr(dc, rd); |
2134 | c7785e16 | Richard Henderson | TCGv_i32 r_asi = gen_get_asi(insn, addr); |
2135 | 1a2fb1c0 | blueswir1 | |
2136 | 81634eea | Richard Henderson | gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi); |
2137 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
2138 | 81634eea | Richard Henderson | gen_store_gpr(dc, rd, dst); |
2139 | 1a2fb1c0 | blueswir1 | } |
2140 | 1a2fb1c0 | blueswir1 | |
2141 | 81634eea | Richard Henderson | static inline void gen_casx_asi(DisasContext *dc, TCGv addr, |
2142 | c7785e16 | Richard Henderson | TCGv val2, int insn, int rd) |
2143 | 1a2fb1c0 | blueswir1 | { |
2144 | 81634eea | Richard Henderson | TCGv val1 = gen_load_gpr(dc, rd); |
2145 | 81634eea | Richard Henderson | TCGv dst = gen_dest_gpr(dc, rd); |
2146 | c7785e16 | Richard Henderson | TCGv_i32 r_asi = gen_get_asi(insn, addr); |
2147 | 1a2fb1c0 | blueswir1 | |
2148 | 81634eea | Richard Henderson | gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi); |
2149 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
2150 | 81634eea | Richard Henderson | gen_store_gpr(dc, rd, dst); |
2151 | 1a2fb1c0 | blueswir1 | } |
2152 | 1a2fb1c0 | blueswir1 | |
2153 | 1a2fb1c0 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
2154 | 1a2fb1c0 | blueswir1 | |
2155 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
2156 | 77f193da | blueswir1 | int sign)
|
2157 | 1a2fb1c0 | blueswir1 | { |
2158 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
2159 | 1ec789ab | Richard Henderson | TCGv_i64 t64 = tcg_temp_new_i64(); |
2160 | 1a2fb1c0 | blueswir1 | |
2161 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
2162 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
2163 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
2164 | 1ec789ab | Richard Henderson | gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign); |
2165 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_sign); |
2166 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_size); |
2167 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_asi); |
2168 | 1ec789ab | Richard Henderson | tcg_gen_trunc_i64_tl(dst, t64); |
2169 | 1ec789ab | Richard Henderson | tcg_temp_free_i64(t64); |
2170 | 1a2fb1c0 | blueswir1 | } |
2171 | 1a2fb1c0 | blueswir1 | |
2172 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
2173 | 1a2fb1c0 | blueswir1 | { |
2174 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
2175 | 1ec789ab | Richard Henderson | TCGv_i64 t64 = tcg_temp_new_i64(); |
2176 | 1a2fb1c0 | blueswir1 | |
2177 | 1ec789ab | Richard Henderson | tcg_gen_extu_tl_i64(t64, src); |
2178 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
2179 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
2180 | 1ec789ab | Richard Henderson | gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size); |
2181 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_size); |
2182 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_asi); |
2183 | 1ec789ab | Richard Henderson | tcg_temp_free_i64(t64); |
2184 | 1a2fb1c0 | blueswir1 | } |
2185 | 1a2fb1c0 | blueswir1 | |
2186 | 06828032 | Richard Henderson | static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn) |
2187 | 1a2fb1c0 | blueswir1 | { |
2188 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
2189 | 1ec789ab | Richard Henderson | TCGv_i64 r_val, t64; |
2190 | 1a2fb1c0 | blueswir1 | |
2191 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
2192 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
2193 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
2194 | 1ec789ab | Richard Henderson | t64 = tcg_temp_new_i64(); |
2195 | 1ec789ab | Richard Henderson | gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign); |
2196 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
2197 | a7812ae4 | pbrook | r_val = tcg_temp_new_i64(); |
2198 | 06828032 | Richard Henderson | tcg_gen_extu_tl_i64(r_val, src); |
2199 | fe8d8f0f | Blue Swirl | gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size); |
2200 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
2201 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_size); |
2202 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_asi); |
2203 | 1ec789ab | Richard Henderson | tcg_gen_trunc_i64_tl(dst, t64); |
2204 | 1ec789ab | Richard Henderson | tcg_temp_free_i64(t64); |
2205 | 1a2fb1c0 | blueswir1 | } |
2206 | 1a2fb1c0 | blueswir1 | |
2207 | c7785e16 | Richard Henderson | static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr, |
2208 | c7785e16 | Richard Henderson | int insn, int rd) |
2209 | 1a2fb1c0 | blueswir1 | { |
2210 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
2211 | c7785e16 | Richard Henderson | TCGv t; |
2212 | 1ec789ab | Richard Henderson | TCGv_i64 t64; |
2213 | 1a2fb1c0 | blueswir1 | |
2214 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
2215 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
2216 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
2217 | 1ec789ab | Richard Henderson | t64 = tcg_temp_new_i64(); |
2218 | 1ec789ab | Richard Henderson | gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign); |
2219 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_sign); |
2220 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_size); |
2221 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_asi); |
2222 | c7785e16 | Richard Henderson | |
2223 | c7785e16 | Richard Henderson | t = gen_dest_gpr(dc, rd + 1);
|
2224 | 1ec789ab | Richard Henderson | tcg_gen_trunc_i64_tl(t, t64); |
2225 | c7785e16 | Richard Henderson | gen_store_gpr(dc, rd + 1, t);
|
2226 | c7785e16 | Richard Henderson | |
2227 | 1ec789ab | Richard Henderson | tcg_gen_shri_i64(t64, t64, 32);
|
2228 | 1ec789ab | Richard Henderson | tcg_gen_trunc_i64_tl(hi, t64); |
2229 | 1ec789ab | Richard Henderson | tcg_temp_free_i64(t64); |
2230 | c7785e16 | Richard Henderson | gen_store_gpr(dc, rd, hi); |
2231 | 0425bee5 | blueswir1 | } |
2232 | 0425bee5 | blueswir1 | |
2233 | c7785e16 | Richard Henderson | static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, |
2234 | c7785e16 | Richard Henderson | int insn, int rd) |
2235 | 0425bee5 | blueswir1 | { |
2236 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
2237 | c7785e16 | Richard Henderson | TCGv lo = gen_load_gpr(dc, rd + 1);
|
2238 | 1ec789ab | Richard Henderson | TCGv_i64 t64 = tcg_temp_new_i64(); |
2239 | a7ec4229 | blueswir1 | |
2240 | 1ec789ab | Richard Henderson | tcg_gen_concat_tl_i64(t64, lo, hi); |
2241 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
2242 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
2243 | 1ec789ab | Richard Henderson | gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size); |
2244 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_size); |
2245 | 1ec789ab | Richard Henderson | tcg_temp_free_i32(r_asi); |
2246 | 1ec789ab | Richard Henderson | tcg_temp_free_i64(t64); |
2247 | 1a2fb1c0 | blueswir1 | } |
2248 | 1a2fb1c0 | blueswir1 | #endif
|
2249 | 1a2fb1c0 | blueswir1 | |
2250 | 1a2fb1c0 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
2251 | 4af984a7 | blueswir1 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
2252 | 1a2fb1c0 | blueswir1 | { |
2253 | a7812ae4 | pbrook | TCGv_i64 r_val; |
2254 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
2255 | 1a2fb1c0 | blueswir1 | |
2256 | 4af984a7 | blueswir1 | gen_ld_asi(dst, addr, insn, 1, 0); |
2257 | 1a2fb1c0 | blueswir1 | |
2258 | 2ea815ca | blueswir1 | r_val = tcg_const_i64(0xffULL);
|
2259 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
2260 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(1);
|
2261 | fe8d8f0f | Blue Swirl | gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size); |
2262 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
2263 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
2264 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
2265 | 1a2fb1c0 | blueswir1 | } |
2266 | 1a2fb1c0 | blueswir1 | #endif
|
2267 | 1a2fb1c0 | blueswir1 | |
2268 | 9d1d4e34 | Richard Henderson | static TCGv get_src1(DisasContext *dc, unsigned int insn) |
2269 | 9322a4bf | blueswir1 | { |
2270 | 9d1d4e34 | Richard Henderson | unsigned int rs1 = GET_FIELD(insn, 13, 17); |
2271 | 9d1d4e34 | Richard Henderson | return gen_load_gpr(dc, rs1);
|
2272 | 9322a4bf | blueswir1 | } |
2273 | 9322a4bf | blueswir1 | |
2274 | 9d1d4e34 | Richard Henderson | static TCGv get_src2(DisasContext *dc, unsigned int insn) |
2275 | a49d9390 | blueswir1 | { |
2276 | a49d9390 | blueswir1 | if (IS_IMM) { /* immediate */ |
2277 | 42a8aa83 | Richard Henderson | target_long simm = GET_FIELDs(insn, 19, 31); |
2278 | 9d1d4e34 | Richard Henderson | TCGv t = get_temp_tl(dc); |
2279 | 9d1d4e34 | Richard Henderson | tcg_gen_movi_tl(t, simm); |
2280 | 9d1d4e34 | Richard Henderson | return t;
|
2281 | 9d1d4e34 | Richard Henderson | } else { /* register */ |
2282 | 42a8aa83 | Richard Henderson | unsigned int rs2 = GET_FIELD(insn, 27, 31); |
2283 | 9d1d4e34 | Richard Henderson | return gen_load_gpr(dc, rs2);
|
2284 | a49d9390 | blueswir1 | } |
2285 | a49d9390 | blueswir1 | } |
2286 | a49d9390 | blueswir1 | |
2287 | 8194f35a | Igor Kovalenko | #ifdef TARGET_SPARC64
|
2288 | 7e480893 | Richard Henderson | static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) |
2289 | 7e480893 | Richard Henderson | { |
2290 | 7e480893 | Richard Henderson | TCGv_i32 c32, zero, dst, s1, s2; |
2291 | 7e480893 | Richard Henderson | |
2292 | 7e480893 | Richard Henderson | /* We have two choices here: extend the 32 bit data and use movcond_i64,
|
2293 | 7e480893 | Richard Henderson | or fold the comparison down to 32 bits and use movcond_i32. Choose
|
2294 | 7e480893 | Richard Henderson | the later. */
|
2295 | 7e480893 | Richard Henderson | c32 = tcg_temp_new_i32(); |
2296 | 7e480893 | Richard Henderson | if (cmp->is_bool) {
|
2297 | 7e480893 | Richard Henderson | tcg_gen_trunc_i64_i32(c32, cmp->c1); |
2298 | 7e480893 | Richard Henderson | } else {
|
2299 | 7e480893 | Richard Henderson | TCGv_i64 c64 = tcg_temp_new_i64(); |
2300 | 7e480893 | Richard Henderson | tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2); |
2301 | 7e480893 | Richard Henderson | tcg_gen_trunc_i64_i32(c32, c64); |
2302 | 7e480893 | Richard Henderson | tcg_temp_free_i64(c64); |
2303 | 7e480893 | Richard Henderson | } |
2304 | 7e480893 | Richard Henderson | |
2305 | 7e480893 | Richard Henderson | s1 = gen_load_fpr_F(dc, rs); |
2306 | 7e480893 | Richard Henderson | s2 = gen_load_fpr_F(dc, rd); |
2307 | ba5f5179 | Richard Henderson | dst = gen_dest_fpr_F(dc); |
2308 | 7e480893 | Richard Henderson | zero = tcg_const_i32(0);
|
2309 | 7e480893 | Richard Henderson | |
2310 | 7e480893 | Richard Henderson | tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); |
2311 | 7e480893 | Richard Henderson | |
2312 | 7e480893 | Richard Henderson | tcg_temp_free_i32(c32); |
2313 | 7e480893 | Richard Henderson | tcg_temp_free_i32(zero); |
2314 | 7e480893 | Richard Henderson | gen_store_fpr_F(dc, rd, dst); |
2315 | 7e480893 | Richard Henderson | } |
2316 | 7e480893 | Richard Henderson | |
2317 | 7e480893 | Richard Henderson | static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs) |
2318 | 7e480893 | Richard Henderson | { |
2319 | 3886b8a3 | Richard Henderson | TCGv_i64 dst = gen_dest_fpr_D(dc, rd); |
2320 | 7e480893 | Richard Henderson | tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2, |
2321 | 7e480893 | Richard Henderson | gen_load_fpr_D(dc, rs), |
2322 | 7e480893 | Richard Henderson | gen_load_fpr_D(dc, rd)); |
2323 | 7e480893 | Richard Henderson | gen_store_fpr_D(dc, rd, dst); |
2324 | 7e480893 | Richard Henderson | } |
2325 | 7e480893 | Richard Henderson | |
2326 | 7e480893 | Richard Henderson | static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) |
2327 | 7e480893 | Richard Henderson | { |
2328 | 7e480893 | Richard Henderson | int qd = QFPREG(rd);
|
2329 | 7e480893 | Richard Henderson | int qs = QFPREG(rs);
|
2330 | 7e480893 | Richard Henderson | |
2331 | 7e480893 | Richard Henderson | tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
|
2332 | 7e480893 | Richard Henderson | cpu_fpr[qs / 2], cpu_fpr[qd / 2]); |
2333 | 7e480893 | Richard Henderson | tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2, |
2334 | 7e480893 | Richard Henderson | cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]); |
2335 | 7e480893 | Richard Henderson | |
2336 | 7e480893 | Richard Henderson | gen_update_fprs_dirty(qd); |
2337 | 7e480893 | Richard Henderson | } |
2338 | 7e480893 | Richard Henderson | |
2339 | 8194f35a | Igor Kovalenko | static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env) |
2340 | 8194f35a | Igor Kovalenko | { |
2341 | b551ec04 | Jay Foad | TCGv_i32 r_tl = tcg_temp_new_i32(); |
2342 | 8194f35a | Igor Kovalenko | |
2343 | 8194f35a | Igor Kovalenko | /* load env->tl into r_tl */
|
2344 | b551ec04 | Jay Foad | tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl)); |
2345 | 8194f35a | Igor Kovalenko | |
2346 | 8194f35a | Igor Kovalenko | /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
|
2347 | b551ec04 | Jay Foad | tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK); |
2348 | 8194f35a | Igor Kovalenko | |
2349 | 8194f35a | Igor Kovalenko | /* calculate offset to current trap state from env->ts, reuse r_tl */
|
2350 | b551ec04 | Jay Foad | tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
|
2351 | c5f9864e | Andreas Färber | tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts)); |
2352 | 8194f35a | Igor Kovalenko | |
2353 | 8194f35a | Igor Kovalenko | /* tsptr = env->ts[env->tl & MAXTL_MASK] */
|
2354 | b551ec04 | Jay Foad | { |
2355 | b551ec04 | Jay Foad | TCGv_ptr r_tl_tmp = tcg_temp_new_ptr(); |
2356 | b551ec04 | Jay Foad | tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl); |
2357 | b551ec04 | Jay Foad | tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); |
2358 | bc57c114 | Stefan Weil | tcg_temp_free_ptr(r_tl_tmp); |
2359 | b551ec04 | Jay Foad | } |
2360 | 8194f35a | Igor Kovalenko | |
2361 | b551ec04 | Jay Foad | tcg_temp_free_i32(r_tl); |
2362 | 8194f35a | Igor Kovalenko | } |
2363 | 6c073553 | Richard Henderson | |
2364 | 6c073553 | Richard Henderson | static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, |
2365 | 6c073553 | Richard Henderson | int width, bool cc, bool left) |
2366 | 6c073553 | Richard Henderson | { |
2367 | 6c073553 | Richard Henderson | TCGv lo1, lo2, t1, t2; |
2368 | 6c073553 | Richard Henderson | uint64_t amask, tabl, tabr; |
2369 | 6c073553 | Richard Henderson | int shift, imask, omask;
|
2370 | 6c073553 | Richard Henderson | |
2371 | 6c073553 | Richard Henderson | if (cc) {
|
2372 | 6c073553 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_src, s1); |
2373 | 6c073553 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_src2, s2); |
2374 | 6c073553 | Richard Henderson | tcg_gen_sub_tl(cpu_cc_dst, s1, s2); |
2375 | 6c073553 | Richard Henderson | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
2376 | 6c073553 | Richard Henderson | dc->cc_op = CC_OP_SUB; |
2377 | 6c073553 | Richard Henderson | } |
2378 | 6c073553 | Richard Henderson | |
2379 | 6c073553 | Richard Henderson | /* Theory of operation: there are two tables, left and right (not to
|
2380 | 6c073553 | Richard Henderson | be confused with the left and right versions of the opcode). These
|
2381 | 6c073553 | Richard Henderson | are indexed by the low 3 bits of the inputs. To make things "easy",
|
2382 | 6c073553 | Richard Henderson | these tables are loaded into two constants, TABL and TABR below.
|
2383 | 6c073553 | Richard Henderson | The operation index = (input & imask) << shift calculates the index
|
2384 | 6c073553 | Richard Henderson | into the constant, while val = (table >> index) & omask calculates
|
2385 | 6c073553 | Richard Henderson | the value we're looking for. */
|
2386 | 6c073553 | Richard Henderson | switch (width) {
|
2387 | 6c073553 | Richard Henderson | case 8: |
2388 | 6c073553 | Richard Henderson | imask = 0x7;
|
2389 | 6c073553 | Richard Henderson | shift = 3;
|
2390 | 6c073553 | Richard Henderson | omask = 0xff;
|
2391 | 6c073553 | Richard Henderson | if (left) {
|
2392 | 6c073553 | Richard Henderson | tabl = 0x80c0e0f0f8fcfeffULL;
|
2393 | 6c073553 | Richard Henderson | tabr = 0xff7f3f1f0f070301ULL;
|
2394 | 6c073553 | Richard Henderson | } else {
|
2395 | 6c073553 | Richard Henderson | tabl = 0x0103070f1f3f7fffULL;
|
2396 | 6c073553 | Richard Henderson | tabr = 0xfffefcf8f0e0c080ULL;
|
2397 | 6c073553 | Richard Henderson | } |
2398 | 6c073553 | Richard Henderson | break;
|
2399 | 6c073553 | Richard Henderson | case 16: |
2400 | 6c073553 | Richard Henderson | imask = 0x6;
|
2401 | 6c073553 | Richard Henderson | shift = 1;
|
2402 | 6c073553 | Richard Henderson | omask = 0xf;
|
2403 | 6c073553 | Richard Henderson | if (left) {
|
2404 | 6c073553 | Richard Henderson | tabl = 0x8cef;
|
2405 | 6c073553 | Richard Henderson | tabr = 0xf731;
|
2406 | 6c073553 | Richard Henderson | } else {
|
2407 | 6c073553 | Richard Henderson | tabl = 0x137f;
|
2408 | 6c073553 | Richard Henderson | tabr = 0xfec8;
|
2409 | 6c073553 | Richard Henderson | } |
2410 | 6c073553 | Richard Henderson | break;
|
2411 | 6c073553 | Richard Henderson | case 32: |
2412 | 6c073553 | Richard Henderson | imask = 0x4;
|
2413 | 6c073553 | Richard Henderson | shift = 0;
|
2414 | 6c073553 | Richard Henderson | omask = 0x3;
|
2415 | 6c073553 | Richard Henderson | if (left) {
|
2416 | 6c073553 | Richard Henderson | tabl = (2 << 2) | 3; |
2417 | 6c073553 | Richard Henderson | tabr = (3 << 2) | 1; |
2418 | 6c073553 | Richard Henderson | } else {
|
2419 | 6c073553 | Richard Henderson | tabl = (1 << 2) | 3; |
2420 | 6c073553 | Richard Henderson | tabr = (3 << 2) | 2; |
2421 | 6c073553 | Richard Henderson | } |
2422 | 6c073553 | Richard Henderson | break;
|
2423 | 6c073553 | Richard Henderson | default:
|
2424 | 6c073553 | Richard Henderson | abort(); |
2425 | 6c073553 | Richard Henderson | } |
2426 | 6c073553 | Richard Henderson | |
2427 | 6c073553 | Richard Henderson | lo1 = tcg_temp_new(); |
2428 | 6c073553 | Richard Henderson | lo2 = tcg_temp_new(); |
2429 | 6c073553 | Richard Henderson | tcg_gen_andi_tl(lo1, s1, imask); |
2430 | 6c073553 | Richard Henderson | tcg_gen_andi_tl(lo2, s2, imask); |
2431 | 6c073553 | Richard Henderson | tcg_gen_shli_tl(lo1, lo1, shift); |
2432 | 6c073553 | Richard Henderson | tcg_gen_shli_tl(lo2, lo2, shift); |
2433 | 6c073553 | Richard Henderson | |
2434 | 6c073553 | Richard Henderson | t1 = tcg_const_tl(tabl); |
2435 | 6c073553 | Richard Henderson | t2 = tcg_const_tl(tabr); |
2436 | 6c073553 | Richard Henderson | tcg_gen_shr_tl(lo1, t1, lo1); |
2437 | 6c073553 | Richard Henderson | tcg_gen_shr_tl(lo2, t2, lo2); |
2438 | 6c073553 | Richard Henderson | tcg_gen_andi_tl(dst, lo1, omask); |
2439 | 6c073553 | Richard Henderson | tcg_gen_andi_tl(lo2, lo2, omask); |
2440 | 6c073553 | Richard Henderson | |
2441 | 6c073553 | Richard Henderson | amask = -8;
|
2442 | 6c073553 | Richard Henderson | if (AM_CHECK(dc)) {
|
2443 | 6c073553 | Richard Henderson | amask &= 0xffffffffULL;
|
2444 | 6c073553 | Richard Henderson | } |
2445 | 6c073553 | Richard Henderson | tcg_gen_andi_tl(s1, s1, amask); |
2446 | 6c073553 | Richard Henderson | tcg_gen_andi_tl(s2, s2, amask); |
2447 | 6c073553 | Richard Henderson | |
2448 | 6c073553 | Richard Henderson | /* We want to compute
|
2449 | 6c073553 | Richard Henderson | dst = (s1 == s2 ? lo1 : lo1 & lo2).
|
2450 | 6c073553 | Richard Henderson | We've already done dst = lo1, so this reduces to
|
2451 | 6c073553 | Richard Henderson | dst &= (s1 == s2 ? -1 : lo2)
|
2452 | 6c073553 | Richard Henderson | Which we perform by
|
2453 | 6c073553 | Richard Henderson | lo2 |= -(s1 == s2)
|
2454 | 6c073553 | Richard Henderson | dst &= lo2
|
2455 | 6c073553 | Richard Henderson | */
|
2456 | 6c073553 | Richard Henderson | tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2); |
2457 | 6c073553 | Richard Henderson | tcg_gen_neg_tl(t1, t1); |
2458 | 6c073553 | Richard Henderson | tcg_gen_or_tl(lo2, lo2, t1); |
2459 | 6c073553 | Richard Henderson | tcg_gen_and_tl(dst, dst, lo2); |
2460 | 6c073553 | Richard Henderson | |
2461 | 6c073553 | Richard Henderson | tcg_temp_free(lo1); |
2462 | 6c073553 | Richard Henderson | tcg_temp_free(lo2); |
2463 | 6c073553 | Richard Henderson | tcg_temp_free(t1); |
2464 | 6c073553 | Richard Henderson | tcg_temp_free(t2); |
2465 | 6c073553 | Richard Henderson | } |
2466 | add545ab | Richard Henderson | |
2467 | add545ab | Richard Henderson | static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) |
2468 | add545ab | Richard Henderson | { |
2469 | add545ab | Richard Henderson | TCGv tmp = tcg_temp_new(); |
2470 | add545ab | Richard Henderson | |
2471 | add545ab | Richard Henderson | tcg_gen_add_tl(tmp, s1, s2); |
2472 | add545ab | Richard Henderson | tcg_gen_andi_tl(dst, tmp, -8);
|
2473 | add545ab | Richard Henderson | if (left) {
|
2474 | add545ab | Richard Henderson | tcg_gen_neg_tl(tmp, tmp); |
2475 | add545ab | Richard Henderson | } |
2476 | add545ab | Richard Henderson | tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); |
2477 | add545ab | Richard Henderson | |
2478 | add545ab | Richard Henderson | tcg_temp_free(tmp); |
2479 | add545ab | Richard Henderson | } |
2480 | 50c796f9 | Richard Henderson | |
2481 | 50c796f9 | Richard Henderson | static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) |
2482 | 50c796f9 | Richard Henderson | { |
2483 | 50c796f9 | Richard Henderson | TCGv t1, t2, shift; |
2484 | 50c796f9 | Richard Henderson | |
2485 | 50c796f9 | Richard Henderson | t1 = tcg_temp_new(); |
2486 | 50c796f9 | Richard Henderson | t2 = tcg_temp_new(); |
2487 | 50c796f9 | Richard Henderson | shift = tcg_temp_new(); |
2488 | 50c796f9 | Richard Henderson | |
2489 | 50c796f9 | Richard Henderson | tcg_gen_andi_tl(shift, gsr, 7);
|
2490 | 50c796f9 | Richard Henderson | tcg_gen_shli_tl(shift, shift, 3);
|
2491 | 50c796f9 | Richard Henderson | tcg_gen_shl_tl(t1, s1, shift); |
2492 | 50c796f9 | Richard Henderson | |
2493 | 50c796f9 | Richard Henderson | /* A shift of 64 does not produce 0 in TCG. Divide this into a
|
2494 | 50c796f9 | Richard Henderson | shift of (up to 63) followed by a constant shift of 1. */
|
2495 | 50c796f9 | Richard Henderson | tcg_gen_xori_tl(shift, shift, 63);
|
2496 | 50c796f9 | Richard Henderson | tcg_gen_shr_tl(t2, s2, shift); |
2497 | 50c796f9 | Richard Henderson | tcg_gen_shri_tl(t2, t2, 1);
|
2498 | 50c796f9 | Richard Henderson | |
2499 | 50c796f9 | Richard Henderson | tcg_gen_or_tl(dst, t1, t2); |
2500 | 50c796f9 | Richard Henderson | |
2501 | 50c796f9 | Richard Henderson | tcg_temp_free(t1); |
2502 | 50c796f9 | Richard Henderson | tcg_temp_free(t2); |
2503 | 50c796f9 | Richard Henderson | tcg_temp_free(shift); |
2504 | 50c796f9 | Richard Henderson | } |
2505 | 8194f35a | Igor Kovalenko | #endif
|
2506 | 8194f35a | Igor Kovalenko | |
2507 | 64a88d5d | blueswir1 | #define CHECK_IU_FEATURE(dc, FEATURE) \
|
2508 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
2509 | 64a88d5d | blueswir1 | goto illegal_insn;
|
2510 | 64a88d5d | blueswir1 | #define CHECK_FPU_FEATURE(dc, FEATURE) \
|
2511 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
2512 | 64a88d5d | blueswir1 | goto nfpu_insn;
|
2513 | 64a88d5d | blueswir1 | |
2514 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
2515 | 0184e266 | Blue Swirl | static void disas_sparc_insn(DisasContext * dc, unsigned int insn) |
2516 | cf495bcf | bellard | { |
2517 | 0184e266 | Blue Swirl | unsigned int opc, rs1, rs2, rd; |
2518 | a4273524 | Richard Henderson | TCGv cpu_src1, cpu_src2; |
2519 | 208ae657 | Richard Henderson | TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; |
2520 | 96eda024 | Richard Henderson | TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; |
2521 | 67526b20 | Blue Swirl | target_long simm; |
2522 | 7a3f1944 | bellard | |
2523 | fdefe51c | Richard Henderson | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
|
2524 | a8c768c0 | blueswir1 | tcg_gen_debug_insn_start(dc->pc); |
2525 | fdefe51c | Richard Henderson | } |
2526 | 0184e266 | Blue Swirl | |
2527 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
2528 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
2529 | 6ae20372 | blueswir1 | |
2530 | cf495bcf | bellard | switch (opc) {
|
2531 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
2532 | 0f8a249a | blueswir1 | { |
2533 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
2534 | 0f8a249a | blueswir1 | int32_t target; |
2535 | 0f8a249a | blueswir1 | switch (xop) {
|
2536 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2537 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
2538 | 0f8a249a | blueswir1 | { |
2539 | 0f8a249a | blueswir1 | int cc;
|
2540 | 0f8a249a | blueswir1 | |
2541 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
2542 | 86f1f2ae | Blue Swirl | target = sign_extend(target, 19);
|
2543 | 0f8a249a | blueswir1 | target <<= 2;
|
2544 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
2545 | 0f8a249a | blueswir1 | if (cc == 0) |
2546 | d4a288ef | Richard Henderson | do_branch(dc, target, insn, 0);
|
2547 | 0f8a249a | blueswir1 | else if (cc == 2) |
2548 | d4a288ef | Richard Henderson | do_branch(dc, target, insn, 1);
|
2549 | 0f8a249a | blueswir1 | else
|
2550 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2551 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2552 | 0f8a249a | blueswir1 | } |
2553 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
2554 | 0f8a249a | blueswir1 | { |
2555 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
2556 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
2557 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
2558 | 0f8a249a | blueswir1 | target <<= 2;
|
2559 | 9d1d4e34 | Richard Henderson | cpu_src1 = get_src1(dc, insn); |
2560 | d4a288ef | Richard Henderson | do_branch_reg(dc, target, insn, cpu_src1); |
2561 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2562 | 0f8a249a | blueswir1 | } |
2563 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
2564 | 0f8a249a | blueswir1 | { |
2565 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
2566 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
2567 | a80dde08 | bellard | goto jmp_insn;
|
2568 | 5b12f1e8 | Richard Henderson | } |
2569 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
2570 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
2571 | 0f8a249a | blueswir1 | target <<= 2;
|
2572 | d4a288ef | Richard Henderson | do_fbranch(dc, target, insn, cc); |
2573 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2574 | 0f8a249a | blueswir1 | } |
2575 | a4d17f19 | blueswir1 | #else
|
2576 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
2577 | 0f8a249a | blueswir1 | { |
2578 | 0f8a249a | blueswir1 | goto ncp_insn;
|
2579 | 0f8a249a | blueswir1 | } |
2580 | 0f8a249a | blueswir1 | #endif
|
2581 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
2582 | 0f8a249a | blueswir1 | { |
2583 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
2584 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
2585 | 0f8a249a | blueswir1 | target <<= 2;
|
2586 | d4a288ef | Richard Henderson | do_branch(dc, target, insn, 0);
|
2587 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2588 | 0f8a249a | blueswir1 | } |
2589 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
2590 | 0f8a249a | blueswir1 | { |
2591 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
2592 | a80dde08 | bellard | goto jmp_insn;
|
2593 | 5b12f1e8 | Richard Henderson | } |
2594 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
2595 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
2596 | 0f8a249a | blueswir1 | target <<= 2;
|
2597 | d4a288ef | Richard Henderson | do_fbranch(dc, target, insn, 0);
|
2598 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2599 | 0f8a249a | blueswir1 | } |
2600 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
2601 | 97ea2859 | Richard Henderson | /* Special-case %g0 because that's the canonical nop. */
|
2602 | 97ea2859 | Richard Henderson | if (rd) {
|
2603 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
2604 | 97ea2859 | Richard Henderson | TCGv t = gen_dest_gpr(dc, rd); |
2605 | 97ea2859 | Richard Henderson | tcg_gen_movi_tl(t, value << 10);
|
2606 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, t); |
2607 | 0f8a249a | blueswir1 | } |
2608 | 0f8a249a | blueswir1 | break;
|
2609 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
2610 | 0f8a249a | blueswir1 | default:
|
2611 | 3475187d | bellard | goto illegal_insn;
|
2612 | 0f8a249a | blueswir1 | } |
2613 | 0f8a249a | blueswir1 | break;
|
2614 | 0f8a249a | blueswir1 | } |
2615 | 0f8a249a | blueswir1 | break;
|
2616 | dc1a6971 | Blue Swirl | case 1: /*CALL*/ |
2617 | dc1a6971 | Blue Swirl | { |
2618 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
2619 | 97ea2859 | Richard Henderson | TCGv o7 = gen_dest_gpr(dc, 15);
|
2620 | cf495bcf | bellard | |
2621 | 97ea2859 | Richard Henderson | tcg_gen_movi_tl(o7, dc->pc); |
2622 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, 15, o7);
|
2623 | 0f8a249a | blueswir1 | target += dc->pc; |
2624 | 13a6dd00 | Richard Henderson | gen_mov_pc_npc(dc); |
2625 | 22036a49 | Artyom Tarasenko | #ifdef TARGET_SPARC64
|
2626 | 22036a49 | Artyom Tarasenko | if (unlikely(AM_CHECK(dc))) {
|
2627 | 22036a49 | Artyom Tarasenko | target &= 0xffffffffULL;
|
2628 | 22036a49 | Artyom Tarasenko | } |
2629 | 22036a49 | Artyom Tarasenko | #endif
|
2630 | 0f8a249a | blueswir1 | dc->npc = target; |
2631 | 0f8a249a | blueswir1 | } |
2632 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2633 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
2634 | 0f8a249a | blueswir1 | { |
2635 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
2636 | e7d51b34 | Richard Henderson | TCGv cpu_dst = get_temp_tl(dc); |
2637 | de9e9d9f | Richard Henderson | TCGv cpu_tmp0; |
2638 | 5793f2a4 | Richard Henderson | |
2639 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
2640 | bd49ed41 | Richard Henderson | int cond = GET_FIELD(insn, 3, 6); |
2641 | bd49ed41 | Richard Henderson | TCGv_i32 trap; |
2642 | bd49ed41 | Richard Henderson | int l1 = -1, mask; |
2643 | 3475187d | bellard | |
2644 | bd49ed41 | Richard Henderson | if (cond == 0) { |
2645 | bd49ed41 | Richard Henderson | /* Trap never. */
|
2646 | bd49ed41 | Richard Henderson | break;
|
2647 | cf495bcf | bellard | } |
2648 | b04d9890 | Fabien Chouteau | |
2649 | bd49ed41 | Richard Henderson | save_state(dc); |
2650 | b04d9890 | Fabien Chouteau | |
2651 | bd49ed41 | Richard Henderson | if (cond != 8) { |
2652 | bd49ed41 | Richard Henderson | /* Conditional trap. */
|
2653 | 3a49e759 | Richard Henderson | DisasCompare cmp; |
2654 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2655 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
2656 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
2657 | 3a49e759 | Richard Henderson | if (cc == 0) { |
2658 | 3a49e759 | Richard Henderson | gen_compare(&cmp, 0, cond, dc);
|
2659 | 3a49e759 | Richard Henderson | } else if (cc == 2) { |
2660 | 3a49e759 | Richard Henderson | gen_compare(&cmp, 1, cond, dc);
|
2661 | 3a49e759 | Richard Henderson | } else {
|
2662 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2663 | 3a49e759 | Richard Henderson | } |
2664 | 3475187d | bellard | #else
|
2665 | 3a49e759 | Richard Henderson | gen_compare(&cmp, 0, cond, dc);
|
2666 | 3475187d | bellard | #endif
|
2667 | b158a785 | blueswir1 | l1 = gen_new_label(); |
2668 | 3a49e759 | Richard Henderson | tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond), |
2669 | 3a49e759 | Richard Henderson | cmp.c1, cmp.c2, l1); |
2670 | 3a49e759 | Richard Henderson | free_compare(&cmp); |
2671 | bd49ed41 | Richard Henderson | } |
2672 | b158a785 | blueswir1 | |
2673 | bd49ed41 | Richard Henderson | mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc) |
2674 | bd49ed41 | Richard Henderson | ? UA2005_HTRAP_MASK : V8_TRAP_MASK); |
2675 | bd49ed41 | Richard Henderson | |
2676 | bd49ed41 | Richard Henderson | /* Don't use the normal temporaries, as they may well have
|
2677 | bd49ed41 | Richard Henderson | gone out of scope with the branch above. While we're
|
2678 | bd49ed41 | Richard Henderson | doing that we might as well pre-truncate to 32-bit. */
|
2679 | bd49ed41 | Richard Henderson | trap = tcg_temp_new_i32(); |
2680 | bd49ed41 | Richard Henderson | |
2681 | bd49ed41 | Richard Henderson | rs1 = GET_FIELD_SP(insn, 14, 18); |
2682 | bd49ed41 | Richard Henderson | if (IS_IMM) {
|
2683 | bd49ed41 | Richard Henderson | rs2 = GET_FIELD_SP(insn, 0, 6); |
2684 | bd49ed41 | Richard Henderson | if (rs1 == 0) { |
2685 | bd49ed41 | Richard Henderson | tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP); |
2686 | bd49ed41 | Richard Henderson | /* Signal that the trap value is fully constant. */
|
2687 | bd49ed41 | Richard Henderson | mask = 0;
|
2688 | bd49ed41 | Richard Henderson | } else {
|
2689 | 97ea2859 | Richard Henderson | TCGv t1 = gen_load_gpr(dc, rs1); |
2690 | bd49ed41 | Richard Henderson | tcg_gen_trunc_tl_i32(trap, t1); |
2691 | bd49ed41 | Richard Henderson | tcg_gen_addi_i32(trap, trap, rs2); |
2692 | bd49ed41 | Richard Henderson | } |
2693 | bd49ed41 | Richard Henderson | } else {
|
2694 | 97ea2859 | Richard Henderson | TCGv t1, t2; |
2695 | bd49ed41 | Richard Henderson | rs2 = GET_FIELD_SP(insn, 0, 4); |
2696 | 97ea2859 | Richard Henderson | t1 = gen_load_gpr(dc, rs1); |
2697 | 97ea2859 | Richard Henderson | t2 = gen_load_gpr(dc, rs2); |
2698 | bd49ed41 | Richard Henderson | tcg_gen_add_tl(t1, t1, t2); |
2699 | bd49ed41 | Richard Henderson | tcg_gen_trunc_tl_i32(trap, t1); |
2700 | bd49ed41 | Richard Henderson | } |
2701 | bd49ed41 | Richard Henderson | if (mask != 0) { |
2702 | bd49ed41 | Richard Henderson | tcg_gen_andi_i32(trap, trap, mask); |
2703 | bd49ed41 | Richard Henderson | tcg_gen_addi_i32(trap, trap, TT_TRAP); |
2704 | bd49ed41 | Richard Henderson | } |
2705 | bd49ed41 | Richard Henderson | |
2706 | bd49ed41 | Richard Henderson | gen_helper_raise_exception(cpu_env, trap); |
2707 | bd49ed41 | Richard Henderson | tcg_temp_free_i32(trap); |
2708 | b158a785 | blueswir1 | |
2709 | fe1755cb | Richard Henderson | if (cond == 8) { |
2710 | fe1755cb | Richard Henderson | /* An unconditional trap ends the TB. */
|
2711 | fe1755cb | Richard Henderson | dc->is_br = 1;
|
2712 | fe1755cb | Richard Henderson | goto jmp_insn;
|
2713 | fe1755cb | Richard Henderson | } else {
|
2714 | fe1755cb | Richard Henderson | /* A conditional trap falls through to the next insn. */
|
2715 | b158a785 | blueswir1 | gen_set_label(l1); |
2716 | fe1755cb | Richard Henderson | break;
|
2717 | cf495bcf | bellard | } |
2718 | cf495bcf | bellard | } else if (xop == 0x28) { |
2719 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2720 | cf495bcf | bellard | switch(rs1) {
|
2721 | cf495bcf | bellard | case 0: /* rdy */ |
2722 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
2723 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
2724 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
2725 | 65fe7b09 | blueswir1 | II */
|
2726 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
2727 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
2728 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
2729 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
2730 | 65fe7b09 | blueswir1 | microSPARC II */
|
2731 | 4a2ba232 | Fabien Chouteau | /* Read Asr17 */
|
2732 | 4a2ba232 | Fabien Chouteau | if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) { |
2733 | 97ea2859 | Richard Henderson | TCGv t = gen_dest_gpr(dc, rd); |
2734 | 4a2ba232 | Fabien Chouteau | /* Read Asr17 for a Leon3 monoprocessor */
|
2735 | 97ea2859 | Richard Henderson | tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1)); |
2736 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, t); |
2737 | 4a2ba232 | Fabien Chouteau | break;
|
2738 | 4a2ba232 | Fabien Chouteau | } |
2739 | 65fe7b09 | blueswir1 | #endif
|
2740 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_y); |
2741 | cf495bcf | bellard | break;
|
2742 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2743 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
2744 | 20132b96 | Richard Henderson | update_psr(dc); |
2745 | 063c3675 | Blue Swirl | gen_helper_rdccr(cpu_dst, cpu_env); |
2746 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
2747 | 3475187d | bellard | break;
|
2748 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
2749 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_asi); |
2750 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
2751 | 3475187d | bellard | break;
|
2752 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
2753 | ccd4a219 | blueswir1 | { |
2754 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2755 | ccd4a219 | blueswir1 | |
2756 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2757 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2758 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, tick)); |
2759 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
2760 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2761 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
2762 | ccd4a219 | blueswir1 | } |
2763 | 3475187d | bellard | break;
|
2764 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
2765 | 2ea815ca | blueswir1 | { |
2766 | 97ea2859 | Richard Henderson | TCGv t = gen_dest_gpr(dc, rd); |
2767 | 22036a49 | Artyom Tarasenko | if (unlikely(AM_CHECK(dc))) {
|
2768 | 97ea2859 | Richard Henderson | tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
|
2769 | 22036a49 | Artyom Tarasenko | } else {
|
2770 | 97ea2859 | Richard Henderson | tcg_gen_movi_tl(t, dc->pc); |
2771 | 22036a49 | Artyom Tarasenko | } |
2772 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, t); |
2773 | 2ea815ca | blueswir1 | } |
2774 | 0f8a249a | blueswir1 | break;
|
2775 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
2776 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); |
2777 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
2778 | 3475187d | bellard | break;
|
2779 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
2780 | 65fe7b09 | blueswir1 | break; /* no effect */ |
2781 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
2782 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
2783 | 725cb90b | bellard | goto jmp_insn;
|
2784 | 5b12f1e8 | Richard Henderson | } |
2785 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_gsr); |
2786 | 725cb90b | bellard | break;
|
2787 | 9d926598 | blueswir1 | case 0x16: /* Softint */ |
2788 | 9d926598 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_softint); |
2789 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
2790 | 9d926598 | blueswir1 | break;
|
2791 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
2792 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_tick_cmpr); |
2793 | 83469015 | bellard | break;
|
2794 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
2795 | ccd4a219 | blueswir1 | { |
2796 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2797 | ccd4a219 | blueswir1 | |
2798 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2799 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2800 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, stick)); |
2801 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
2802 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2803 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
2804 | ccd4a219 | blueswir1 | } |
2805 | 83469015 | bellard | break;
|
2806 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
2807 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_stick_cmpr); |
2808 | 83469015 | bellard | break;
|
2809 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
2810 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
2811 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
2812 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
2813 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
2814 | 3475187d | bellard | #endif
|
2815 | 3475187d | bellard | default:
|
2816 | cf495bcf | bellard | goto illegal_insn;
|
2817 | cf495bcf | bellard | } |
2818 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2819 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
2820 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
2821 | 20132b96 | Richard Henderson | if (!supervisor(dc)) {
|
2822 | 0f8a249a | blueswir1 | goto priv_insn;
|
2823 | 20132b96 | Richard Henderson | } |
2824 | 20132b96 | Richard Henderson | update_psr(dc); |
2825 | 063c3675 | Blue Swirl | gen_helper_rdpsr(cpu_dst, cpu_env); |
2826 | e9ebed4d | blueswir1 | #else
|
2827 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2828 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2829 | e9ebed4d | blueswir1 | goto priv_insn;
|
2830 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2831 | e9ebed4d | blueswir1 | switch (rs1) {
|
2832 | e9ebed4d | blueswir1 | case 0: // hpstate |
2833 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
2834 | e9ebed4d | blueswir1 | break;
|
2835 | e9ebed4d | blueswir1 | case 1: // htstate |
2836 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
2837 | e9ebed4d | blueswir1 | break;
|
2838 | e9ebed4d | blueswir1 | case 3: // hintp |
2839 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hintp); |
2840 | e9ebed4d | blueswir1 | break;
|
2841 | e9ebed4d | blueswir1 | case 5: // htba |
2842 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_htba); |
2843 | e9ebed4d | blueswir1 | break;
|
2844 | e9ebed4d | blueswir1 | case 6: // hver |
2845 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hver); |
2846 | e9ebed4d | blueswir1 | break;
|
2847 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
2848 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); |
2849 | e9ebed4d | blueswir1 | break;
|
2850 | e9ebed4d | blueswir1 | default:
|
2851 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2852 | e9ebed4d | blueswir1 | } |
2853 | e9ebed4d | blueswir1 | #endif
|
2854 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
2855 | e8af50a3 | bellard | break;
|
2856 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
2857 | de9e9d9f | Richard Henderson | if (!supervisor(dc)) {
|
2858 | 0f8a249a | blueswir1 | goto priv_insn;
|
2859 | de9e9d9f | Richard Henderson | } |
2860 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
2861 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2862 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2863 | 0f8a249a | blueswir1 | switch (rs1) {
|
2864 | 0f8a249a | blueswir1 | case 0: // tpc |
2865 | 375ee38b | blueswir1 | { |
2866 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2867 | 375ee38b | blueswir1 | |
2868 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2869 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2870 | a7812ae4 | pbrook | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2871 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
2872 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2873 | 375ee38b | blueswir1 | } |
2874 | 0f8a249a | blueswir1 | break;
|
2875 | 0f8a249a | blueswir1 | case 1: // tnpc |
2876 | 375ee38b | blueswir1 | { |
2877 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2878 | 375ee38b | blueswir1 | |
2879 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2880 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2881 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2882 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
2883 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2884 | 375ee38b | blueswir1 | } |
2885 | 0f8a249a | blueswir1 | break;
|
2886 | 0f8a249a | blueswir1 | case 2: // tstate |
2887 | 375ee38b | blueswir1 | { |
2888 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2889 | 375ee38b | blueswir1 | |
2890 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2891 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2892 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2893 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
2894 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2895 | 375ee38b | blueswir1 | } |
2896 | 0f8a249a | blueswir1 | break;
|
2897 | 0f8a249a | blueswir1 | case 3: // tt |
2898 | 375ee38b | blueswir1 | { |
2899 | 45778f99 | Richard Henderson | TCGv_ptr r_tsptr = tcg_temp_new_ptr(); |
2900 | 375ee38b | blueswir1 | |
2901 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2902 | 45778f99 | Richard Henderson | tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr, |
2903 | 45778f99 | Richard Henderson | offsetof(trap_state, tt)); |
2904 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2905 | 375ee38b | blueswir1 | } |
2906 | 0f8a249a | blueswir1 | break;
|
2907 | 0f8a249a | blueswir1 | case 4: // tick |
2908 | ccd4a219 | blueswir1 | { |
2909 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2910 | ccd4a219 | blueswir1 | |
2911 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2912 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2913 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, tick)); |
2914 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_tmp0, r_tickptr); |
2915 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2916 | ccd4a219 | blueswir1 | } |
2917 | 0f8a249a | blueswir1 | break;
|
2918 | 0f8a249a | blueswir1 | case 5: // tba |
2919 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); |
2920 | 0f8a249a | blueswir1 | break;
|
2921 | 0f8a249a | blueswir1 | case 6: // pstate |
2922 | 45778f99 | Richard Henderson | tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, |
2923 | 45778f99 | Richard Henderson | offsetof(CPUSPARCState, pstate)); |
2924 | 0f8a249a | blueswir1 | break;
|
2925 | 0f8a249a | blueswir1 | case 7: // tl |
2926 | 45778f99 | Richard Henderson | tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, |
2927 | 45778f99 | Richard Henderson | offsetof(CPUSPARCState, tl)); |
2928 | 0f8a249a | blueswir1 | break;
|
2929 | 0f8a249a | blueswir1 | case 8: // pil |
2930 | 45778f99 | Richard Henderson | tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, |
2931 | 45778f99 | Richard Henderson | offsetof(CPUSPARCState, psrpil)); |
2932 | 0f8a249a | blueswir1 | break;
|
2933 | 0f8a249a | blueswir1 | case 9: // cwp |
2934 | 063c3675 | Blue Swirl | gen_helper_rdcwp(cpu_tmp0, cpu_env); |
2935 | 0f8a249a | blueswir1 | break;
|
2936 | 0f8a249a | blueswir1 | case 10: // cansave |
2937 | 45778f99 | Richard Henderson | tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, |
2938 | 45778f99 | Richard Henderson | offsetof(CPUSPARCState, cansave)); |
2939 | 0f8a249a | blueswir1 | break;
|
2940 | 0f8a249a | blueswir1 | case 11: // canrestore |
2941 | 45778f99 | Richard Henderson | tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, |
2942 | 45778f99 | Richard Henderson | offsetof(CPUSPARCState, canrestore)); |
2943 | 0f8a249a | blueswir1 | break;
|
2944 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2945 | 45778f99 | Richard Henderson | tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, |
2946 | 45778f99 | Richard Henderson | offsetof(CPUSPARCState, cleanwin)); |
2947 | 0f8a249a | blueswir1 | break;
|
2948 | 0f8a249a | blueswir1 | case 13: // otherwin |
2949 | 45778f99 | Richard Henderson | tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, |
2950 | 45778f99 | Richard Henderson | offsetof(CPUSPARCState, otherwin)); |
2951 | 0f8a249a | blueswir1 | break;
|
2952 | 0f8a249a | blueswir1 | case 14: // wstate |
2953 | 45778f99 | Richard Henderson | tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, |
2954 | 45778f99 | Richard Henderson | offsetof(CPUSPARCState, wstate)); |
2955 | 0f8a249a | blueswir1 | break;
|
2956 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2957 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
2958 | 45778f99 | Richard Henderson | tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, |
2959 | 45778f99 | Richard Henderson | offsetof(CPUSPARCState, gl)); |
2960 | e9ebed4d | blueswir1 | break;
|
2961 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2962 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2963 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2964 | e9ebed4d | blueswir1 | goto priv_insn;
|
2965 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ssr); |
2966 | e9ebed4d | blueswir1 | break;
|
2967 | 0f8a249a | blueswir1 | case 31: // ver |
2968 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ver); |
2969 | 0f8a249a | blueswir1 | break;
|
2970 | 0f8a249a | blueswir1 | case 15: // fq |
2971 | 0f8a249a | blueswir1 | default:
|
2972 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2973 | 0f8a249a | blueswir1 | } |
2974 | 3475187d | bellard | #else
|
2975 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); |
2976 | 3475187d | bellard | #endif
|
2977 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_tmp0); |
2978 | e8af50a3 | bellard | break;
|
2979 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2980 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2981 | 66442b07 | Richard Henderson | save_state(dc); |
2982 | 063c3675 | Blue Swirl | gen_helper_flushw(cpu_env); |
2983 | 3475187d | bellard | #else
|
2984 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2985 | 0f8a249a | blueswir1 | goto priv_insn;
|
2986 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_tbr); |
2987 | 3475187d | bellard | #endif
|
2988 | e8af50a3 | bellard | break;
|
2989 | e8af50a3 | bellard | #endif
|
2990 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
2991 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
2992 | a80dde08 | bellard | goto jmp_insn;
|
2993 | 5b12f1e8 | Richard Henderson | } |
2994 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2995 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2996 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2997 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2998 | 66442b07 | Richard Henderson | save_state(dc); |
2999 | 0f8a249a | blueswir1 | switch (xop) {
|
3000 | dc1a6971 | Blue Swirl | case 0x1: /* fmovs */ |
3001 | 208ae657 | Richard Henderson | cpu_src1_32 = gen_load_fpr_F(dc, rs2); |
3002 | 208ae657 | Richard Henderson | gen_store_fpr_F(dc, rd, cpu_src1_32); |
3003 | dc1a6971 | Blue Swirl | break;
|
3004 | dc1a6971 | Blue Swirl | case 0x5: /* fnegs */ |
3005 | 61f17f6e | Richard Henderson | gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs); |
3006 | dc1a6971 | Blue Swirl | break;
|
3007 | dc1a6971 | Blue Swirl | case 0x9: /* fabss */ |
3008 | 61f17f6e | Richard Henderson | gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss); |
3009 | dc1a6971 | Blue Swirl | break;
|
3010 | dc1a6971 | Blue Swirl | case 0x29: /* fsqrts */ |
3011 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
3012 | 61f17f6e | Richard Henderson | gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); |
3013 | dc1a6971 | Blue Swirl | break;
|
3014 | dc1a6971 | Blue Swirl | case 0x2a: /* fsqrtd */ |
3015 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
3016 | 61f17f6e | Richard Henderson | gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); |
3017 | dc1a6971 | Blue Swirl | break;
|
3018 | dc1a6971 | Blue Swirl | case 0x2b: /* fsqrtq */ |
3019 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3020 | 61f17f6e | Richard Henderson | gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq); |
3021 | dc1a6971 | Blue Swirl | break;
|
3022 | dc1a6971 | Blue Swirl | case 0x41: /* fadds */ |
3023 | 61f17f6e | Richard Henderson | gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds); |
3024 | dc1a6971 | Blue Swirl | break;
|
3025 | dc1a6971 | Blue Swirl | case 0x42: /* faddd */ |
3026 | 61f17f6e | Richard Henderson | gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd); |
3027 | dc1a6971 | Blue Swirl | break;
|
3028 | dc1a6971 | Blue Swirl | case 0x43: /* faddq */ |
3029 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3030 | 61f17f6e | Richard Henderson | gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); |
3031 | dc1a6971 | Blue Swirl | break;
|
3032 | dc1a6971 | Blue Swirl | case 0x45: /* fsubs */ |
3033 | 61f17f6e | Richard Henderson | gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs); |
3034 | dc1a6971 | Blue Swirl | break;
|
3035 | dc1a6971 | Blue Swirl | case 0x46: /* fsubd */ |
3036 | 61f17f6e | Richard Henderson | gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd); |
3037 | dc1a6971 | Blue Swirl | break;
|
3038 | dc1a6971 | Blue Swirl | case 0x47: /* fsubq */ |
3039 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3040 | 61f17f6e | Richard Henderson | gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); |
3041 | dc1a6971 | Blue Swirl | break;
|
3042 | dc1a6971 | Blue Swirl | case 0x49: /* fmuls */ |
3043 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
3044 | 61f17f6e | Richard Henderson | gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls); |
3045 | dc1a6971 | Blue Swirl | break;
|
3046 | dc1a6971 | Blue Swirl | case 0x4a: /* fmuld */ |
3047 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
3048 | 61f17f6e | Richard Henderson | gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); |
3049 | dc1a6971 | Blue Swirl | break;
|
3050 | dc1a6971 | Blue Swirl | case 0x4b: /* fmulq */ |
3051 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3052 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
3053 | 61f17f6e | Richard Henderson | gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); |
3054 | dc1a6971 | Blue Swirl | break;
|
3055 | dc1a6971 | Blue Swirl | case 0x4d: /* fdivs */ |
3056 | 61f17f6e | Richard Henderson | gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs); |
3057 | dc1a6971 | Blue Swirl | break;
|
3058 | dc1a6971 | Blue Swirl | case 0x4e: /* fdivd */ |
3059 | 61f17f6e | Richard Henderson | gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd); |
3060 | dc1a6971 | Blue Swirl | break;
|
3061 | dc1a6971 | Blue Swirl | case 0x4f: /* fdivq */ |
3062 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3063 | 61f17f6e | Richard Henderson | gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq); |
3064 | dc1a6971 | Blue Swirl | break;
|
3065 | dc1a6971 | Blue Swirl | case 0x69: /* fsmuld */ |
3066 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSMULD); |
3067 | 61f17f6e | Richard Henderson | gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld); |
3068 | dc1a6971 | Blue Swirl | break;
|
3069 | dc1a6971 | Blue Swirl | case 0x6e: /* fdmulq */ |
3070 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3071 | 61f17f6e | Richard Henderson | gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq); |
3072 | dc1a6971 | Blue Swirl | break;
|
3073 | dc1a6971 | Blue Swirl | case 0xc4: /* fitos */ |
3074 | 61f17f6e | Richard Henderson | gen_fop_FF(dc, rd, rs2, gen_helper_fitos); |
3075 | dc1a6971 | Blue Swirl | break;
|
3076 | dc1a6971 | Blue Swirl | case 0xc6: /* fdtos */ |
3077 | 61f17f6e | Richard Henderson | gen_fop_FD(dc, rd, rs2, gen_helper_fdtos); |
3078 | dc1a6971 | Blue Swirl | break;
|
3079 | dc1a6971 | Blue Swirl | case 0xc7: /* fqtos */ |
3080 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3081 | 61f17f6e | Richard Henderson | gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos); |
3082 | dc1a6971 | Blue Swirl | break;
|
3083 | dc1a6971 | Blue Swirl | case 0xc8: /* fitod */ |
3084 | 61f17f6e | Richard Henderson | gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod); |
3085 | dc1a6971 | Blue Swirl | break;
|
3086 | dc1a6971 | Blue Swirl | case 0xc9: /* fstod */ |
3087 | 61f17f6e | Richard Henderson | gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod); |
3088 | dc1a6971 | Blue Swirl | break;
|
3089 | dc1a6971 | Blue Swirl | case 0xcb: /* fqtod */ |
3090 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3091 | 61f17f6e | Richard Henderson | gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod); |
3092 | dc1a6971 | Blue Swirl | break;
|
3093 | dc1a6971 | Blue Swirl | case 0xcc: /* fitoq */ |
3094 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3095 | 61f17f6e | Richard Henderson | gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq); |
3096 | dc1a6971 | Blue Swirl | break;
|
3097 | dc1a6971 | Blue Swirl | case 0xcd: /* fstoq */ |
3098 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3099 | 61f17f6e | Richard Henderson | gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq); |
3100 | dc1a6971 | Blue Swirl | break;
|
3101 | dc1a6971 | Blue Swirl | case 0xce: /* fdtoq */ |
3102 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3103 | 61f17f6e | Richard Henderson | gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); |
3104 | dc1a6971 | Blue Swirl | break;
|
3105 | dc1a6971 | Blue Swirl | case 0xd1: /* fstoi */ |
3106 | 61f17f6e | Richard Henderson | gen_fop_FF(dc, rd, rs2, gen_helper_fstoi); |
3107 | dc1a6971 | Blue Swirl | break;
|
3108 | dc1a6971 | Blue Swirl | case 0xd2: /* fdtoi */ |
3109 | 61f17f6e | Richard Henderson | gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi); |
3110 | dc1a6971 | Blue Swirl | break;
|
3111 | dc1a6971 | Blue Swirl | case 0xd3: /* fqtoi */ |
3112 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3113 | 61f17f6e | Richard Henderson | gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi); |
3114 | dc1a6971 | Blue Swirl | break;
|
3115 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3116 | dc1a6971 | Blue Swirl | case 0x2: /* V9 fmovd */ |
3117 | 96eda024 | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs2); |
3118 | 96eda024 | Richard Henderson | gen_store_fpr_D(dc, rd, cpu_src1_64); |
3119 | dc1a6971 | Blue Swirl | break;
|
3120 | dc1a6971 | Blue Swirl | case 0x3: /* V9 fmovq */ |
3121 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3122 | ac11f776 | Richard Henderson | gen_move_Q(rd, rs2); |
3123 | dc1a6971 | Blue Swirl | break;
|
3124 | dc1a6971 | Blue Swirl | case 0x6: /* V9 fnegd */ |
3125 | 61f17f6e | Richard Henderson | gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd); |
3126 | dc1a6971 | Blue Swirl | break;
|
3127 | dc1a6971 | Blue Swirl | case 0x7: /* V9 fnegq */ |
3128 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3129 | 61f17f6e | Richard Henderson | gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq); |
3130 | dc1a6971 | Blue Swirl | break;
|
3131 | dc1a6971 | Blue Swirl | case 0xa: /* V9 fabsd */ |
3132 | 61f17f6e | Richard Henderson | gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd); |
3133 | dc1a6971 | Blue Swirl | break;
|
3134 | dc1a6971 | Blue Swirl | case 0xb: /* V9 fabsq */ |
3135 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3136 | 61f17f6e | Richard Henderson | gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); |
3137 | dc1a6971 | Blue Swirl | break;
|
3138 | dc1a6971 | Blue Swirl | case 0x81: /* V9 fstox */ |
3139 | 61f17f6e | Richard Henderson | gen_fop_DF(dc, rd, rs2, gen_helper_fstox); |
3140 | dc1a6971 | Blue Swirl | break;
|
3141 | dc1a6971 | Blue Swirl | case 0x82: /* V9 fdtox */ |
3142 | 61f17f6e | Richard Henderson | gen_fop_DD(dc, rd, rs2, gen_helper_fdtox); |
3143 | dc1a6971 | Blue Swirl | break;
|
3144 | dc1a6971 | Blue Swirl | case 0x83: /* V9 fqtox */ |
3145 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3146 | 61f17f6e | Richard Henderson | gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); |
3147 | dc1a6971 | Blue Swirl | break;
|
3148 | dc1a6971 | Blue Swirl | case 0x84: /* V9 fxtos */ |
3149 | 61f17f6e | Richard Henderson | gen_fop_FD(dc, rd, rs2, gen_helper_fxtos); |
3150 | dc1a6971 | Blue Swirl | break;
|
3151 | dc1a6971 | Blue Swirl | case 0x88: /* V9 fxtod */ |
3152 | 61f17f6e | Richard Henderson | gen_fop_DD(dc, rd, rs2, gen_helper_fxtod); |
3153 | dc1a6971 | Blue Swirl | break;
|
3154 | dc1a6971 | Blue Swirl | case 0x8c: /* V9 fxtoq */ |
3155 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
3156 | 61f17f6e | Richard Henderson | gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); |
3157 | dc1a6971 | Blue Swirl | break;
|
3158 | 1f587329 | blueswir1 | #endif
|
3159 | dc1a6971 | Blue Swirl | default:
|
3160 | dc1a6971 | Blue Swirl | goto illegal_insn;
|
3161 | 0f8a249a | blueswir1 | } |
3162 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
3163 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3164 | 0f8a249a | blueswir1 | int cond;
|
3165 | 3475187d | bellard | #endif
|
3166 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
3167 | a80dde08 | bellard | goto jmp_insn;
|
3168 | 5b12f1e8 | Richard Henderson | } |
3169 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
3170 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3171 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3172 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
3173 | 66442b07 | Richard Henderson | save_state(dc); |
3174 | dcf24905 | blueswir1 | |
3175 | 690995a6 | Richard Henderson | #ifdef TARGET_SPARC64
|
3176 | 690995a6 | Richard Henderson | #define FMOVR(sz) \
|
3177 | 690995a6 | Richard Henderson | do { \
|
3178 | 690995a6 | Richard Henderson | DisasCompare cmp; \ |
3179 | e7c8afb9 | Aurelien Jarno | cond = GET_FIELD_SP(insn, 10, 12); \ |
3180 | 9d1d4e34 | Richard Henderson | cpu_src1 = get_src1(dc, insn); \ |
3181 | 690995a6 | Richard Henderson | gen_compare_reg(&cmp, cond, cpu_src1); \ |
3182 | 690995a6 | Richard Henderson | gen_fmov##sz(dc, &cmp, rd, rs2); \ |
3183 | 690995a6 | Richard Henderson | free_compare(&cmp); \ |
3184 | 690995a6 | Richard Henderson | } while (0) |
3185 | 690995a6 | Richard Henderson | |
3186 | 690995a6 | Richard Henderson | if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */ |
3187 | 690995a6 | Richard Henderson | FMOVR(s); |
3188 | 0f8a249a | blueswir1 | break;
|
3189 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
3190 | 690995a6 | Richard Henderson | FMOVR(d); |
3191 | 0f8a249a | blueswir1 | break;
|
3192 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
3193 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
3194 | 690995a6 | Richard Henderson | FMOVR(q); |
3195 | 1f587329 | blueswir1 | break;
|
3196 | 0f8a249a | blueswir1 | } |
3197 | 690995a6 | Richard Henderson | #undef FMOVR
|
3198 | 0f8a249a | blueswir1 | #endif
|
3199 | 0f8a249a | blueswir1 | switch (xop) {
|
3200 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3201 | 7e480893 | Richard Henderson | #define FMOVCC(fcc, sz) \
|
3202 | 7e480893 | Richard Henderson | do { \
|
3203 | 7e480893 | Richard Henderson | DisasCompare cmp; \ |
3204 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
3205 | 7e480893 | Richard Henderson | gen_fcompare(&cmp, fcc, cond); \ |
3206 | 7e480893 | Richard Henderson | gen_fmov##sz(dc, &cmp, rd, rs2); \ |
3207 | 7e480893 | Richard Henderson | free_compare(&cmp); \ |
3208 | 7e480893 | Richard Henderson | } while (0) |
3209 | 7e480893 | Richard Henderson | |
3210 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
3211 | 7e480893 | Richard Henderson | FMOVCC(0, s);
|
3212 | 0f8a249a | blueswir1 | break;
|
3213 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
3214 | 7e480893 | Richard Henderson | FMOVCC(0, d);
|
3215 | 0f8a249a | blueswir1 | break;
|
3216 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
3217 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
3218 | 7e480893 | Richard Henderson | FMOVCC(0, q);
|
3219 | 1f587329 | blueswir1 | break;
|
3220 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
3221 | 7e480893 | Richard Henderson | FMOVCC(1, s);
|
3222 | 0f8a249a | blueswir1 | break;
|
3223 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
3224 | 7e480893 | Richard Henderson | FMOVCC(1, d);
|
3225 | 0f8a249a | blueswir1 | break;
|
3226 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
3227 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
3228 | 7e480893 | Richard Henderson | FMOVCC(1, q);
|
3229 | 1f587329 | blueswir1 | break;
|
3230 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
3231 | 7e480893 | Richard Henderson | FMOVCC(2, s);
|
3232 | 0f8a249a | blueswir1 | break;
|
3233 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
3234 | 7e480893 | Richard Henderson | FMOVCC(2, d);
|
3235 | 0f8a249a | blueswir1 | break;
|
3236 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
3237 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
3238 | 7e480893 | Richard Henderson | FMOVCC(2, q);
|
3239 | 1f587329 | blueswir1 | break;
|
3240 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
3241 | 7e480893 | Richard Henderson | FMOVCC(3, s);
|
3242 | 0f8a249a | blueswir1 | break;
|
3243 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
3244 | 7e480893 | Richard Henderson | FMOVCC(3, d);
|
3245 | 0f8a249a | blueswir1 | break;
|
3246 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
3247 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
3248 | 7e480893 | Richard Henderson | FMOVCC(3, q);
|
3249 | 1f587329 | blueswir1 | break;
|
3250 | 7e480893 | Richard Henderson | #undef FMOVCC
|
3251 | 7e480893 | Richard Henderson | #define FMOVCC(xcc, sz) \
|
3252 | 7e480893 | Richard Henderson | do { \
|
3253 | 7e480893 | Richard Henderson | DisasCompare cmp; \ |
3254 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
3255 | 7e480893 | Richard Henderson | gen_compare(&cmp, xcc, cond, dc); \ |
3256 | 7e480893 | Richard Henderson | gen_fmov##sz(dc, &cmp, rd, rs2); \ |
3257 | 7e480893 | Richard Henderson | free_compare(&cmp); \ |
3258 | 7e480893 | Richard Henderson | } while (0) |
3259 | 19f329ad | blueswir1 | |
3260 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
3261 | 7e480893 | Richard Henderson | FMOVCC(0, s);
|
3262 | 0f8a249a | blueswir1 | break;
|
3263 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
3264 | 7e480893 | Richard Henderson | FMOVCC(0, d);
|
3265 | b7d69dc2 | Tsuneo Saito | break;
|
3266 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
3267 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
3268 | 7e480893 | Richard Henderson | FMOVCC(0, q);
|
3269 | 1f587329 | blueswir1 | break;
|
3270 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
3271 | 7e480893 | Richard Henderson | FMOVCC(1, s);
|
3272 | 0f8a249a | blueswir1 | break;
|
3273 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
3274 | 7e480893 | Richard Henderson | FMOVCC(1, d);
|
3275 | 0f8a249a | blueswir1 | break;
|
3276 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
3277 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
3278 | 7e480893 | Richard Henderson | FMOVCC(1, q);
|
3279 | 1f587329 | blueswir1 | break;
|
3280 | 7e480893 | Richard Henderson | #undef FMOVCC
|
3281 | 1f587329 | blueswir1 | #endif
|
3282 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
3283 | 208ae657 | Richard Henderson | cpu_src1_32 = gen_load_fpr_F(dc, rs1); |
3284 | 208ae657 | Richard Henderson | cpu_src2_32 = gen_load_fpr_F(dc, rs2); |
3285 | 208ae657 | Richard Henderson | gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
|
3286 | 0f8a249a | blueswir1 | break;
|
3287 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
3288 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
3289 | 03fb8cfc | Richard Henderson | cpu_src2_64 = gen_load_fpr_D(dc, rs2); |
3290 | 03fb8cfc | Richard Henderson | gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
|
3291 | 0f8a249a | blueswir1 | break;
|
3292 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
3293 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
3294 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
3295 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
3296 | 7e8c2b6c | blueswir1 | gen_op_fcmpq(rd & 3);
|
3297 | 1f587329 | blueswir1 | break;
|
3298 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
3299 | 208ae657 | Richard Henderson | cpu_src1_32 = gen_load_fpr_F(dc, rs1); |
3300 | 208ae657 | Richard Henderson | cpu_src2_32 = gen_load_fpr_F(dc, rs2); |
3301 | 208ae657 | Richard Henderson | gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
|
3302 | 0f8a249a | blueswir1 | break;
|
3303 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
3304 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
3305 | 03fb8cfc | Richard Henderson | cpu_src2_64 = gen_load_fpr_D(dc, rs2); |
3306 | 03fb8cfc | Richard Henderson | gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
|
3307 | 0f8a249a | blueswir1 | break;
|
3308 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
3309 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
3310 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
3311 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
3312 | 7e8c2b6c | blueswir1 | gen_op_fcmpeq(rd & 3);
|
3313 | 1f587329 | blueswir1 | break;
|
3314 | 0f8a249a | blueswir1 | default:
|
3315 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3316 | 0f8a249a | blueswir1 | } |
3317 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
3318 | 97ea2859 | Richard Henderson | TCGv dst = gen_dest_gpr(dc, rd); |
3319 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3320 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
3321 | 97ea2859 | Richard Henderson | /* clr/mov shortcut : or %g0, x, y -> mov x, y */
|
3322 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3323 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3324 | 97ea2859 | Richard Henderson | tcg_gen_movi_tl(dst, simm); |
3325 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, dst); |
3326 | 0f8a249a | blueswir1 | } else { /* register */ |
3327 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3328 | 97ea2859 | Richard Henderson | if (rs2 == 0) { |
3329 | 97ea2859 | Richard Henderson | tcg_gen_movi_tl(dst, 0);
|
3330 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, dst); |
3331 | 97ea2859 | Richard Henderson | } else {
|
3332 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
3333 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_src2); |
3334 | 97ea2859 | Richard Henderson | } |
3335 | 0f8a249a | blueswir1 | } |
3336 | 0f8a249a | blueswir1 | } else {
|
3337 | 9d1d4e34 | Richard Henderson | cpu_src1 = get_src1(dc, insn); |
3338 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3339 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3340 | 97ea2859 | Richard Henderson | tcg_gen_ori_tl(dst, cpu_src1, simm); |
3341 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, dst); |
3342 | 0f8a249a | blueswir1 | } else { /* register */ |
3343 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3344 | 97ea2859 | Richard Henderson | if (rs2 == 0) { |
3345 | 97ea2859 | Richard Henderson | /* mov shortcut: or x, %g0, y -> mov x, y */
|
3346 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_src1); |
3347 | 97ea2859 | Richard Henderson | } else {
|
3348 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
3349 | 97ea2859 | Richard Henderson | tcg_gen_or_tl(dst, cpu_src1, cpu_src2); |
3350 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, dst); |
3351 | 97ea2859 | Richard Henderson | } |
3352 | 0f8a249a | blueswir1 | } |
3353 | 0f8a249a | blueswir1 | } |
3354 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
3355 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
3356 | 9d1d4e34 | Richard Henderson | cpu_src1 = get_src1(dc, insn); |
3357 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3358 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3359 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3360 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
3361 | 1a2fb1c0 | blueswir1 | } else {
|
3362 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
|
3363 | 1a2fb1c0 | blueswir1 | } |
3364 | 0f8a249a | blueswir1 | } else { /* register */ |
3365 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3366 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
3367 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
3368 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3369 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
3370 | 1a2fb1c0 | blueswir1 | } else {
|
3371 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
3372 | 1a2fb1c0 | blueswir1 | } |
3373 | 01b1fa6d | blueswir1 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); |
3374 | 83469015 | bellard | } |
3375 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3376 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
3377 | 9d1d4e34 | Richard Henderson | cpu_src1 = get_src1(dc, insn); |
3378 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3379 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3380 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3381 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
3382 | 1a2fb1c0 | blueswir1 | } else {
|
3383 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
3384 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
3385 | 1a2fb1c0 | blueswir1 | } |
3386 | 0f8a249a | blueswir1 | } else { /* register */ |
3387 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3388 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
3389 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
3390 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3391 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
3392 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); |
3393 | 1a2fb1c0 | blueswir1 | } else {
|
3394 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
3395 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
3396 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); |
3397 | 1a2fb1c0 | blueswir1 | } |
3398 | 83469015 | bellard | } |
3399 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3400 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
3401 | 9d1d4e34 | Richard Henderson | cpu_src1 = get_src1(dc, insn); |
3402 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3403 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3404 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3405 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
3406 | 1a2fb1c0 | blueswir1 | } else {
|
3407 | 97ea2859 | Richard Henderson | tcg_gen_ext32s_i64(cpu_dst, cpu_src1); |
3408 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
3409 | 1a2fb1c0 | blueswir1 | } |
3410 | 0f8a249a | blueswir1 | } else { /* register */ |
3411 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3412 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
3413 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
3414 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
3415 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
3416 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); |
3417 | 1a2fb1c0 | blueswir1 | } else {
|
3418 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
3419 | 97ea2859 | Richard Henderson | tcg_gen_ext32s_i64(cpu_dst, cpu_src1); |
3420 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); |
3421 | 1a2fb1c0 | blueswir1 | } |
3422 | 83469015 | bellard | } |
3423 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3424 | 83469015 | bellard | #endif
|
3425 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
3426 | cf495bcf | bellard | if (xop < 0x20) { |
3427 | 9d1d4e34 | Richard Henderson | cpu_src1 = get_src1(dc, insn); |
3428 | 9d1d4e34 | Richard Henderson | cpu_src2 = get_src2(dc, insn); |
3429 | cf495bcf | bellard | switch (xop & ~0x10) { |
3430 | b89e94af | Blue Swirl | case 0x0: /* add */ |
3431 | 97ea2859 | Richard Henderson | if (xop & 0x10) { |
3432 | 97ea2859 | Richard Henderson | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
3433 | 97ea2859 | Richard Henderson | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
3434 | 97ea2859 | Richard Henderson | dc->cc_op = CC_OP_ADD; |
3435 | 41d72852 | Blue Swirl | } else {
|
3436 | 97ea2859 | Richard Henderson | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
3437 | 41d72852 | Blue Swirl | } |
3438 | cf495bcf | bellard | break;
|
3439 | b89e94af | Blue Swirl | case 0x1: /* and */ |
3440 | 97ea2859 | Richard Henderson | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
3441 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3442 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3443 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3444 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3445 | 41d72852 | Blue Swirl | } |
3446 | cf495bcf | bellard | break;
|
3447 | b89e94af | Blue Swirl | case 0x2: /* or */ |
3448 | 97ea2859 | Richard Henderson | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
3449 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3450 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3451 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3452 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3453 | 8393617c | Blue Swirl | } |
3454 | 0f8a249a | blueswir1 | break;
|
3455 | b89e94af | Blue Swirl | case 0x3: /* xor */ |
3456 | 97ea2859 | Richard Henderson | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3457 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3458 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3459 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3460 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3461 | 8393617c | Blue Swirl | } |
3462 | cf495bcf | bellard | break;
|
3463 | b89e94af | Blue Swirl | case 0x4: /* sub */ |
3464 | 97ea2859 | Richard Henderson | if (xop & 0x10) { |
3465 | 97ea2859 | Richard Henderson | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
3466 | 97ea2859 | Richard Henderson | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
3467 | 97ea2859 | Richard Henderson | dc->cc_op = CC_OP_SUB; |
3468 | 41d72852 | Blue Swirl | } else {
|
3469 | 97ea2859 | Richard Henderson | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
3470 | 41d72852 | Blue Swirl | } |
3471 | cf495bcf | bellard | break;
|
3472 | b89e94af | Blue Swirl | case 0x5: /* andn */ |
3473 | 97ea2859 | Richard Henderson | tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); |
3474 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3475 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3476 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3477 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3478 | 8393617c | Blue Swirl | } |
3479 | cf495bcf | bellard | break;
|
3480 | b89e94af | Blue Swirl | case 0x6: /* orn */ |
3481 | 97ea2859 | Richard Henderson | tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); |
3482 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3483 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3484 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3485 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3486 | 8393617c | Blue Swirl | } |
3487 | cf495bcf | bellard | break;
|
3488 | b89e94af | Blue Swirl | case 0x7: /* xorn */ |
3489 | 97ea2859 | Richard Henderson | tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2); |
3490 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3491 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3492 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3493 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3494 | 8393617c | Blue Swirl | } |
3495 | cf495bcf | bellard | break;
|
3496 | b89e94af | Blue Swirl | case 0x8: /* addx, V9 addc */ |
3497 | 70c48285 | Richard Henderson | gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2, |
3498 | 70c48285 | Richard Henderson | (xop & 0x10));
|
3499 | cf495bcf | bellard | break;
|
3500 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3501 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
3502 | 97ea2859 | Richard Henderson | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
3503 | ded3ab80 | pbrook | break;
|
3504 | ded3ab80 | pbrook | #endif
|
3505 | b89e94af | Blue Swirl | case 0xa: /* umul */ |
3506 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
3507 | 6ae20372 | blueswir1 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
3508 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3509 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3510 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3511 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3512 | 8393617c | Blue Swirl | } |
3513 | cf495bcf | bellard | break;
|
3514 | b89e94af | Blue Swirl | case 0xb: /* smul */ |
3515 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
3516 | 6ae20372 | blueswir1 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
3517 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3518 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3519 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3520 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3521 | 8393617c | Blue Swirl | } |
3522 | cf495bcf | bellard | break;
|
3523 | b89e94af | Blue Swirl | case 0xc: /* subx, V9 subc */ |
3524 | 70c48285 | Richard Henderson | gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, |
3525 | 70c48285 | Richard Henderson | (xop & 0x10));
|
3526 | cf495bcf | bellard | break;
|
3527 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3528 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
3529 | c28ae41e | Richard Henderson | gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2); |
3530 | ded3ab80 | pbrook | break;
|
3531 | ded3ab80 | pbrook | #endif
|
3532 | b89e94af | Blue Swirl | case 0xe: /* udiv */ |
3533 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3534 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3535 | 7a5e4488 | Blue Swirl | gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1, |
3536 | 7a5e4488 | Blue Swirl | cpu_src2); |
3537 | 6c78ea32 | Blue Swirl | dc->cc_op = CC_OP_DIV; |
3538 | 0fcec41e | Aurelien Jarno | } else {
|
3539 | 7a5e4488 | Blue Swirl | gen_helper_udiv(cpu_dst, cpu_env, cpu_src1, |
3540 | 7a5e4488 | Blue Swirl | cpu_src2); |
3541 | 8393617c | Blue Swirl | } |
3542 | cf495bcf | bellard | break;
|
3543 | b89e94af | Blue Swirl | case 0xf: /* sdiv */ |
3544 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3545 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3546 | 7a5e4488 | Blue Swirl | gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1, |
3547 | 7a5e4488 | Blue Swirl | cpu_src2); |
3548 | 6c78ea32 | Blue Swirl | dc->cc_op = CC_OP_DIV; |
3549 | 0fcec41e | Aurelien Jarno | } else {
|
3550 | 7a5e4488 | Blue Swirl | gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1, |
3551 | 7a5e4488 | Blue Swirl | cpu_src2); |
3552 | 8393617c | Blue Swirl | } |
3553 | cf495bcf | bellard | break;
|
3554 | cf495bcf | bellard | default:
|
3555 | cf495bcf | bellard | goto illegal_insn;
|
3556 | cf495bcf | bellard | } |
3557 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3558 | cf495bcf | bellard | } else {
|
3559 | 9d1d4e34 | Richard Henderson | cpu_src1 = get_src1(dc, insn); |
3560 | 9d1d4e34 | Richard Henderson | cpu_src2 = get_src2(dc, insn); |
3561 | cf495bcf | bellard | switch (xop) {
|
3562 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
3563 | a2ea4aa9 | Richard Henderson | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
3564 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3565 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD); |
3566 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TADD; |
3567 | 0f8a249a | blueswir1 | break;
|
3568 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
3569 | a2ea4aa9 | Richard Henderson | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
3570 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3571 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB); |
3572 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TSUB; |
3573 | 0f8a249a | blueswir1 | break;
|
3574 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
3575 | a2ea4aa9 | Richard Henderson | gen_helper_taddcctv(cpu_dst, cpu_env, |
3576 | a2ea4aa9 | Richard Henderson | cpu_src1, cpu_src2); |
3577 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3578 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TADDTV; |
3579 | 0f8a249a | blueswir1 | break;
|
3580 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
3581 | a2ea4aa9 | Richard Henderson | gen_helper_tsubcctv(cpu_dst, cpu_env, |
3582 | a2ea4aa9 | Richard Henderson | cpu_src1, cpu_src2); |
3583 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3584 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TSUBTV; |
3585 | 0f8a249a | blueswir1 | break;
|
3586 | cf495bcf | bellard | case 0x24: /* mulscc */ |
3587 | 20132b96 | Richard Henderson | update_psr(dc); |
3588 | 6ae20372 | blueswir1 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3589 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3590 | d084469c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
3591 | d084469c | Blue Swirl | dc->cc_op = CC_OP_ADD; |
3592 | cf495bcf | bellard | break;
|
3593 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
3594 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
3595 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3596 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3597 | 67526b20 | Blue Swirl | tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3598 | e35298cd | blueswir1 | } else { /* register */ |
3599 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
3600 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3601 | e35298cd | blueswir1 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3602 | e35298cd | blueswir1 | } |
3603 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3604 | cf495bcf | bellard | break;
|
3605 | 83469015 | bellard | case 0x26: /* srl */ |
3606 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3607 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3608 | 67526b20 | Blue Swirl | tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3609 | e35298cd | blueswir1 | } else { /* register */ |
3610 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
3611 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3612 | e35298cd | blueswir1 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3613 | e35298cd | blueswir1 | } |
3614 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3615 | cf495bcf | bellard | break;
|
3616 | 83469015 | bellard | case 0x27: /* sra */ |
3617 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3618 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3619 | 67526b20 | Blue Swirl | tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3620 | e35298cd | blueswir1 | } else { /* register */ |
3621 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
3622 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3623 | e35298cd | blueswir1 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3624 | e35298cd | blueswir1 | } |
3625 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
3626 | cf495bcf | bellard | break;
|
3627 | 83469015 | bellard | #endif
|
3628 | cf495bcf | bellard | case 0x30: |
3629 | cf495bcf | bellard | { |
3630 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
3631 | cf495bcf | bellard | switch(rd) {
|
3632 | 3475187d | bellard | case 0: /* wry */ |
3633 | 5068cbd9 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3634 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
3635 | cf495bcf | bellard | break;
|
3636 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
3637 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
3638 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
3639 | 65fe7b09 | blueswir1 | on the microSPARC
|
3640 | 65fe7b09 | blueswir1 | II */
|
3641 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
3642 | 65fe7b09 | blueswir1 | in the SPARCv8
|
3643 | 65fe7b09 | blueswir1 | manual, nop on the
|
3644 | 65fe7b09 | blueswir1 | microSPARC II */
|
3645 | 65fe7b09 | blueswir1 | break;
|
3646 | 65fe7b09 | blueswir1 | #else
|
3647 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
3648 | 7b04bd5c | Richard Henderson | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3649 | 7b04bd5c | Richard Henderson | gen_helper_wrccr(cpu_env, cpu_tmp0); |
3650 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3651 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3652 | 0f8a249a | blueswir1 | break;
|
3653 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
3654 | 7b04bd5c | Richard Henderson | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3655 | 7b04bd5c | Richard Henderson | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
|
3656 | 7b04bd5c | Richard Henderson | tcg_gen_trunc_tl_i32(cpu_asi, cpu_tmp0); |
3657 | 0f8a249a | blueswir1 | break;
|
3658 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
3659 | 7b04bd5c | Richard Henderson | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3660 | 7b04bd5c | Richard Henderson | tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0); |
3661 | 66442b07 | Richard Henderson | save_state(dc); |
3662 | 3299908c | blueswir1 | gen_op_next_insn(); |
3663 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3664 | 3299908c | blueswir1 | dc->is_br = 1;
|
3665 | 0f8a249a | blueswir1 | break;
|
3666 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
3667 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
3668 | 6ad6135d | Blue Swirl | if (supervisor(dc)) {
|
3669 | 1a2fb1c0 | blueswir1 | ; // XXX
|
3670 | 6ad6135d | Blue Swirl | } |
3671 | 3475187d | bellard | #endif
|
3672 | 0f8a249a | blueswir1 | break;
|
3673 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
3674 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
3675 | 725cb90b | bellard | goto jmp_insn;
|
3676 | 5b12f1e8 | Richard Henderson | } |
3677 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); |
3678 | 0f8a249a | blueswir1 | break;
|
3679 | 9d926598 | blueswir1 | case 0x14: /* Softint set */ |
3680 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3681 | 9d926598 | blueswir1 | goto illegal_insn;
|
3682 | aeff993c | Richard Henderson | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3683 | aeff993c | Richard Henderson | gen_helper_set_softint(cpu_env, cpu_tmp0); |
3684 | 9d926598 | blueswir1 | break;
|
3685 | 9d926598 | blueswir1 | case 0x15: /* Softint clear */ |
3686 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3687 | 9d926598 | blueswir1 | goto illegal_insn;
|
3688 | aeff993c | Richard Henderson | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3689 | aeff993c | Richard Henderson | gen_helper_clear_softint(cpu_env, cpu_tmp0); |
3690 | 9d926598 | blueswir1 | break;
|
3691 | 9d926598 | blueswir1 | case 0x16: /* Softint write */ |
3692 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3693 | 9d926598 | blueswir1 | goto illegal_insn;
|
3694 | aeff993c | Richard Henderson | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3695 | aeff993c | Richard Henderson | gen_helper_write_softint(cpu_env, cpu_tmp0); |
3696 | 9d926598 | blueswir1 | break;
|
3697 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
3698 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3699 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3700 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3701 | 83469015 | bellard | #endif
|
3702 | ccd4a219 | blueswir1 | { |
3703 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3704 | ccd4a219 | blueswir1 | |
3705 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, |
3706 | 6ae20372 | blueswir1 | cpu_src2); |
3707 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3708 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3709 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, tick)); |
3710 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3711 | a7812ae4 | pbrook | cpu_tick_cmpr); |
3712 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3713 | ccd4a219 | blueswir1 | } |
3714 | 0f8a249a | blueswir1 | break;
|
3715 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
3716 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3717 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3718 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3719 | 83469015 | bellard | #endif
|
3720 | ccd4a219 | blueswir1 | { |
3721 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3722 | ccd4a219 | blueswir1 | |
3723 | 7b04bd5c | Richard Henderson | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, |
3724 | 6ae20372 | blueswir1 | cpu_src2); |
3725 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3726 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3727 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, stick)); |
3728 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3729 | 7b04bd5c | Richard Henderson | cpu_tmp0); |
3730 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3731 | ccd4a219 | blueswir1 | } |
3732 | 0f8a249a | blueswir1 | break;
|
3733 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
3734 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3735 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3736 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3737 | 3475187d | bellard | #endif
|
3738 | ccd4a219 | blueswir1 | { |
3739 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3740 | ccd4a219 | blueswir1 | |
3741 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, |
3742 | 6ae20372 | blueswir1 | cpu_src2); |
3743 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3744 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3745 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, stick)); |
3746 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3747 | a7812ae4 | pbrook | cpu_stick_cmpr); |
3748 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3749 | ccd4a219 | blueswir1 | } |
3750 | 0f8a249a | blueswir1 | break;
|
3751 | 83469015 | bellard | |
3752 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
3753 | 77f193da | blueswir1 | case 0x11: /* Performance Instrumentation |
3754 | 77f193da | blueswir1 | Counter */
|
3755 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
3756 | 83469015 | bellard | #endif
|
3757 | 3475187d | bellard | default:
|
3758 | cf495bcf | bellard | goto illegal_insn;
|
3759 | cf495bcf | bellard | } |
3760 | cf495bcf | bellard | } |
3761 | cf495bcf | bellard | break;
|
3762 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3763 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
3764 | e8af50a3 | bellard | { |
3765 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3766 | 0f8a249a | blueswir1 | goto priv_insn;
|
3767 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3768 | 0f8a249a | blueswir1 | switch (rd) {
|
3769 | 0f8a249a | blueswir1 | case 0: |
3770 | 063c3675 | Blue Swirl | gen_helper_saved(cpu_env); |
3771 | 0f8a249a | blueswir1 | break;
|
3772 | 0f8a249a | blueswir1 | case 1: |
3773 | 063c3675 | Blue Swirl | gen_helper_restored(cpu_env); |
3774 | 0f8a249a | blueswir1 | break;
|
3775 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
3776 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
3777 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
3778 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
3779 | e9ebed4d | blueswir1 | // XXX
|
3780 | 0f8a249a | blueswir1 | default:
|
3781 | 3475187d | bellard | goto illegal_insn;
|
3782 | 3475187d | bellard | } |
3783 | 3475187d | bellard | #else
|
3784 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
3785 | 7b04bd5c | Richard Henderson | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3786 | 7b04bd5c | Richard Henderson | gen_helper_wrpsr(cpu_env, cpu_tmp0); |
3787 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3788 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3789 | 66442b07 | Richard Henderson | save_state(dc); |
3790 | 9e61bde5 | bellard | gen_op_next_insn(); |
3791 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3792 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3793 | 3475187d | bellard | #endif
|
3794 | e8af50a3 | bellard | } |
3795 | e8af50a3 | bellard | break;
|
3796 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
3797 | e8af50a3 | bellard | { |
3798 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3799 | 0f8a249a | blueswir1 | goto priv_insn;
|
3800 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
3801 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3802 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3803 | 0f8a249a | blueswir1 | switch (rd) {
|
3804 | 0f8a249a | blueswir1 | case 0: // tpc |
3805 | 375ee38b | blueswir1 | { |
3806 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3807 | 375ee38b | blueswir1 | |
3808 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3809 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3810 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3811 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
3812 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3813 | 375ee38b | blueswir1 | } |
3814 | 0f8a249a | blueswir1 | break;
|
3815 | 0f8a249a | blueswir1 | case 1: // tnpc |
3816 | 375ee38b | blueswir1 | { |
3817 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3818 | 375ee38b | blueswir1 | |
3819 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3820 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3821 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3822 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
3823 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3824 | 375ee38b | blueswir1 | } |
3825 | 0f8a249a | blueswir1 | break;
|
3826 | 0f8a249a | blueswir1 | case 2: // tstate |
3827 | 375ee38b | blueswir1 | { |
3828 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3829 | 375ee38b | blueswir1 | |
3830 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3831 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3832 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3833 | 77f193da | blueswir1 | offsetof(trap_state, |
3834 | 77f193da | blueswir1 | tstate)); |
3835 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3836 | 375ee38b | blueswir1 | } |
3837 | 0f8a249a | blueswir1 | break;
|
3838 | 0f8a249a | blueswir1 | case 3: // tt |
3839 | 375ee38b | blueswir1 | { |
3840 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3841 | 375ee38b | blueswir1 | |
3842 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3843 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3844 | 7b9e066b | Richard Henderson | tcg_gen_st32_tl(cpu_tmp0, r_tsptr, |
3845 | 7b9e066b | Richard Henderson | offsetof(trap_state, tt)); |
3846 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3847 | 375ee38b | blueswir1 | } |
3848 | 0f8a249a | blueswir1 | break;
|
3849 | 0f8a249a | blueswir1 | case 4: // tick |
3850 | ccd4a219 | blueswir1 | { |
3851 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3852 | ccd4a219 | blueswir1 | |
3853 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3854 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3855 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, tick)); |
3856 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3857 | a7812ae4 | pbrook | cpu_tmp0); |
3858 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3859 | ccd4a219 | blueswir1 | } |
3860 | 0f8a249a | blueswir1 | break;
|
3861 | 0f8a249a | blueswir1 | case 5: // tba |
3862 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); |
3863 | 0f8a249a | blueswir1 | break;
|
3864 | 0f8a249a | blueswir1 | case 6: // pstate |
3865 | 6234ac09 | Richard Henderson | save_state(dc); |
3866 | 6234ac09 | Richard Henderson | gen_helper_wrpstate(cpu_env, cpu_tmp0); |
3867 | 6234ac09 | Richard Henderson | dc->npc = DYNAMIC_PC; |
3868 | 0f8a249a | blueswir1 | break;
|
3869 | 0f8a249a | blueswir1 | case 7: // tl |
3870 | 6234ac09 | Richard Henderson | save_state(dc); |
3871 | 7b9e066b | Richard Henderson | tcg_gen_st32_tl(cpu_tmp0, cpu_env, |
3872 | 6234ac09 | Richard Henderson | offsetof(CPUSPARCState, tl)); |
3873 | 6234ac09 | Richard Henderson | dc->npc = DYNAMIC_PC; |
3874 | 0f8a249a | blueswir1 | break;
|
3875 | 0f8a249a | blueswir1 | case 8: // pil |
3876 | 063c3675 | Blue Swirl | gen_helper_wrpil(cpu_env, cpu_tmp0); |
3877 | 0f8a249a | blueswir1 | break;
|
3878 | 0f8a249a | blueswir1 | case 9: // cwp |
3879 | 063c3675 | Blue Swirl | gen_helper_wrcwp(cpu_env, cpu_tmp0); |
3880 | 0f8a249a | blueswir1 | break;
|
3881 | 0f8a249a | blueswir1 | case 10: // cansave |
3882 | 7b9e066b | Richard Henderson | tcg_gen_st32_tl(cpu_tmp0, cpu_env, |
3883 | 7b9e066b | Richard Henderson | offsetof(CPUSPARCState, |
3884 | 7b9e066b | Richard Henderson | cansave)); |
3885 | 0f8a249a | blueswir1 | break;
|
3886 | 0f8a249a | blueswir1 | case 11: // canrestore |
3887 | 7b9e066b | Richard Henderson | tcg_gen_st32_tl(cpu_tmp0, cpu_env, |
3888 | 7b9e066b | Richard Henderson | offsetof(CPUSPARCState, |
3889 | 7b9e066b | Richard Henderson | canrestore)); |
3890 | 0f8a249a | blueswir1 | break;
|
3891 | 0f8a249a | blueswir1 | case 12: // cleanwin |
3892 | 7b9e066b | Richard Henderson | tcg_gen_st32_tl(cpu_tmp0, cpu_env, |
3893 | 7b9e066b | Richard Henderson | offsetof(CPUSPARCState, |
3894 | 7b9e066b | Richard Henderson | cleanwin)); |
3895 | 0f8a249a | blueswir1 | break;
|
3896 | 0f8a249a | blueswir1 | case 13: // otherwin |
3897 | 7b9e066b | Richard Henderson | tcg_gen_st32_tl(cpu_tmp0, cpu_env, |
3898 | 7b9e066b | Richard Henderson | offsetof(CPUSPARCState, |
3899 | 7b9e066b | Richard Henderson | otherwin)); |
3900 | 0f8a249a | blueswir1 | break;
|
3901 | 0f8a249a | blueswir1 | case 14: // wstate |
3902 | 7b9e066b | Richard Henderson | tcg_gen_st32_tl(cpu_tmp0, cpu_env, |
3903 | 7b9e066b | Richard Henderson | offsetof(CPUSPARCState, |
3904 | 7b9e066b | Richard Henderson | wstate)); |
3905 | 0f8a249a | blueswir1 | break;
|
3906 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
3907 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
3908 | 7b9e066b | Richard Henderson | tcg_gen_st32_tl(cpu_tmp0, cpu_env, |
3909 | 7b9e066b | Richard Henderson | offsetof(CPUSPARCState, gl)); |
3910 | e9ebed4d | blueswir1 | break;
|
3911 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
3912 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3913 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3914 | e9ebed4d | blueswir1 | goto priv_insn;
|
3915 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_ssr, cpu_tmp0); |
3916 | e9ebed4d | blueswir1 | break;
|
3917 | 0f8a249a | blueswir1 | default:
|
3918 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3919 | 0f8a249a | blueswir1 | } |
3920 | 3475187d | bellard | #else
|
3921 | 7b9e066b | Richard Henderson | tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0); |
3922 | 7b9e066b | Richard Henderson | if (dc->def->nwindows != 32) { |
3923 | 7b9e066b | Richard Henderson | tcg_gen_andi_tl(cpu_wim, cpu_wim, |
3924 | c93e7817 | blueswir1 | (1 << dc->def->nwindows) - 1); |
3925 | 7b9e066b | Richard Henderson | } |
3926 | 3475187d | bellard | #endif
|
3927 | e8af50a3 | bellard | } |
3928 | e8af50a3 | bellard | break;
|
3929 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
3930 | e8af50a3 | bellard | { |
3931 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
3932 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3933 | 0f8a249a | blueswir1 | goto priv_insn;
|
3934 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); |
3935 | e9ebed4d | blueswir1 | #else
|
3936 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3937 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3938 | e9ebed4d | blueswir1 | goto priv_insn;
|
3939 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
3940 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3941 | e9ebed4d | blueswir1 | switch (rd) {
|
3942 | e9ebed4d | blueswir1 | case 0: // hpstate |
3943 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
3944 | 66442b07 | Richard Henderson | save_state(dc); |
3945 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
3946 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3947 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
3948 | e9ebed4d | blueswir1 | break;
|
3949 | e9ebed4d | blueswir1 | case 1: // htstate |
3950 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
3951 | e9ebed4d | blueswir1 | break;
|
3952 | e9ebed4d | blueswir1 | case 3: // hintp |
3953 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); |
3954 | e9ebed4d | blueswir1 | break;
|
3955 | e9ebed4d | blueswir1 | case 5: // htba |
3956 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_htba, cpu_tmp0); |
3957 | e9ebed4d | blueswir1 | break;
|
3958 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
3959 | ccd4a219 | blueswir1 | { |
3960 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3961 | ccd4a219 | blueswir1 | |
3962 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); |
3963 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3964 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3965 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, hstick)); |
3966 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3967 | a7812ae4 | pbrook | cpu_hstick_cmpr); |
3968 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3969 | ccd4a219 | blueswir1 | } |
3970 | e9ebed4d | blueswir1 | break;
|
3971 | e9ebed4d | blueswir1 | case 6: // hver readonly |
3972 | e9ebed4d | blueswir1 | default:
|
3973 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3974 | e9ebed4d | blueswir1 | } |
3975 | e9ebed4d | blueswir1 | #endif
|
3976 | e8af50a3 | bellard | } |
3977 | e8af50a3 | bellard | break;
|
3978 | e8af50a3 | bellard | #endif
|
3979 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3980 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
3981 | 0f8a249a | blueswir1 | { |
3982 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
3983 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
3984 | f52879b4 | Richard Henderson | DisasCompare cmp; |
3985 | 97ea2859 | Richard Henderson | TCGv dst; |
3986 | 00f219bf | blueswir1 | |
3987 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
3988 | f52879b4 | Richard Henderson | if (cc == 0) { |
3989 | f52879b4 | Richard Henderson | gen_compare(&cmp, 0, cond, dc);
|
3990 | f52879b4 | Richard Henderson | } else if (cc == 2) { |
3991 | f52879b4 | Richard Henderson | gen_compare(&cmp, 1, cond, dc);
|
3992 | f52879b4 | Richard Henderson | } else {
|
3993 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3994 | f52879b4 | Richard Henderson | } |
3995 | 0f8a249a | blueswir1 | } else {
|
3996 | f52879b4 | Richard Henderson | gen_fcompare(&cmp, cc, cond); |
3997 | 0f8a249a | blueswir1 | } |
3998 | 00f219bf | blueswir1 | |
3999 | f52879b4 | Richard Henderson | /* The get_src2 above loaded the normal 13-bit
|
4000 | f52879b4 | Richard Henderson | immediate field, not the 11-bit field we have
|
4001 | f52879b4 | Richard Henderson | in movcc. But it did handle the reg case. */
|
4002 | f52879b4 | Richard Henderson | if (IS_IMM) {
|
4003 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 10); |
4004 | f52879b4 | Richard Henderson | tcg_gen_movi_tl(cpu_src2, simm); |
4005 | 00f219bf | blueswir1 | } |
4006 | f52879b4 | Richard Henderson | |
4007 | 97ea2859 | Richard Henderson | dst = gen_load_gpr(dc, rd); |
4008 | 97ea2859 | Richard Henderson | tcg_gen_movcond_tl(cmp.cond, dst, |
4009 | f52879b4 | Richard Henderson | cmp.c1, cmp.c2, |
4010 | 97ea2859 | Richard Henderson | cpu_src2, dst); |
4011 | f52879b4 | Richard Henderson | free_compare(&cmp); |
4012 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, dst); |
4013 | 0f8a249a | blueswir1 | break;
|
4014 | 0f8a249a | blueswir1 | } |
4015 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
4016 | c28ae41e | Richard Henderson | gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2); |
4017 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4018 | 0f8a249a | blueswir1 | break;
|
4019 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
4020 | 97ea2859 | Richard Henderson | gen_helper_popc(cpu_dst, cpu_src2); |
4021 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4022 | 97ea2859 | Richard Henderson | break;
|
4023 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
4024 | 0f8a249a | blueswir1 | { |
4025 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
4026 | c33f80f5 | Richard Henderson | DisasCompare cmp; |
4027 | 97ea2859 | Richard Henderson | TCGv dst; |
4028 | 00f219bf | blueswir1 | |
4029 | c33f80f5 | Richard Henderson | gen_compare_reg(&cmp, cond, cpu_src1); |
4030 | 2ea815ca | blueswir1 | |
4031 | c33f80f5 | Richard Henderson | /* The get_src2 above loaded the normal 13-bit
|
4032 | c33f80f5 | Richard Henderson | immediate field, not the 10-bit field we have
|
4033 | c33f80f5 | Richard Henderson | in movr. But it did handle the reg case. */
|
4034 | c33f80f5 | Richard Henderson | if (IS_IMM) {
|
4035 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 9); |
4036 | c33f80f5 | Richard Henderson | tcg_gen_movi_tl(cpu_src2, simm); |
4037 | 0f8a249a | blueswir1 | } |
4038 | c33f80f5 | Richard Henderson | |
4039 | 97ea2859 | Richard Henderson | dst = gen_load_gpr(dc, rd); |
4040 | 97ea2859 | Richard Henderson | tcg_gen_movcond_tl(cmp.cond, dst, |
4041 | c33f80f5 | Richard Henderson | cmp.c1, cmp.c2, |
4042 | 97ea2859 | Richard Henderson | cpu_src2, dst); |
4043 | c33f80f5 | Richard Henderson | free_compare(&cmp); |
4044 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, dst); |
4045 | 0f8a249a | blueswir1 | break;
|
4046 | 0f8a249a | blueswir1 | } |
4047 | 0f8a249a | blueswir1 | #endif
|
4048 | 0f8a249a | blueswir1 | default:
|
4049 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4050 | 0f8a249a | blueswir1 | } |
4051 | 0f8a249a | blueswir1 | } |
4052 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
4053 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
4054 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
4055 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
4056 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4057 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
4058 | e9ebed4d | blueswir1 | goto jmp_insn;
|
4059 | 5b12f1e8 | Richard Henderson | } |
4060 | 3299908c | blueswir1 | |
4061 | 3299908c | blueswir1 | switch (opf) {
|
4062 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
4063 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4064 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4065 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4066 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0); |
4067 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4068 | 6c073553 | Richard Henderson | break;
|
4069 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
4070 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS2); |
4071 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4072 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4073 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0); |
4074 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4075 | 6c073553 | Richard Henderson | break;
|
4076 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
4077 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4078 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4079 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4080 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1); |
4081 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4082 | 6c073553 | Richard Henderson | break;
|
4083 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
4084 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS2); |
4085 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4086 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4087 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1); |
4088 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4089 | 6c073553 | Richard Henderson | break;
|
4090 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
4091 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4092 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4093 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4094 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0); |
4095 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4096 | 6c073553 | Richard Henderson | break;
|
4097 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
4098 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS2); |
4099 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4100 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4101 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0); |
4102 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4103 | 6c073553 | Richard Henderson | break;
|
4104 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
4105 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4106 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4107 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4108 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1); |
4109 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4110 | 6c073553 | Richard Henderson | break;
|
4111 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
4112 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS2); |
4113 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4114 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4115 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1); |
4116 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4117 | 6c073553 | Richard Henderson | break;
|
4118 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
4119 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4120 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4121 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4122 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0); |
4123 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4124 | 6c073553 | Richard Henderson | break;
|
4125 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
4126 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS2); |
4127 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4128 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4129 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0); |
4130 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4131 | 6c073553 | Richard Henderson | break;
|
4132 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
4133 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4134 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4135 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4136 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1); |
4137 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4138 | 6c073553 | Richard Henderson | break;
|
4139 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
4140 | 6c073553 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS2); |
4141 | 97ea2859 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4142 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4143 | 6c073553 | Richard Henderson | gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1); |
4144 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4145 | 6c073553 | Richard Henderson | break;
|
4146 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
4147 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4148 | 9d1d4e34 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4149 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4150 | f027c3b1 | Richard Henderson | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
4151 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4152 | e9ebed4d | blueswir1 | break;
|
4153 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
4154 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4155 | 9d1d4e34 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4156 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4157 | f027c3b1 | Richard Henderson | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
4158 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
|
4159 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4160 | e9ebed4d | blueswir1 | break;
|
4161 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
4162 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4163 | 9d1d4e34 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4164 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4165 | f027c3b1 | Richard Henderson | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
4166 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
|
4167 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4168 | e9ebed4d | blueswir1 | break;
|
4169 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
4170 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4171 | 9d1d4e34 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4172 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4173 | add545ab | Richard Henderson | gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
|
4174 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4175 | 3299908c | blueswir1 | break;
|
4176 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
4177 | add545ab | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4178 | 9d1d4e34 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4179 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4180 | add545ab | Richard Henderson | gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
|
4181 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4182 | add545ab | Richard Henderson | break;
|
4183 | add545ab | Richard Henderson | case 0x019: /* VIS II bmask */ |
4184 | 793a137a | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS2); |
4185 | 9d1d4e34 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rs1); |
4186 | 9d1d4e34 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4187 | 793a137a | Richard Henderson | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4188 | 793a137a | Richard Henderson | tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32); |
4189 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4190 | 793a137a | Richard Henderson | break;
|
4191 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
4192 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4193 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
4194 | 03fb8cfc | Richard Henderson | cpu_src2_64 = gen_load_fpr_D(dc, rs2); |
4195 | f027c3b1 | Richard Henderson | gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64); |
4196 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4197 | e9ebed4d | blueswir1 | break;
|
4198 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
4199 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4200 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
4201 | 03fb8cfc | Richard Henderson | cpu_src2_64 = gen_load_fpr_D(dc, rs2); |
4202 | f027c3b1 | Richard Henderson | gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64); |
4203 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4204 | 3299908c | blueswir1 | break;
|
4205 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
4206 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4207 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
4208 | 03fb8cfc | Richard Henderson | cpu_src2_64 = gen_load_fpr_D(dc, rs2); |
4209 | f027c3b1 | Richard Henderson | gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64); |
4210 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4211 | e9ebed4d | blueswir1 | break;
|
4212 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
4213 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4214 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
4215 | 03fb8cfc | Richard Henderson | cpu_src2_64 = gen_load_fpr_D(dc, rs2); |
4216 | f027c3b1 | Richard Henderson | gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64); |
4217 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4218 | e9ebed4d | blueswir1 | break;
|
4219 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
4220 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4221 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
4222 | 03fb8cfc | Richard Henderson | cpu_src2_64 = gen_load_fpr_D(dc, rs2); |
4223 | f027c3b1 | Richard Henderson | gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64); |
4224 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4225 | e9ebed4d | blueswir1 | break;
|
4226 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
4227 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4228 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
4229 | 03fb8cfc | Richard Henderson | cpu_src2_64 = gen_load_fpr_D(dc, rs2); |
4230 | f027c3b1 | Richard Henderson | gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64); |
4231 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4232 | e9ebed4d | blueswir1 | break;
|
4233 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
4234 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4235 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
4236 | 03fb8cfc | Richard Henderson | cpu_src2_64 = gen_load_fpr_D(dc, rs2); |
4237 | f027c3b1 | Richard Henderson | gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64); |
4238 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4239 | e9ebed4d | blueswir1 | break;
|
4240 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
4241 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4242 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
4243 | 03fb8cfc | Richard Henderson | cpu_src2_64 = gen_load_fpr_D(dc, rs2); |
4244 | f027c3b1 | Richard Henderson | gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); |
4245 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_dst); |
4246 | e9ebed4d | blueswir1 | break;
|
4247 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
4248 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4249 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16); |
4250 | e9ebed4d | blueswir1 | break;
|
4251 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
4252 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4253 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au); |
4254 | e9ebed4d | blueswir1 | break;
|
4255 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
4256 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4257 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al); |
4258 | e9ebed4d | blueswir1 | break;
|
4259 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
4260 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4261 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16); |
4262 | e9ebed4d | blueswir1 | break;
|
4263 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
4264 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4265 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16); |
4266 | e9ebed4d | blueswir1 | break;
|
4267 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
4268 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4269 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16); |
4270 | e9ebed4d | blueswir1 | break;
|
4271 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
4272 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4273 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16); |
4274 | e9ebed4d | blueswir1 | break;
|
4275 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
4276 | 2dedf314 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4277 | 2dedf314 | Richard Henderson | gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32); |
4278 | 2dedf314 | Richard Henderson | break;
|
4279 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
4280 | 2dedf314 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4281 | 2dedf314 | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs2); |
4282 | ba5f5179 | Richard Henderson | cpu_dst_32 = gen_dest_fpr_F(dc); |
4283 | 2dedf314 | Richard Henderson | gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64); |
4284 | 2dedf314 | Richard Henderson | gen_store_fpr_F(dc, rd, cpu_dst_32); |
4285 | 2dedf314 | Richard Henderson | break;
|
4286 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
4287 | 2dedf314 | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4288 | 2dedf314 | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs2); |
4289 | ba5f5179 | Richard Henderson | cpu_dst_32 = gen_dest_fpr_F(dc); |
4290 | 2dedf314 | Richard Henderson | gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); |
4291 | 2dedf314 | Richard Henderson | gen_store_fpr_F(dc, rd, cpu_dst_32); |
4292 | 2dedf314 | Richard Henderson | break;
|
4293 | f888300b | Richard Henderson | case 0x03e: /* VIS I pdist */ |
4294 | f888300b | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS1); |
4295 | f888300b | Richard Henderson | gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist); |
4296 | f888300b | Richard Henderson | break;
|
4297 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
4298 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4299 | 50c796f9 | Richard Henderson | gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); |
4300 | 3299908c | blueswir1 | break;
|
4301 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
4302 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4303 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge); |
4304 | e9ebed4d | blueswir1 | break;
|
4305 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
4306 | 793a137a | Richard Henderson | CHECK_FPU_FEATURE(dc, VIS2); |
4307 | 793a137a | Richard Henderson | gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); |
4308 | 793a137a | Richard Henderson | break;
|
4309 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
4310 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4311 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand); |
4312 | e9ebed4d | blueswir1 | break;
|
4313 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
4314 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4315 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16); |
4316 | e9ebed4d | blueswir1 | break;
|
4317 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
4318 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4319 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s); |
4320 | e9ebed4d | blueswir1 | break;
|
4321 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
4322 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4323 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32); |
4324 | e9ebed4d | blueswir1 | break;
|
4325 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
4326 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4327 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32); |
4328 | e9ebed4d | blueswir1 | break;
|
4329 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
4330 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4331 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16); |
4332 | e9ebed4d | blueswir1 | break;
|
4333 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
4334 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4335 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s); |
4336 | e9ebed4d | blueswir1 | break;
|
4337 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
4338 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4339 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32); |
4340 | e9ebed4d | blueswir1 | break;
|
4341 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
4342 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4343 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32); |
4344 | e9ebed4d | blueswir1 | break;
|
4345 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
4346 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4347 | 3886b8a3 | Richard Henderson | cpu_dst_64 = gen_dest_fpr_D(dc, rd); |
4348 | 96eda024 | Richard Henderson | tcg_gen_movi_i64(cpu_dst_64, 0);
|
4349 | 96eda024 | Richard Henderson | gen_store_fpr_D(dc, rd, cpu_dst_64); |
4350 | 3299908c | blueswir1 | break;
|
4351 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
4352 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4353 | ba5f5179 | Richard Henderson | cpu_dst_32 = gen_dest_fpr_F(dc); |
4354 | 208ae657 | Richard Henderson | tcg_gen_movi_i32(cpu_dst_32, 0);
|
4355 | 208ae657 | Richard Henderson | gen_store_fpr_F(dc, rd, cpu_dst_32); |
4356 | 3299908c | blueswir1 | break;
|
4357 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
4358 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4359 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64); |
4360 | e9ebed4d | blueswir1 | break;
|
4361 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
4362 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4363 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32); |
4364 | e9ebed4d | blueswir1 | break;
|
4365 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
4366 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4367 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64); |
4368 | e9ebed4d | blueswir1 | break;
|
4369 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
4370 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4371 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32); |
4372 | e9ebed4d | blueswir1 | break;
|
4373 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
4374 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4375 | 61f17f6e | Richard Henderson | gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64); |
4376 | e9ebed4d | blueswir1 | break;
|
4377 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
4378 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4379 | 61f17f6e | Richard Henderson | gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32); |
4380 | e9ebed4d | blueswir1 | break;
|
4381 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
4382 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4383 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); |
4384 | e9ebed4d | blueswir1 | break;
|
4385 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
4386 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4387 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32); |
4388 | e9ebed4d | blueswir1 | break;
|
4389 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
4390 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4391 | 61f17f6e | Richard Henderson | gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64); |
4392 | e9ebed4d | blueswir1 | break;
|
4393 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
4394 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4395 | 61f17f6e | Richard Henderson | gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32); |
4396 | e9ebed4d | blueswir1 | break;
|
4397 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
4398 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4399 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); |
4400 | e9ebed4d | blueswir1 | break;
|
4401 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
4402 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4403 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32); |
4404 | e9ebed4d | blueswir1 | break;
|
4405 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
4406 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4407 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64); |
4408 | e9ebed4d | blueswir1 | break;
|
4409 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
4410 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4411 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32); |
4412 | e9ebed4d | blueswir1 | break;
|
4413 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
4414 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4415 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64); |
4416 | e9ebed4d | blueswir1 | break;
|
4417 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
4418 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4419 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32); |
4420 | e9ebed4d | blueswir1 | break;
|
4421 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
4422 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4423 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64); |
4424 | e9ebed4d | blueswir1 | break;
|
4425 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
4426 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4427 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32); |
4428 | e9ebed4d | blueswir1 | break;
|
4429 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
4430 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4431 | 96eda024 | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs1); |
4432 | 96eda024 | Richard Henderson | gen_store_fpr_D(dc, rd, cpu_src1_64); |
4433 | 3299908c | blueswir1 | break;
|
4434 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
4435 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4436 | 208ae657 | Richard Henderson | cpu_src1_32 = gen_load_fpr_F(dc, rs1); |
4437 | 208ae657 | Richard Henderson | gen_store_fpr_F(dc, rd, cpu_src1_32); |
4438 | 3299908c | blueswir1 | break;
|
4439 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
4440 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4441 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64); |
4442 | e9ebed4d | blueswir1 | break;
|
4443 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
4444 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4445 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32); |
4446 | e9ebed4d | blueswir1 | break;
|
4447 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
4448 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4449 | 96eda024 | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rs2); |
4450 | 96eda024 | Richard Henderson | gen_store_fpr_D(dc, rd, cpu_src1_64); |
4451 | 3299908c | blueswir1 | break;
|
4452 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
4453 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4454 | 208ae657 | Richard Henderson | cpu_src1_32 = gen_load_fpr_F(dc, rs2); |
4455 | 208ae657 | Richard Henderson | gen_store_fpr_F(dc, rd, cpu_src1_32); |
4456 | 3299908c | blueswir1 | break;
|
4457 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
4458 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4459 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); |
4460 | e9ebed4d | blueswir1 | break;
|
4461 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
4462 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4463 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32); |
4464 | e9ebed4d | blueswir1 | break;
|
4465 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
4466 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4467 | 61f17f6e | Richard Henderson | gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64); |
4468 | e9ebed4d | blueswir1 | break;
|
4469 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
4470 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4471 | 61f17f6e | Richard Henderson | gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32); |
4472 | e9ebed4d | blueswir1 | break;
|
4473 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
4474 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4475 | 3886b8a3 | Richard Henderson | cpu_dst_64 = gen_dest_fpr_D(dc, rd); |
4476 | 96eda024 | Richard Henderson | tcg_gen_movi_i64(cpu_dst_64, -1);
|
4477 | 96eda024 | Richard Henderson | gen_store_fpr_D(dc, rd, cpu_dst_64); |
4478 | 3299908c | blueswir1 | break;
|
4479 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
4480 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4481 | ba5f5179 | Richard Henderson | cpu_dst_32 = gen_dest_fpr_F(dc); |
4482 | 208ae657 | Richard Henderson | tcg_gen_movi_i32(cpu_dst_32, -1);
|
4483 | 208ae657 | Richard Henderson | gen_store_fpr_F(dc, rd, cpu_dst_32); |
4484 | 3299908c | blueswir1 | break;
|
4485 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
4486 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
4487 | e9ebed4d | blueswir1 | // XXX
|
4488 | e9ebed4d | blueswir1 | goto illegal_insn;
|
4489 | 3299908c | blueswir1 | default:
|
4490 | 3299908c | blueswir1 | goto illegal_insn;
|
4491 | 3299908c | blueswir1 | } |
4492 | 3299908c | blueswir1 | #else
|
4493 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4494 | 3299908c | blueswir1 | #endif
|
4495 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
4496 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
4497 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4498 | fcc72045 | blueswir1 | #else
|
4499 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4500 | fcc72045 | blueswir1 | #endif
|
4501 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4502 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
4503 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4504 | 2ea815ca | blueswir1 | |
4505 | 66442b07 | Richard Henderson | save_state(dc); |
4506 | 9d1d4e34 | Richard Henderson | cpu_src1 = get_src1(dc, insn); |
4507 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
4508 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4509 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4510 | 7b04bd5c | Richard Henderson | tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); |
4511 | 0f8a249a | blueswir1 | } else { /* register */ |
4512 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4513 | 0f8a249a | blueswir1 | if (rs2) {
|
4514 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4515 | 7b04bd5c | Richard Henderson | tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2); |
4516 | 97ea2859 | Richard Henderson | } else {
|
4517 | 7b04bd5c | Richard Henderson | tcg_gen_mov_tl(cpu_tmp0, cpu_src1); |
4518 | 97ea2859 | Richard Henderson | } |
4519 | 3475187d | bellard | } |
4520 | 063c3675 | Blue Swirl | gen_helper_restore(cpu_env); |
4521 | 13a6dd00 | Richard Henderson | gen_mov_pc_npc(dc); |
4522 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4523 | 7b04bd5c | Richard Henderson | gen_helper_check_align(cpu_env, cpu_tmp0, r_const); |
4524 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4525 | 7b04bd5c | Richard Henderson | tcg_gen_mov_tl(cpu_npc, cpu_tmp0); |
4526 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4527 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4528 | 3475187d | bellard | #endif
|
4529 | 0f8a249a | blueswir1 | } else {
|
4530 | 9d1d4e34 | Richard Henderson | cpu_src1 = get_src1(dc, insn); |
4531 | de9e9d9f | Richard Henderson | cpu_tmp0 = get_temp_tl(dc); |
4532 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4533 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4534 | 7b04bd5c | Richard Henderson | tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); |
4535 | 0f8a249a | blueswir1 | } else { /* register */ |
4536 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4537 | 0f8a249a | blueswir1 | if (rs2) {
|
4538 | 97ea2859 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
4539 | 7b04bd5c | Richard Henderson | tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2); |
4540 | 97ea2859 | Richard Henderson | } else {
|
4541 | 7b04bd5c | Richard Henderson | tcg_gen_mov_tl(cpu_tmp0, cpu_src1); |
4542 | 97ea2859 | Richard Henderson | } |
4543 | cf495bcf | bellard | } |
4544 | 0f8a249a | blueswir1 | switch (xop) {
|
4545 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
4546 | 0f8a249a | blueswir1 | { |
4547 | 97ea2859 | Richard Henderson | TCGv t; |
4548 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4549 | 2ea815ca | blueswir1 | |
4550 | 97ea2859 | Richard Henderson | t = gen_dest_gpr(dc, rd); |
4551 | 97ea2859 | Richard Henderson | tcg_gen_movi_tl(t, dc->pc); |
4552 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, t); |
4553 | 13a6dd00 | Richard Henderson | gen_mov_pc_npc(dc); |
4554 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4555 | 7b04bd5c | Richard Henderson | gen_helper_check_align(cpu_env, cpu_tmp0, r_const); |
4556 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4557 | 7b04bd5c | Richard Henderson | gen_address_mask(dc, cpu_tmp0); |
4558 | 7b04bd5c | Richard Henderson | tcg_gen_mov_tl(cpu_npc, cpu_tmp0); |
4559 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4560 | 0f8a249a | blueswir1 | } |
4561 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4562 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4563 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
4564 | 0f8a249a | blueswir1 | { |
4565 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4566 | 2ea815ca | blueswir1 | |
4567 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4568 | 0f8a249a | blueswir1 | goto priv_insn;
|
4569 | 13a6dd00 | Richard Henderson | gen_mov_pc_npc(dc); |
4570 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4571 | 7b04bd5c | Richard Henderson | gen_helper_check_align(cpu_env, cpu_tmp0, r_const); |
4572 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4573 | 7b04bd5c | Richard Henderson | tcg_gen_mov_tl(cpu_npc, cpu_tmp0); |
4574 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4575 | 063c3675 | Blue Swirl | gen_helper_rett(cpu_env); |
4576 | 0f8a249a | blueswir1 | } |
4577 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4578 | 0f8a249a | blueswir1 | #endif
|
4579 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
4580 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_FLUSH))
|
4581 | 64a88d5d | blueswir1 | goto unimp_flush;
|
4582 | dcfd14b3 | Blue Swirl | /* nop */
|
4583 | 0f8a249a | blueswir1 | break;
|
4584 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
4585 | 66442b07 | Richard Henderson | save_state(dc); |
4586 | 063c3675 | Blue Swirl | gen_helper_save(cpu_env); |
4587 | 7b04bd5c | Richard Henderson | gen_store_gpr(dc, rd, cpu_tmp0); |
4588 | 0f8a249a | blueswir1 | break;
|
4589 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
4590 | 66442b07 | Richard Henderson | save_state(dc); |
4591 | 063c3675 | Blue Swirl | gen_helper_restore(cpu_env); |
4592 | 7b04bd5c | Richard Henderson | gen_store_gpr(dc, rd, cpu_tmp0); |
4593 | 0f8a249a | blueswir1 | break;
|
4594 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
4595 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
4596 | 0f8a249a | blueswir1 | { |
4597 | 0f8a249a | blueswir1 | switch (rd) {
|
4598 | 0f8a249a | blueswir1 | case 0: |
4599 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4600 | 0f8a249a | blueswir1 | goto priv_insn;
|
4601 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4602 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4603 | 063c3675 | Blue Swirl | gen_helper_done(cpu_env); |
4604 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4605 | 0f8a249a | blueswir1 | case 1: |
4606 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4607 | 0f8a249a | blueswir1 | goto priv_insn;
|
4608 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4609 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4610 | 063c3675 | Blue Swirl | gen_helper_retry(cpu_env); |
4611 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4612 | 0f8a249a | blueswir1 | default:
|
4613 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4614 | 0f8a249a | blueswir1 | } |
4615 | 0f8a249a | blueswir1 | } |
4616 | 0f8a249a | blueswir1 | break;
|
4617 | 0f8a249a | blueswir1 | #endif
|
4618 | 0f8a249a | blueswir1 | default:
|
4619 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4620 | 0f8a249a | blueswir1 | } |
4621 | cf495bcf | bellard | } |
4622 | 0f8a249a | blueswir1 | break;
|
4623 | 0f8a249a | blueswir1 | } |
4624 | 0f8a249a | blueswir1 | break;
|
4625 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
4626 | 0f8a249a | blueswir1 | { |
4627 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
4628 | 5e6ed439 | Richard Henderson | /* ??? gen_address_mask prevents us from using a source
|
4629 | 5e6ed439 | Richard Henderson | register directly. Always generate a temporary. */
|
4630 | 5e6ed439 | Richard Henderson | TCGv cpu_addr = get_temp_tl(dc); |
4631 | 9322a4bf | blueswir1 | |
4632 | 5e6ed439 | Richard Henderson | tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn)); |
4633 | 5e6ed439 | Richard Henderson | if (xop == 0x3c || xop == 0x3e) { |
4634 | 5e6ed439 | Richard Henderson | /* V9 casa/casxa : no offset */
|
4635 | 71817e48 | blueswir1 | } else if (IS_IMM) { /* immediate */ |
4636 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4637 | 5e6ed439 | Richard Henderson | if (simm != 0) { |
4638 | 5e6ed439 | Richard Henderson | tcg_gen_addi_tl(cpu_addr, cpu_addr, simm); |
4639 | 5e6ed439 | Richard Henderson | } |
4640 | 0f8a249a | blueswir1 | } else { /* register */ |
4641 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4642 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
4643 | 5e6ed439 | Richard Henderson | tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2)); |
4644 | 97ea2859 | Richard Henderson | } |
4645 | 0f8a249a | blueswir1 | } |
4646 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4647 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
4648 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
4649 | 81634eea | Richard Henderson | TCGv cpu_val = gen_dest_gpr(dc, rd); |
4650 | 81634eea | Richard Henderson | |
4651 | 0f8a249a | blueswir1 | switch (xop) {
|
4652 | b89e94af | Blue Swirl | case 0x0: /* ld, V9 lduw, load unsigned word */ |
4653 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4654 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
4655 | 0f8a249a | blueswir1 | break;
|
4656 | b89e94af | Blue Swirl | case 0x1: /* ldub, load unsigned byte */ |
4657 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4658 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
4659 | 0f8a249a | blueswir1 | break;
|
4660 | b89e94af | Blue Swirl | case 0x2: /* lduh, load unsigned halfword */ |
4661 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4662 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
4663 | 0f8a249a | blueswir1 | break;
|
4664 | b89e94af | Blue Swirl | case 0x3: /* ldd, load double word */ |
4665 | 0f8a249a | blueswir1 | if (rd & 1) |
4666 | d4218d99 | blueswir1 | goto illegal_insn;
|
4667 | 1a2fb1c0 | blueswir1 | else {
|
4668 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4669 | abcc7191 | Richard Henderson | TCGv_i64 t64; |
4670 | 2ea815ca | blueswir1 | |
4671 | 66442b07 | Richard Henderson | save_state(dc); |
4672 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4673 | fe8d8f0f | Blue Swirl | /* XXX remove alignment check */
|
4674 | fe8d8f0f | Blue Swirl | gen_helper_check_align(cpu_env, cpu_addr, r_const); |
4675 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4676 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4677 | abcc7191 | Richard Henderson | t64 = tcg_temp_new_i64(); |
4678 | abcc7191 | Richard Henderson | tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx); |
4679 | de9e9d9f | Richard Henderson | tcg_gen_trunc_i64_tl(cpu_val, t64); |
4680 | de9e9d9f | Richard Henderson | tcg_gen_ext32u_tl(cpu_val, cpu_val); |
4681 | de9e9d9f | Richard Henderson | gen_store_gpr(dc, rd + 1, cpu_val);
|
4682 | abcc7191 | Richard Henderson | tcg_gen_shri_i64(t64, t64, 32);
|
4683 | abcc7191 | Richard Henderson | tcg_gen_trunc_i64_tl(cpu_val, t64); |
4684 | abcc7191 | Richard Henderson | tcg_temp_free_i64(t64); |
4685 | de9e9d9f | Richard Henderson | tcg_gen_ext32u_tl(cpu_val, cpu_val); |
4686 | 1a2fb1c0 | blueswir1 | } |
4687 | 0f8a249a | blueswir1 | break;
|
4688 | b89e94af | Blue Swirl | case 0x9: /* ldsb, load signed byte */ |
4689 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4690 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4691 | 0f8a249a | blueswir1 | break;
|
4692 | b89e94af | Blue Swirl | case 0xa: /* ldsh, load signed halfword */ |
4693 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4694 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
4695 | 0f8a249a | blueswir1 | break;
|
4696 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
4697 | 2ea815ca | blueswir1 | { |
4698 | 2ea815ca | blueswir1 | TCGv r_const; |
4699 | 2ea815ca | blueswir1 | |
4700 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4701 | 2ea815ca | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4702 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(0xff);
|
4703 | 2ea815ca | blueswir1 | tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); |
4704 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4705 | 2ea815ca | blueswir1 | } |
4706 | 0f8a249a | blueswir1 | break;
|
4707 | de9e9d9f | Richard Henderson | case 0x0f: |
4708 | de9e9d9f | Richard Henderson | /* swap, swap register with memory. Also atomically */
|
4709 | de9e9d9f | Richard Henderson | { |
4710 | de9e9d9f | Richard Henderson | TCGv t0 = get_temp_tl(dc); |
4711 | de9e9d9f | Richard Henderson | CHECK_IU_FEATURE(dc, SWAP); |
4712 | de9e9d9f | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rd); |
4713 | de9e9d9f | Richard Henderson | gen_address_mask(dc, cpu_addr); |
4714 | de9e9d9f | Richard Henderson | tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx); |
4715 | de9e9d9f | Richard Henderson | tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx); |
4716 | de9e9d9f | Richard Henderson | tcg_gen_mov_tl(cpu_val, t0); |
4717 | de9e9d9f | Richard Henderson | } |
4718 | 0f8a249a | blueswir1 | break;
|
4719 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4720 | b89e94af | Blue Swirl | case 0x10: /* lda, V9 lduwa, load word alternate */ |
4721 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4722 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4723 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4724 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4725 | 0f8a249a | blueswir1 | goto priv_insn;
|
4726 | 6ea4a6c8 | blueswir1 | #endif
|
4727 | 66442b07 | Richard Henderson | save_state(dc); |
4728 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
4729 | 0f8a249a | blueswir1 | break;
|
4730 | b89e94af | Blue Swirl | case 0x11: /* lduba, load unsigned byte alternate */ |
4731 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4732 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4733 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4734 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4735 | 0f8a249a | blueswir1 | goto priv_insn;
|
4736 | 0f8a249a | blueswir1 | #endif
|
4737 | 66442b07 | Richard Henderson | save_state(dc); |
4738 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
4739 | 0f8a249a | blueswir1 | break;
|
4740 | b89e94af | Blue Swirl | case 0x12: /* lduha, load unsigned halfword alternate */ |
4741 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4742 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4743 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4744 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4745 | 0f8a249a | blueswir1 | goto priv_insn;
|
4746 | 6ea4a6c8 | blueswir1 | #endif
|
4747 | 66442b07 | Richard Henderson | save_state(dc); |
4748 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
4749 | 0f8a249a | blueswir1 | break;
|
4750 | b89e94af | Blue Swirl | case 0x13: /* ldda, load double word alternate */ |
4751 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4752 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4753 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4754 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4755 | 0f8a249a | blueswir1 | goto priv_insn;
|
4756 | 3475187d | bellard | #endif
|
4757 | 0f8a249a | blueswir1 | if (rd & 1) |
4758 | d4218d99 | blueswir1 | goto illegal_insn;
|
4759 | 66442b07 | Richard Henderson | save_state(dc); |
4760 | c7785e16 | Richard Henderson | gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd); |
4761 | db166940 | blueswir1 | goto skip_move;
|
4762 | b89e94af | Blue Swirl | case 0x19: /* ldsba, load signed byte alternate */ |
4763 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4764 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4765 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4766 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4767 | 0f8a249a | blueswir1 | goto priv_insn;
|
4768 | 0f8a249a | blueswir1 | #endif
|
4769 | 66442b07 | Richard Henderson | save_state(dc); |
4770 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
4771 | 0f8a249a | blueswir1 | break;
|
4772 | b89e94af | Blue Swirl | case 0x1a: /* ldsha, load signed halfword alternate */ |
4773 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4774 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4775 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4776 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4777 | 0f8a249a | blueswir1 | goto priv_insn;
|
4778 | 6ea4a6c8 | blueswir1 | #endif
|
4779 | 66442b07 | Richard Henderson | save_state(dc); |
4780 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
4781 | 0f8a249a | blueswir1 | break;
|
4782 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
4783 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4784 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4785 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4786 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4787 | 0f8a249a | blueswir1 | goto priv_insn;
|
4788 | 0f8a249a | blueswir1 | #endif
|
4789 | 66442b07 | Richard Henderson | save_state(dc); |
4790 | 6ae20372 | blueswir1 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
4791 | 0f8a249a | blueswir1 | break;
|
4792 | b89e94af | Blue Swirl | case 0x1f: /* swapa, swap reg with alt. memory. Also |
4793 | 77f193da | blueswir1 | atomically */
|
4794 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4795 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4796 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4797 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4798 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4799 | 0f8a249a | blueswir1 | goto priv_insn;
|
4800 | 6ea4a6c8 | blueswir1 | #endif
|
4801 | 66442b07 | Richard Henderson | save_state(dc); |
4802 | 06828032 | Richard Henderson | cpu_src1 = gen_load_gpr(dc, rd); |
4803 | 06828032 | Richard Henderson | gen_swap_asi(cpu_val, cpu_src1, cpu_addr, insn); |
4804 | 0f8a249a | blueswir1 | break;
|
4805 | 3475187d | bellard | |
4806 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4807 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
4808 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
4809 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
4810 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4811 | 3475187d | bellard | #endif
|
4812 | 3475187d | bellard | #endif
|
4813 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4814 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
4815 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4816 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); |
4817 | 0f8a249a | blueswir1 | break;
|
4818 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
4819 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4820 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); |
4821 | 0f8a249a | blueswir1 | break;
|
4822 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
4823 | 66442b07 | Richard Henderson | save_state(dc); |
4824 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
4825 | 0f8a249a | blueswir1 | break;
|
4826 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
4827 | 66442b07 | Richard Henderson | save_state(dc); |
4828 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
4829 | 0f8a249a | blueswir1 | break;
|
4830 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
4831 | 0f8a249a | blueswir1 | goto skip_move;
|
4832 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
4833 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
4834 | 8872eb4f | Tsuneo Saito | goto jmp_insn;
|
4835 | 8872eb4f | Tsuneo Saito | } |
4836 | 66442b07 | Richard Henderson | save_state(dc); |
4837 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 4, rd);
|
4838 | 638737ad | Tsuneo Saito | gen_update_fprs_dirty(rd); |
4839 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4840 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
4841 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
4842 | 8872eb4f | Tsuneo Saito | goto jmp_insn;
|
4843 | 8872eb4f | Tsuneo Saito | } |
4844 | 66442b07 | Richard Henderson | save_state(dc); |
4845 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4846 | 638737ad | Tsuneo Saito | gen_update_fprs_dirty(DFPREG(rd)); |
4847 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4848 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
4849 | 0f8a249a | blueswir1 | goto skip_move;
|
4850 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
4851 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4852 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
4853 | 8872eb4f | Tsuneo Saito | goto jmp_insn;
|
4854 | 8872eb4f | Tsuneo Saito | } |
4855 | 66442b07 | Richard Henderson | save_state(dc); |
4856 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4857 | 638737ad | Tsuneo Saito | gen_update_fprs_dirty(QFPREG(rd)); |
4858 | 1f587329 | blueswir1 | goto skip_move;
|
4859 | 1f587329 | blueswir1 | #endif
|
4860 | 0f8a249a | blueswir1 | default:
|
4861 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4862 | 0f8a249a | blueswir1 | } |
4863 | 97ea2859 | Richard Henderson | gen_store_gpr(dc, rd, cpu_val); |
4864 | db166940 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4865 | 0f8a249a | blueswir1 | skip_move: ;
|
4866 | 3475187d | bellard | #endif
|
4867 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
4868 | de9e9d9f | Richard Henderson | TCGv t0; |
4869 | de9e9d9f | Richard Henderson | |
4870 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
4871 | a80dde08 | bellard | goto jmp_insn;
|
4872 | 5b12f1e8 | Richard Henderson | } |
4873 | 66442b07 | Richard Henderson | save_state(dc); |
4874 | 0f8a249a | blueswir1 | switch (xop) {
|
4875 | b89e94af | Blue Swirl | case 0x20: /* ldf, load fpreg */ |
4876 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4877 | de9e9d9f | Richard Henderson | t0 = get_temp_tl(dc); |
4878 | de9e9d9f | Richard Henderson | tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx); |
4879 | ba5f5179 | Richard Henderson | cpu_dst_32 = gen_dest_fpr_F(dc); |
4880 | de9e9d9f | Richard Henderson | tcg_gen_trunc_tl_i32(cpu_dst_32, t0); |
4881 | 208ae657 | Richard Henderson | gen_store_fpr_F(dc, rd, cpu_dst_32); |
4882 | 0f8a249a | blueswir1 | break;
|
4883 | 3a3b925d | blueswir1 | case 0x21: /* ldfsr, V9 ldxfsr */ |
4884 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4885 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4886 | 3a3b925d | blueswir1 | if (rd == 1) { |
4887 | abcc7191 | Richard Henderson | TCGv_i64 t64 = tcg_temp_new_i64(); |
4888 | abcc7191 | Richard Henderson | tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx); |
4889 | abcc7191 | Richard Henderson | gen_helper_ldxfsr(cpu_env, t64); |
4890 | abcc7191 | Richard Henderson | tcg_temp_free_i64(t64); |
4891 | f8641947 | Richard Henderson | break;
|
4892 | fe987e23 | Igor V. Kovalenko | } |
4893 | f8641947 | Richard Henderson | #endif
|
4894 | de9e9d9f | Richard Henderson | cpu_dst_32 = get_temp_i32(dc); |
4895 | de9e9d9f | Richard Henderson | t0 = get_temp_tl(dc); |
4896 | de9e9d9f | Richard Henderson | tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx); |
4897 | de9e9d9f | Richard Henderson | tcg_gen_trunc_tl_i32(cpu_dst_32, t0); |
4898 | de9e9d9f | Richard Henderson | gen_helper_ldfsr(cpu_env, cpu_dst_32); |
4899 | 0f8a249a | blueswir1 | break;
|
4900 | b89e94af | Blue Swirl | case 0x22: /* ldqf, load quad fpreg */ |
4901 | 2ea815ca | blueswir1 | { |
4902 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4903 | 2ea815ca | blueswir1 | |
4904 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4905 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4906 | 1295001c | Igor V. Kovalenko | gen_address_mask(dc, cpu_addr); |
4907 | fe8d8f0f | Blue Swirl | gen_helper_ldqf(cpu_env, cpu_addr, r_const); |
4908 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4909 | 2ea815ca | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4910 | 638737ad | Tsuneo Saito | gen_update_fprs_dirty(QFPREG(rd)); |
4911 | 2ea815ca | blueswir1 | } |
4912 | 1f587329 | blueswir1 | break;
|
4913 | b89e94af | Blue Swirl | case 0x23: /* lddf, load double fpreg */ |
4914 | 03fb8cfc | Richard Henderson | gen_address_mask(dc, cpu_addr); |
4915 | 3886b8a3 | Richard Henderson | cpu_dst_64 = gen_dest_fpr_D(dc, rd); |
4916 | 03fb8cfc | Richard Henderson | tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx); |
4917 | 03fb8cfc | Richard Henderson | gen_store_fpr_D(dc, rd, cpu_dst_64); |
4918 | 0f8a249a | blueswir1 | break;
|
4919 | 0f8a249a | blueswir1 | default:
|
4920 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4921 | 0f8a249a | blueswir1 | } |
4922 | dc1a6971 | Blue Swirl | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || |
4923 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
4924 | 81634eea | Richard Henderson | TCGv cpu_val = gen_load_gpr(dc, rd); |
4925 | 81634eea | Richard Henderson | |
4926 | 0f8a249a | blueswir1 | switch (xop) {
|
4927 | b89e94af | Blue Swirl | case 0x4: /* st, store word */ |
4928 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4929 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4930 | 0f8a249a | blueswir1 | break;
|
4931 | b89e94af | Blue Swirl | case 0x5: /* stb, store byte */ |
4932 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4933 | 6ae20372 | blueswir1 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
4934 | 0f8a249a | blueswir1 | break;
|
4935 | b89e94af | Blue Swirl | case 0x6: /* sth, store halfword */ |
4936 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4937 | 6ae20372 | blueswir1 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
4938 | 0f8a249a | blueswir1 | break;
|
4939 | b89e94af | Blue Swirl | case 0x7: /* std, store double word */ |
4940 | 0f8a249a | blueswir1 | if (rd & 1) |
4941 | d4218d99 | blueswir1 | goto illegal_insn;
|
4942 | 1a2fb1c0 | blueswir1 | else {
|
4943 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4944 | abcc7191 | Richard Henderson | TCGv_i64 t64; |
4945 | 81634eea | Richard Henderson | TCGv lo; |
4946 | 1a2fb1c0 | blueswir1 | |
4947 | 66442b07 | Richard Henderson | save_state(dc); |
4948 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4949 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4950 | fe8d8f0f | Blue Swirl | /* XXX remove alignment check */
|
4951 | fe8d8f0f | Blue Swirl | gen_helper_check_align(cpu_env, cpu_addr, r_const); |
4952 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4953 | 81634eea | Richard Henderson | lo = gen_load_gpr(dc, rd + 1);
|
4954 | abcc7191 | Richard Henderson | |
4955 | abcc7191 | Richard Henderson | t64 = tcg_temp_new_i64(); |
4956 | abcc7191 | Richard Henderson | tcg_gen_concat_tl_i64(t64, lo, cpu_val); |
4957 | abcc7191 | Richard Henderson | tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx); |
4958 | abcc7191 | Richard Henderson | tcg_temp_free_i64(t64); |
4959 | 7fa76c0b | blueswir1 | } |
4960 | 0f8a249a | blueswir1 | break;
|
4961 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4962 | b89e94af | Blue Swirl | case 0x14: /* sta, V9 stwa, store word alternate */ |
4963 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4964 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4965 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4966 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4967 | 0f8a249a | blueswir1 | goto priv_insn;
|
4968 | 3475187d | bellard | #endif
|
4969 | 66442b07 | Richard Henderson | save_state(dc); |
4970 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 4);
|
4971 | 9fd1ae3a | Igor V. Kovalenko | dc->npc = DYNAMIC_PC; |
4972 | d39c0b99 | bellard | break;
|
4973 | b89e94af | Blue Swirl | case 0x15: /* stba, store byte alternate */ |
4974 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4975 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4976 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4977 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4978 | 0f8a249a | blueswir1 | goto priv_insn;
|
4979 | 3475187d | bellard | #endif
|
4980 | 66442b07 | Richard Henderson | save_state(dc); |
4981 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 1);
|
4982 | 9fd1ae3a | Igor V. Kovalenko | dc->npc = DYNAMIC_PC; |
4983 | d39c0b99 | bellard | break;
|
4984 | b89e94af | Blue Swirl | case 0x16: /* stha, store halfword alternate */ |
4985 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4986 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4987 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4988 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4989 | 0f8a249a | blueswir1 | goto priv_insn;
|
4990 | 3475187d | bellard | #endif
|
4991 | 66442b07 | Richard Henderson | save_state(dc); |
4992 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 2);
|
4993 | 9fd1ae3a | Igor V. Kovalenko | dc->npc = DYNAMIC_PC; |
4994 | d39c0b99 | bellard | break;
|
4995 | b89e94af | Blue Swirl | case 0x17: /* stda, store double word alternate */ |
4996 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4997 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4998 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4999 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
5000 | 0f8a249a | blueswir1 | goto priv_insn;
|
5001 | 3475187d | bellard | #endif
|
5002 | 0f8a249a | blueswir1 | if (rd & 1) |
5003 | d4218d99 | blueswir1 | goto illegal_insn;
|
5004 | 1a2fb1c0 | blueswir1 | else {
|
5005 | 66442b07 | Richard Henderson | save_state(dc); |
5006 | c7785e16 | Richard Henderson | gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd); |
5007 | 1a2fb1c0 | blueswir1 | } |
5008 | d39c0b99 | bellard | break;
|
5009 | e80cfcfc | bellard | #endif
|
5010 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
5011 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
5012 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
5013 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); |
5014 | 0f8a249a | blueswir1 | break;
|
5015 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
5016 | 66442b07 | Richard Henderson | save_state(dc); |
5017 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 8);
|
5018 | 9fd1ae3a | Igor V. Kovalenko | dc->npc = DYNAMIC_PC; |
5019 | 0f8a249a | blueswir1 | break;
|
5020 | 3475187d | bellard | #endif
|
5021 | 0f8a249a | blueswir1 | default:
|
5022 | 0f8a249a | blueswir1 | goto illegal_insn;
|
5023 | 0f8a249a | blueswir1 | } |
5024 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
5025 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
5026 | a80dde08 | bellard | goto jmp_insn;
|
5027 | 5b12f1e8 | Richard Henderson | } |
5028 | 66442b07 | Richard Henderson | save_state(dc); |
5029 | 0f8a249a | blueswir1 | switch (xop) {
|
5030 | b89e94af | Blue Swirl | case 0x24: /* stf, store fpreg */ |
5031 | de9e9d9f | Richard Henderson | { |
5032 | de9e9d9f | Richard Henderson | TCGv t = get_temp_tl(dc); |
5033 | de9e9d9f | Richard Henderson | gen_address_mask(dc, cpu_addr); |
5034 | de9e9d9f | Richard Henderson | cpu_src1_32 = gen_load_fpr_F(dc, rd); |
5035 | de9e9d9f | Richard Henderson | tcg_gen_ext_i32_tl(t, cpu_src1_32); |
5036 | de9e9d9f | Richard Henderson | tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx); |
5037 | de9e9d9f | Richard Henderson | } |
5038 | 0f8a249a | blueswir1 | break;
|
5039 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
5040 | f8641947 | Richard Henderson | { |
5041 | f8641947 | Richard Henderson | TCGv t = get_temp_tl(dc); |
5042 | f8641947 | Richard Henderson | |
5043 | f8641947 | Richard Henderson | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr)); |
5044 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
5045 | f8641947 | Richard Henderson | gen_address_mask(dc, cpu_addr); |
5046 | f8641947 | Richard Henderson | if (rd == 1) { |
5047 | f8641947 | Richard Henderson | tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx); |
5048 | f8641947 | Richard Henderson | break;
|
5049 | f8641947 | Richard Henderson | } |
5050 | 3a3b925d | blueswir1 | #endif
|
5051 | f8641947 | Richard Henderson | tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx); |
5052 | f8641947 | Richard Henderson | } |
5053 | 0f8a249a | blueswir1 | break;
|
5054 | 1f587329 | blueswir1 | case 0x26: |
5055 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
5056 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
5057 | 2ea815ca | blueswir1 | { |
5058 | a7812ae4 | pbrook | TCGv_i32 r_const; |
5059 | 2ea815ca | blueswir1 | |
5060 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
5061 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
5062 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
5063 | 1295001c | Igor V. Kovalenko | gen_address_mask(dc, cpu_addr); |
5064 | fe8d8f0f | Blue Swirl | gen_helper_stqf(cpu_env, cpu_addr, r_const); |
5065 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
5066 | 2ea815ca | blueswir1 | } |
5067 | 1f587329 | blueswir1 | break;
|
5068 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
5069 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
5070 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
5071 | 1f587329 | blueswir1 | goto illegal_insn;
|
5072 | 1f587329 | blueswir1 | #else
|
5073 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
5074 | 0f8a249a | blueswir1 | goto priv_insn;
|
5075 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
5076 | 0f8a249a | blueswir1 | goto jmp_insn;
|
5077 | 5b12f1e8 | Richard Henderson | } |
5078 | 0f8a249a | blueswir1 | goto nfq_insn;
|
5079 | 0f8a249a | blueswir1 | #endif
|
5080 | 1f587329 | blueswir1 | #endif
|
5081 | b89e94af | Blue Swirl | case 0x27: /* stdf, store double fpreg */ |
5082 | 03fb8cfc | Richard Henderson | gen_address_mask(dc, cpu_addr); |
5083 | 03fb8cfc | Richard Henderson | cpu_src1_64 = gen_load_fpr_D(dc, rd); |
5084 | 03fb8cfc | Richard Henderson | tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx); |
5085 | 0f8a249a | blueswir1 | break;
|
5086 | 0f8a249a | blueswir1 | default:
|
5087 | 0f8a249a | blueswir1 | goto illegal_insn;
|
5088 | 0f8a249a | blueswir1 | } |
5089 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
5090 | 66442b07 | Richard Henderson | save_state(dc); |
5091 | 0f8a249a | blueswir1 | switch (xop) {
|
5092 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
5093 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
5094 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
5095 | 5f06b547 | Tsuneo Saito | goto jmp_insn;
|
5096 | 5f06b547 | Tsuneo Saito | } |
5097 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 4, rd);
|
5098 | 0f8a249a | blueswir1 | break;
|
5099 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
5100 | 2ea815ca | blueswir1 | { |
5101 | a7812ae4 | pbrook | TCGv_i32 r_const; |
5102 | 2ea815ca | blueswir1 | |
5103 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
5104 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
5105 | 5f06b547 | Tsuneo Saito | goto jmp_insn;
|
5106 | 5f06b547 | Tsuneo Saito | } |
5107 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
5108 | fe8d8f0f | Blue Swirl | gen_helper_check_align(cpu_env, cpu_addr, r_const); |
5109 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
5110 | 2ea815ca | blueswir1 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
5111 | 2ea815ca | blueswir1 | } |
5112 | 1f587329 | blueswir1 | break;
|
5113 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
5114 | 5b12f1e8 | Richard Henderson | if (gen_trap_ifnofpu(dc)) {
|
5115 | 5f06b547 | Tsuneo Saito | goto jmp_insn;
|
5116 | 5f06b547 | Tsuneo Saito | } |
5117 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
5118 | 0f8a249a | blueswir1 | break;
|
5119 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
5120 | a4273524 | Richard Henderson | rs2 = GET_FIELD(insn, 27, 31); |
5121 | a4273524 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
5122 | 81634eea | Richard Henderson | gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); |
5123 | 0f8a249a | blueswir1 | break;
|
5124 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
5125 | a4273524 | Richard Henderson | rs2 = GET_FIELD(insn, 27, 31); |
5126 | a4273524 | Richard Henderson | cpu_src2 = gen_load_gpr(dc, rs2); |
5127 | 81634eea | Richard Henderson | gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd); |
5128 | 0f8a249a | blueswir1 | break;
|
5129 | a4d17f19 | blueswir1 | #else
|
5130 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
5131 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
5132 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
5133 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
5134 | 0f8a249a | blueswir1 | goto ncp_insn;
|
5135 | 0f8a249a | blueswir1 | #endif
|
5136 | 0f8a249a | blueswir1 | default:
|
5137 | 0f8a249a | blueswir1 | goto illegal_insn;
|
5138 | 0f8a249a | blueswir1 | } |
5139 | a4273524 | Richard Henderson | } else {
|
5140 | 0f8a249a | blueswir1 | goto illegal_insn;
|
5141 | a4273524 | Richard Henderson | } |
5142 | 0f8a249a | blueswir1 | } |
5143 | 0f8a249a | blueswir1 | break;
|
5144 | cf495bcf | bellard | } |
5145 | cf495bcf | bellard | /* default case for non jump instructions */
|
5146 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
5147 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
5148 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
5149 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
5150 | 72cbca10 | bellard | /* we can do a static jump */
|
5151 | 6ae20372 | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
5152 | 72cbca10 | bellard | dc->is_br = 1;
|
5153 | 72cbca10 | bellard | } else {
|
5154 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
5155 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
5156 | cf495bcf | bellard | } |
5157 | e80cfcfc | bellard | jmp_insn:
|
5158 | 42a8aa83 | Richard Henderson | goto egress;
|
5159 | cf495bcf | bellard | illegal_insn:
|
5160 | 2ea815ca | blueswir1 | { |
5161 | a7812ae4 | pbrook | TCGv_i32 r_const; |
5162 | 2ea815ca | blueswir1 | |
5163 | 66442b07 | Richard Henderson | save_state(dc); |
5164 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_ILL_INSN); |
5165 | bc265319 | Blue Swirl | gen_helper_raise_exception(cpu_env, r_const); |
5166 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
5167 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
5168 | 2ea815ca | blueswir1 | } |
5169 | 42a8aa83 | Richard Henderson | goto egress;
|
5170 | 64a88d5d | blueswir1 | unimp_flush:
|
5171 | 2ea815ca | blueswir1 | { |
5172 | a7812ae4 | pbrook | TCGv_i32 r_const; |
5173 | 2ea815ca | blueswir1 | |
5174 | 66442b07 | Richard Henderson | save_state(dc); |
5175 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_UNIMP_FLUSH); |
5176 | bc265319 | Blue Swirl | gen_helper_raise_exception(cpu_env, r_const); |
5177 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
5178 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
5179 | 2ea815ca | blueswir1 | } |
5180 | 42a8aa83 | Richard Henderson | goto egress;
|
5181 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
5182 | e8af50a3 | bellard | priv_insn:
|
5183 | 2ea815ca | blueswir1 | { |
5184 | a7812ae4 | pbrook | TCGv_i32 r_const; |
5185 | 2ea815ca | blueswir1 | |
5186 | 66442b07 | Richard Henderson | save_state(dc); |
5187 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_PRIV_INSN); |
5188 | bc265319 | Blue Swirl | gen_helper_raise_exception(cpu_env, r_const); |
5189 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
5190 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
5191 | 2ea815ca | blueswir1 | } |
5192 | 42a8aa83 | Richard Henderson | goto egress;
|
5193 | 64a88d5d | blueswir1 | #endif
|
5194 | e80cfcfc | bellard | nfpu_insn:
|
5195 | 66442b07 | Richard Henderson | save_state(dc); |
5196 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
5197 | e80cfcfc | bellard | dc->is_br = 1;
|
5198 | 42a8aa83 | Richard Henderson | goto egress;
|
5199 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
5200 | 9143e598 | blueswir1 | nfq_insn:
|
5201 | 66442b07 | Richard Henderson | save_state(dc); |
5202 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
5203 | 9143e598 | blueswir1 | dc->is_br = 1;
|
5204 | 42a8aa83 | Richard Henderson | goto egress;
|
5205 | 9143e598 | blueswir1 | #endif
|
5206 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
5207 | fcc72045 | blueswir1 | ncp_insn:
|
5208 | 2ea815ca | blueswir1 | { |
5209 | 2ea815ca | blueswir1 | TCGv r_const; |
5210 | 2ea815ca | blueswir1 | |
5211 | 66442b07 | Richard Henderson | save_state(dc); |
5212 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NCP_INSN); |
5213 | bc265319 | Blue Swirl | gen_helper_raise_exception(cpu_env, r_const); |
5214 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
5215 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
5216 | 2ea815ca | blueswir1 | } |
5217 | 42a8aa83 | Richard Henderson | goto egress;
|
5218 | fcc72045 | blueswir1 | #endif
|
5219 | 42a8aa83 | Richard Henderson | egress:
|
5220 | 30038fd8 | Richard Henderson | if (dc->n_t32 != 0) { |
5221 | 30038fd8 | Richard Henderson | int i;
|
5222 | 30038fd8 | Richard Henderson | for (i = dc->n_t32 - 1; i >= 0; --i) { |
5223 | 30038fd8 | Richard Henderson | tcg_temp_free_i32(dc->t32[i]); |
5224 | 30038fd8 | Richard Henderson | } |
5225 | 30038fd8 | Richard Henderson | dc->n_t32 = 0;
|
5226 | 30038fd8 | Richard Henderson | } |
5227 | 88023616 | Richard Henderson | if (dc->n_ttl != 0) { |
5228 | 88023616 | Richard Henderson | int i;
|
5229 | 88023616 | Richard Henderson | for (i = dc->n_ttl - 1; i >= 0; --i) { |
5230 | 88023616 | Richard Henderson | tcg_temp_free(dc->ttl[i]); |
5231 | 88023616 | Richard Henderson | } |
5232 | 88023616 | Richard Henderson | dc->n_ttl = 0;
|
5233 | 88023616 | Richard Henderson | } |
5234 | 7a3f1944 | bellard | } |
5235 | 7a3f1944 | bellard | |
5236 | 2cfc5f17 | ths | static inline void gen_intermediate_code_internal(TranslationBlock * tb, |
5237 | 2cfc5f17 | ths | int spc, CPUSPARCState *env)
|
5238 | 7a3f1944 | bellard | { |
5239 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
5240 | cf495bcf | bellard | uint16_t *gen_opc_end; |
5241 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
5242 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
5243 | e8af50a3 | bellard | int j, lj = -1; |
5244 | 2e70f6ef | pbrook | int num_insns;
|
5245 | 2e70f6ef | pbrook | int max_insns;
|
5246 | 0184e266 | Blue Swirl | unsigned int insn; |
5247 | cf495bcf | bellard | |
5248 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
5249 | cf495bcf | bellard | dc->tb = tb; |
5250 | 72cbca10 | bellard | pc_start = tb->pc; |
5251 | cf495bcf | bellard | dc->pc = pc_start; |
5252 | e80cfcfc | bellard | last_pc = dc->pc; |
5253 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
5254 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_DYNAMIC; |
5255 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
5256 | 5578ceab | blueswir1 | dc->def = env->def; |
5257 | f838e2c5 | Blue Swirl | dc->fpu_enabled = tb_fpu_enabled(tb->flags); |
5258 | f838e2c5 | Blue Swirl | dc->address_mask_32bit = tb_am_enabled(tb->flags); |
5259 | 060718c1 | Richard Henderson | dc->singlestep = (env->singlestep_enabled || singlestep); |
5260 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
5261 | cf495bcf | bellard | |
5262 | 2e70f6ef | pbrook | num_insns = 0;
|
5263 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
5264 | 2e70f6ef | pbrook | if (max_insns == 0) |
5265 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
5266 | 2e70f6ef | pbrook | gen_icount_start(); |
5267 | cf495bcf | bellard | do {
|
5268 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
5269 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
5270 | a1d1bb31 | aliguori | if (bp->pc == dc->pc) {
|
5271 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
5272 | 66442b07 | Richard Henderson | save_state(dc); |
5273 | bc265319 | Blue Swirl | gen_helper_debug(cpu_env); |
5274 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
5275 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
5276 | e80cfcfc | bellard | goto exit_gen_loop;
|
5277 | e8af50a3 | bellard | } |
5278 | e8af50a3 | bellard | } |
5279 | e8af50a3 | bellard | } |
5280 | e8af50a3 | bellard | if (spc) {
|
5281 | 93fcfe39 | aliguori | qemu_log("Search PC...\n");
|
5282 | efd7f486 | Evgeny Voevodin | j = tcg_ctx.gen_opc_ptr - gen_opc_buf; |
5283 | e8af50a3 | bellard | if (lj < j) {
|
5284 | e8af50a3 | bellard | lj++; |
5285 | e8af50a3 | bellard | while (lj < j)
|
5286 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
5287 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
5288 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
5289 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
5290 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
5291 | e8af50a3 | bellard | } |
5292 | e8af50a3 | bellard | } |
5293 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
5294 | 2e70f6ef | pbrook | gen_io_start(); |
5295 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
5296 | 0184e266 | Blue Swirl | insn = cpu_ldl_code(env, dc->pc); |
5297 | b09b2fd3 | Richard Henderson | |
5298 | 0184e266 | Blue Swirl | disas_sparc_insn(dc, insn); |
5299 | 2e70f6ef | pbrook | num_insns++; |
5300 | 0f8a249a | blueswir1 | |
5301 | 0f8a249a | blueswir1 | if (dc->is_br)
|
5302 | 0f8a249a | blueswir1 | break;
|
5303 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
5304 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
5305 | 0f8a249a | blueswir1 | break;
|
5306 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
5307 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
5308 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
5309 | d39c0b99 | bellard | break;
|
5310 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
5311 | e80cfcfc | bellard | generate an exception */
|
5312 | 060718c1 | Richard Henderson | if (dc->singlestep) {
|
5313 | e80cfcfc | bellard | break;
|
5314 | e80cfcfc | bellard | } |
5315 | efd7f486 | Evgeny Voevodin | } while ((tcg_ctx.gen_opc_ptr < gen_opc_end) &&
|
5316 | 2e70f6ef | pbrook | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
|
5317 | 2e70f6ef | pbrook | num_insns < max_insns); |
5318 | e80cfcfc | bellard | |
5319 | e80cfcfc | bellard | exit_gen_loop:
|
5320 | b09b2fd3 | Richard Henderson | if (tb->cflags & CF_LAST_IO) {
|
5321 | 2e70f6ef | pbrook | gen_io_end(); |
5322 | b09b2fd3 | Richard Henderson | } |
5323 | 72cbca10 | bellard | if (!dc->is_br) {
|
5324 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
5325 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
5326 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
5327 | 2f5680ee | blueswir1 | gen_goto_tb(dc, 0, dc->pc, dc->npc);
|
5328 | 72cbca10 | bellard | } else {
|
5329 | b09b2fd3 | Richard Henderson | if (dc->pc != DYNAMIC_PC) {
|
5330 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
5331 | b09b2fd3 | Richard Henderson | } |
5332 | 934da7ee | Richard Henderson | save_npc(dc); |
5333 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
5334 | 72cbca10 | bellard | } |
5335 | 72cbca10 | bellard | } |
5336 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
5337 | efd7f486 | Evgeny Voevodin | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
5338 | e8af50a3 | bellard | if (spc) {
|
5339 | efd7f486 | Evgeny Voevodin | j = tcg_ctx.gen_opc_ptr - gen_opc_buf; |
5340 | e8af50a3 | bellard | lj++; |
5341 | e8af50a3 | bellard | while (lj <= j)
|
5342 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
5343 | e8af50a3 | bellard | #if 0
|
5344 | 93fcfe39 | aliguori | log_page_dump();
|
5345 | e8af50a3 | bellard | #endif
|
5346 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
5347 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
5348 | e8af50a3 | bellard | } else {
|
5349 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
5350 | 2e70f6ef | pbrook | tb->icount = num_insns; |
5351 | e8af50a3 | bellard | } |
5352 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
5353 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
5354 | 93fcfe39 | aliguori | qemu_log("--------------\n");
|
5355 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
5356 | f4359b9f | Blue Swirl | log_target_disas(env, pc_start, last_pc + 4 - pc_start, 0); |
5357 | 93fcfe39 | aliguori | qemu_log("\n");
|
5358 | cf495bcf | bellard | } |
5359 | 7a3f1944 | bellard | #endif
|
5360 | 7a3f1944 | bellard | } |
5361 | 7a3f1944 | bellard | |
5362 | 2cfc5f17 | ths | void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
5363 | 7a3f1944 | bellard | { |
5364 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 0, env);
|
5365 | 7a3f1944 | bellard | } |
5366 | 7a3f1944 | bellard | |
5367 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
5368 | 7a3f1944 | bellard | { |
5369 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 1, env);
|
5370 | 7a3f1944 | bellard | } |
5371 | 7a3f1944 | bellard | |
5372 | c48fcb47 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env)
|
5373 | e80cfcfc | bellard | { |
5374 | f5069b26 | blueswir1 | unsigned int i; |
5375 | c48fcb47 | blueswir1 | static int inited; |
5376 | f5069b26 | blueswir1 | static const char * const gregnames[8] = { |
5377 | f5069b26 | blueswir1 | NULL, // g0 not used |
5378 | f5069b26 | blueswir1 | "g1",
|
5379 | f5069b26 | blueswir1 | "g2",
|
5380 | f5069b26 | blueswir1 | "g3",
|
5381 | f5069b26 | blueswir1 | "g4",
|
5382 | f5069b26 | blueswir1 | "g5",
|
5383 | f5069b26 | blueswir1 | "g6",
|
5384 | f5069b26 | blueswir1 | "g7",
|
5385 | f5069b26 | blueswir1 | }; |
5386 | 30038fd8 | Richard Henderson | static const char * const fregnames[32] = { |
5387 | 30038fd8 | Richard Henderson | "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14", |
5388 | 30038fd8 | Richard Henderson | "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30", |
5389 | 30038fd8 | Richard Henderson | "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", |
5390 | 30038fd8 | Richard Henderson | "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", |
5391 | 714547bb | blueswir1 | }; |
5392 | aaed909a | bellard | |
5393 | 1a2fb1c0 | blueswir1 | /* init various static tables */
|
5394 | 1a2fb1c0 | blueswir1 | if (!inited) {
|
5395 | 1a2fb1c0 | blueswir1 | inited = 1;
|
5396 | 1a2fb1c0 | blueswir1 | |
5397 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
5398 | a7812ae4 | pbrook | cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0, |
5399 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, regwptr), |
5400 | a7812ae4 | pbrook | "regwptr");
|
5401 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
5402 | c5f9864e | Andreas Färber | cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, xcc), |
5403 | a7812ae4 | pbrook | "xcc");
|
5404 | c5f9864e | Andreas Färber | cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, asi), |
5405 | a7812ae4 | pbrook | "asi");
|
5406 | c5f9864e | Andreas Färber | cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, fprs), |
5407 | a7812ae4 | pbrook | "fprs");
|
5408 | c5f9864e | Andreas Färber | cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, gsr), |
5409 | 255e1fcb | blueswir1 | "gsr");
|
5410 | a7812ae4 | pbrook | cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0, |
5411 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, tick_cmpr), |
5412 | 255e1fcb | blueswir1 | "tick_cmpr");
|
5413 | a7812ae4 | pbrook | cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0, |
5414 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, stick_cmpr), |
5415 | 255e1fcb | blueswir1 | "stick_cmpr");
|
5416 | a7812ae4 | pbrook | cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0, |
5417 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, hstick_cmpr), |
5418 | 255e1fcb | blueswir1 | "hstick_cmpr");
|
5419 | c5f9864e | Andreas Färber | cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hintp), |
5420 | 255e1fcb | blueswir1 | "hintp");
|
5421 | c5f9864e | Andreas Färber | cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, htba), |
5422 | a7812ae4 | pbrook | "htba");
|
5423 | c5f9864e | Andreas Färber | cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, hver), |
5424 | a7812ae4 | pbrook | "hver");
|
5425 | a7812ae4 | pbrook | cpu_ssr = tcg_global_mem_new(TCG_AREG0, |
5426 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, ssr), "ssr");
|
5427 | a7812ae4 | pbrook | cpu_ver = tcg_global_mem_new(TCG_AREG0, |
5428 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, version), "ver");
|
5429 | a7812ae4 | pbrook | cpu_softint = tcg_global_mem_new_i32(TCG_AREG0, |
5430 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, softint), |
5431 | a7812ae4 | pbrook | "softint");
|
5432 | 255e1fcb | blueswir1 | #else
|
5433 | c5f9864e | Andreas Färber | cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, wim), |
5434 | 255e1fcb | blueswir1 | "wim");
|
5435 | 1a2fb1c0 | blueswir1 | #endif
|
5436 | c5f9864e | Andreas Färber | cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cond), |
5437 | 77f193da | blueswir1 | "cond");
|
5438 | c5f9864e | Andreas Färber | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_src), |
5439 | dc99a3f2 | blueswir1 | "cc_src");
|
5440 | a7812ae4 | pbrook | cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, |
5441 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, cc_src2), |
5442 | d9bdab86 | blueswir1 | "cc_src2");
|
5443 | c5f9864e | Andreas Färber | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, cc_dst), |
5444 | dc99a3f2 | blueswir1 | "cc_dst");
|
5445 | c5f9864e | Andreas Färber | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, cc_op), |
5446 | 8393617c | Blue Swirl | "cc_op");
|
5447 | c5f9864e | Andreas Färber | cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSPARCState, psr), |
5448 | a7812ae4 | pbrook | "psr");
|
5449 | c5f9864e | Andreas Färber | cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, fsr), |
5450 | 87e92502 | blueswir1 | "fsr");
|
5451 | c5f9864e | Andreas Färber | cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, pc), |
5452 | 48d5c82b | blueswir1 | "pc");
|
5453 | c5f9864e | Andreas Färber | cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, npc), |
5454 | a7812ae4 | pbrook | "npc");
|
5455 | c5f9864e | Andreas Färber | cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, y), "y");
|
5456 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
|
5457 | c5f9864e | Andreas Färber | cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUSPARCState, tbr), |
5458 | 255e1fcb | blueswir1 | "tbr");
|
5459 | 255e1fcb | blueswir1 | #endif
|
5460 | 30038fd8 | Richard Henderson | for (i = 1; i < 8; i++) { |
5461 | a7812ae4 | pbrook | cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0, |
5462 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, gregs[i]), |
5463 | f5069b26 | blueswir1 | gregnames[i]); |
5464 | 30038fd8 | Richard Henderson | } |
5465 | 30038fd8 | Richard Henderson | for (i = 0; i < TARGET_DPREGS; i++) { |
5466 | 30038fd8 | Richard Henderson | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
5467 | c5f9864e | Andreas Färber | offsetof(CPUSPARCState, fpr[i]), |
5468 | 45c7b743 | Richard Henderson | fregnames[i]); |
5469 | 30038fd8 | Richard Henderson | } |
5470 | 714547bb | blueswir1 | |
5471 | c9e03d8f | blueswir1 | /* register helpers */
|
5472 | c9e03d8f | blueswir1 | |
5473 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
5474 | c9e03d8f | blueswir1 | #include "helper.h" |
5475 | 1a2fb1c0 | blueswir1 | } |
5476 | 658138bc | bellard | } |
5477 | d2856f1a | aurel32 | |
5478 | c5f9864e | Andreas Färber | void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb, int pc_pos) |
5479 | d2856f1a | aurel32 | { |
5480 | d2856f1a | aurel32 | target_ulong npc; |
5481 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
5482 | d2856f1a | aurel32 | npc = gen_opc_npc[pc_pos]; |
5483 | d2856f1a | aurel32 | if (npc == 1) { |
5484 | d2856f1a | aurel32 | /* dynamic NPC: already stored */
|
5485 | d2856f1a | aurel32 | } else if (npc == 2) { |
5486 | d7da2a10 | Blue Swirl | /* jump PC: use 'cond' and the jump targets of the translation */
|
5487 | d7da2a10 | Blue Swirl | if (env->cond) {
|
5488 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[0];
|
5489 | d7da2a10 | Blue Swirl | } else {
|
5490 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[1];
|
5491 | d7da2a10 | Blue Swirl | } |
5492 | d2856f1a | aurel32 | } else {
|
5493 | d2856f1a | aurel32 | env->npc = npc; |
5494 | d2856f1a | aurel32 | } |
5495 | d2856f1a | aurel32 | } |