Statistics
| Branch: | Revision:

root / dis-asm.h @ efe72c8d

History | View | Annotate | Download (18.2 kB)

1 dc99065b bellard
/* Interface between the opcode library and its callers.
2 dc99065b bellard
   Written by Cygnus Support, 1993.
3 dc99065b bellard

4 dc99065b bellard
   The opcode library (libopcodes.a) provides instruction decoders for
5 dc99065b bellard
   a large variety of instruction sets, callable with an identical
6 dc99065b bellard
   interface, for making instruction-processing programs more independent
7 dc99065b bellard
   of the instruction set being processed.  */
8 dc99065b bellard
9 dc99065b bellard
#ifndef DIS_ASM_H
10 dc99065b bellard
#define DIS_ASM_H
11 dc99065b bellard
12 c27004ec bellard
#include <stdlib.h>
13 47cbc7aa Juan Quintela
#include <stdbool.h>
14 dc99065b bellard
#include <stdio.h>
15 04369ff2 bellard
#include <string.h>
16 43d4145a bellard
#include <inttypes.h>
17 43d4145a bellard
18 43d4145a bellard
typedef void *PTR;
19 43d4145a bellard
typedef uint64_t bfd_vma;
20 bc51c5c9 bellard
typedef int64_t bfd_signed_vma;
21 43d4145a bellard
typedef uint8_t bfd_byte;
22 bc51c5c9 bellard
#define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)
23 363a37d5 blueswir1
#define snprintf_vma(s,ss,x) snprintf (s, ss, "%0" PRIx64, x)
24 43d4145a bellard
25 c27004ec bellard
#define BFD64
26 c27004ec bellard
27 43d4145a bellard
enum bfd_flavour {
28 43d4145a bellard
  bfd_target_unknown_flavour,
29 43d4145a bellard
  bfd_target_aout_flavour,
30 43d4145a bellard
  bfd_target_coff_flavour,
31 43d4145a bellard
  bfd_target_ecoff_flavour,
32 43d4145a bellard
  bfd_target_elf_flavour,
33 43d4145a bellard
  bfd_target_ieee_flavour,
34 43d4145a bellard
  bfd_target_nlm_flavour,
35 43d4145a bellard
  bfd_target_oasys_flavour,
36 43d4145a bellard
  bfd_target_tekhex_flavour,
37 43d4145a bellard
  bfd_target_srec_flavour,
38 43d4145a bellard
  bfd_target_ihex_flavour,
39 43d4145a bellard
  bfd_target_som_flavour,
40 43d4145a bellard
  bfd_target_os9k_flavour,
41 43d4145a bellard
  bfd_target_versados_flavour,
42 43d4145a bellard
  bfd_target_msdos_flavour,
43 43d4145a bellard
  bfd_target_evax_flavour
44 43d4145a bellard
};
45 43d4145a bellard
46 43d4145a bellard
enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
47 43d4145a bellard
48 5fafdf24 ths
enum bfd_architecture
49 43d4145a bellard
{
50 43d4145a bellard
  bfd_arch_unknown,    /* File arch not known */
51 43d4145a bellard
  bfd_arch_obscure,    /* Arch known, not one of these */
52 43d4145a bellard
  bfd_arch_m68k,       /* Motorola 68xxx */
53 43d4145a bellard
#define bfd_mach_m68000 1
54 43d4145a bellard
#define bfd_mach_m68008 2
55 43d4145a bellard
#define bfd_mach_m68010 3
56 43d4145a bellard
#define bfd_mach_m68020 4
57 43d4145a bellard
#define bfd_mach_m68030 5
58 43d4145a bellard
#define bfd_mach_m68040 6
59 43d4145a bellard
#define bfd_mach_m68060 7
60 48024e4a bellard
#define bfd_mach_cpu32  8
61 48024e4a bellard
#define bfd_mach_mcf5200  9
62 48024e4a bellard
#define bfd_mach_mcf5206e 10
63 48024e4a bellard
#define bfd_mach_mcf5307  11
64 48024e4a bellard
#define bfd_mach_mcf5407  12
65 48024e4a bellard
#define bfd_mach_mcf528x  13
66 48024e4a bellard
#define bfd_mach_mcfv4e   14
67 48024e4a bellard
#define bfd_mach_mcf521x   15
68 48024e4a bellard
#define bfd_mach_mcf5249   16
69 48024e4a bellard
#define bfd_mach_mcf547x   17
70 48024e4a bellard
#define bfd_mach_mcf548x   18
71 3b46e624 ths
  bfd_arch_vax,        /* DEC Vax */
72 43d4145a bellard
  bfd_arch_i960,       /* Intel 960 */
73 43d4145a bellard
     /* The order of the following is important.
74 5fafdf24 ths
       lower number indicates a machine type that
75 43d4145a bellard
       only accepts a subset of the instructions
76 43d4145a bellard
       available to machines with higher numbers.
77 43d4145a bellard
       The exception is the "ca", which is
78 5fafdf24 ths
       incompatible with all other machines except
79 43d4145a bellard
       "core". */
80 43d4145a bellard
81 43d4145a bellard
#define bfd_mach_i960_core      1
82 43d4145a bellard
#define bfd_mach_i960_ka_sa     2
83 43d4145a bellard
#define bfd_mach_i960_kb_sb     3
84 43d4145a bellard
#define bfd_mach_i960_mc        4
85 43d4145a bellard
#define bfd_mach_i960_xa        5
86 43d4145a bellard
#define bfd_mach_i960_ca        6
87 43d4145a bellard
#define bfd_mach_i960_jx        7
88 43d4145a bellard
#define bfd_mach_i960_hx        8
89 43d4145a bellard
90 43d4145a bellard
  bfd_arch_a29k,       /* AMD 29000 */
91 43d4145a bellard
  bfd_arch_sparc,      /* SPARC */
92 43d4145a bellard
#define bfd_mach_sparc                 1
93 aa0aa4fa bellard
/* The difference between v8plus and v9 is that v9 is a true 64 bit env.  */
94 43d4145a bellard
#define bfd_mach_sparc_sparclet        2
95 43d4145a bellard
#define bfd_mach_sparc_sparclite       3
96 43d4145a bellard
#define bfd_mach_sparc_v8plus          4
97 aa0aa4fa bellard
#define bfd_mach_sparc_v8plusa         5 /* with ultrasparc add'ns.  */
98 aa0aa4fa bellard
#define bfd_mach_sparc_sparclite_le    6
99 aa0aa4fa bellard
#define bfd_mach_sparc_v9              7
100 aa0aa4fa bellard
#define bfd_mach_sparc_v9a             8 /* with ultrasparc add'ns.  */
101 aa0aa4fa bellard
#define bfd_mach_sparc_v8plusb         9 /* with cheetah add'ns.  */
102 aa0aa4fa bellard
#define bfd_mach_sparc_v9b             10 /* with cheetah add'ns.  */
103 aa0aa4fa bellard
/* Nonzero if MACH has the v9 instruction set.  */
104 43d4145a bellard
#define bfd_mach_sparc_v9_p(mach) \
105 aa0aa4fa bellard
  ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
106 aa0aa4fa bellard
   && (mach) != bfd_mach_sparc_sparclite_le)
107 43d4145a bellard
  bfd_arch_mips,       /* MIPS Rxxxx */
108 43d4145a bellard
#define bfd_mach_mips3000              3000
109 43d4145a bellard
#define bfd_mach_mips3900              3900
110 43d4145a bellard
#define bfd_mach_mips4000              4000
111 43d4145a bellard
#define bfd_mach_mips4010              4010
112 43d4145a bellard
#define bfd_mach_mips4100              4100
113 43d4145a bellard
#define bfd_mach_mips4300              4300
114 43d4145a bellard
#define bfd_mach_mips4400              4400
115 43d4145a bellard
#define bfd_mach_mips4600              4600
116 43d4145a bellard
#define bfd_mach_mips4650              4650
117 43d4145a bellard
#define bfd_mach_mips5000              5000
118 43d4145a bellard
#define bfd_mach_mips6000              6000
119 43d4145a bellard
#define bfd_mach_mips8000              8000
120 43d4145a bellard
#define bfd_mach_mips10000             10000
121 43d4145a bellard
#define bfd_mach_mips16                16
122 43d4145a bellard
  bfd_arch_i386,       /* Intel 386 */
123 43d4145a bellard
#define bfd_mach_i386_i386 0
124 43d4145a bellard
#define bfd_mach_i386_i8086 1
125 bc51c5c9 bellard
#define bfd_mach_i386_i386_intel_syntax 2
126 bc51c5c9 bellard
#define bfd_mach_x86_64 3
127 bc51c5c9 bellard
#define bfd_mach_x86_64_intel_syntax 4
128 43d4145a bellard
  bfd_arch_we32k,      /* AT&T WE32xxx */
129 43d4145a bellard
  bfd_arch_tahoe,      /* CCI/Harris Tahoe */
130 43d4145a bellard
  bfd_arch_i860,       /* Intel 860 */
131 43d4145a bellard
  bfd_arch_romp,       /* IBM ROMP PC/RT */
132 43d4145a bellard
  bfd_arch_alliant,    /* Alliant */
133 43d4145a bellard
  bfd_arch_convex,     /* Convex */
134 43d4145a bellard
  bfd_arch_m88k,       /* Motorola 88xxx */
135 43d4145a bellard
  bfd_arch_pyramid,    /* Pyramid Technology */
136 43d4145a bellard
  bfd_arch_h8300,      /* Hitachi H8/300 */
137 43d4145a bellard
#define bfd_mach_h8300   1
138 43d4145a bellard
#define bfd_mach_h8300h  2
139 43d4145a bellard
#define bfd_mach_h8300s  3
140 43d4145a bellard
  bfd_arch_powerpc,    /* PowerPC */
141 a2458627 bellard
#define bfd_mach_ppc           0
142 a2458627 bellard
#define bfd_mach_ppc64         1
143 a2458627 bellard
#define bfd_mach_ppc_403       403
144 a2458627 bellard
#define bfd_mach_ppc_403gc     4030
145 eca8f888 blueswir1
#define bfd_mach_ppc_e500      500
146 a2458627 bellard
#define bfd_mach_ppc_505       505
147 a2458627 bellard
#define bfd_mach_ppc_601       601
148 a2458627 bellard
#define bfd_mach_ppc_602       602
149 a2458627 bellard
#define bfd_mach_ppc_603       603
150 a2458627 bellard
#define bfd_mach_ppc_ec603e    6031
151 a2458627 bellard
#define bfd_mach_ppc_604       604
152 a2458627 bellard
#define bfd_mach_ppc_620       620
153 a2458627 bellard
#define bfd_mach_ppc_630       630
154 a2458627 bellard
#define bfd_mach_ppc_750       750
155 a2458627 bellard
#define bfd_mach_ppc_860       860
156 a2458627 bellard
#define bfd_mach_ppc_a35       35
157 a2458627 bellard
#define bfd_mach_ppc_rs64ii    642
158 a2458627 bellard
#define bfd_mach_ppc_rs64iii   643
159 a2458627 bellard
#define bfd_mach_ppc_7400      7400
160 43d4145a bellard
  bfd_arch_rs6000,     /* IBM RS/6000 */
161 43d4145a bellard
  bfd_arch_hppa,       /* HP PA RISC */
162 f54b3f92 aurel32
#define bfd_mach_hppa10        10
163 f54b3f92 aurel32
#define bfd_mach_hppa11        11
164 f54b3f92 aurel32
#define bfd_mach_hppa20        20
165 f54b3f92 aurel32
#define bfd_mach_hppa20w       25
166 43d4145a bellard
  bfd_arch_d10v,       /* Mitsubishi D10V */
167 43d4145a bellard
  bfd_arch_z8k,        /* Zilog Z8000 */
168 43d4145a bellard
#define bfd_mach_z8001         1
169 43d4145a bellard
#define bfd_mach_z8002         2
170 43d4145a bellard
  bfd_arch_h8500,      /* Hitachi H8/500 */
171 43d4145a bellard
  bfd_arch_sh,         /* Hitachi SH */
172 fdf9b3e8 bellard
#define bfd_mach_sh            1
173 fdf9b3e8 bellard
#define bfd_mach_sh2        0x20
174 fdf9b3e8 bellard
#define bfd_mach_sh_dsp     0x2d
175 fdf9b3e8 bellard
#define bfd_mach_sh2a       0x2a
176 fdf9b3e8 bellard
#define bfd_mach_sh2a_nofpu 0x2b
177 fdf9b3e8 bellard
#define bfd_mach_sh2e       0x2e
178 43d4145a bellard
#define bfd_mach_sh3        0x30
179 fdf9b3e8 bellard
#define bfd_mach_sh3_nommu  0x31
180 fdf9b3e8 bellard
#define bfd_mach_sh3_dsp    0x3d
181 43d4145a bellard
#define bfd_mach_sh3e       0x3e
182 43d4145a bellard
#define bfd_mach_sh4        0x40
183 fdf9b3e8 bellard
#define bfd_mach_sh4_nofpu  0x41
184 fdf9b3e8 bellard
#define bfd_mach_sh4_nommu_nofpu  0x42
185 fdf9b3e8 bellard
#define bfd_mach_sh4a       0x4a
186 fdf9b3e8 bellard
#define bfd_mach_sh4a_nofpu 0x4b
187 fdf9b3e8 bellard
#define bfd_mach_sh4al_dsp  0x4d
188 fdf9b3e8 bellard
#define bfd_mach_sh5        0x50
189 43d4145a bellard
  bfd_arch_alpha,      /* Dec Alpha */
190 eddf68a6 j_mayer
#define bfd_mach_alpha 1
191 43d4145a bellard
  bfd_arch_arm,        /* Advanced Risc Machines ARM */
192 4b0f1a8b pbrook
#define bfd_mach_arm_unknown        0
193 4b0f1a8b pbrook
#define bfd_mach_arm_2                1
194 4b0f1a8b pbrook
#define bfd_mach_arm_2a                2
195 4b0f1a8b pbrook
#define bfd_mach_arm_3                3
196 4b0f1a8b pbrook
#define bfd_mach_arm_3M         4
197 4b0f1a8b pbrook
#define bfd_mach_arm_4                 5
198 4b0f1a8b pbrook
#define bfd_mach_arm_4T         6
199 4b0f1a8b pbrook
#define bfd_mach_arm_5                 7
200 4b0f1a8b pbrook
#define bfd_mach_arm_5T                8
201 4b0f1a8b pbrook
#define bfd_mach_arm_5TE        9
202 4b0f1a8b pbrook
#define bfd_mach_arm_XScale        10
203 4b0f1a8b pbrook
#define bfd_mach_arm_ep9312        11
204 4b0f1a8b pbrook
#define bfd_mach_arm_iWMMXt        12
205 4b0f1a8b pbrook
#define bfd_mach_arm_iWMMXt2        13
206 43d4145a bellard
  bfd_arch_ns32k,      /* National Semiconductors ns32000 */
207 43d4145a bellard
  bfd_arch_w65,        /* WDC 65816 */
208 43d4145a bellard
  bfd_arch_tic30,      /* Texas Instruments TMS320C30 */
209 43d4145a bellard
  bfd_arch_v850,       /* NEC V850 */
210 43d4145a bellard
#define bfd_mach_v850          0
211 43d4145a bellard
  bfd_arch_arc,        /* Argonaut RISC Core */
212 43d4145a bellard
#define bfd_mach_arc_base 0
213 43d4145a bellard
  bfd_arch_m32r,       /* Mitsubishi M32R/D */
214 43d4145a bellard
#define bfd_mach_m32r          0  /* backwards compatibility */
215 43d4145a bellard
  bfd_arch_mn10200,    /* Matsushita MN10200 */
216 43d4145a bellard
  bfd_arch_mn10300,    /* Matsushita MN10300 */
217 a25fd137 ths
  bfd_arch_cris,       /* Axis CRIS */
218 a25fd137 ths
#define bfd_mach_cris_v0_v10   255
219 a25fd137 ths
#define bfd_mach_cris_v32      32
220 a25fd137 ths
#define bfd_mach_cris_v10_v32  1032
221 e90e390c Edgar E. Iglesias
  bfd_arch_microblaze, /* Xilinx MicroBlaze.  */
222 903ec55c Aurelien Jarno
  bfd_arch_ia64,      /* HP/Intel ia64 */
223 903ec55c Aurelien Jarno
#define bfd_mach_ia64_elf64    64
224 903ec55c Aurelien Jarno
#define bfd_mach_ia64_elf32    32
225 43d4145a bellard
  bfd_arch_last
226 43d4145a bellard
  };
227 8f860bb8 ths
#define bfd_mach_s390_31 31
228 8f860bb8 ths
#define bfd_mach_s390_64 64
229 43d4145a bellard
230 43d4145a bellard
typedef struct symbol_cache_entry
231 43d4145a bellard
{
232 43d4145a bellard
    const char *name;
233 43d4145a bellard
    union
234 43d4145a bellard
    {
235 43d4145a bellard
        PTR p;
236 43d4145a bellard
        bfd_vma i;
237 43d4145a bellard
    } udata;
238 43d4145a bellard
} asymbol;
239 dc99065b bellard
240 9262f384 Juan Quintela
typedef int (*fprintf_ftype) (FILE*, const char*, ...);
241 dc99065b bellard
242 dc99065b bellard
enum dis_insn_type {
243 dc99065b bellard
  dis_noninsn,                        /* Not a valid instruction */
244 dc99065b bellard
  dis_nonbranch,                /* Not a branch instruction */
245 dc99065b bellard
  dis_branch,                        /* Unconditional branch */
246 dc99065b bellard
  dis_condbranch,                /* Conditional branch */
247 dc99065b bellard
  dis_jsr,                        /* Jump to subroutine */
248 dc99065b bellard
  dis_condjsr,                        /* Conditional jump to subroutine */
249 dc99065b bellard
  dis_dref,                        /* Data reference instruction */
250 dc99065b bellard
  dis_dref2                        /* Two data references in instruction */
251 dc99065b bellard
};
252 dc99065b bellard
253 5fafdf24 ths
/* This struct is passed into the instruction decoding routine,
254 dc99065b bellard
   and is passed back out into each callback.  The various fields are used
255 dc99065b bellard
   for conveying information from your main routine into your callbacks,
256 dc99065b bellard
   for passing information into the instruction decoders (such as the
257 dc99065b bellard
   addresses of the callback functions), or for passing information
258 dc99065b bellard
   back from the instruction decoders to their callers.
259 dc99065b bellard

260 dc99065b bellard
   It must be initialized before it is first passed; this can be done
261 dc99065b bellard
   by hand, or using one of the initialization macros below.  */
262 dc99065b bellard
263 dc99065b bellard
typedef struct disassemble_info {
264 dc99065b bellard
  fprintf_ftype fprintf_func;
265 dc99065b bellard
  FILE *stream;
266 dc99065b bellard
  PTR application_data;
267 dc99065b bellard
268 dc99065b bellard
  /* Target description.  We could replace this with a pointer to the bfd,
269 dc99065b bellard
     but that would require one.  There currently isn't any such requirement
270 dc99065b bellard
     so to avoid introducing one we record these explicitly.  */
271 dc99065b bellard
  /* The bfd_flavour.  This can be bfd_target_unknown_flavour.  */
272 dc99065b bellard
  enum bfd_flavour flavour;
273 dc99065b bellard
  /* The bfd_arch value.  */
274 dc99065b bellard
  enum bfd_architecture arch;
275 dc99065b bellard
  /* The bfd_mach value.  */
276 dc99065b bellard
  unsigned long mach;
277 dc99065b bellard
  /* Endianness (for bi-endian cpus).  Mono-endian cpus can ignore this.  */
278 dc99065b bellard
  enum bfd_endian endian;
279 dc99065b bellard
280 dc99065b bellard
  /* An array of pointers to symbols either at the location being disassembled
281 dc99065b bellard
     or at the start of the function being disassembled.  The array is sorted
282 dc99065b bellard
     so that the first symbol is intended to be the one used.  The others are
283 dc99065b bellard
     present for any misc. purposes.  This is not set reliably, but if it is
284 dc99065b bellard
     not NULL, it is correct.  */
285 dc99065b bellard
  asymbol **symbols;
286 dc99065b bellard
  /* Number of symbols in array.  */
287 dc99065b bellard
  int num_symbols;
288 dc99065b bellard
289 dc99065b bellard
  /* For use by the disassembler.
290 dc99065b bellard
     The top 16 bits are reserved for public use (and are documented here).
291 dc99065b bellard
     The bottom 16 bits are for the internal use of the disassembler.  */
292 dc99065b bellard
  unsigned long flags;
293 dc99065b bellard
#define INSN_HAS_RELOC        0x80000000
294 dc99065b bellard
  PTR private_data;
295 dc99065b bellard
296 dc99065b bellard
  /* Function used to get bytes to disassemble.  MEMADDR is the
297 dc99065b bellard
     address of the stuff to be disassembled, MYADDR is the address to
298 dc99065b bellard
     put the bytes in, and LENGTH is the number of bytes to read.
299 dc99065b bellard
     INFO is a pointer to this struct.
300 dc99065b bellard
     Returns an errno value or 0 for success.  */
301 dc99065b bellard
  int (*read_memory_func)
302 9262f384 Juan Quintela
    (bfd_vma memaddr, bfd_byte *myaddr, int length,
303 9262f384 Juan Quintela
             struct disassemble_info *info);
304 dc99065b bellard
305 dc99065b bellard
  /* Function which should be called if we get an error that we can't
306 dc99065b bellard
     recover from.  STATUS is the errno value from read_memory_func and
307 dc99065b bellard
     MEMADDR is the address that we were trying to read.  INFO is a
308 dc99065b bellard
     pointer to this struct.  */
309 dc99065b bellard
  void (*memory_error_func)
310 9262f384 Juan Quintela
    (int status, bfd_vma memaddr, struct disassemble_info *info);
311 dc99065b bellard
312 dc99065b bellard
  /* Function called to print ADDR.  */
313 dc99065b bellard
  void (*print_address_func)
314 9262f384 Juan Quintela
    (bfd_vma addr, struct disassemble_info *info);
315 dc99065b bellard
316 dc99065b bellard
  /* Function called to determine if there is a symbol at the given ADDR.
317 dc99065b bellard
     If there is, the function returns 1, otherwise it returns 0.
318 dc99065b bellard
     This is used by ports which support an overlay manager where
319 dc99065b bellard
     the overlay number is held in the top part of an address.  In
320 dc99065b bellard
     some circumstances we want to include the overlay number in the
321 dc99065b bellard
     address, (normally because there is a symbol associated with
322 dc99065b bellard
     that address), but sometimes we want to mask out the overlay bits.  */
323 dc99065b bellard
  int (* symbol_at_address_func)
324 9262f384 Juan Quintela
    (bfd_vma addr, struct disassemble_info * info);
325 dc99065b bellard
326 dc99065b bellard
  /* These are for buffer_read_memory.  */
327 dc99065b bellard
  bfd_byte *buffer;
328 dc99065b bellard
  bfd_vma buffer_vma;
329 dc99065b bellard
  int buffer_length;
330 dc99065b bellard
331 dc99065b bellard
  /* This variable may be set by the instruction decoder.  It suggests
332 dc99065b bellard
      the number of bytes objdump should display on a single line.  If
333 dc99065b bellard
      the instruction decoder sets this, it should always set it to
334 dc99065b bellard
      the same value in order to get reasonable looking output.  */
335 dc99065b bellard
  int bytes_per_line;
336 dc99065b bellard
337 dc99065b bellard
  /* the next two variables control the way objdump displays the raw data */
338 dc99065b bellard
  /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
339 dc99065b bellard
  /* output will look like this:
340 dc99065b bellard
     00:   00000000 00000000
341 dc99065b bellard
     with the chunks displayed according to "display_endian". */
342 dc99065b bellard
  int bytes_per_chunk;
343 dc99065b bellard
  enum bfd_endian display_endian;
344 dc99065b bellard
345 dc99065b bellard
  /* Results from instruction decoders.  Not all decoders yet support
346 dc99065b bellard
     this information.  This info is set each time an instruction is
347 dc99065b bellard
     decoded, and is only valid for the last such instruction.
348 dc99065b bellard

349 dc99065b bellard
     To determine whether this decoder supports this information, set
350 dc99065b bellard
     insn_info_valid to 0, decode an instruction, then check it.  */
351 dc99065b bellard
352 dc99065b bellard
  char insn_info_valid;                /* Branch info has been set. */
353 dc99065b bellard
  char branch_delay_insns;        /* How many sequential insn's will run before
354 dc99065b bellard
                                   a branch takes effect.  (0 = normal) */
355 dc99065b bellard
  char data_size;                /* Size of data reference in insn, in bytes */
356 dc99065b bellard
  enum dis_insn_type insn_type;        /* Type of instruction */
357 dc99065b bellard
  bfd_vma target;                /* Target address of branch or dref, if known;
358 dc99065b bellard
                                   zero if unknown.  */
359 dc99065b bellard
  bfd_vma target2;                /* Second target address for dref2 */
360 dc99065b bellard
361 aa0aa4fa bellard
  /* Command line options specific to the target disassembler.  */
362 aa0aa4fa bellard
  char * disassembler_options;
363 aa0aa4fa bellard
364 dc99065b bellard
} disassemble_info;
365 dc99065b bellard
366 dc99065b bellard
 
367 dc99065b bellard
/* Standard disassemblers.  Disassemble one instruction at the given
368 dc99065b bellard
   target address.  Return number of bytes processed.  */
369 9262f384 Juan Quintela
typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
370 9262f384 Juan Quintela
371 9262f384 Juan Quintela
extern int print_insn_big_mips                (bfd_vma, disassemble_info*);
372 9262f384 Juan Quintela
extern int print_insn_little_mips        (bfd_vma, disassemble_info*);
373 9262f384 Juan Quintela
extern int print_insn_i386                (bfd_vma, disassemble_info*);
374 9262f384 Juan Quintela
extern int print_insn_m68k                (bfd_vma, disassemble_info*);
375 9262f384 Juan Quintela
extern int print_insn_z8001                (bfd_vma, disassemble_info*);
376 9262f384 Juan Quintela
extern int print_insn_z8002                (bfd_vma, disassemble_info*);
377 9262f384 Juan Quintela
extern int print_insn_h8300                (bfd_vma, disassemble_info*);
378 9262f384 Juan Quintela
extern int print_insn_h8300h                (bfd_vma, disassemble_info*);
379 9262f384 Juan Quintela
extern int print_insn_h8300s                (bfd_vma, disassemble_info*);
380 9262f384 Juan Quintela
extern int print_insn_h8500                (bfd_vma, disassemble_info*);
381 9262f384 Juan Quintela
extern int print_insn_alpha                (bfd_vma, disassemble_info*);
382 9262f384 Juan Quintela
extern disassembler_ftype arc_get_disassembler (int, int);
383 9262f384 Juan Quintela
extern int print_insn_arm                (bfd_vma, disassemble_info*);
384 9262f384 Juan Quintela
extern int print_insn_sparc                (bfd_vma, disassemble_info*);
385 9262f384 Juan Quintela
extern int print_insn_big_a29k                (bfd_vma, disassemble_info*);
386 9262f384 Juan Quintela
extern int print_insn_little_a29k        (bfd_vma, disassemble_info*);
387 9262f384 Juan Quintela
extern int print_insn_i960                (bfd_vma, disassemble_info*);
388 9262f384 Juan Quintela
extern int print_insn_sh                (bfd_vma, disassemble_info*);
389 9262f384 Juan Quintela
extern int print_insn_shl                (bfd_vma, disassemble_info*);
390 9262f384 Juan Quintela
extern int print_insn_hppa                (bfd_vma, disassemble_info*);
391 9262f384 Juan Quintela
extern int print_insn_m32r                (bfd_vma, disassemble_info*);
392 9262f384 Juan Quintela
extern int print_insn_m88k                (bfd_vma, disassemble_info*);
393 9262f384 Juan Quintela
extern int print_insn_mn10200                (bfd_vma, disassemble_info*);
394 9262f384 Juan Quintela
extern int print_insn_mn10300                (bfd_vma, disassemble_info*);
395 9262f384 Juan Quintela
extern int print_insn_ns32k                (bfd_vma, disassemble_info*);
396 9262f384 Juan Quintela
extern int print_insn_big_powerpc        (bfd_vma, disassemble_info*);
397 9262f384 Juan Quintela
extern int print_insn_little_powerpc        (bfd_vma, disassemble_info*);
398 9262f384 Juan Quintela
extern int print_insn_rs6000                (bfd_vma, disassemble_info*);
399 9262f384 Juan Quintela
extern int print_insn_w65                (bfd_vma, disassemble_info*);
400 9262f384 Juan Quintela
extern int print_insn_d10v                (bfd_vma, disassemble_info*);
401 9262f384 Juan Quintela
extern int print_insn_v850                (bfd_vma, disassemble_info*);
402 9262f384 Juan Quintela
extern int print_insn_tic30                (bfd_vma, disassemble_info*);
403 9262f384 Juan Quintela
extern int print_insn_ppc                (bfd_vma, disassemble_info*);
404 9262f384 Juan Quintela
extern int print_insn_s390                (bfd_vma, disassemble_info*);
405 9262f384 Juan Quintela
extern int print_insn_crisv32           (bfd_vma, disassemble_info*);
406 9262f384 Juan Quintela
extern int print_insn_microblaze        (bfd_vma, disassemble_info*);
407 903ec55c Aurelien Jarno
extern int print_insn_ia64              (bfd_vma, disassemble_info*);
408 dc99065b bellard
409 43d4145a bellard
#if 0
410 dc99065b bellard
/* Fetch the disassembler for a given BFD, if that support is available.  */
411 9262f384 Juan Quintela
extern disassembler_ftype disassembler        (bfd *);
412 43d4145a bellard
#endif
413 dc99065b bellard
414 dc99065b bellard
 
415 dc99065b bellard
/* This block of definitions is for particular callers who read instructions
416 dc99065b bellard
   into a buffer before calling the instruction decoder.  */
417 dc99065b bellard
418 dc99065b bellard
/* Here is a function which callers may wish to use for read_memory_func.
419 dc99065b bellard
   It gets bytes from a buffer.  */
420 dc99065b bellard
extern int buffer_read_memory
421 9262f384 Juan Quintela
  (bfd_vma, bfd_byte *, int, struct disassemble_info *);
422 dc99065b bellard
423 dc99065b bellard
/* This function goes with buffer_read_memory.
424 dc99065b bellard
   It prints a message using info->fprintf_func and info->stream.  */
425 9262f384 Juan Quintela
extern void perror_memory (int, bfd_vma, struct disassemble_info *);
426 dc99065b bellard
427 dc99065b bellard
428 dc99065b bellard
/* Just print the address in hex.  This is included for completeness even
429 dc99065b bellard
   though both GDB and objdump provide their own (to print symbolic
430 dc99065b bellard
   addresses).  */
431 9262f384 Juan Quintela
extern void generic_print_address (bfd_vma, struct disassemble_info *);
432 dc99065b bellard
433 dc99065b bellard
/* Always true.  */
434 9262f384 Juan Quintela
extern int generic_symbol_at_address (bfd_vma, struct disassemble_info *);
435 dc99065b bellard
436 dc99065b bellard
/* Macro to initialize a disassemble_info struct.  This should be called
437 dc99065b bellard
   by all applications creating such a struct.  */
438 dc99065b bellard
#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
439 dc99065b bellard
  (INFO).flavour = bfd_target_unknown_flavour, \
440 dc99065b bellard
  (INFO).arch = bfd_arch_unknown, \
441 dc99065b bellard
  (INFO).mach = 0, \
442 dc99065b bellard
  (INFO).endian = BFD_ENDIAN_UNKNOWN, \
443 dc99065b bellard
  INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC)
444 dc99065b bellard
445 dc99065b bellard
/* Call this macro to initialize only the internal variables for the
446 dc99065b bellard
   disassembler.  Architecture dependent things such as byte order, or machine
447 dc99065b bellard
   variant are not touched by this macro.  This makes things much easier for
448 aa1f17c1 ths
   GDB which must initialize these things separately.  */
449 dc99065b bellard
450 dc99065b bellard
#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
451 dc99065b bellard
  (INFO).fprintf_func = (FPRINTF_FUNC), \
452 dc99065b bellard
  (INFO).stream = (STREAM), \
453 dc99065b bellard
  (INFO).symbols = NULL, \
454 dc99065b bellard
  (INFO).num_symbols = 0, \
455 77b087cd edgar_igl
  (INFO).private_data = NULL, \
456 dc99065b bellard
  (INFO).buffer = NULL, \
457 dc99065b bellard
  (INFO).buffer_vma = 0, \
458 dc99065b bellard
  (INFO).buffer_length = 0, \
459 dc99065b bellard
  (INFO).read_memory_func = buffer_read_memory, \
460 dc99065b bellard
  (INFO).memory_error_func = perror_memory, \
461 dc99065b bellard
  (INFO).print_address_func = generic_print_address, \
462 dc99065b bellard
  (INFO).symbol_at_address_func = generic_symbol_at_address, \
463 dc99065b bellard
  (INFO).flags = 0, \
464 dc99065b bellard
  (INFO).bytes_per_line = 0, \
465 dc99065b bellard
  (INFO).bytes_per_chunk = 0, \
466 dc99065b bellard
  (INFO).display_endian = BFD_ENDIAN_UNKNOWN, \
467 aa0aa4fa bellard
  (INFO).disassembler_options = NULL, \
468 dc99065b bellard
  (INFO).insn_info_valid = 0
469 dc99065b bellard
470 aa0aa4fa bellard
#define _(x) x
471 48024e4a bellard
#define ATTRIBUTE_UNUSED __attribute__((unused))
472 aa0aa4fa bellard
473 aa0aa4fa bellard
/* from libbfd */
474 aa0aa4fa bellard
475 903ec55c Aurelien Jarno
bfd_vma bfd_getl64 (const bfd_byte *addr);
476 aa0aa4fa bellard
bfd_vma bfd_getl32 (const bfd_byte *addr);
477 aa0aa4fa bellard
bfd_vma bfd_getb32 (const bfd_byte *addr);
478 6af0bf9c bellard
bfd_vma bfd_getl16 (const bfd_byte *addr);
479 6af0bf9c bellard
bfd_vma bfd_getb16 (const bfd_byte *addr);
480 47cbc7aa Juan Quintela
typedef bool bfd_boolean;
481 aa0aa4fa bellard
482 dc99065b bellard
#endif /* ! defined (DIS_ASM_H) */