root / hw / display / pl110.c @ efec3dd6
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/*
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* Arm PrimeCell PL110 Color LCD Controller
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*
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* Copyright (c) 2005-2009 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GNU LGPL
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*/
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#include "hw/sysbus.h" |
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#include "ui/console.h" |
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#include "framebuffer.h" |
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#include "ui/pixel_ops.h" |
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|
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#define PL110_CR_EN 0x001 |
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#define PL110_CR_BGR 0x100 |
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#define PL110_CR_BEBO 0x200 |
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#define PL110_CR_BEPO 0x400 |
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#define PL110_CR_PWR 0x800 |
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|
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enum pl110_bppmode
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{ |
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BPP_1, |
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BPP_2, |
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BPP_4, |
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BPP_8, |
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BPP_16, |
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BPP_32, |
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BPP_16_565, /* PL111 only */
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BPP_12 /* PL111 only */
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}; |
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|
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/* The Versatile/PB uses a slightly modified PL110 controller. */
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enum pl110_version
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{ |
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PL110, |
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PL110_VERSATILE, |
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PL111 |
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}; |
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#define TYPE_PL110 "pl110" |
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#define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
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typedef struct PL110State { |
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SysBusDevice parent_obj; |
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|
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MemoryRegion iomem; |
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QemuConsole *con; |
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int version;
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uint32_t timing[4];
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uint32_t cr; |
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uint32_t upbase; |
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uint32_t lpbase; |
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uint32_t int_status; |
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uint32_t int_mask; |
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int cols;
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int rows;
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enum pl110_bppmode bpp;
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int invalidate;
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uint32_t mux_ctrl; |
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uint32_t palette[256];
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uint32_t raw_palette[128];
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qemu_irq irq; |
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} PL110State; |
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static int vmstate_pl110_post_load(void *opaque, int version_id); |
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static const VMStateDescription vmstate_pl110 = { |
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.name = "pl110",
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.version_id = 2,
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.minimum_version_id = 1,
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.post_load = vmstate_pl110_post_load, |
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.fields = (VMStateField[]) { |
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VMSTATE_INT32(version, PL110State), |
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VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
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VMSTATE_UINT32(cr, PL110State), |
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VMSTATE_UINT32(upbase, PL110State), |
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VMSTATE_UINT32(lpbase, PL110State), |
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VMSTATE_UINT32(int_status, PL110State), |
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VMSTATE_UINT32(int_mask, PL110State), |
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VMSTATE_INT32(cols, PL110State), |
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VMSTATE_INT32(rows, PL110State), |
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VMSTATE_UINT32(bpp, PL110State), |
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VMSTATE_INT32(invalidate, PL110State), |
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VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
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VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
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VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const unsigned char pl110_id[] = |
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{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
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static const unsigned char pl111_id[] = { |
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0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1 |
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}; |
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/* Indexed by pl110_version */
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static const unsigned char *idregs[] = { |
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pl110_id, |
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/* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
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* has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
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* itself has the same ID values as a stock PL110, and guests (in
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* particular Linux) rely on this. We emulate what the hardware does,
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* rather than what the docs claim it ought to do.
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*/
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pl110_id, |
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pl111_id |
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}; |
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#define BITS 8 |
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#include "pl110_template.h" |
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#define BITS 15 |
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#include "pl110_template.h" |
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#define BITS 16 |
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#include "pl110_template.h" |
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#define BITS 24 |
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#include "pl110_template.h" |
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#define BITS 32 |
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#include "pl110_template.h" |
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static int pl110_enabled(PL110State *s) |
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{ |
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return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
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} |
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static void pl110_update_display(void *opaque) |
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{ |
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PL110State *s = (PL110State *)opaque; |
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SysBusDevice *sbd; |
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DisplaySurface *surface = qemu_console_surface(s->con); |
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drawfn* fntable; |
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drawfn fn; |
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int dest_width;
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int src_width;
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int bpp_offset;
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int first;
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int last;
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if (!pl110_enabled(s)) {
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return;
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} |
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sbd = SYS_BUS_DEVICE(s); |
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switch (surface_bits_per_pixel(surface)) {
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case 0: |
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return;
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case 8: |
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fntable = pl110_draw_fn_8; |
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dest_width = 1;
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break;
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case 15: |
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fntable = pl110_draw_fn_15; |
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dest_width = 2;
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break;
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case 16: |
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fntable = pl110_draw_fn_16; |
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dest_width = 2;
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break;
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case 24: |
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fntable = pl110_draw_fn_24; |
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dest_width = 3;
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break;
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case 32: |
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fntable = pl110_draw_fn_32; |
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dest_width = 4;
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break;
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default:
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fprintf(stderr, "pl110: Bad color depth\n");
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exit(1);
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} |
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if (s->cr & PL110_CR_BGR)
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bpp_offset = 0;
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else
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bpp_offset = 24;
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if ((s->version != PL111) && (s->bpp == BPP_16)) {
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/* The PL110's native 16 bit mode is 5551; however
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* most boards with a PL110 implement an external
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* mux which allows bits to be reshuffled to give
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* 565 format. The mux is typically controlled by
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* an external system register.
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* This is controlled by a GPIO input pin
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* so boards can wire it up to their register.
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*
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* The PL111 straightforwardly implements both
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* 5551 and 565 under control of the bpp field
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* in the LCDControl register.
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*/
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switch (s->mux_ctrl) {
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case 3: /* 565 BGR */ |
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bpp_offset = (BPP_16_565 - BPP_16); |
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break;
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case 1: /* 5551 */ |
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break;
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case 0: /* 888; also if we have loaded vmstate from an old version */ |
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case 2: /* 565 RGB */ |
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default:
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/* treat as 565 but honour BGR bit */
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bpp_offset += (BPP_16_565 - BPP_16); |
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break;
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} |
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} |
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if (s->cr & PL110_CR_BEBO)
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fn = fntable[s->bpp + 8 + bpp_offset];
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else if (s->cr & PL110_CR_BEPO) |
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fn = fntable[s->bpp + 16 + bpp_offset];
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else
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fn = fntable[s->bpp + bpp_offset]; |
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src_width = s->cols; |
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switch (s->bpp) {
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case BPP_1:
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src_width >>= 3;
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break;
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case BPP_2:
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src_width >>= 2;
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break;
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case BPP_4:
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src_width >>= 1;
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break;
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case BPP_8:
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break;
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case BPP_16:
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case BPP_16_565:
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case BPP_12:
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src_width <<= 1;
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break;
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case BPP_32:
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src_width <<= 2;
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break;
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} |
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dest_width *= s->cols; |
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first = 0;
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framebuffer_update_display(surface, sysbus_address_space(sbd), |
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s->upbase, s->cols, s->rows, |
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src_width, dest_width, 0,
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s->invalidate, |
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fn, s->palette, |
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&first, &last); |
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if (first >= 0) { |
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dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1); |
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} |
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s->invalidate = 0;
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} |
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static void pl110_invalidate_display(void * opaque) |
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{ |
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PL110State *s = (PL110State *)opaque; |
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s->invalidate = 1;
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if (pl110_enabled(s)) {
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qemu_console_resize(s->con, s->cols, s->rows); |
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} |
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} |
261 |
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static void pl110_update_palette(PL110State *s, int n) |
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{ |
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DisplaySurface *surface = qemu_console_surface(s->con); |
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int i;
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uint32_t raw; |
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unsigned int r, g, b; |
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raw = s->raw_palette[n]; |
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n <<= 1;
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for (i = 0; i < 2; i++) { |
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r = (raw & 0x1f) << 3; |
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raw >>= 5;
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g = (raw & 0x1f) << 3; |
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raw >>= 5;
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b = (raw & 0x1f) << 3; |
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/* The I bit is ignored. */
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raw >>= 6;
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switch (surface_bits_per_pixel(surface)) {
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case 8: |
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s->palette[n] = rgb_to_pixel8(r, g, b); |
282 |
break;
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case 15: |
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s->palette[n] = rgb_to_pixel15(r, g, b); |
285 |
break;
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case 16: |
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s->palette[n] = rgb_to_pixel16(r, g, b); |
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break;
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case 24: |
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case 32: |
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s->palette[n] = rgb_to_pixel32(r, g, b); |
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break;
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} |
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n++; |
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} |
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} |
297 |
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static void pl110_resize(PL110State *s, int width, int height) |
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{ |
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if (width != s->cols || height != s->rows) {
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if (pl110_enabled(s)) {
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qemu_console_resize(s->con, width, height); |
303 |
} |
304 |
} |
305 |
s->cols = width; |
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s->rows = height; |
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} |
308 |
|
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/* Update interrupts. */
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static void pl110_update(PL110State *s) |
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{ |
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/* TODO: Implement interrupts. */
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} |
314 |
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315 |
static uint64_t pl110_read(void *opaque, hwaddr offset, |
316 |
unsigned size)
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{ |
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PL110State *s = (PL110State *)opaque; |
319 |
|
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if (offset >= 0xfe0 && offset < 0x1000) { |
321 |
return idregs[s->version][(offset - 0xfe0) >> 2]; |
322 |
} |
323 |
if (offset >= 0x200 && offset < 0x400) { |
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return s->raw_palette[(offset - 0x200) >> 2]; |
325 |
} |
326 |
switch (offset >> 2) { |
327 |
case 0: /* LCDTiming0 */ |
328 |
return s->timing[0]; |
329 |
case 1: /* LCDTiming1 */ |
330 |
return s->timing[1]; |
331 |
case 2: /* LCDTiming2 */ |
332 |
return s->timing[2]; |
333 |
case 3: /* LCDTiming3 */ |
334 |
return s->timing[3]; |
335 |
case 4: /* LCDUPBASE */ |
336 |
return s->upbase;
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case 5: /* LCDLPBASE */ |
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return s->lpbase;
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case 6: /* LCDIMSC */ |
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if (s->version != PL110) {
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return s->cr;
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} |
343 |
return s->int_mask;
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case 7: /* LCDControl */ |
345 |
if (s->version != PL110) {
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return s->int_mask;
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} |
348 |
return s->cr;
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case 8: /* LCDRIS */ |
350 |
return s->int_status;
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case 9: /* LCDMIS */ |
352 |
return s->int_status & s->int_mask;
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353 |
case 11: /* LCDUPCURR */ |
354 |
/* TODO: Implement vertical refresh. */
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return s->upbase;
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case 12: /* LCDLPCURR */ |
357 |
return s->lpbase;
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default:
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359 |
qemu_log_mask(LOG_GUEST_ERROR, |
360 |
"pl110_read: Bad offset %x\n", (int)offset); |
361 |
return 0; |
362 |
} |
363 |
} |
364 |
|
365 |
static void pl110_write(void *opaque, hwaddr offset, |
366 |
uint64_t val, unsigned size)
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{ |
368 |
PL110State *s = (PL110State *)opaque; |
369 |
int n;
|
370 |
|
371 |
/* For simplicity invalidate the display whenever a control register
|
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is written to. */
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373 |
s->invalidate = 1;
|
374 |
if (offset >= 0x200 && offset < 0x400) { |
375 |
/* Palette. */
|
376 |
n = (offset - 0x200) >> 2; |
377 |
s->raw_palette[(offset - 0x200) >> 2] = val; |
378 |
pl110_update_palette(s, n); |
379 |
return;
|
380 |
} |
381 |
switch (offset >> 2) { |
382 |
case 0: /* LCDTiming0 */ |
383 |
s->timing[0] = val;
|
384 |
n = ((val & 0xfc) + 4) * 4; |
385 |
pl110_resize(s, n, s->rows); |
386 |
break;
|
387 |
case 1: /* LCDTiming1 */ |
388 |
s->timing[1] = val;
|
389 |
n = (val & 0x3ff) + 1; |
390 |
pl110_resize(s, s->cols, n); |
391 |
break;
|
392 |
case 2: /* LCDTiming2 */ |
393 |
s->timing[2] = val;
|
394 |
break;
|
395 |
case 3: /* LCDTiming3 */ |
396 |
s->timing[3] = val;
|
397 |
break;
|
398 |
case 4: /* LCDUPBASE */ |
399 |
s->upbase = val; |
400 |
break;
|
401 |
case 5: /* LCDLPBASE */ |
402 |
s->lpbase = val; |
403 |
break;
|
404 |
case 6: /* LCDIMSC */ |
405 |
if (s->version != PL110) {
|
406 |
goto control;
|
407 |
} |
408 |
imsc:
|
409 |
s->int_mask = val; |
410 |
pl110_update(s); |
411 |
break;
|
412 |
case 7: /* LCDControl */ |
413 |
if (s->version != PL110) {
|
414 |
goto imsc;
|
415 |
} |
416 |
control:
|
417 |
s->cr = val; |
418 |
s->bpp = (val >> 1) & 7; |
419 |
if (pl110_enabled(s)) {
|
420 |
qemu_console_resize(s->con, s->cols, s->rows); |
421 |
} |
422 |
break;
|
423 |
case 10: /* LCDICR */ |
424 |
s->int_status &= ~val; |
425 |
pl110_update(s); |
426 |
break;
|
427 |
default:
|
428 |
qemu_log_mask(LOG_GUEST_ERROR, |
429 |
"pl110_write: Bad offset %x\n", (int)offset); |
430 |
} |
431 |
} |
432 |
|
433 |
static const MemoryRegionOps pl110_ops = { |
434 |
.read = pl110_read, |
435 |
.write = pl110_write, |
436 |
.endianness = DEVICE_NATIVE_ENDIAN, |
437 |
}; |
438 |
|
439 |
static void pl110_mux_ctrl_set(void *opaque, int line, int level) |
440 |
{ |
441 |
PL110State *s = (PL110State *)opaque; |
442 |
s->mux_ctrl = level; |
443 |
} |
444 |
|
445 |
static int vmstate_pl110_post_load(void *opaque, int version_id) |
446 |
{ |
447 |
PL110State *s = opaque; |
448 |
/* Make sure we redraw, and at the right size */
|
449 |
pl110_invalidate_display(s); |
450 |
return 0; |
451 |
} |
452 |
|
453 |
static const GraphicHwOps pl110_gfx_ops = { |
454 |
.invalidate = pl110_invalidate_display, |
455 |
.gfx_update = pl110_update_display, |
456 |
}; |
457 |
|
458 |
static int pl110_initfn(SysBusDevice *sbd) |
459 |
{ |
460 |
DeviceState *dev = DEVICE(sbd); |
461 |
PL110State *s = PL110(dev); |
462 |
|
463 |
memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000); |
464 |
sysbus_init_mmio(sbd, &s->iomem); |
465 |
sysbus_init_irq(sbd, &s->irq); |
466 |
qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
|
467 |
s->con = graphic_console_init(dev, &pl110_gfx_ops, s); |
468 |
return 0; |
469 |
} |
470 |
|
471 |
static void pl110_init(Object *obj) |
472 |
{ |
473 |
PL110State *s = PL110(obj); |
474 |
|
475 |
s->version = PL110; |
476 |
} |
477 |
|
478 |
static void pl110_versatile_init(Object *obj) |
479 |
{ |
480 |
PL110State *s = PL110(obj); |
481 |
|
482 |
s->version = PL110_VERSATILE; |
483 |
} |
484 |
|
485 |
static void pl111_init(Object *obj) |
486 |
{ |
487 |
PL110State *s = PL110(obj); |
488 |
|
489 |
s->version = PL111; |
490 |
} |
491 |
|
492 |
static void pl110_class_init(ObjectClass *klass, void *data) |
493 |
{ |
494 |
DeviceClass *dc = DEVICE_CLASS(klass); |
495 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
496 |
|
497 |
k->init = pl110_initfn; |
498 |
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
499 |
dc->cannot_instantiate_with_device_add_yet = true; /* FIXME explain why */ |
500 |
dc->vmsd = &vmstate_pl110; |
501 |
} |
502 |
|
503 |
static const TypeInfo pl110_info = { |
504 |
.name = TYPE_PL110, |
505 |
.parent = TYPE_SYS_BUS_DEVICE, |
506 |
.instance_size = sizeof(PL110State),
|
507 |
.instance_init = pl110_init, |
508 |
.class_init = pl110_class_init, |
509 |
}; |
510 |
|
511 |
static const TypeInfo pl110_versatile_info = { |
512 |
.name = "pl110_versatile",
|
513 |
.parent = TYPE_PL110, |
514 |
.instance_init = pl110_versatile_init, |
515 |
}; |
516 |
|
517 |
static const TypeInfo pl111_info = { |
518 |
.name = "pl111",
|
519 |
.parent = TYPE_PL110, |
520 |
.instance_init = pl111_init, |
521 |
}; |
522 |
|
523 |
static void pl110_register_types(void) |
524 |
{ |
525 |
type_register_static(&pl110_info); |
526 |
type_register_static(&pl110_versatile_info); |
527 |
type_register_static(&pl111_info); |
528 |
} |
529 |
|
530 |
type_init(pl110_register_types) |