root / hw / timer / m48t59.c @ efec3dd6
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/*
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* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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*
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* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h" |
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#include "hw/timer/m48t59.h" |
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#include "qemu/timer.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/sysbus.h" |
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#include "hw/isa/isa.h" |
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#include "exec/address-spaces.h" |
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//#define DEBUG_NVRAM
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#if defined(DEBUG_NVRAM)
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#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define NVRAM_PRINTF(fmt, ...) do { } while (0) |
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#endif
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/*
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* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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* alarm and a watchdog timer and related control registers. In the
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* PPC platform there is also a nvram lock function.
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*/
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/*
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* Chipset docs:
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* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
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* http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
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* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
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*/
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struct M48t59State {
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/* Hardware parameters */
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qemu_irq IRQ; |
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MemoryRegion iomem; |
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uint32_t io_base; |
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uint32_t size; |
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/* RTC management */
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time_t time_offset; |
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time_t stop_time; |
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/* Alarm & watchdog */
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struct tm alarm;
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QEMUTimer *alrm_timer; |
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QEMUTimer *wd_timer; |
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/* NVRAM storage */
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uint8_t *buffer; |
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/* Model parameters */
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uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
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/* NVRAM storage */
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uint16_t addr; |
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uint8_t lock; |
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}; |
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|
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#define TYPE_ISA_M48T59 "m48t59_isa" |
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#define ISA_M48T59(obj) \
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OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59) |
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typedef struct M48t59ISAState { |
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ISADevice parent_obj; |
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|
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M48t59State state; |
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MemoryRegion io; |
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} M48t59ISAState; |
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#define SYSBUS_M48T59(obj) \
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OBJECT_CHECK(M48t59SysBusState, (obj), TYPE_SYSBUS_M48T59) |
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typedef struct M48t59SysBusState { |
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SysBusDevice parent_obj; |
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|
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M48t59State state; |
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MemoryRegion io; |
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} M48t59SysBusState; |
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|
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/* Fake timer functions */
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|
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/* Alarm management */
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static void alarm_cb (void *opaque) |
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{
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struct tm tm;
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uint64_t next_time; |
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M48t59State *NVRAM = opaque; |
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qemu_set_irq(NVRAM->IRQ, 1);
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if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a month */
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qemu_get_timedate(&tm, NVRAM->time_offset); |
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tm.tm_mon++; |
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if (tm.tm_mon == 13) { |
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tm.tm_mon = 1;
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tm.tm_year++; |
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} |
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next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a day */
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next_time = 24 * 60 * 60; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once an hour */
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next_time = 60 * 60; |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a minute */
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next_time = 60;
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} else {
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/* Repeat once a second */
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next_time = 1;
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} |
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timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) + |
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next_time * 1000);
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qemu_set_irq(NVRAM->IRQ, 0);
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} |
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|
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static void set_alarm(M48t59State *NVRAM) |
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{
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int diff;
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if (NVRAM->alrm_timer != NULL) { |
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timer_del(NVRAM->alrm_timer); |
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diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
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if (diff > 0) |
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timer_mod(NVRAM->alrm_timer, diff * 1000);
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} |
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} |
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|
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/* RTC management helpers */
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static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
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{
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qemu_get_timedate(tm, NVRAM->time_offset); |
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} |
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static void set_time(M48t59State *NVRAM, struct tm *tm) |
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{
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NVRAM->time_offset = qemu_timedate_diff(tm); |
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set_alarm(NVRAM); |
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} |
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/* Watchdog management */
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static void watchdog_cb (void *opaque) |
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{
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M48t59State *NVRAM = opaque; |
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|
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NVRAM->buffer[0x1FF0] |= 0x80; |
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if (NVRAM->buffer[0x1FF7] & 0x80) { |
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NVRAM->buffer[0x1FF7] = 0x00; |
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NVRAM->buffer[0x1FFC] &= ~0x40; |
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/* May it be a hw CPU Reset instead ? */
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qemu_system_reset_request(); |
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} else {
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qemu_set_irq(NVRAM->IRQ, 1);
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qemu_set_irq(NVRAM->IRQ, 0);
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} |
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} |
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|
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static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
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{
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uint64_t interval; /* in 1/16 seconds */
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NVRAM->buffer[0x1FF0] &= ~0x80; |
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if (NVRAM->wd_timer != NULL) { |
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timer_del(NVRAM->wd_timer); |
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if (value != 0) { |
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interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
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timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
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((interval * 1000) >> 4)); |
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} |
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} |
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} |
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|
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/* Direct access to NVRAM */
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void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
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{
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M48t59State *NVRAM = opaque; |
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struct tm tm;
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int tmp;
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|
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if (addr > 0x1FF8 && addr < 0x2000) |
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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|
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/* check for NVRAM access */
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if ((NVRAM->model == 2 && addr < 0x7f8) || |
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(NVRAM->model == 8 && addr < 0x1ff8) || |
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(NVRAM->model == 59 && addr < 0x1ff0)) { |
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goto do_write;
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} |
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|
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/* TOD access */
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switch (addr) {
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case 0x1FF0: |
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/* flags register : read-only */
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break;
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case 0x1FF1: |
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/* unused */
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break;
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case 0x1FF2: |
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/* alarm seconds */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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NVRAM->alarm.tm_sec = tmp; |
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM); |
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} |
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break;
|
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case 0x1FF3: |
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/* alarm minutes */
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tmp = from_bcd(val & 0x7F);
|
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if (tmp >= 0 && tmp <= 59) { |
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NVRAM->alarm.tm_min = tmp; |
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NVRAM->buffer[0x1FF3] = val;
|
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set_alarm(NVRAM); |
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} |
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break;
|
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case 0x1FF4: |
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/* alarm hours */
|
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tmp = from_bcd(val & 0x3F);
|
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if (tmp >= 0 && tmp <= 23) { |
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NVRAM->alarm.tm_hour = tmp; |
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NVRAM->buffer[0x1FF4] = val;
|
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set_alarm(NVRAM); |
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} |
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break;
|
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case 0x1FF5: |
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/* alarm date */
|
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tmp = from_bcd(val & 0x3F);
|
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if (tmp != 0) { |
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NVRAM->alarm.tm_mday = tmp; |
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NVRAM->buffer[0x1FF5] = val;
|
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set_alarm(NVRAM); |
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} |
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break;
|
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case 0x1FF6: |
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/* interrupts */
|
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NVRAM->buffer[0x1FF6] = val;
|
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break;
|
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case 0x1FF7: |
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/* watchdog */
|
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NVRAM->buffer[0x1FF7] = val;
|
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set_up_watchdog(NVRAM, val); |
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break;
|
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case 0x1FF8: |
| 271 |
case 0x07F8: |
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/* control */
|
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NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
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break;
|
| 275 |
case 0x1FF9: |
| 276 |
case 0x07F9: |
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/* seconds (BCD) */
|
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tmp = from_bcd(val & 0x7F);
|
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if (tmp >= 0 && tmp <= 59) { |
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get_time(NVRAM, &tm); |
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tm.tm_sec = tmp; |
| 282 |
set_time(NVRAM, &tm); |
| 283 |
} |
| 284 |
if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
| 285 |
if (val & 0x80) { |
| 286 |
NVRAM->stop_time = time(NULL);
|
| 287 |
} else {
|
| 288 |
NVRAM->time_offset += NVRAM->stop_time - time(NULL);
|
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NVRAM->stop_time = 0;
|
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} |
| 291 |
} |
| 292 |
NVRAM->buffer[addr] = val & 0x80;
|
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break;
|
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case 0x1FFA: |
| 295 |
case 0x07FA: |
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/* minutes (BCD) */
|
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tmp = from_bcd(val & 0x7F);
|
| 298 |
if (tmp >= 0 && tmp <= 59) { |
| 299 |
get_time(NVRAM, &tm); |
| 300 |
tm.tm_min = tmp; |
| 301 |
set_time(NVRAM, &tm); |
| 302 |
} |
| 303 |
break;
|
| 304 |
case 0x1FFB: |
| 305 |
case 0x07FB: |
| 306 |
/* hours (BCD) */
|
| 307 |
tmp = from_bcd(val & 0x3F);
|
| 308 |
if (tmp >= 0 && tmp <= 23) { |
| 309 |
get_time(NVRAM, &tm); |
| 310 |
tm.tm_hour = tmp; |
| 311 |
set_time(NVRAM, &tm); |
| 312 |
} |
| 313 |
break;
|
| 314 |
case 0x1FFC: |
| 315 |
case 0x07FC: |
| 316 |
/* day of the week / century */
|
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tmp = from_bcd(val & 0x07);
|
| 318 |
get_time(NVRAM, &tm); |
| 319 |
tm.tm_wday = tmp; |
| 320 |
set_time(NVRAM, &tm); |
| 321 |
NVRAM->buffer[addr] = val & 0x40;
|
| 322 |
break;
|
| 323 |
case 0x1FFD: |
| 324 |
case 0x07FD: |
| 325 |
/* date (BCD) */
|
| 326 |
tmp = from_bcd(val & 0x3F);
|
| 327 |
if (tmp != 0) { |
| 328 |
get_time(NVRAM, &tm); |
| 329 |
tm.tm_mday = tmp; |
| 330 |
set_time(NVRAM, &tm); |
| 331 |
} |
| 332 |
break;
|
| 333 |
case 0x1FFE: |
| 334 |
case 0x07FE: |
| 335 |
/* month */
|
| 336 |
tmp = from_bcd(val & 0x1F);
|
| 337 |
if (tmp >= 1 && tmp <= 12) { |
| 338 |
get_time(NVRAM, &tm); |
| 339 |
tm.tm_mon = tmp - 1;
|
| 340 |
set_time(NVRAM, &tm); |
| 341 |
} |
| 342 |
break;
|
| 343 |
case 0x1FFF: |
| 344 |
case 0x07FF: |
| 345 |
/* year */
|
| 346 |
tmp = from_bcd(val); |
| 347 |
if (tmp >= 0 && tmp <= 99) { |
| 348 |
get_time(NVRAM, &tm); |
| 349 |
if (NVRAM->model == 8) { |
| 350 |
tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
| 351 |
} else {
|
| 352 |
tm.tm_year = from_bcd(val); |
| 353 |
} |
| 354 |
set_time(NVRAM, &tm); |
| 355 |
} |
| 356 |
break;
|
| 357 |
default:
|
| 358 |
/* Check lock registers state */
|
| 359 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
| 360 |
break;
|
| 361 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
| 362 |
break;
|
| 363 |
do_write:
|
| 364 |
if (addr < NVRAM->size) {
|
| 365 |
NVRAM->buffer[addr] = val & 0xFF;
|
| 366 |
} |
| 367 |
break;
|
| 368 |
} |
| 369 |
} |
| 370 |
|
| 371 |
uint32_t m48t59_read (void *opaque, uint32_t addr)
|
| 372 |
{
|
| 373 |
M48t59State *NVRAM = opaque; |
| 374 |
struct tm tm;
|
| 375 |
uint32_t retval = 0xFF;
|
| 376 |
|
| 377 |
/* check for NVRAM access */
|
| 378 |
if ((NVRAM->model == 2 && addr < 0x078f) || |
| 379 |
(NVRAM->model == 8 && addr < 0x1ff8) || |
| 380 |
(NVRAM->model == 59 && addr < 0x1ff0)) { |
| 381 |
goto do_read;
|
| 382 |
} |
| 383 |
|
| 384 |
/* TOD access */
|
| 385 |
switch (addr) {
|
| 386 |
case 0x1FF0: |
| 387 |
/* flags register */
|
| 388 |
goto do_read;
|
| 389 |
case 0x1FF1: |
| 390 |
/* unused */
|
| 391 |
retval = 0;
|
| 392 |
break;
|
| 393 |
case 0x1FF2: |
| 394 |
/* alarm seconds */
|
| 395 |
goto do_read;
|
| 396 |
case 0x1FF3: |
| 397 |
/* alarm minutes */
|
| 398 |
goto do_read;
|
| 399 |
case 0x1FF4: |
| 400 |
/* alarm hours */
|
| 401 |
goto do_read;
|
| 402 |
case 0x1FF5: |
| 403 |
/* alarm date */
|
| 404 |
goto do_read;
|
| 405 |
case 0x1FF6: |
| 406 |
/* interrupts */
|
| 407 |
goto do_read;
|
| 408 |
case 0x1FF7: |
| 409 |
/* A read resets the watchdog */
|
| 410 |
set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
| 411 |
goto do_read;
|
| 412 |
case 0x1FF8: |
| 413 |
case 0x07F8: |
| 414 |
/* control */
|
| 415 |
goto do_read;
|
| 416 |
case 0x1FF9: |
| 417 |
case 0x07F9: |
| 418 |
/* seconds (BCD) */
|
| 419 |
get_time(NVRAM, &tm); |
| 420 |
retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
|
| 421 |
break;
|
| 422 |
case 0x1FFA: |
| 423 |
case 0x07FA: |
| 424 |
/* minutes (BCD) */
|
| 425 |
get_time(NVRAM, &tm); |
| 426 |
retval = to_bcd(tm.tm_min); |
| 427 |
break;
|
| 428 |
case 0x1FFB: |
| 429 |
case 0x07FB: |
| 430 |
/* hours (BCD) */
|
| 431 |
get_time(NVRAM, &tm); |
| 432 |
retval = to_bcd(tm.tm_hour); |
| 433 |
break;
|
| 434 |
case 0x1FFC: |
| 435 |
case 0x07FC: |
| 436 |
/* day of the week / century */
|
| 437 |
get_time(NVRAM, &tm); |
| 438 |
retval = NVRAM->buffer[addr] | tm.tm_wday; |
| 439 |
break;
|
| 440 |
case 0x1FFD: |
| 441 |
case 0x07FD: |
| 442 |
/* date */
|
| 443 |
get_time(NVRAM, &tm); |
| 444 |
retval = to_bcd(tm.tm_mday); |
| 445 |
break;
|
| 446 |
case 0x1FFE: |
| 447 |
case 0x07FE: |
| 448 |
/* month */
|
| 449 |
get_time(NVRAM, &tm); |
| 450 |
retval = to_bcd(tm.tm_mon + 1);
|
| 451 |
break;
|
| 452 |
case 0x1FFF: |
| 453 |
case 0x07FF: |
| 454 |
/* year */
|
| 455 |
get_time(NVRAM, &tm); |
| 456 |
if (NVRAM->model == 8) { |
| 457 |
retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
| 458 |
} else {
|
| 459 |
retval = to_bcd(tm.tm_year); |
| 460 |
} |
| 461 |
break;
|
| 462 |
default:
|
| 463 |
/* Check lock registers state */
|
| 464 |
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
| 465 |
break;
|
| 466 |
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
| 467 |
break;
|
| 468 |
do_read:
|
| 469 |
if (addr < NVRAM->size) {
|
| 470 |
retval = NVRAM->buffer[addr]; |
| 471 |
} |
| 472 |
break;
|
| 473 |
} |
| 474 |
if (addr > 0x1FF9 && addr < 0x2000) |
| 475 |
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
| 476 |
|
| 477 |
return retval;
|
| 478 |
} |
| 479 |
|
| 480 |
void m48t59_toggle_lock (void *opaque, int lock) |
| 481 |
{
|
| 482 |
M48t59State *NVRAM = opaque; |
| 483 |
|
| 484 |
NVRAM->lock ^= 1 << lock;
|
| 485 |
} |
| 486 |
|
| 487 |
/* IO access to NVRAM */
|
| 488 |
static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val, |
| 489 |
unsigned size)
|
| 490 |
{
|
| 491 |
M48t59State *NVRAM = opaque; |
| 492 |
|
| 493 |
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
|
| 494 |
switch (addr) {
|
| 495 |
case 0: |
| 496 |
NVRAM->addr &= ~0x00FF;
|
| 497 |
NVRAM->addr |= val; |
| 498 |
break;
|
| 499 |
case 1: |
| 500 |
NVRAM->addr &= ~0xFF00;
|
| 501 |
NVRAM->addr |= val << 8;
|
| 502 |
break;
|
| 503 |
case 3: |
| 504 |
m48t59_write(NVRAM, NVRAM->addr, val); |
| 505 |
NVRAM->addr = 0x0000;
|
| 506 |
break;
|
| 507 |
default:
|
| 508 |
break;
|
| 509 |
} |
| 510 |
} |
| 511 |
|
| 512 |
static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size) |
| 513 |
{
|
| 514 |
M48t59State *NVRAM = opaque; |
| 515 |
uint32_t retval; |
| 516 |
|
| 517 |
switch (addr) {
|
| 518 |
case 3: |
| 519 |
retval = m48t59_read(NVRAM, NVRAM->addr); |
| 520 |
break;
|
| 521 |
default:
|
| 522 |
retval = -1;
|
| 523 |
break;
|
| 524 |
} |
| 525 |
NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
|
| 526 |
|
| 527 |
return retval;
|
| 528 |
} |
| 529 |
|
| 530 |
static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value) |
| 531 |
{
|
| 532 |
M48t59State *NVRAM = opaque; |
| 533 |
|
| 534 |
m48t59_write(NVRAM, addr, value & 0xff);
|
| 535 |
} |
| 536 |
|
| 537 |
static void nvram_writew (void *opaque, hwaddr addr, uint32_t value) |
| 538 |
{
|
| 539 |
M48t59State *NVRAM = opaque; |
| 540 |
|
| 541 |
m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
| 542 |
m48t59_write(NVRAM, addr + 1, value & 0xff); |
| 543 |
} |
| 544 |
|
| 545 |
static void nvram_writel (void *opaque, hwaddr addr, uint32_t value) |
| 546 |
{
|
| 547 |
M48t59State *NVRAM = opaque; |
| 548 |
|
| 549 |
m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
| 550 |
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
| 551 |
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
| 552 |
m48t59_write(NVRAM, addr + 3, value & 0xff); |
| 553 |
} |
| 554 |
|
| 555 |
static uint32_t nvram_readb (void *opaque, hwaddr addr) |
| 556 |
{
|
| 557 |
M48t59State *NVRAM = opaque; |
| 558 |
uint32_t retval; |
| 559 |
|
| 560 |
retval = m48t59_read(NVRAM, addr); |
| 561 |
return retval;
|
| 562 |
} |
| 563 |
|
| 564 |
static uint32_t nvram_readw (void *opaque, hwaddr addr) |
| 565 |
{
|
| 566 |
M48t59State *NVRAM = opaque; |
| 567 |
uint32_t retval; |
| 568 |
|
| 569 |
retval = m48t59_read(NVRAM, addr) << 8;
|
| 570 |
retval |= m48t59_read(NVRAM, addr + 1);
|
| 571 |
return retval;
|
| 572 |
} |
| 573 |
|
| 574 |
static uint32_t nvram_readl (void *opaque, hwaddr addr) |
| 575 |
{
|
| 576 |
M48t59State *NVRAM = opaque; |
| 577 |
uint32_t retval; |
| 578 |
|
| 579 |
retval = m48t59_read(NVRAM, addr) << 24;
|
| 580 |
retval |= m48t59_read(NVRAM, addr + 1) << 16; |
| 581 |
retval |= m48t59_read(NVRAM, addr + 2) << 8; |
| 582 |
retval |= m48t59_read(NVRAM, addr + 3);
|
| 583 |
return retval;
|
| 584 |
} |
| 585 |
|
| 586 |
static const MemoryRegionOps nvram_ops = { |
| 587 |
.old_mmio = {
|
| 588 |
.read = { nvram_readb, nvram_readw, nvram_readl, },
|
| 589 |
.write = { nvram_writeb, nvram_writew, nvram_writel, },
|
| 590 |
}, |
| 591 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 592 |
}; |
| 593 |
|
| 594 |
static const VMStateDescription vmstate_m48t59 = { |
| 595 |
.name = "m48t59",
|
| 596 |
.version_id = 1,
|
| 597 |
.minimum_version_id = 1,
|
| 598 |
.minimum_version_id_old = 1,
|
| 599 |
.fields = (VMStateField[]) {
|
| 600 |
VMSTATE_UINT8(lock, M48t59State), |
| 601 |
VMSTATE_UINT16(addr, M48t59State), |
| 602 |
VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), |
| 603 |
VMSTATE_END_OF_LIST() |
| 604 |
} |
| 605 |
}; |
| 606 |
|
| 607 |
static void m48t59_reset_common(M48t59State *NVRAM) |
| 608 |
{
|
| 609 |
NVRAM->addr = 0;
|
| 610 |
NVRAM->lock = 0;
|
| 611 |
if (NVRAM->alrm_timer != NULL) |
| 612 |
timer_del(NVRAM->alrm_timer); |
| 613 |
|
| 614 |
if (NVRAM->wd_timer != NULL) |
| 615 |
timer_del(NVRAM->wd_timer); |
| 616 |
} |
| 617 |
|
| 618 |
static void m48t59_reset_isa(DeviceState *d) |
| 619 |
{
|
| 620 |
M48t59ISAState *isa = ISA_M48T59(d); |
| 621 |
M48t59State *NVRAM = &isa->state; |
| 622 |
|
| 623 |
m48t59_reset_common(NVRAM); |
| 624 |
} |
| 625 |
|
| 626 |
static void m48t59_reset_sysbus(DeviceState *d) |
| 627 |
{
|
| 628 |
M48t59SysBusState *sys = SYSBUS_M48T59(d); |
| 629 |
M48t59State *NVRAM = &sys->state; |
| 630 |
|
| 631 |
m48t59_reset_common(NVRAM); |
| 632 |
} |
| 633 |
|
| 634 |
static const MemoryRegionOps m48t59_io_ops = { |
| 635 |
.read = NVRAM_readb, |
| 636 |
.write = NVRAM_writeb, |
| 637 |
.impl = {
|
| 638 |
.min_access_size = 1,
|
| 639 |
.max_access_size = 1,
|
| 640 |
}, |
| 641 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 642 |
}; |
| 643 |
|
| 644 |
/* Initialisation routine */
|
| 645 |
M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, |
| 646 |
uint32_t io_base, uint16_t size, int model)
|
| 647 |
{
|
| 648 |
DeviceState *dev; |
| 649 |
SysBusDevice *s; |
| 650 |
M48t59SysBusState *d; |
| 651 |
M48t59State *state; |
| 652 |
|
| 653 |
dev = qdev_create(NULL, TYPE_SYSBUS_M48T59);
|
| 654 |
qdev_prop_set_uint32(dev, "model", model);
|
| 655 |
qdev_prop_set_uint32(dev, "size", size);
|
| 656 |
qdev_prop_set_uint32(dev, "io_base", io_base);
|
| 657 |
qdev_init_nofail(dev); |
| 658 |
s = SYS_BUS_DEVICE(dev); |
| 659 |
d = SYSBUS_M48T59(dev); |
| 660 |
state = &d->state; |
| 661 |
sysbus_connect_irq(s, 0, IRQ);
|
| 662 |
memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, state, |
| 663 |
"m48t59", 4); |
| 664 |
if (io_base != 0) { |
| 665 |
memory_region_add_subregion(get_system_io(), io_base, &d->io); |
| 666 |
} |
| 667 |
if (mem_base != 0) { |
| 668 |
sysbus_mmio_map(s, 0, mem_base);
|
| 669 |
} |
| 670 |
|
| 671 |
return state;
|
| 672 |
} |
| 673 |
|
| 674 |
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, |
| 675 |
int model)
|
| 676 |
{
|
| 677 |
M48t59ISAState *d; |
| 678 |
ISADevice *isadev; |
| 679 |
DeviceState *dev; |
| 680 |
M48t59State *s; |
| 681 |
|
| 682 |
isadev = isa_create(bus, TYPE_ISA_M48T59); |
| 683 |
dev = DEVICE(isadev); |
| 684 |
qdev_prop_set_uint32(dev, "model", model);
|
| 685 |
qdev_prop_set_uint32(dev, "size", size);
|
| 686 |
qdev_prop_set_uint32(dev, "io_base", io_base);
|
| 687 |
qdev_init_nofail(dev); |
| 688 |
d = ISA_M48T59(isadev); |
| 689 |
s = &d->state; |
| 690 |
|
| 691 |
memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, s, "m48t59", 4); |
| 692 |
if (io_base != 0) { |
| 693 |
isa_register_ioport(isadev, &d->io, io_base); |
| 694 |
} |
| 695 |
|
| 696 |
return s;
|
| 697 |
} |
| 698 |
|
| 699 |
static void m48t59_realize_common(M48t59State *s, Error **errp) |
| 700 |
{
|
| 701 |
s->buffer = g_malloc0(s->size); |
| 702 |
if (s->model == 59) { |
| 703 |
s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s); |
| 704 |
s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s); |
| 705 |
} |
| 706 |
qemu_get_timedate(&s->alarm, 0);
|
| 707 |
|
| 708 |
vmstate_register(NULL, -1, &vmstate_m48t59, s); |
| 709 |
} |
| 710 |
|
| 711 |
static void m48t59_isa_realize(DeviceState *dev, Error **errp) |
| 712 |
{
|
| 713 |
ISADevice *isadev = ISA_DEVICE(dev); |
| 714 |
M48t59ISAState *d = ISA_M48T59(dev); |
| 715 |
M48t59State *s = &d->state; |
| 716 |
|
| 717 |
isa_init_irq(isadev, &s->IRQ, 8);
|
| 718 |
m48t59_realize_common(s, errp); |
| 719 |
} |
| 720 |
|
| 721 |
static int m48t59_init1(SysBusDevice *dev) |
| 722 |
{
|
| 723 |
M48t59SysBusState *d = SYSBUS_M48T59(dev); |
| 724 |
M48t59State *s = &d->state; |
| 725 |
Error *err = NULL;
|
| 726 |
|
| 727 |
sysbus_init_irq(dev, &s->IRQ); |
| 728 |
|
| 729 |
memory_region_init_io(&s->iomem, OBJECT(d), &nvram_ops, s, |
| 730 |
"m48t59.nvram", s->size);
|
| 731 |
sysbus_init_mmio(dev, &s->iomem); |
| 732 |
m48t59_realize_common(s, &err); |
| 733 |
if (err != NULL) { |
| 734 |
error_free(err); |
| 735 |
return -1; |
| 736 |
} |
| 737 |
|
| 738 |
return 0; |
| 739 |
} |
| 740 |
|
| 741 |
static Property m48t59_isa_properties[] = {
|
| 742 |
DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), |
| 743 |
DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), |
| 744 |
DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), |
| 745 |
DEFINE_PROP_END_OF_LIST(), |
| 746 |
}; |
| 747 |
|
| 748 |
static void m48t59_isa_class_init(ObjectClass *klass, void *data) |
| 749 |
{
|
| 750 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 751 |
|
| 752 |
dc->realize = m48t59_isa_realize; |
| 753 |
dc->cannot_instantiate_with_device_add_yet = true; /* FIXME explain why */ |
| 754 |
dc->reset = m48t59_reset_isa; |
| 755 |
dc->props = m48t59_isa_properties; |
| 756 |
} |
| 757 |
|
| 758 |
static const TypeInfo m48t59_isa_info = { |
| 759 |
.name = TYPE_ISA_M48T59, |
| 760 |
.parent = TYPE_ISA_DEVICE, |
| 761 |
.instance_size = sizeof(M48t59ISAState),
|
| 762 |
.class_init = m48t59_isa_class_init, |
| 763 |
}; |
| 764 |
|
| 765 |
static Property m48t59_properties[] = {
|
| 766 |
DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), |
| 767 |
DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), |
| 768 |
DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), |
| 769 |
DEFINE_PROP_END_OF_LIST(), |
| 770 |
}; |
| 771 |
|
| 772 |
static void m48t59_class_init(ObjectClass *klass, void *data) |
| 773 |
{
|
| 774 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 775 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 776 |
|
| 777 |
k->init = m48t59_init1; |
| 778 |
dc->reset = m48t59_reset_sysbus; |
| 779 |
dc->props = m48t59_properties; |
| 780 |
} |
| 781 |
|
| 782 |
static const TypeInfo m48t59_info = { |
| 783 |
.name = TYPE_SYSBUS_M48T59, |
| 784 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 785 |
.instance_size = sizeof(M48t59SysBusState),
|
| 786 |
.class_init = m48t59_class_init, |
| 787 |
}; |
| 788 |
|
| 789 |
static void m48t59_register_types(void) |
| 790 |
{
|
| 791 |
type_register_static(&m48t59_info); |
| 792 |
type_register_static(&m48t59_isa_info); |
| 793 |
} |
| 794 |
|
| 795 |
type_init(m48t59_register_types) |