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/*
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 *  S/390 FPU helper routines
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 *
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 *  Copyright (c) 2009 Ulrich Hecht
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 *  Copyright (c) 2009 Alexander Graf
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "cpu.h"
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#include "helper.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "exec/softmmu_exec.h"
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#endif
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/* #define DEBUG_HELPER */
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#ifdef DEBUG_HELPER
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#define HELPER_LOG(x...) qemu_log(x)
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#else
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#define HELPER_LOG(x...)
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#endif
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#define RET128(F) (env->retxl = F.low, F.high)
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#define convert_bit(mask, from, to) \
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    (to < from                      \
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     ? (mask / (from / to)) & to    \
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     : (mask & from) * (to / from))
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static void ieee_exception(CPUS390XState *env, uint32_t dxc, uintptr_t retaddr)
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{
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    /* Install the DXC code.  */
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    env->fpc = (env->fpc & ~0xff00) | (dxc << 8);
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    /* Trap.  */
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    runtime_exception(env, PGM_DATA, retaddr);
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}
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/* Should be called after any operation that may raise IEEE exceptions.  */
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static void handle_exceptions(CPUS390XState *env, uintptr_t retaddr)
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{
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    unsigned s390_exc, qemu_exc;
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    /* Get the exceptions raised by the current operation.  Reset the
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       fpu_status contents so that the next operation has a clean slate.  */
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    qemu_exc = env->fpu_status.float_exception_flags;
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    if (qemu_exc == 0) {
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        return;
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    }
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    env->fpu_status.float_exception_flags = 0;
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    /* Convert softfloat exception bits to s390 exception bits.  */
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    s390_exc = 0;
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    s390_exc |= convert_bit(qemu_exc, float_flag_invalid, 0x80);
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    s390_exc |= convert_bit(qemu_exc, float_flag_divbyzero, 0x40);
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    s390_exc |= convert_bit(qemu_exc, float_flag_overflow, 0x20);
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    s390_exc |= convert_bit(qemu_exc, float_flag_underflow, 0x10);
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    s390_exc |= convert_bit(qemu_exc, float_flag_inexact, 0x08);
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    /* Install the exceptions that we raised.  */
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    env->fpc |= s390_exc << 16;
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    /* Send signals for enabled exceptions.  */
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    s390_exc &= env->fpc >> 24;
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    if (s390_exc) {
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        ieee_exception(env, s390_exc, retaddr);
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    }
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}
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static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
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{
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    switch (float_compare) {
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    case float_relation_equal:
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        return 0;
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    case float_relation_less:
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        return 1;
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    case float_relation_greater:
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        return 2;
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    case float_relation_unordered:
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        return 3;
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    default:
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        cpu_abort(env, "unknown return value for float compare\n");
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    }
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}
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/* condition codes for unary FP ops */
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uint32_t set_cc_nz_f32(float32 v)
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{
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    if (float32_is_any_nan(v)) {
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        return 3;
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    } else if (float32_is_zero(v)) {
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        return 0;
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    } else if (float32_is_neg(v)) {
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        return 1;
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    } else {
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        return 2;
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    }
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}
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uint32_t set_cc_nz_f64(float64 v)
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{
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    if (float64_is_any_nan(v)) {
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        return 3;
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    } else if (float64_is_zero(v)) {
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        return 0;
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    } else if (float64_is_neg(v)) {
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        return 1;
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    } else {
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        return 2;
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    }
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}
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uint32_t set_cc_nz_f128(float128 v)
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{
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    if (float128_is_any_nan(v)) {
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        return 3;
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    } else if (float128_is_zero(v)) {
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        return 0;
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    } else if (float128_is_neg(v)) {
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        return 1;
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    } else {
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        return 2;
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    }
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}
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/* convert 32-bit int to 64-bit float */
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void HELPER(cdfbr)(CPUS390XState *env, uint32_t f1, int32_t v2)
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{
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    HELPER_LOG("%s: converting %d to f%d\n", __func__, v2, f1);
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    env->fregs[f1].d = int32_to_float64(v2, &env->fpu_status);
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}
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/* convert 32-bit int to 128-bit float */
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void HELPER(cxfbr)(CPUS390XState *env, uint32_t f1, int32_t v2)
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{
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    CPU_QuadU v1;
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    v1.q = int32_to_float128(v2, &env->fpu_status);
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    env->fregs[f1].ll = v1.ll.upper;
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    env->fregs[f1 + 2].ll = v1.ll.lower;
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}
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/* convert 64-bit int to 32-bit float */
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void HELPER(cegbr)(CPUS390XState *env, uint32_t f1, int64_t v2)
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{
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    HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
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    env->fregs[f1].l.upper = int64_to_float32(v2, &env->fpu_status);
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}
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/* convert 64-bit int to 64-bit float */
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void HELPER(cdgbr)(CPUS390XState *env, uint32_t f1, int64_t v2)
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{
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    HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
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    env->fregs[f1].d = int64_to_float64(v2, &env->fpu_status);
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}
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/* convert 64-bit int to 128-bit float */
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void HELPER(cxgbr)(CPUS390XState *env, uint32_t f1, int64_t v2)
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{
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    CPU_QuadU x1;
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    x1.q = int64_to_float128(v2, &env->fpu_status);
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    HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __func__, v2,
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               x1.ll.upper, x1.ll.lower);
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    env->fregs[f1].ll = x1.ll.upper;
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    env->fregs[f1 + 2].ll = x1.ll.lower;
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}
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/* convert 32-bit int to 32-bit float */
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void HELPER(cefbr)(CPUS390XState *env, uint32_t f1, int32_t v2)
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{
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    env->fregs[f1].l.upper = int32_to_float32(v2, &env->fpu_status);
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    HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __func__, v2,
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               env->fregs[f1].l.upper, f1);
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}
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/* 32-bit FP addition */
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uint64_t HELPER(aeb)(CPUS390XState *env, uint64_t f1, uint64_t f2)
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{
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    float32 ret = float32_add(f1, f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return ret;
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}
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/* 64-bit FP addition */
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uint64_t HELPER(adb)(CPUS390XState *env, uint64_t f1, uint64_t f2)
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{
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    float64 ret = float64_add(f1, f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return ret;
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}
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/* 128-bit FP addition */
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uint64_t HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al,
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                     uint64_t bh, uint64_t bl)
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{
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    float128 ret = float128_add(make_float128(ah, al),
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                                make_float128(bh, bl),
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                                &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return RET128(ret);
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}
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/* 32-bit FP subtraction */
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uint64_t HELPER(seb)(CPUS390XState *env, uint64_t f1, uint64_t f2)
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{
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    float32 ret = float32_sub(f1, f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return ret;
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}
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/* 64-bit FP subtraction */
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uint64_t HELPER(sdb)(CPUS390XState *env, uint64_t f1, uint64_t f2)
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{
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    float64 ret = float64_sub(f1, f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return ret;
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}
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/* 128-bit FP subtraction */
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uint64_t HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al,
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                     uint64_t bh, uint64_t bl)
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{
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    float128 ret = float128_sub(make_float128(ah, al),
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                                make_float128(bh, bl),
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                                &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return RET128(ret);
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}
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/* 32-bit FP division */
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uint64_t HELPER(deb)(CPUS390XState *env, uint64_t f1, uint64_t f2)
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{
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    float32 ret = float32_div(f1, f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return ret;
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}
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/* 64-bit FP division */
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uint64_t HELPER(ddb)(CPUS390XState *env, uint64_t f1, uint64_t f2)
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{
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    float64 ret = float64_div(f1, f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return ret;
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}
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/* 128-bit FP division */
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uint64_t HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al,
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                     uint64_t bh, uint64_t bl)
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{
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    float128 ret = float128_div(make_float128(ah, al),
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                                make_float128(bh, bl),
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                                &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return RET128(ret);
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}
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/* 64-bit FP multiplication RR */
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void HELPER(mdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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{
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    env->fregs[f1].d = float64_mul(env->fregs[f1].d, env->fregs[f2].d,
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                                   &env->fpu_status);
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}
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/* 128-bit FP multiplication RR */
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void HELPER(mxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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{
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    CPU_QuadU v1;
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    CPU_QuadU v2;
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    CPU_QuadU res;
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    v1.ll.upper = env->fregs[f1].ll;
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    v1.ll.lower = env->fregs[f1 + 2].ll;
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    v2.ll.upper = env->fregs[f2].ll;
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    v2.ll.lower = env->fregs[f2 + 2].ll;
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    res.q = float128_mul(v1.q, v2.q, &env->fpu_status);
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    env->fregs[f1].ll = res.ll.upper;
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    env->fregs[f1 + 2].ll = res.ll.lower;
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}
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/* convert 32-bit float to 64-bit float */
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uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2)
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{
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    float64 ret = float32_to_float64(f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return ret;
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}
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/* convert 128-bit float to 64-bit float */
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uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al)
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{
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    float64 ret = float128_to_float64(make_float128(ah, al), &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return ret;
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}
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/* convert 64-bit float to 128-bit float */
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uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2)
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{
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    float128 ret = float64_to_float128(f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return RET128(ret);
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}
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/* convert 32-bit float to 128-bit float */
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uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2)
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{
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    float128 ret = float32_to_float128(f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return RET128(ret);
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}
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/* convert 64-bit float to 32-bit float */
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uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2)
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{
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    float32 ret = float64_to_float32(f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return ret;
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}
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/* convert 128-bit float to 32-bit float */
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uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, uint64_t al)
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{
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    float32 ret = float128_to_float32(make_float128(ah, al), &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return ret;
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}
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/* absolute value of 32-bit float */
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uint32_t HELPER(lpebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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{
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    float32 v1;
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    float32 v2 = env->fregs[f2].d;
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    v1 = float32_abs(v2);
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    env->fregs[f1].d = v1;
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    return set_cc_nz_f32(v1);
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}
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/* absolute value of 64-bit float */
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uint32_t HELPER(lpdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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{
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    float64 v1;
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    float64 v2 = env->fregs[f2].d;
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    v1 = float64_abs(v2);
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    env->fregs[f1].d = v1;
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    return set_cc_nz_f64(v1);
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}
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/* absolute value of 128-bit float */
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uint32_t HELPER(lpxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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{
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    CPU_QuadU v1;
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    CPU_QuadU v2;
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    v2.ll.upper = env->fregs[f2].ll;
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    v2.ll.lower = env->fregs[f2 + 2].ll;
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    v1.q = float128_abs(v2.q);
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    env->fregs[f1].ll = v1.ll.upper;
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    env->fregs[f1 + 2].ll = v1.ll.lower;
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    return set_cc_nz_f128(v1.q);
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}
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/* load complement of 32-bit float */
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uint32_t HELPER(lcebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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{
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    env->fregs[f1].l.upper = float32_chs(env->fregs[f2].l.upper);
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    return set_cc_nz_f32(env->fregs[f1].l.upper);
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}
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/* load complement of 64-bit float */
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uint32_t HELPER(lcdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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{
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    env->fregs[f1].d = float64_chs(env->fregs[f2].d);
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    return set_cc_nz_f64(env->fregs[f1].d);
390 e72ca652 Blue Swirl
}
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/* load complement of 128-bit float */
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uint32_t HELPER(lcxbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
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{
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    CPU_QuadU x1, x2;
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    x2.ll.upper = env->fregs[f2].ll;
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    x2.ll.lower = env->fregs[f2 + 2].ll;
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    x1.q = float128_chs(x2.q);
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    env->fregs[f1].ll = x1.ll.upper;
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    env->fregs[f1 + 2].ll = x1.ll.lower;
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    return set_cc_nz_f128(x1.q);
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}
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/* 32-bit FP multiplication RM */
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void HELPER(meeb)(CPUS390XState *env, uint32_t f1, uint32_t val)
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{
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    float32 v1 = env->fregs[f1].l.upper;
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    CPU_FloatU v2;
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    v2.l = val;
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    HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __func__,
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               v1, f1, v2.f);
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    env->fregs[f1].l.upper = float32_mul(v1, v2.f, &env->fpu_status);
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}
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417 587626f8 Richard Henderson
/* 32-bit FP compare */
418 587626f8 Richard Henderson
uint32_t HELPER(ceb)(CPUS390XState *env, uint64_t f1, uint64_t f2)
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{
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    int cmp = float32_compare_quiet(f1, f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return float_comp_to_cc(env, cmp);
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}
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425 587626f8 Richard Henderson
/* 64-bit FP compare */
426 587626f8 Richard Henderson
uint32_t HELPER(cdb)(CPUS390XState *env, uint64_t f1, uint64_t f2)
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{
428 587626f8 Richard Henderson
    int cmp = float64_compare_quiet(f1, f2, &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return float_comp_to_cc(env, cmp);
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}
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433 587626f8 Richard Henderson
/* 128-bit FP compare */
434 587626f8 Richard Henderson
uint32_t HELPER(cxb)(CPUS390XState *env, uint64_t ah, uint64_t al,
435 587626f8 Richard Henderson
                     uint64_t bh, uint64_t bl)
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{
437 587626f8 Richard Henderson
    int cmp = float128_compare_quiet(make_float128(ah, al),
438 587626f8 Richard Henderson
                                     make_float128(bh, bl),
439 587626f8 Richard Henderson
                                     &env->fpu_status);
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    handle_exceptions(env, GETPC());
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    return float_comp_to_cc(env, cmp);
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}
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/* 64-bit FP multiplication RM */
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void HELPER(mdb)(CPUS390XState *env, uint32_t f1, uint64_t a2)
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{
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    float64 v1 = env->fregs[f1].d;
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    CPU_DoubleU v2;
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    v2.ll = cpu_ldq_data(env, a2);
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    HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __func__,
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               v1, f1, v2.d);
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    env->fregs[f1].d = float64_mul(v1, v2.d, &env->fpu_status);
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}
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static void set_round_mode(CPUS390XState *env, int m3)
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{
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    switch (m3) {
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    case 0:
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        /* current mode */
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        break;
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    case 1:
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        /* biased round no nearest */
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    case 4:
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        /* round to nearest */
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        set_float_rounding_mode(float_round_nearest_even, &env->fpu_status);
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        break;
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    case 5:
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        /* round to zero */
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        set_float_rounding_mode(float_round_to_zero, &env->fpu_status);
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        break;
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    case 6:
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        /* round to +inf */
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        set_float_rounding_mode(float_round_up, &env->fpu_status);
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        break;
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    case 7:
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        /* round to -inf */
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        set_float_rounding_mode(float_round_down, &env->fpu_status);
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        break;
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    }
481 e72ca652 Blue Swirl
}
482 e72ca652 Blue Swirl
483 e72ca652 Blue Swirl
/* convert 32-bit float to 64-bit int */
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uint32_t HELPER(cgebr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
485 449c0d70 Blue Swirl
                       uint32_t m3)
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{
487 e72ca652 Blue Swirl
    float32 v2 = env->fregs[f2].l.upper;
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    set_round_mode(env, m3);
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    env->regs[r1] = float32_to_int64(v2, &env->fpu_status);
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    return set_cc_nz_f32(v2);
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}
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494 e72ca652 Blue Swirl
/* convert 64-bit float to 64-bit int */
495 449c0d70 Blue Swirl
uint32_t HELPER(cgdbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
496 449c0d70 Blue Swirl
                       uint32_t m3)
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{
498 e72ca652 Blue Swirl
    float64 v2 = env->fregs[f2].d;
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    set_round_mode(env, m3);
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    env->regs[r1] = float64_to_int64(v2, &env->fpu_status);
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    return set_cc_nz_f64(v2);
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}
504 e72ca652 Blue Swirl
505 e72ca652 Blue Swirl
/* convert 128-bit float to 64-bit int */
506 449c0d70 Blue Swirl
uint32_t HELPER(cgxbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
507 449c0d70 Blue Swirl
                       uint32_t m3)
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{
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    CPU_QuadU v2;
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    v2.ll.upper = env->fregs[f2].ll;
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    v2.ll.lower = env->fregs[f2 + 2].ll;
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    set_round_mode(env, m3);
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    env->regs[r1] = float128_to_int64(v2.q, &env->fpu_status);
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    if (float128_is_any_nan(v2.q)) {
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        return 3;
517 e72ca652 Blue Swirl
    } else if (float128_is_zero(v2.q)) {
518 e72ca652 Blue Swirl
        return 0;
519 e72ca652 Blue Swirl
    } else if (float128_is_neg(v2.q)) {
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        return 1;
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    } else {
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        return 2;
523 e72ca652 Blue Swirl
    }
524 e72ca652 Blue Swirl
}
525 e72ca652 Blue Swirl
526 e72ca652 Blue Swirl
/* convert 32-bit float to 32-bit int */
527 449c0d70 Blue Swirl
uint32_t HELPER(cfebr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
528 449c0d70 Blue Swirl
                       uint32_t m3)
529 e72ca652 Blue Swirl
{
530 e72ca652 Blue Swirl
    float32 v2 = env->fregs[f2].l.upper;
531 e72ca652 Blue Swirl
532 449c0d70 Blue Swirl
    set_round_mode(env, m3);
533 e72ca652 Blue Swirl
    env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
534 e72ca652 Blue Swirl
        float32_to_int32(v2, &env->fpu_status);
535 e72ca652 Blue Swirl
    return set_cc_nz_f32(v2);
536 e72ca652 Blue Swirl
}
537 e72ca652 Blue Swirl
538 e72ca652 Blue Swirl
/* convert 64-bit float to 32-bit int */
539 449c0d70 Blue Swirl
uint32_t HELPER(cfdbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
540 449c0d70 Blue Swirl
                       uint32_t m3)
541 e72ca652 Blue Swirl
{
542 e72ca652 Blue Swirl
    float64 v2 = env->fregs[f2].d;
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544 449c0d70 Blue Swirl
    set_round_mode(env, m3);
545 e72ca652 Blue Swirl
    env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
546 e72ca652 Blue Swirl
        float64_to_int32(v2, &env->fpu_status);
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    return set_cc_nz_f64(v2);
548 e72ca652 Blue Swirl
}
549 e72ca652 Blue Swirl
550 e72ca652 Blue Swirl
/* convert 128-bit float to 32-bit int */
551 449c0d70 Blue Swirl
uint32_t HELPER(cfxbr)(CPUS390XState *env, uint32_t r1, uint32_t f2,
552 449c0d70 Blue Swirl
                       uint32_t m3)
553 e72ca652 Blue Swirl
{
554 e72ca652 Blue Swirl
    CPU_QuadU v2;
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556 e72ca652 Blue Swirl
    v2.ll.upper = env->fregs[f2].ll;
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    v2.ll.lower = env->fregs[f2 + 2].ll;
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    env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
559 e72ca652 Blue Swirl
        float128_to_int32(v2.q, &env->fpu_status);
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    return set_cc_nz_f128(v2.q);
561 e72ca652 Blue Swirl
}
562 e72ca652 Blue Swirl
563 e72ca652 Blue Swirl
/* load 32-bit FP zero */
564 449c0d70 Blue Swirl
void HELPER(lzer)(CPUS390XState *env, uint32_t f1)
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{
566 e72ca652 Blue Swirl
    env->fregs[f1].l.upper = float32_zero;
567 e72ca652 Blue Swirl
}
568 e72ca652 Blue Swirl
569 e72ca652 Blue Swirl
/* load 64-bit FP zero */
570 449c0d70 Blue Swirl
void HELPER(lzdr)(CPUS390XState *env, uint32_t f1)
571 e72ca652 Blue Swirl
{
572 e72ca652 Blue Swirl
    env->fregs[f1].d = float64_zero;
573 e72ca652 Blue Swirl
}
574 e72ca652 Blue Swirl
575 e72ca652 Blue Swirl
/* load 128-bit FP zero */
576 449c0d70 Blue Swirl
void HELPER(lzxr)(CPUS390XState *env, uint32_t f1)
577 e72ca652 Blue Swirl
{
578 e72ca652 Blue Swirl
    CPU_QuadU x;
579 e72ca652 Blue Swirl
580 e72ca652 Blue Swirl
    x.q = float64_to_float128(float64_zero, &env->fpu_status);
581 e72ca652 Blue Swirl
    env->fregs[f1].ll = x.ll.upper;
582 e72ca652 Blue Swirl
    env->fregs[f1 + 1].ll = x.ll.lower;
583 e72ca652 Blue Swirl
}
584 e72ca652 Blue Swirl
585 e72ca652 Blue Swirl
/* 32-bit FP multiplication RR */
586 449c0d70 Blue Swirl
void HELPER(meebr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
587 e72ca652 Blue Swirl
{
588 e72ca652 Blue Swirl
    env->fregs[f1].l.upper = float32_mul(env->fregs[f1].l.upper,
589 e72ca652 Blue Swirl
                                         env->fregs[f2].l.upper,
590 e72ca652 Blue Swirl
                                         &env->fpu_status);
591 e72ca652 Blue Swirl
}
592 e72ca652 Blue Swirl
593 e72ca652 Blue Swirl
/* 64-bit FP multiply and add RM */
594 449c0d70 Blue Swirl
void HELPER(madb)(CPUS390XState *env, uint32_t f1, uint64_t a2, uint32_t f3)
595 e72ca652 Blue Swirl
{
596 e72ca652 Blue Swirl
    CPU_DoubleU v2;
597 e72ca652 Blue Swirl
598 e72ca652 Blue Swirl
    HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __func__, f1, a2, f3);
599 449c0d70 Blue Swirl
    v2.ll = cpu_ldq_data(env, a2);
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    env->fregs[f1].d = float64_add(env->fregs[f1].d,
601 e72ca652 Blue Swirl
                                   float64_mul(v2.d, env->fregs[f3].d,
602 e72ca652 Blue Swirl
                                               &env->fpu_status),
603 e72ca652 Blue Swirl
                                   &env->fpu_status);
604 e72ca652 Blue Swirl
}
605 e72ca652 Blue Swirl
606 e72ca652 Blue Swirl
/* 64-bit FP multiply and add RR */
607 449c0d70 Blue Swirl
void HELPER(madbr)(CPUS390XState *env, uint32_t f1, uint32_t f3, uint32_t f2)
608 e72ca652 Blue Swirl
{
609 e72ca652 Blue Swirl
    HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
610 e72ca652 Blue Swirl
    env->fregs[f1].d = float64_add(float64_mul(env->fregs[f2].d,
611 e72ca652 Blue Swirl
                                               env->fregs[f3].d,
612 e72ca652 Blue Swirl
                                               &env->fpu_status),
613 e72ca652 Blue Swirl
                                   env->fregs[f1].d, &env->fpu_status);
614 e72ca652 Blue Swirl
}
615 e72ca652 Blue Swirl
616 e72ca652 Blue Swirl
/* 64-bit FP multiply and subtract RR */
617 449c0d70 Blue Swirl
void HELPER(msdbr)(CPUS390XState *env, uint32_t f1, uint32_t f3, uint32_t f2)
618 e72ca652 Blue Swirl
{
619 e72ca652 Blue Swirl
    HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
620 e72ca652 Blue Swirl
    env->fregs[f1].d = float64_sub(float64_mul(env->fregs[f2].d,
621 e72ca652 Blue Swirl
                                               env->fregs[f3].d,
622 e72ca652 Blue Swirl
                                               &env->fpu_status),
623 e72ca652 Blue Swirl
                                   env->fregs[f1].d, &env->fpu_status);
624 e72ca652 Blue Swirl
}
625 e72ca652 Blue Swirl
626 e72ca652 Blue Swirl
/* 32-bit FP multiply and add RR */
627 449c0d70 Blue Swirl
void HELPER(maebr)(CPUS390XState *env, uint32_t f1, uint32_t f3, uint32_t f2)
628 e72ca652 Blue Swirl
{
629 e72ca652 Blue Swirl
    env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
630 e72ca652 Blue Swirl
                                         float32_mul(env->fregs[f2].l.upper,
631 e72ca652 Blue Swirl
                                                     env->fregs[f3].l.upper,
632 e72ca652 Blue Swirl
                                                     &env->fpu_status),
633 e72ca652 Blue Swirl
                                         &env->fpu_status);
634 e72ca652 Blue Swirl
}
635 e72ca652 Blue Swirl
636 e72ca652 Blue Swirl
/* test data class 32-bit */
637 449c0d70 Blue Swirl
uint32_t HELPER(tceb)(CPUS390XState *env, uint32_t f1, uint64_t m2)
638 e72ca652 Blue Swirl
{
639 e72ca652 Blue Swirl
    float32 v1 = env->fregs[f1].l.upper;
640 e72ca652 Blue Swirl
    int neg = float32_is_neg(v1);
641 e72ca652 Blue Swirl
    uint32_t cc = 0;
642 e72ca652 Blue Swirl
643 e72ca652 Blue Swirl
    HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, (long)v1, m2, neg);
644 e72ca652 Blue Swirl
    if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
645 e72ca652 Blue Swirl
        (float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
646 e72ca652 Blue Swirl
        (float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
647 e72ca652 Blue Swirl
        (float32_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
648 e72ca652 Blue Swirl
        cc = 1;
649 e72ca652 Blue Swirl
    } else if (m2 & (1 << (9-neg))) {
650 e72ca652 Blue Swirl
        /* assume normalized number */
651 e72ca652 Blue Swirl
        cc = 1;
652 e72ca652 Blue Swirl
    }
653 e72ca652 Blue Swirl
654 e72ca652 Blue Swirl
    /* FIXME: denormalized? */
655 e72ca652 Blue Swirl
    return cc;
656 e72ca652 Blue Swirl
}
657 e72ca652 Blue Swirl
658 e72ca652 Blue Swirl
/* test data class 64-bit */
659 449c0d70 Blue Swirl
uint32_t HELPER(tcdb)(CPUS390XState *env, uint32_t f1, uint64_t m2)
660 e72ca652 Blue Swirl
{
661 e72ca652 Blue Swirl
    float64 v1 = env->fregs[f1].d;
662 e72ca652 Blue Swirl
    int neg = float64_is_neg(v1);
663 e72ca652 Blue Swirl
    uint32_t cc = 0;
664 e72ca652 Blue Swirl
665 e72ca652 Blue Swirl
    HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, v1, m2, neg);
666 e72ca652 Blue Swirl
    if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
667 e72ca652 Blue Swirl
        (float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
668 e72ca652 Blue Swirl
        (float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
669 e72ca652 Blue Swirl
        (float64_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
670 e72ca652 Blue Swirl
        cc = 1;
671 e72ca652 Blue Swirl
    } else if (m2 & (1 << (9-neg))) {
672 e72ca652 Blue Swirl
        /* assume normalized number */
673 e72ca652 Blue Swirl
        cc = 1;
674 e72ca652 Blue Swirl
    }
675 e72ca652 Blue Swirl
    /* FIXME: denormalized? */
676 e72ca652 Blue Swirl
    return cc;
677 e72ca652 Blue Swirl
}
678 e72ca652 Blue Swirl
679 e72ca652 Blue Swirl
/* test data class 128-bit */
680 449c0d70 Blue Swirl
uint32_t HELPER(tcxb)(CPUS390XState *env, uint32_t f1, uint64_t m2)
681 e72ca652 Blue Swirl
{
682 e72ca652 Blue Swirl
    CPU_QuadU v1;
683 e72ca652 Blue Swirl
    uint32_t cc = 0;
684 e72ca652 Blue Swirl
    int neg;
685 e72ca652 Blue Swirl
686 e72ca652 Blue Swirl
    v1.ll.upper = env->fregs[f1].ll;
687 e72ca652 Blue Swirl
    v1.ll.lower = env->fregs[f1 + 2].ll;
688 e72ca652 Blue Swirl
689 e72ca652 Blue Swirl
    neg = float128_is_neg(v1.q);
690 e72ca652 Blue Swirl
    if ((float128_is_zero(v1.q) && (m2 & (1 << (11-neg)))) ||
691 e72ca652 Blue Swirl
        (float128_is_infinity(v1.q) && (m2 & (1 << (5-neg)))) ||
692 e72ca652 Blue Swirl
        (float128_is_any_nan(v1.q) && (m2 & (1 << (3-neg)))) ||
693 e72ca652 Blue Swirl
        (float128_is_signaling_nan(v1.q) && (m2 & (1 << (1-neg))))) {
694 e72ca652 Blue Swirl
        cc = 1;
695 e72ca652 Blue Swirl
    } else if (m2 & (1 << (9-neg))) {
696 e72ca652 Blue Swirl
        /* assume normalized number */
697 e72ca652 Blue Swirl
        cc = 1;
698 e72ca652 Blue Swirl
    }
699 e72ca652 Blue Swirl
    /* FIXME: denormalized? */
700 e72ca652 Blue Swirl
    return cc;
701 e72ca652 Blue Swirl
}
702 e72ca652 Blue Swirl
703 e72ca652 Blue Swirl
/* square root 64-bit RR */
704 449c0d70 Blue Swirl
void HELPER(sqdbr)(CPUS390XState *env, uint32_t f1, uint32_t f2)
705 e72ca652 Blue Swirl
{
706 e72ca652 Blue Swirl
    env->fregs[f1].d = float64_sqrt(env->fregs[f2].d, &env->fpu_status);
707 e72ca652 Blue Swirl
}