Revision f0aabd1a
| b/target-ppc/translate.c | ||
|---|---|---|
| 5316 | 5316 |
} |
| 5317 | 5317 |
|
| 5318 | 5318 |
/* SPE load and stores */ |
| 5319 |
static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh) |
|
| 5319 |
static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
|
|
| 5320 | 5320 |
{
|
| 5321 | 5321 |
target_long simm = rB(ctx->opcode); |
| 5322 | 5322 |
|
| 5323 |
if (rA(ctx->opcode) == 0) {
|
|
| 5324 |
tcg_gen_movi_tl(cpu_T[0], simm << sh); |
|
| 5325 |
} else {
|
|
| 5326 |
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); |
|
| 5327 |
if (likely(simm != 0)) |
|
| 5328 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh); |
|
| 5329 |
} |
|
| 5323 |
if (rA(ctx->opcode) == 0) |
|
| 5324 |
tcg_gen_movi_tl(EA, simm << sh); |
|
| 5325 |
else if (likely(simm != 0)) |
|
| 5326 |
tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh); |
|
| 5327 |
else |
|
| 5328 |
tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
|
| 5330 | 5329 |
} |
| 5331 | 5330 |
|
| 5332 | 5331 |
#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
| ... | ... | |
| 5346 | 5345 |
GEN_EXCP_NO_AP(ctx); \ |
| 5347 | 5346 |
return; \ |
| 5348 | 5347 |
} \ |
| 5349 |
gen_addr_spe_imm_index(ctx, sh); \
|
|
| 5348 |
gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
|
|
| 5350 | 5349 |
op_spe_ldst(spe_l##name); \ |
| 5351 | 5350 |
gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \ |
| 5352 | 5351 |
} |
| ... | ... | |
| 5375 | 5374 |
GEN_EXCP_NO_AP(ctx); \ |
| 5376 | 5375 |
return; \ |
| 5377 | 5376 |
} \ |
| 5378 |
gen_addr_spe_imm_index(ctx, sh); \
|
|
| 5377 |
gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
|
|
| 5379 | 5378 |
gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \ |
| 5380 | 5379 |
op_spe_ldst(spe_st##name); \ |
| 5381 | 5380 |
} |
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