/ - Diff - qemu - Greek Research and Technology Network's projects

Revision f0b3f3ae

     #endif
     /* CP0 functions */
     void op_mfc0_index (void)
+    {
         T0 = env->CP0_Index;
         FORCE_RET();
+    }
     void op_mfc0_mvpcontrol (void)
+    {
         T0 = env->mvp->CP0_MVPControl;
-...
         FORCE_RET();
+    }
     void op_mfc0_vpecontrol (void)
+    {
         T0 = env->CP0_VPEControl;
         FORCE_RET();
+    }
     void op_mfc0_vpeconf0 (void)
+    {
         T0 = env->CP0_VPEConf0;
         FORCE_RET();
+    }
     void op_mfc0_vpeconf1 (void)
+    {
         T0 = env->CP0_VPEConf1;
         FORCE_RET();
+    }
     void op_mfc0_yqmask (void)
+    {
         T0 = env->CP0_YQMask;
         FORCE_RET();
+    }
     void op_mfc0_vpeschedule (void)
+    {
         T0 = env->CP0_VPESchedule;
         FORCE_RET();
+    }
     void op_mfc0_vpeschefback (void)
+    {
         T0 = env->CP0_VPEScheFBack;
         FORCE_RET();
+    }
     void op_mfc0_vpeopt (void)
+    {
         T0 = env->CP0_VPEOpt;
         FORCE_RET();
+    }
     void op_mfc0_entrylo0 (void)
+    {
         T0 = (int32_t)env->CP0_EntryLo0;
         FORCE_RET();
+    }
     void op_mfc0_tcstatus (void)
+    {
         T0 = env->CP0_TCStatus[env->current_tc];
-...
         FORCE_RET();
+    }
     void op_mfc0_entrylo1 (void)
+    {
         T0 = (int32_t)env->CP0_EntryLo1;
         FORCE_RET();
+    }
     void op_mfc0_context (void)
+    {
         T0 = (int32_t)env->CP0_Context;
         FORCE_RET();
+    }
     void op_mfc0_pagemask (void)
+    {
         T0 = env->CP0_PageMask;
         FORCE_RET();
+    }
     void op_mfc0_pagegrain (void)
+    {
         T0 = env->CP0_PageGrain;
         FORCE_RET();
+    }
     void op_mfc0_wired (void)
+    {
         T0 = env->CP0_Wired;
         FORCE_RET();
+    }
     void op_mfc0_srsconf0 (void)
+    {
         T0 = env->CP0_SRSConf0;
         FORCE_RET();
+    }
     void op_mfc0_srsconf1 (void)
+    {
         T0 = env->CP0_SRSConf1;
         FORCE_RET();
+    }
     void op_mfc0_srsconf2 (void)
+    {
         T0 = env->CP0_SRSConf2;
         FORCE_RET();
+    }
     void op_mfc0_srsconf3 (void)
+    {
         T0 = env->CP0_SRSConf3;
         FORCE_RET();
+    }
     void op_mfc0_srsconf4 (void)
+    {
         T0 = env->CP0_SRSConf4;
         FORCE_RET();
+    }
     void op_mfc0_hwrena (void)
+    {
         T0 = env->CP0_HWREna;
         FORCE_RET();
+    }
     void op_mfc0_badvaddr (void)
+    {
         T0 = (int32_t)env->CP0_BadVAddr;
         FORCE_RET();
+    }
     void op_mfc0_count (void)
+    {
         CALL_FROM_TB0(do_mfc0_count);
         FORCE_RET();
+    }
     void op_mfc0_entryhi (void)
+    {
         T0 = (int32_t)env->CP0_EntryHi;
         FORCE_RET();
+    }
     void op_mftc0_entryhi(void)
+    {
         int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
-...
         FORCE_RET();
+    }
     void op_mfc0_compare (void)
+    {
         T0 = env->CP0_Compare;
         FORCE_RET();
+    }
     void op_mfc0_status (void)
+    {
         T0 = env->CP0_Status;
         FORCE_RET();
+    }
     void op_mftc0_status(void)
+    {
         int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
-...
         FORCE_RET();
+    }
     void op_mfc0_intctl (void)
+    {
         T0 = env->CP0_IntCtl;
         FORCE_RET();
+    }
     void op_mfc0_srsctl (void)
+    {
         T0 = env->CP0_SRSCtl;
         FORCE_RET();
+    }
     void op_mfc0_srsmap (void)
+    {
         T0 = env->CP0_SRSMap;
         FORCE_RET();
+    }
     void op_mfc0_cause (void)
+    {
         T0 = env->CP0_Cause;
         FORCE_RET();
+    }
     void op_mfc0_epc (void)
+    {
         T0 = (int32_t)env->CP0_EPC;
         FORCE_RET();
+    }
     void op_mfc0_prid (void)
+    {
         T0 = env->CP0_PRid;
         FORCE_RET();
+    }
     void op_mfc0_ebase (void)
+    {
         T0 = env->CP0_EBase;
         FORCE_RET();
+    }
     void op_mfc0_config0 (void)
+    {
         T0 = env->CP0_Config0;
         FORCE_RET();
+    }
     void op_mfc0_config1 (void)
+    {
         T0 = env->CP0_Config1;
         FORCE_RET();
+    }
     void op_mfc0_config2 (void)
+    {
         T0 = env->CP0_Config2;
         FORCE_RET();
+    }
     void op_mfc0_config3 (void)
+    {
         T0 = env->CP0_Config3;
         FORCE_RET();
+    }
     void op_mfc0_config6 (void)
+    {
         T0 = env->CP0_Config6;
         FORCE_RET();
+    }
     void op_mfc0_config7 (void)
+    {
         T0 = env->CP0_Config7;
         FORCE_RET();
+    }
     void op_mfc0_lladdr (void)
+    {
         T0 = (int32_t)env->CP0_LLAddr >> 4;
-...
         FORCE_RET();
+    }
     void op_mfc0_xcontext (void)
+    {
         T0 = (int32_t)env->CP0_XContext;
         FORCE_RET();
+    }
     void op_mfc0_framemask (void)
+    {
         T0 = env->CP0_Framemask;
         FORCE_RET();
+    }
     void op_mfc0_debug (void)
+    {
         T0 = env->CP0_Debug;
-...
         FORCE_RET();
+    }
     void op_mfc0_depc (void)
+    {
         T0 = (int32_t)env->CP0_DEPC;
         FORCE_RET();
+    }
     void op_mfc0_performance0 (void)
+    {
         T0 = env->CP0_Performance0;
         FORCE_RET();
+    }
     void op_mfc0_taglo (void)
+    {
         T0 = env->CP0_TagLo;
         FORCE_RET();
+    }
     void op_mfc0_datalo (void)
+    {
         T0 = env->CP0_DataLo;
         FORCE_RET();
+    }
     void op_mfc0_taghi (void)
+    {
         T0 = env->CP0_TagHi;
         FORCE_RET();
+    }
     void op_mfc0_datahi (void)
+    {
         T0 = env->CP0_DataHi;
         FORCE_RET();
+    }
     void op_mfc0_errorepc (void)
+    {
         T0 = (int32_t)env->CP0_ErrorEPC;
         FORCE_RET();
+    }
     void op_mfc0_desave (void)
+    {
         T0 = env->CP0_DESAVE;
         FORCE_RET();
+    }
     void op_mtc0_index (void)
+    {
         int num = 1;
-...
+    }
     #if defined(TARGET_MIPS64)
     void op_dmfc0_yqmask (void)
+    {
         T0 = env->CP0_YQMask;
         FORCE_RET();
+    }
     void op_dmfc0_vpeschedule (void)
+    {
         T0 = env->CP0_VPESchedule;
         FORCE_RET();
+    }
     void op_dmfc0_vpeschefback (void)
+    {
         T0 = env->CP0_VPEScheFBack;
         FORCE_RET();
+    }
     void op_dmfc0_entrylo0 (void)
+    {
         T0 = env->CP0_EntryLo0;
         FORCE_RET();
+    }
     void op_dmfc0_tcrestart (void)
+    {
         T0 = env->PC[env->current_tc];
-...
         FORCE_RET();
+    }
     void op_dmfc0_entrylo1 (void)
+    {
         T0 = env->CP0_EntryLo1;
         FORCE_RET();
+    }
     void op_dmfc0_context (void)
+    {
         T0 = env->CP0_Context;
         FORCE_RET();
+    }
     void op_dmfc0_badvaddr (void)
+    {
         T0 = env->CP0_BadVAddr;
         FORCE_RET();
+    }
     void op_dmfc0_entryhi (void)
+    {
         T0 = env->CP0_EntryHi;
         FORCE_RET();
+    }
     void op_dmfc0_epc (void)
+    {
         T0 = env->CP0_EPC;
         FORCE_RET();
+    }
     void op_dmfc0_lladdr (void)
+    {
         T0 = env->CP0_LLAddr >> 4;
-...
         T0 = env->CP0_WatchLo[PARAM1];
         FORCE_RET();
+    }
     void op_dmfc0_xcontext (void)
+    {
         T0 = env->CP0_XContext;
         FORCE_RET();
+    }
     void op_dmfc0_depc (void)
+    {
         T0 = env->CP0_DEPC;
         FORCE_RET();
+    }
     void op_dmfc0_errorepc (void)
+    {
         T0 = env->CP0_ErrorEPC;
         FORCE_RET();
+    }
     #endif /* TARGET_MIPS64 */
     /* MIPS MT functions */

         tcg_gen_andi_tl(r_tmp, cpu_T[0], almask);                           \
         tcg_gen_brcond_tl(TCG_COND_EQ, r_tmp, tcg_const_tl(0), l1);         \
         tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
         generate_exception(ctx, EXCP_AdES);                             \
         generate_exception(ctx, EXCP_AdES);                                 \
         gen_set_label(l1);                                                  \
         tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr));      \
         tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], r_tmp, l2);                \
-...
     static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
+    {
         const char *rn = "invalid";
         TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
         TCGv r_tmp64 = tcg_temp_new(TCG_TYPE_I64);
         if (sel != 0)
             check_insn(env, ctx, ISA_MIPS32);
-...
         case 0:
             switch (sel) {
             case 0:
                 gen_op_mfc0_index();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Index));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Index";
                 break;
             case 1:
-...
                 break;
             case 1:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_vpecontrol();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEControl));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "VPEControl";
                 break;
             case 2:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_vpeconf0();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf0));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "VPEConf0";
                 break;
             case 3:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_vpeconf1();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf1));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "VPEConf1";
                 break;
             case 4:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_yqmask();
                 tcg_gen_ld_i64(r_tmp64, cpu_env, offsetof(CPUState, CP0_YQMask));
                 tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
                 rn = "YQMask";
                 break;
             case 5:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_vpeschedule();
                 tcg_gen_ld_tl(r_tmp64, cpu_env, offsetof(CPUState, CP0_VPESchedule));
                 tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
                 rn = "VPESchedule";
                 break;
             case 6:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_vpeschefback();
                 tcg_gen_ld_tl(r_tmp64, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
                 tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64);
                 rn = "VPEScheFBack";
                 break;
             case 7:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_vpeopt();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEOpt));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "VPEOpt";
                 break;
             default:
-...
         case 2:
             switch (sel) {
             case 0:
                 gen_op_mfc0_entrylo0();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0));
                 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
                 rn = "EntryLo0";
                 break;
             case 1:
-...
         case 3:
             switch (sel) {
             case 0:
                 gen_op_mfc0_entrylo1();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1));
                 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
                 rn = "EntryLo1";
                 break;
             default:
-...
         case 4:
             switch (sel) {
             case 0:
                 gen_op_mfc0_context();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context));
                 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
                 rn = "Context";
                 break;
             case 1:
-...
         case 5:
             switch (sel) {
             case 0:
                 gen_op_mfc0_pagemask();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageMask));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "PageMask";
                 break;
             case 1:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_pagegrain();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageGrain));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "PageGrain";
                 break;
             default:
-...
         case 6:
             switch (sel) {
             case 0:
                 gen_op_mfc0_wired();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Wired));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Wired";
                 break;
             case 1:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsconf0();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf0));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSConf0";
                 break;
             case 2:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsconf1();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf1));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSConf1";
                 break;
             case 3:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsconf2();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf2));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSConf2";
                 break;
             case 4:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsconf3();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf3));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSConf3";
                 break;
             case 5:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsconf4();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf4));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSConf4";
                 break;
             default:
-...
             switch (sel) {
             case 0:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_hwrena();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_HWREna));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "HWREna";
                 break;
             default:
-...
         case 8:
             switch (sel) {
             case 0:
                 gen_op_mfc0_badvaddr();
                 rn = "BadVaddr";
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr));
                 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
                 rn = "BadVAddr";
                 break;
             default:
                 goto die;
-...
         case 10:
             switch (sel) {
             case 0:
                 gen_op_mfc0_entryhi();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi));
                 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
                 rn = "EntryHi";
                 break;
             default:
-...
         case 11:
             switch (sel) {
             case 0:
                 gen_op_mfc0_compare();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Compare));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Compare";
                 break;
             /* 6,7 are implementation dependent */
-...
         case 12:
             switch (sel) {
             case 0:
                 gen_op_mfc0_status();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Status";
                 break;
             case 1:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_intctl();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_IntCtl));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "IntCtl";
                 break;
             case 2:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsctl();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSCtl";
                 break;
             case 3:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsmap();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSMap));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSMap";
                 break;
             default:
-...
         case 13:
             switch (sel) {
             case 0:
                 gen_op_mfc0_cause();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Cause));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Cause";
                 break;
             default:
-...
         case 14:
             switch (sel) {
             case 0:
                 gen_op_mfc0_epc();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
                 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
                 rn = "EPC";
                 break;
             default:
-...
         case 15:
             switch (sel) {
             case 0:
                 gen_op_mfc0_prid();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PRid));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "PRid";
                 break;
             case 1:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_ebase();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_EBase));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "EBase";
                 break;
             default:
-...
         case 16:
             switch (sel) {
             case 0:
                 gen_op_mfc0_config0();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config0));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config";
                 break;
             case 1:
                 gen_op_mfc0_config1();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config1));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config1";
                 break;
             case 2:
                 gen_op_mfc0_config2();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config2));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config2";
                 break;
             case 3:
                 gen_op_mfc0_config3();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config3));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config3";
                 break;
             /* 4,5 are reserved */
             /* 6,7 are implementation dependent */
             case 6:
                 gen_op_mfc0_config6();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config6));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config6";
                 break;
             case 7:
                 gen_op_mfc0_config7();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config7));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config7";
                 break;
             default:
-...
             case 0:
     #if defined(TARGET_MIPS64)
                 check_insn(env, ctx, ISA_MIPS3);
                 gen_op_mfc0_xcontext();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext));
                 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
                 rn = "XContext";
                 break;
     #endif
-...
            /* Officially reserved, but sel 0 is used for R1x000 framemask */
             switch (sel) {
             case 0:
                 gen_op_mfc0_framemask();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Framemask));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Framemask";
                 break;
             default:
-...
         case 24:
             switch (sel) {
             case 0:
                 gen_op_mfc0_depc(); /* EJTAG support */
                 /* EJTAG support */
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
                 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
                 rn = "DEPC";
                 break;
             default:
-...
         case 25:
             switch (sel) {
             case 0:
                 gen_op_mfc0_performance0();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Performance0));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Performance0";
                 break;
             case 1:
-...
             case 2:
             case 4:
             case 6:
                 gen_op_mfc0_taglo();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagLo));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "TagLo";
                 break;
             case 1:
             case 3:
             case 5:
             case 7:
                 gen_op_mfc0_datalo();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataLo));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "DataLo";
                 break;
             default:
-...
             case 2:
             case 4:
             case 6:
                 gen_op_mfc0_taghi();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagHi));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "TagHi";
                 break;
             case 1:
             case 3:
             case 5:
             case 7:
                 gen_op_mfc0_datahi();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataHi));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "DataHi";
                 break;
             default:
-...
         case 30:
             switch (sel) {
             case 0:
                 gen_op_mfc0_errorepc();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
                 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
                 rn = "ErrorEPC";
                 break;
             default:
-...
         case 31:
             switch (sel) {
             case 0:
                 gen_op_mfc0_desave(); /* EJTAG support */
                 /* EJTAG support */
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DESAVE));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "DESAVE";
                 break;
             default:
-...
             break;
         case 8:
             /* ignored */
             rn = "BadVaddr";
             rn = "BadVAddr";
             break;
         case 9:
             switch (sel) {
-...
     static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
+    {
         const char *rn = "invalid";
         TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
         if (sel != 0)
             check_insn(env, ctx, ISA_MIPS64);
-...
         case 0:
             switch (sel) {
             case 0:
                 gen_op_mfc0_index();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Index));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Index";
                 break;
             case 1:
-...
                 break;
             case 1:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_vpecontrol();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEControl));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "VPEControl";
                 break;
             case 2:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_vpeconf0();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf0));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "VPEConf0";
                 break;
             case 3:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_vpeconf1();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf1));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "VPEConf1";
                 break;
             case 4:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_dmfc0_yqmask();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_YQMask));
                 rn = "YQMask";
                 break;
             case 5:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_dmfc0_vpeschedule();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule));
                 rn = "VPESchedule";
                 break;
             case 6:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_dmfc0_vpeschefback();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
                 rn = "VPEScheFBack";
                 break;
             case 7:
                 check_insn(env, ctx, ASE_MT);
                 gen_op_mfc0_vpeopt();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEOpt));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "VPEOpt";
                 break;
             default:
-...
         case 2:
             switch (sel) {
             case 0:
                 gen_op_dmfc0_entrylo0();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0));
                 rn = "EntryLo0";
                 break;
             case 1:
-...
         case 3:
             switch (sel) {
             case 0:
                 gen_op_dmfc0_entrylo1();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1));
                 rn = "EntryLo1";
                 break;
             default:
-...
         case 4:
             switch (sel) {
             case 0:
                 gen_op_dmfc0_context();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context));
                 rn = "Context";
                 break;
             case 1:
-...
         case 5:
             switch (sel) {
             case 0:
                 gen_op_mfc0_pagemask();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageMask));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "PageMask";
                 break;
             case 1:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_pagegrain();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageGrain));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "PageGrain";
                 break;
             default:
-...
         case 6:
             switch (sel) {
             case 0:
                 gen_op_mfc0_wired();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Wired));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Wired";
                 break;
             case 1:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsconf0();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf0));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSConf0";
                 break;
             case 2:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsconf1();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf1));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSConf1";
                 break;
             case 3:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsconf2();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf2));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSConf2";
                 break;
             case 4:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsconf3();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf3));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSConf3";
                 break;
             case 5:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsconf4();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf4));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSConf4";
                 break;
             default:
-...
             switch (sel) {
             case 0:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_hwrena();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_HWREna));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "HWREna";
                 break;
             default:
-...
         case 8:
             switch (sel) {
             case 0:
                 gen_op_dmfc0_badvaddr();
                 rn = "BadVaddr";
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr));
                 rn = "BadVAddr";
                 break;
             default:
                 goto die;
-...
         case 10:
             switch (sel) {
             case 0:
                 gen_op_dmfc0_entryhi();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi));
                 rn = "EntryHi";
                 break;
             default:
-...
         case 11:
             switch (sel) {
             case 0:
                 gen_op_mfc0_compare();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Compare));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Compare";
                 break;
             /* 6,7 are implementation dependent */
-...
         case 12:
             switch (sel) {
             case 0:
                 gen_op_mfc0_status();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Status";
                 break;
             case 1:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_intctl();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_IntCtl));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "IntCtl";
                 break;
             case 2:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsctl();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSCtl";
                 break;
             case 3:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_srsmap();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSMap));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "SRSMap";
                 break;
             default:
-...
         case 13:
             switch (sel) {
             case 0:
                 gen_op_mfc0_cause();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Cause));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Cause";
                 break;
             default:
-...
         case 14:
             switch (sel) {
             case 0:
                 gen_op_dmfc0_epc();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
                 rn = "EPC";
                 break;
             default:
-...
         case 15:
             switch (sel) {
             case 0:
                 gen_op_mfc0_prid();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PRid));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "PRid";
                 break;
             case 1:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 gen_op_mfc0_ebase();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_EBase));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "EBase";
                 break;
             default:
-...
         case 16:
             switch (sel) {
             case 0:
                 gen_op_mfc0_config0();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config0));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config";
                 break;
             case 1:
                 gen_op_mfc0_config1();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config1));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config1";
                 break;
             case 2:
                 gen_op_mfc0_config2();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config2));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config2";
                 break;
             case 3:
                 gen_op_mfc0_config3();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config3));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config3";
                 break;
            /* 6,7 are implementation dependent */
             case 6:
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config6));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config6";
                 break;
             case 7:
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config7));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Config7";
                 break;
             default:
                 goto die;
+            }
-...
             switch (sel) {
             case 0:
                 check_insn(env, ctx, ISA_MIPS3);
                 gen_op_dmfc0_xcontext();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext));
                 rn = "XContext";
                 break;
             default:
-...
            /* Officially reserved, but sel 0 is used for R1x000 framemask */
             switch (sel) {
             case 0:
                 gen_op_mfc0_framemask();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Framemask));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Framemask";
                 break;
             default:
-...
         case 24:
             switch (sel) {
             case 0:
                 gen_op_dmfc0_depc(); /* EJTAG support */
                 /* EJTAG support */
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
                 rn = "DEPC";
                 break;
             default:
-...
         case 25:
             switch (sel) {
             case 0:
                 gen_op_mfc0_performance0();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Performance0));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "Performance0";
                 break;
             case 1:
-...
             case 2:
             case 4:
             case 6:
                 gen_op_mfc0_taglo();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagLo));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "TagLo";
                 break;
             case 1:
             case 3:
             case 5:
             case 7:
                 gen_op_mfc0_datalo();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataLo));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "DataLo";
                 break;
             default:
-...
             case 2:
             case 4:
             case 6:
                 gen_op_mfc0_taghi();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagHi));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "TagHi";
                 break;
             case 1:
             case 3:
             case 5:
             case 7:
                 gen_op_mfc0_datahi();
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataHi));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "DataHi";
                 break;
             default:
-...
         case 30:
             switch (sel) {
             case 0:
                 gen_op_dmfc0_errorepc();
                 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
                 rn = "ErrorEPC";
                 break;
             default:
-...
         case 31:
             switch (sel) {
             case 0:
                 gen_op_mfc0_desave(); /* EJTAG support */
                 /* EJTAG support */
                 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DESAVE));
                 tcg_gen_ext_i32_tl(cpu_T[0], r_tmp);
                 rn = "DESAVE";
                 break;
             default:
-...
             break;
         case 8:
             /* ignored */
             rn = "BadVaddr";
             rn = "BadVAddr";
             break;
         case 9:
             switch (sel) {

Also available in: Unified diff

Archipelago » qemu

Revision f0b3f3ae