Revision f0b3f3ae target-mips/op.c
| b/target-mips/op.c | ||
|---|---|---|
| 461 | 461 |
#endif |
| 462 | 462 |
|
| 463 | 463 |
/* CP0 functions */ |
| 464 |
void op_mfc0_index (void) |
|
| 465 |
{
|
|
| 466 |
T0 = env->CP0_Index; |
|
| 467 |
FORCE_RET(); |
|
| 468 |
} |
|
| 469 |
|
|
| 470 | 464 |
void op_mfc0_mvpcontrol (void) |
| 471 | 465 |
{
|
| 472 | 466 |
T0 = env->mvp->CP0_MVPControl; |
| ... | ... | |
| 491 | 485 |
FORCE_RET(); |
| 492 | 486 |
} |
| 493 | 487 |
|
| 494 |
void op_mfc0_vpecontrol (void) |
|
| 495 |
{
|
|
| 496 |
T0 = env->CP0_VPEControl; |
|
| 497 |
FORCE_RET(); |
|
| 498 |
} |
|
| 499 |
|
|
| 500 |
void op_mfc0_vpeconf0 (void) |
|
| 501 |
{
|
|
| 502 |
T0 = env->CP0_VPEConf0; |
|
| 503 |
FORCE_RET(); |
|
| 504 |
} |
|
| 505 |
|
|
| 506 |
void op_mfc0_vpeconf1 (void) |
|
| 507 |
{
|
|
| 508 |
T0 = env->CP0_VPEConf1; |
|
| 509 |
FORCE_RET(); |
|
| 510 |
} |
|
| 511 |
|
|
| 512 |
void op_mfc0_yqmask (void) |
|
| 513 |
{
|
|
| 514 |
T0 = env->CP0_YQMask; |
|
| 515 |
FORCE_RET(); |
|
| 516 |
} |
|
| 517 |
|
|
| 518 |
void op_mfc0_vpeschedule (void) |
|
| 519 |
{
|
|
| 520 |
T0 = env->CP0_VPESchedule; |
|
| 521 |
FORCE_RET(); |
|
| 522 |
} |
|
| 523 |
|
|
| 524 |
void op_mfc0_vpeschefback (void) |
|
| 525 |
{
|
|
| 526 |
T0 = env->CP0_VPEScheFBack; |
|
| 527 |
FORCE_RET(); |
|
| 528 |
} |
|
| 529 |
|
|
| 530 |
void op_mfc0_vpeopt (void) |
|
| 531 |
{
|
|
| 532 |
T0 = env->CP0_VPEOpt; |
|
| 533 |
FORCE_RET(); |
|
| 534 |
} |
|
| 535 |
|
|
| 536 |
void op_mfc0_entrylo0 (void) |
|
| 537 |
{
|
|
| 538 |
T0 = (int32_t)env->CP0_EntryLo0; |
|
| 539 |
FORCE_RET(); |
|
| 540 |
} |
|
| 541 |
|
|
| 542 | 488 |
void op_mfc0_tcstatus (void) |
| 543 | 489 |
{
|
| 544 | 490 |
T0 = env->CP0_TCStatus[env->current_tc]; |
| ... | ... | |
| 637 | 583 |
FORCE_RET(); |
| 638 | 584 |
} |
| 639 | 585 |
|
| 640 |
void op_mfc0_entrylo1 (void) |
|
| 641 |
{
|
|
| 642 |
T0 = (int32_t)env->CP0_EntryLo1; |
|
| 643 |
FORCE_RET(); |
|
| 644 |
} |
|
| 645 |
|
|
| 646 |
void op_mfc0_context (void) |
|
| 647 |
{
|
|
| 648 |
T0 = (int32_t)env->CP0_Context; |
|
| 649 |
FORCE_RET(); |
|
| 650 |
} |
|
| 651 |
|
|
| 652 |
void op_mfc0_pagemask (void) |
|
| 653 |
{
|
|
| 654 |
T0 = env->CP0_PageMask; |
|
| 655 |
FORCE_RET(); |
|
| 656 |
} |
|
| 657 |
|
|
| 658 |
void op_mfc0_pagegrain (void) |
|
| 659 |
{
|
|
| 660 |
T0 = env->CP0_PageGrain; |
|
| 661 |
FORCE_RET(); |
|
| 662 |
} |
|
| 663 |
|
|
| 664 |
void op_mfc0_wired (void) |
|
| 665 |
{
|
|
| 666 |
T0 = env->CP0_Wired; |
|
| 667 |
FORCE_RET(); |
|
| 668 |
} |
|
| 669 |
|
|
| 670 |
void op_mfc0_srsconf0 (void) |
|
| 671 |
{
|
|
| 672 |
T0 = env->CP0_SRSConf0; |
|
| 673 |
FORCE_RET(); |
|
| 674 |
} |
|
| 675 |
|
|
| 676 |
void op_mfc0_srsconf1 (void) |
|
| 677 |
{
|
|
| 678 |
T0 = env->CP0_SRSConf1; |
|
| 679 |
FORCE_RET(); |
|
| 680 |
} |
|
| 681 |
|
|
| 682 |
void op_mfc0_srsconf2 (void) |
|
| 683 |
{
|
|
| 684 |
T0 = env->CP0_SRSConf2; |
|
| 685 |
FORCE_RET(); |
|
| 686 |
} |
|
| 687 |
|
|
| 688 |
void op_mfc0_srsconf3 (void) |
|
| 689 |
{
|
|
| 690 |
T0 = env->CP0_SRSConf3; |
|
| 691 |
FORCE_RET(); |
|
| 692 |
} |
|
| 693 |
|
|
| 694 |
void op_mfc0_srsconf4 (void) |
|
| 695 |
{
|
|
| 696 |
T0 = env->CP0_SRSConf4; |
|
| 697 |
FORCE_RET(); |
|
| 698 |
} |
|
| 699 |
|
|
| 700 |
void op_mfc0_hwrena (void) |
|
| 701 |
{
|
|
| 702 |
T0 = env->CP0_HWREna; |
|
| 703 |
FORCE_RET(); |
|
| 704 |
} |
|
| 705 |
|
|
| 706 |
void op_mfc0_badvaddr (void) |
|
| 707 |
{
|
|
| 708 |
T0 = (int32_t)env->CP0_BadVAddr; |
|
| 709 |
FORCE_RET(); |
|
| 710 |
} |
|
| 711 |
|
|
| 712 | 586 |
void op_mfc0_count (void) |
| 713 | 587 |
{
|
| 714 | 588 |
CALL_FROM_TB0(do_mfc0_count); |
| 715 | 589 |
FORCE_RET(); |
| 716 | 590 |
} |
| 717 | 591 |
|
| 718 |
void op_mfc0_entryhi (void) |
|
| 719 |
{
|
|
| 720 |
T0 = (int32_t)env->CP0_EntryHi; |
|
| 721 |
FORCE_RET(); |
|
| 722 |
} |
|
| 723 |
|
|
| 724 | 592 |
void op_mftc0_entryhi(void) |
| 725 | 593 |
{
|
| 726 | 594 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| ... | ... | |
| 729 | 597 |
FORCE_RET(); |
| 730 | 598 |
} |
| 731 | 599 |
|
| 732 |
void op_mfc0_compare (void) |
|
| 733 |
{
|
|
| 734 |
T0 = env->CP0_Compare; |
|
| 735 |
FORCE_RET(); |
|
| 736 |
} |
|
| 737 |
|
|
| 738 |
void op_mfc0_status (void) |
|
| 739 |
{
|
|
| 740 |
T0 = env->CP0_Status; |
|
| 741 |
FORCE_RET(); |
|
| 742 |
} |
|
| 743 |
|
|
| 744 | 600 |
void op_mftc0_status(void) |
| 745 | 601 |
{
|
| 746 | 602 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| ... | ... | |
| 753 | 609 |
FORCE_RET(); |
| 754 | 610 |
} |
| 755 | 611 |
|
| 756 |
void op_mfc0_intctl (void) |
|
| 757 |
{
|
|
| 758 |
T0 = env->CP0_IntCtl; |
|
| 759 |
FORCE_RET(); |
|
| 760 |
} |
|
| 761 |
|
|
| 762 |
void op_mfc0_srsctl (void) |
|
| 763 |
{
|
|
| 764 |
T0 = env->CP0_SRSCtl; |
|
| 765 |
FORCE_RET(); |
|
| 766 |
} |
|
| 767 |
|
|
| 768 |
void op_mfc0_srsmap (void) |
|
| 769 |
{
|
|
| 770 |
T0 = env->CP0_SRSMap; |
|
| 771 |
FORCE_RET(); |
|
| 772 |
} |
|
| 773 |
|
|
| 774 |
void op_mfc0_cause (void) |
|
| 775 |
{
|
|
| 776 |
T0 = env->CP0_Cause; |
|
| 777 |
FORCE_RET(); |
|
| 778 |
} |
|
| 779 |
|
|
| 780 |
void op_mfc0_epc (void) |
|
| 781 |
{
|
|
| 782 |
T0 = (int32_t)env->CP0_EPC; |
|
| 783 |
FORCE_RET(); |
|
| 784 |
} |
|
| 785 |
|
|
| 786 |
void op_mfc0_prid (void) |
|
| 787 |
{
|
|
| 788 |
T0 = env->CP0_PRid; |
|
| 789 |
FORCE_RET(); |
|
| 790 |
} |
|
| 791 |
|
|
| 792 |
void op_mfc0_ebase (void) |
|
| 793 |
{
|
|
| 794 |
T0 = env->CP0_EBase; |
|
| 795 |
FORCE_RET(); |
|
| 796 |
} |
|
| 797 |
|
|
| 798 |
void op_mfc0_config0 (void) |
|
| 799 |
{
|
|
| 800 |
T0 = env->CP0_Config0; |
|
| 801 |
FORCE_RET(); |
|
| 802 |
} |
|
| 803 |
|
|
| 804 |
void op_mfc0_config1 (void) |
|
| 805 |
{
|
|
| 806 |
T0 = env->CP0_Config1; |
|
| 807 |
FORCE_RET(); |
|
| 808 |
} |
|
| 809 |
|
|
| 810 |
void op_mfc0_config2 (void) |
|
| 811 |
{
|
|
| 812 |
T0 = env->CP0_Config2; |
|
| 813 |
FORCE_RET(); |
|
| 814 |
} |
|
| 815 |
|
|
| 816 |
void op_mfc0_config3 (void) |
|
| 817 |
{
|
|
| 818 |
T0 = env->CP0_Config3; |
|
| 819 |
FORCE_RET(); |
|
| 820 |
} |
|
| 821 |
|
|
| 822 |
void op_mfc0_config6 (void) |
|
| 823 |
{
|
|
| 824 |
T0 = env->CP0_Config6; |
|
| 825 |
FORCE_RET(); |
|
| 826 |
} |
|
| 827 |
|
|
| 828 |
void op_mfc0_config7 (void) |
|
| 829 |
{
|
|
| 830 |
T0 = env->CP0_Config7; |
|
| 831 |
FORCE_RET(); |
|
| 832 |
} |
|
| 833 |
|
|
| 834 | 612 |
void op_mfc0_lladdr (void) |
| 835 | 613 |
{
|
| 836 | 614 |
T0 = (int32_t)env->CP0_LLAddr >> 4; |
| ... | ... | |
| 849 | 627 |
FORCE_RET(); |
| 850 | 628 |
} |
| 851 | 629 |
|
| 852 |
void op_mfc0_xcontext (void) |
|
| 853 |
{
|
|
| 854 |
T0 = (int32_t)env->CP0_XContext; |
|
| 855 |
FORCE_RET(); |
|
| 856 |
} |
|
| 857 |
|
|
| 858 |
void op_mfc0_framemask (void) |
|
| 859 |
{
|
|
| 860 |
T0 = env->CP0_Framemask; |
|
| 861 |
FORCE_RET(); |
|
| 862 |
} |
|
| 863 |
|
|
| 864 | 630 |
void op_mfc0_debug (void) |
| 865 | 631 |
{
|
| 866 | 632 |
T0 = env->CP0_Debug; |
| ... | ... | |
| 880 | 646 |
FORCE_RET(); |
| 881 | 647 |
} |
| 882 | 648 |
|
| 883 |
void op_mfc0_depc (void) |
|
| 884 |
{
|
|
| 885 |
T0 = (int32_t)env->CP0_DEPC; |
|
| 886 |
FORCE_RET(); |
|
| 887 |
} |
|
| 888 |
|
|
| 889 |
void op_mfc0_performance0 (void) |
|
| 890 |
{
|
|
| 891 |
T0 = env->CP0_Performance0; |
|
| 892 |
FORCE_RET(); |
|
| 893 |
} |
|
| 894 |
|
|
| 895 |
void op_mfc0_taglo (void) |
|
| 896 |
{
|
|
| 897 |
T0 = env->CP0_TagLo; |
|
| 898 |
FORCE_RET(); |
|
| 899 |
} |
|
| 900 |
|
|
| 901 |
void op_mfc0_datalo (void) |
|
| 902 |
{
|
|
| 903 |
T0 = env->CP0_DataLo; |
|
| 904 |
FORCE_RET(); |
|
| 905 |
} |
|
| 906 |
|
|
| 907 |
void op_mfc0_taghi (void) |
|
| 908 |
{
|
|
| 909 |
T0 = env->CP0_TagHi; |
|
| 910 |
FORCE_RET(); |
|
| 911 |
} |
|
| 912 |
|
|
| 913 |
void op_mfc0_datahi (void) |
|
| 914 |
{
|
|
| 915 |
T0 = env->CP0_DataHi; |
|
| 916 |
FORCE_RET(); |
|
| 917 |
} |
|
| 918 |
|
|
| 919 |
void op_mfc0_errorepc (void) |
|
| 920 |
{
|
|
| 921 |
T0 = (int32_t)env->CP0_ErrorEPC; |
|
| 922 |
FORCE_RET(); |
|
| 923 |
} |
|
| 924 |
|
|
| 925 |
void op_mfc0_desave (void) |
|
| 926 |
{
|
|
| 927 |
T0 = env->CP0_DESAVE; |
|
| 928 |
FORCE_RET(); |
|
| 929 |
} |
|
| 930 |
|
|
| 931 | 649 |
void op_mtc0_index (void) |
| 932 | 650 |
{
|
| 933 | 651 |
int num = 1; |
| ... | ... | |
| 1488 | 1206 |
} |
| 1489 | 1207 |
|
| 1490 | 1208 |
#if defined(TARGET_MIPS64) |
| 1491 |
void op_dmfc0_yqmask (void) |
|
| 1492 |
{
|
|
| 1493 |
T0 = env->CP0_YQMask; |
|
| 1494 |
FORCE_RET(); |
|
| 1495 |
} |
|
| 1496 |
|
|
| 1497 |
void op_dmfc0_vpeschedule (void) |
|
| 1498 |
{
|
|
| 1499 |
T0 = env->CP0_VPESchedule; |
|
| 1500 |
FORCE_RET(); |
|
| 1501 |
} |
|
| 1502 |
|
|
| 1503 |
void op_dmfc0_vpeschefback (void) |
|
| 1504 |
{
|
|
| 1505 |
T0 = env->CP0_VPEScheFBack; |
|
| 1506 |
FORCE_RET(); |
|
| 1507 |
} |
|
| 1508 |
|
|
| 1509 |
void op_dmfc0_entrylo0 (void) |
|
| 1510 |
{
|
|
| 1511 |
T0 = env->CP0_EntryLo0; |
|
| 1512 |
FORCE_RET(); |
|
| 1513 |
} |
|
| 1514 |
|
|
| 1515 | 1209 |
void op_dmfc0_tcrestart (void) |
| 1516 | 1210 |
{
|
| 1517 | 1211 |
T0 = env->PC[env->current_tc]; |
| ... | ... | |
| 1542 | 1236 |
FORCE_RET(); |
| 1543 | 1237 |
} |
| 1544 | 1238 |
|
| 1545 |
void op_dmfc0_entrylo1 (void) |
|
| 1546 |
{
|
|
| 1547 |
T0 = env->CP0_EntryLo1; |
|
| 1548 |
FORCE_RET(); |
|
| 1549 |
} |
|
| 1550 |
|
|
| 1551 |
void op_dmfc0_context (void) |
|
| 1552 |
{
|
|
| 1553 |
T0 = env->CP0_Context; |
|
| 1554 |
FORCE_RET(); |
|
| 1555 |
} |
|
| 1556 |
|
|
| 1557 |
void op_dmfc0_badvaddr (void) |
|
| 1558 |
{
|
|
| 1559 |
T0 = env->CP0_BadVAddr; |
|
| 1560 |
FORCE_RET(); |
|
| 1561 |
} |
|
| 1562 |
|
|
| 1563 |
void op_dmfc0_entryhi (void) |
|
| 1564 |
{
|
|
| 1565 |
T0 = env->CP0_EntryHi; |
|
| 1566 |
FORCE_RET(); |
|
| 1567 |
} |
|
| 1568 |
|
|
| 1569 |
void op_dmfc0_epc (void) |
|
| 1570 |
{
|
|
| 1571 |
T0 = env->CP0_EPC; |
|
| 1572 |
FORCE_RET(); |
|
| 1573 |
} |
|
| 1574 |
|
|
| 1575 | 1239 |
void op_dmfc0_lladdr (void) |
| 1576 | 1240 |
{
|
| 1577 | 1241 |
T0 = env->CP0_LLAddr >> 4; |
| ... | ... | |
| 1583 | 1247 |
T0 = env->CP0_WatchLo[PARAM1]; |
| 1584 | 1248 |
FORCE_RET(); |
| 1585 | 1249 |
} |
| 1586 |
|
|
| 1587 |
void op_dmfc0_xcontext (void) |
|
| 1588 |
{
|
|
| 1589 |
T0 = env->CP0_XContext; |
|
| 1590 |
FORCE_RET(); |
|
| 1591 |
} |
|
| 1592 |
|
|
| 1593 |
void op_dmfc0_depc (void) |
|
| 1594 |
{
|
|
| 1595 |
T0 = env->CP0_DEPC; |
|
| 1596 |
FORCE_RET(); |
|
| 1597 |
} |
|
| 1598 |
|
|
| 1599 |
void op_dmfc0_errorepc (void) |
|
| 1600 |
{
|
|
| 1601 |
T0 = env->CP0_ErrorEPC; |
|
| 1602 |
FORCE_RET(); |
|
| 1603 |
} |
|
| 1604 | 1250 |
#endif /* TARGET_MIPS64 */ |
| 1605 | 1251 |
|
| 1606 | 1252 |
/* MIPS MT functions */ |
Also available in: Unified diff