Revision f0b3f3ae target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 997 | 997 |
tcg_gen_andi_tl(r_tmp, cpu_T[0], almask); \ |
| 998 | 998 |
tcg_gen_brcond_tl(TCG_COND_EQ, r_tmp, tcg_const_tl(0), l1); \ |
| 999 | 999 |
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr)); \ |
| 1000 |
generate_exception(ctx, EXCP_AdES); \ |
|
| 1000 |
generate_exception(ctx, EXCP_AdES); \
|
|
| 1001 | 1001 |
gen_set_label(l1); \ |
| 1002 | 1002 |
tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \ |
| 1003 | 1003 |
tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], r_tmp, l2); \ |
| ... | ... | |
| 2568 | 2568 |
static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
| 2569 | 2569 |
{
|
| 2570 | 2570 |
const char *rn = "invalid"; |
| 2571 |
TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); |
|
| 2572 |
TCGv r_tmp64 = tcg_temp_new(TCG_TYPE_I64); |
|
| 2571 | 2573 |
|
| 2572 | 2574 |
if (sel != 0) |
| 2573 | 2575 |
check_insn(env, ctx, ISA_MIPS32); |
| ... | ... | |
| 2576 | 2578 |
case 0: |
| 2577 | 2579 |
switch (sel) {
|
| 2578 | 2580 |
case 0: |
| 2579 |
gen_op_mfc0_index(); |
|
| 2581 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Index)); |
|
| 2582 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2580 | 2583 |
rn = "Index"; |
| 2581 | 2584 |
break; |
| 2582 | 2585 |
case 1: |
| ... | ... | |
| 2606 | 2609 |
break; |
| 2607 | 2610 |
case 1: |
| 2608 | 2611 |
check_insn(env, ctx, ASE_MT); |
| 2609 |
gen_op_mfc0_vpecontrol(); |
|
| 2612 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEControl)); |
|
| 2613 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2610 | 2614 |
rn = "VPEControl"; |
| 2611 | 2615 |
break; |
| 2612 | 2616 |
case 2: |
| 2613 | 2617 |
check_insn(env, ctx, ASE_MT); |
| 2614 |
gen_op_mfc0_vpeconf0(); |
|
| 2618 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf0)); |
|
| 2619 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2615 | 2620 |
rn = "VPEConf0"; |
| 2616 | 2621 |
break; |
| 2617 | 2622 |
case 3: |
| 2618 | 2623 |
check_insn(env, ctx, ASE_MT); |
| 2619 |
gen_op_mfc0_vpeconf1(); |
|
| 2624 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf1)); |
|
| 2625 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2620 | 2626 |
rn = "VPEConf1"; |
| 2621 | 2627 |
break; |
| 2622 | 2628 |
case 4: |
| 2623 | 2629 |
check_insn(env, ctx, ASE_MT); |
| 2624 |
gen_op_mfc0_yqmask(); |
|
| 2630 |
tcg_gen_ld_i64(r_tmp64, cpu_env, offsetof(CPUState, CP0_YQMask)); |
|
| 2631 |
tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64); |
|
| 2625 | 2632 |
rn = "YQMask"; |
| 2626 | 2633 |
break; |
| 2627 | 2634 |
case 5: |
| 2628 | 2635 |
check_insn(env, ctx, ASE_MT); |
| 2629 |
gen_op_mfc0_vpeschedule(); |
|
| 2636 |
tcg_gen_ld_tl(r_tmp64, cpu_env, offsetof(CPUState, CP0_VPESchedule)); |
|
| 2637 |
tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64); |
|
| 2630 | 2638 |
rn = "VPESchedule"; |
| 2631 | 2639 |
break; |
| 2632 | 2640 |
case 6: |
| 2633 | 2641 |
check_insn(env, ctx, ASE_MT); |
| 2634 |
gen_op_mfc0_vpeschefback(); |
|
| 2642 |
tcg_gen_ld_tl(r_tmp64, cpu_env, offsetof(CPUState, CP0_VPEScheFBack)); |
|
| 2643 |
tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp64); |
|
| 2635 | 2644 |
rn = "VPEScheFBack"; |
| 2636 | 2645 |
break; |
| 2637 | 2646 |
case 7: |
| 2638 | 2647 |
check_insn(env, ctx, ASE_MT); |
| 2639 |
gen_op_mfc0_vpeopt(); |
|
| 2648 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEOpt)); |
|
| 2649 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2640 | 2650 |
rn = "VPEOpt"; |
| 2641 | 2651 |
break; |
| 2642 | 2652 |
default: |
| ... | ... | |
| 2646 | 2656 |
case 2: |
| 2647 | 2657 |
switch (sel) {
|
| 2648 | 2658 |
case 0: |
| 2649 |
gen_op_mfc0_entrylo0(); |
|
| 2659 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0)); |
|
| 2660 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
|
| 2650 | 2661 |
rn = "EntryLo0"; |
| 2651 | 2662 |
break; |
| 2652 | 2663 |
case 1: |
| ... | ... | |
| 2691 | 2702 |
case 3: |
| 2692 | 2703 |
switch (sel) {
|
| 2693 | 2704 |
case 0: |
| 2694 |
gen_op_mfc0_entrylo1(); |
|
| 2705 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1)); |
|
| 2706 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
|
| 2695 | 2707 |
rn = "EntryLo1"; |
| 2696 | 2708 |
break; |
| 2697 | 2709 |
default: |
| ... | ... | |
| 2701 | 2713 |
case 4: |
| 2702 | 2714 |
switch (sel) {
|
| 2703 | 2715 |
case 0: |
| 2704 |
gen_op_mfc0_context(); |
|
| 2716 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context)); |
|
| 2717 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
|
| 2705 | 2718 |
rn = "Context"; |
| 2706 | 2719 |
break; |
| 2707 | 2720 |
case 1: |
| ... | ... | |
| 2715 | 2728 |
case 5: |
| 2716 | 2729 |
switch (sel) {
|
| 2717 | 2730 |
case 0: |
| 2718 |
gen_op_mfc0_pagemask(); |
|
| 2731 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageMask)); |
|
| 2732 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2719 | 2733 |
rn = "PageMask"; |
| 2720 | 2734 |
break; |
| 2721 | 2735 |
case 1: |
| 2722 | 2736 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2723 |
gen_op_mfc0_pagegrain(); |
|
| 2737 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageGrain)); |
|
| 2738 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2724 | 2739 |
rn = "PageGrain"; |
| 2725 | 2740 |
break; |
| 2726 | 2741 |
default: |
| ... | ... | |
| 2730 | 2745 |
case 6: |
| 2731 | 2746 |
switch (sel) {
|
| 2732 | 2747 |
case 0: |
| 2733 |
gen_op_mfc0_wired(); |
|
| 2748 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Wired)); |
|
| 2749 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2734 | 2750 |
rn = "Wired"; |
| 2735 | 2751 |
break; |
| 2736 | 2752 |
case 1: |
| 2737 | 2753 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2738 |
gen_op_mfc0_srsconf0(); |
|
| 2754 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf0)); |
|
| 2755 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2739 | 2756 |
rn = "SRSConf0"; |
| 2740 | 2757 |
break; |
| 2741 | 2758 |
case 2: |
| 2742 | 2759 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2743 |
gen_op_mfc0_srsconf1(); |
|
| 2760 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf1)); |
|
| 2761 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2744 | 2762 |
rn = "SRSConf1"; |
| 2745 | 2763 |
break; |
| 2746 | 2764 |
case 3: |
| 2747 | 2765 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2748 |
gen_op_mfc0_srsconf2(); |
|
| 2766 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf2)); |
|
| 2767 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2749 | 2768 |
rn = "SRSConf2"; |
| 2750 | 2769 |
break; |
| 2751 | 2770 |
case 4: |
| 2752 | 2771 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2753 |
gen_op_mfc0_srsconf3(); |
|
| 2772 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf3)); |
|
| 2773 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2754 | 2774 |
rn = "SRSConf3"; |
| 2755 | 2775 |
break; |
| 2756 | 2776 |
case 5: |
| 2757 | 2777 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2758 |
gen_op_mfc0_srsconf4(); |
|
| 2778 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf4)); |
|
| 2779 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2759 | 2780 |
rn = "SRSConf4"; |
| 2760 | 2781 |
break; |
| 2761 | 2782 |
default: |
| ... | ... | |
| 2766 | 2787 |
switch (sel) {
|
| 2767 | 2788 |
case 0: |
| 2768 | 2789 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2769 |
gen_op_mfc0_hwrena(); |
|
| 2790 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_HWREna)); |
|
| 2791 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2770 | 2792 |
rn = "HWREna"; |
| 2771 | 2793 |
break; |
| 2772 | 2794 |
default: |
| ... | ... | |
| 2776 | 2798 |
case 8: |
| 2777 | 2799 |
switch (sel) {
|
| 2778 | 2800 |
case 0: |
| 2779 |
gen_op_mfc0_badvaddr(); |
|
| 2780 |
rn = "BadVaddr"; |
|
| 2801 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr)); |
|
| 2802 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
|
| 2803 |
rn = "BadVAddr"; |
|
| 2781 | 2804 |
break; |
| 2782 | 2805 |
default: |
| 2783 | 2806 |
goto die; |
| ... | ... | |
| 2797 | 2820 |
case 10: |
| 2798 | 2821 |
switch (sel) {
|
| 2799 | 2822 |
case 0: |
| 2800 |
gen_op_mfc0_entryhi(); |
|
| 2823 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi)); |
|
| 2824 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
|
| 2801 | 2825 |
rn = "EntryHi"; |
| 2802 | 2826 |
break; |
| 2803 | 2827 |
default: |
| ... | ... | |
| 2807 | 2831 |
case 11: |
| 2808 | 2832 |
switch (sel) {
|
| 2809 | 2833 |
case 0: |
| 2810 |
gen_op_mfc0_compare(); |
|
| 2834 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Compare)); |
|
| 2835 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2811 | 2836 |
rn = "Compare"; |
| 2812 | 2837 |
break; |
| 2813 | 2838 |
/* 6,7 are implementation dependent */ |
| ... | ... | |
| 2818 | 2843 |
case 12: |
| 2819 | 2844 |
switch (sel) {
|
| 2820 | 2845 |
case 0: |
| 2821 |
gen_op_mfc0_status(); |
|
| 2846 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status)); |
|
| 2847 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2822 | 2848 |
rn = "Status"; |
| 2823 | 2849 |
break; |
| 2824 | 2850 |
case 1: |
| 2825 | 2851 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2826 |
gen_op_mfc0_intctl(); |
|
| 2852 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_IntCtl)); |
|
| 2853 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2827 | 2854 |
rn = "IntCtl"; |
| 2828 | 2855 |
break; |
| 2829 | 2856 |
case 2: |
| 2830 | 2857 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2831 |
gen_op_mfc0_srsctl(); |
|
| 2858 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl)); |
|
| 2859 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2832 | 2860 |
rn = "SRSCtl"; |
| 2833 | 2861 |
break; |
| 2834 | 2862 |
case 3: |
| 2835 | 2863 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2836 |
gen_op_mfc0_srsmap(); |
|
| 2864 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSMap)); |
|
| 2865 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2837 | 2866 |
rn = "SRSMap"; |
| 2838 | 2867 |
break; |
| 2839 | 2868 |
default: |
| ... | ... | |
| 2843 | 2872 |
case 13: |
| 2844 | 2873 |
switch (sel) {
|
| 2845 | 2874 |
case 0: |
| 2846 |
gen_op_mfc0_cause(); |
|
| 2875 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Cause)); |
|
| 2876 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2847 | 2877 |
rn = "Cause"; |
| 2848 | 2878 |
break; |
| 2849 | 2879 |
default: |
| ... | ... | |
| 2853 | 2883 |
case 14: |
| 2854 | 2884 |
switch (sel) {
|
| 2855 | 2885 |
case 0: |
| 2856 |
gen_op_mfc0_epc(); |
|
| 2886 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC)); |
|
| 2887 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
|
| 2857 | 2888 |
rn = "EPC"; |
| 2858 | 2889 |
break; |
| 2859 | 2890 |
default: |
| ... | ... | |
| 2863 | 2894 |
case 15: |
| 2864 | 2895 |
switch (sel) {
|
| 2865 | 2896 |
case 0: |
| 2866 |
gen_op_mfc0_prid(); |
|
| 2897 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PRid)); |
|
| 2898 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2867 | 2899 |
rn = "PRid"; |
| 2868 | 2900 |
break; |
| 2869 | 2901 |
case 1: |
| 2870 | 2902 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 2871 |
gen_op_mfc0_ebase(); |
|
| 2903 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_EBase)); |
|
| 2904 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2872 | 2905 |
rn = "EBase"; |
| 2873 | 2906 |
break; |
| 2874 | 2907 |
default: |
| ... | ... | |
| 2878 | 2911 |
case 16: |
| 2879 | 2912 |
switch (sel) {
|
| 2880 | 2913 |
case 0: |
| 2881 |
gen_op_mfc0_config0(); |
|
| 2914 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config0)); |
|
| 2915 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2882 | 2916 |
rn = "Config"; |
| 2883 | 2917 |
break; |
| 2884 | 2918 |
case 1: |
| 2885 |
gen_op_mfc0_config1(); |
|
| 2919 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config1)); |
|
| 2920 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2886 | 2921 |
rn = "Config1"; |
| 2887 | 2922 |
break; |
| 2888 | 2923 |
case 2: |
| 2889 |
gen_op_mfc0_config2(); |
|
| 2924 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config2)); |
|
| 2925 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2890 | 2926 |
rn = "Config2"; |
| 2891 | 2927 |
break; |
| 2892 | 2928 |
case 3: |
| 2893 |
gen_op_mfc0_config3(); |
|
| 2929 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config3)); |
|
| 2930 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2894 | 2931 |
rn = "Config3"; |
| 2895 | 2932 |
break; |
| 2896 | 2933 |
/* 4,5 are reserved */ |
| 2897 | 2934 |
/* 6,7 are implementation dependent */ |
| 2898 | 2935 |
case 6: |
| 2899 |
gen_op_mfc0_config6(); |
|
| 2936 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config6)); |
|
| 2937 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2900 | 2938 |
rn = "Config6"; |
| 2901 | 2939 |
break; |
| 2902 | 2940 |
case 7: |
| 2903 |
gen_op_mfc0_config7(); |
|
| 2941 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config7)); |
|
| 2942 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2904 | 2943 |
rn = "Config7"; |
| 2905 | 2944 |
break; |
| 2906 | 2945 |
default: |
| ... | ... | |
| 2942 | 2981 |
case 0: |
| 2943 | 2982 |
#if defined(TARGET_MIPS64) |
| 2944 | 2983 |
check_insn(env, ctx, ISA_MIPS3); |
| 2945 |
gen_op_mfc0_xcontext(); |
|
| 2984 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext)); |
|
| 2985 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
|
| 2946 | 2986 |
rn = "XContext"; |
| 2947 | 2987 |
break; |
| 2948 | 2988 |
#endif |
| ... | ... | |
| 2954 | 2994 |
/* Officially reserved, but sel 0 is used for R1x000 framemask */ |
| 2955 | 2995 |
switch (sel) {
|
| 2956 | 2996 |
case 0: |
| 2957 |
gen_op_mfc0_framemask(); |
|
| 2997 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Framemask)); |
|
| 2998 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 2958 | 2999 |
rn = "Framemask"; |
| 2959 | 3000 |
break; |
| 2960 | 3001 |
default: |
| ... | ... | |
| 2994 | 3035 |
case 24: |
| 2995 | 3036 |
switch (sel) {
|
| 2996 | 3037 |
case 0: |
| 2997 |
gen_op_mfc0_depc(); /* EJTAG support */ |
|
| 3038 |
/* EJTAG support */ |
|
| 3039 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC)); |
|
| 3040 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
|
| 2998 | 3041 |
rn = "DEPC"; |
| 2999 | 3042 |
break; |
| 3000 | 3043 |
default: |
| ... | ... | |
| 3004 | 3047 |
case 25: |
| 3005 | 3048 |
switch (sel) {
|
| 3006 | 3049 |
case 0: |
| 3007 |
gen_op_mfc0_performance0(); |
|
| 3050 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Performance0)); |
|
| 3051 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3008 | 3052 |
rn = "Performance0"; |
| 3009 | 3053 |
break; |
| 3010 | 3054 |
case 1: |
| ... | ... | |
| 3058 | 3102 |
case 2: |
| 3059 | 3103 |
case 4: |
| 3060 | 3104 |
case 6: |
| 3061 |
gen_op_mfc0_taglo(); |
|
| 3105 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagLo)); |
|
| 3106 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3062 | 3107 |
rn = "TagLo"; |
| 3063 | 3108 |
break; |
| 3064 | 3109 |
case 1: |
| 3065 | 3110 |
case 3: |
| 3066 | 3111 |
case 5: |
| 3067 | 3112 |
case 7: |
| 3068 |
gen_op_mfc0_datalo(); |
|
| 3113 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataLo)); |
|
| 3114 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3069 | 3115 |
rn = "DataLo"; |
| 3070 | 3116 |
break; |
| 3071 | 3117 |
default: |
| ... | ... | |
| 3078 | 3124 |
case 2: |
| 3079 | 3125 |
case 4: |
| 3080 | 3126 |
case 6: |
| 3081 |
gen_op_mfc0_taghi(); |
|
| 3127 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagHi)); |
|
| 3128 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3082 | 3129 |
rn = "TagHi"; |
| 3083 | 3130 |
break; |
| 3084 | 3131 |
case 1: |
| 3085 | 3132 |
case 3: |
| 3086 | 3133 |
case 5: |
| 3087 | 3134 |
case 7: |
| 3088 |
gen_op_mfc0_datahi(); |
|
| 3135 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataHi)); |
|
| 3136 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3089 | 3137 |
rn = "DataHi"; |
| 3090 | 3138 |
break; |
| 3091 | 3139 |
default: |
| ... | ... | |
| 3095 | 3143 |
case 30: |
| 3096 | 3144 |
switch (sel) {
|
| 3097 | 3145 |
case 0: |
| 3098 |
gen_op_mfc0_errorepc(); |
|
| 3146 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC)); |
|
| 3147 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
|
| 3099 | 3148 |
rn = "ErrorEPC"; |
| 3100 | 3149 |
break; |
| 3101 | 3150 |
default: |
| ... | ... | |
| 3105 | 3154 |
case 31: |
| 3106 | 3155 |
switch (sel) {
|
| 3107 | 3156 |
case 0: |
| 3108 |
gen_op_mfc0_desave(); /* EJTAG support */ |
|
| 3157 |
/* EJTAG support */ |
|
| 3158 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DESAVE)); |
|
| 3159 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3109 | 3160 |
rn = "DESAVE"; |
| 3110 | 3161 |
break; |
| 3111 | 3162 |
default: |
| ... | ... | |
| 3343 | 3394 |
break; |
| 3344 | 3395 |
case 8: |
| 3345 | 3396 |
/* ignored */ |
| 3346 |
rn = "BadVaddr";
|
|
| 3397 |
rn = "BadVAddr";
|
|
| 3347 | 3398 |
break; |
| 3348 | 3399 |
case 9: |
| 3349 | 3400 |
switch (sel) {
|
| ... | ... | |
| 3736 | 3787 |
static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
| 3737 | 3788 |
{
|
| 3738 | 3789 |
const char *rn = "invalid"; |
| 3790 |
TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); |
|
| 3739 | 3791 |
|
| 3740 | 3792 |
if (sel != 0) |
| 3741 | 3793 |
check_insn(env, ctx, ISA_MIPS64); |
| ... | ... | |
| 3744 | 3796 |
case 0: |
| 3745 | 3797 |
switch (sel) {
|
| 3746 | 3798 |
case 0: |
| 3747 |
gen_op_mfc0_index(); |
|
| 3799 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Index)); |
|
| 3800 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3748 | 3801 |
rn = "Index"; |
| 3749 | 3802 |
break; |
| 3750 | 3803 |
case 1: |
| ... | ... | |
| 3774 | 3827 |
break; |
| 3775 | 3828 |
case 1: |
| 3776 | 3829 |
check_insn(env, ctx, ASE_MT); |
| 3777 |
gen_op_mfc0_vpecontrol(); |
|
| 3830 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEControl)); |
|
| 3831 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3778 | 3832 |
rn = "VPEControl"; |
| 3779 | 3833 |
break; |
| 3780 | 3834 |
case 2: |
| 3781 | 3835 |
check_insn(env, ctx, ASE_MT); |
| 3782 |
gen_op_mfc0_vpeconf0(); |
|
| 3836 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf0)); |
|
| 3837 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3783 | 3838 |
rn = "VPEConf0"; |
| 3784 | 3839 |
break; |
| 3785 | 3840 |
case 3: |
| 3786 | 3841 |
check_insn(env, ctx, ASE_MT); |
| 3787 |
gen_op_mfc0_vpeconf1(); |
|
| 3842 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEConf1)); |
|
| 3843 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3788 | 3844 |
rn = "VPEConf1"; |
| 3789 | 3845 |
break; |
| 3790 | 3846 |
case 4: |
| 3791 | 3847 |
check_insn(env, ctx, ASE_MT); |
| 3792 |
gen_op_dmfc0_yqmask();
|
|
| 3848 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_YQMask));
|
|
| 3793 | 3849 |
rn = "YQMask"; |
| 3794 | 3850 |
break; |
| 3795 | 3851 |
case 5: |
| 3796 | 3852 |
check_insn(env, ctx, ASE_MT); |
| 3797 |
gen_op_dmfc0_vpeschedule();
|
|
| 3853 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule));
|
|
| 3798 | 3854 |
rn = "VPESchedule"; |
| 3799 | 3855 |
break; |
| 3800 | 3856 |
case 6: |
| 3801 | 3857 |
check_insn(env, ctx, ASE_MT); |
| 3802 |
gen_op_dmfc0_vpeschefback();
|
|
| 3858 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
|
|
| 3803 | 3859 |
rn = "VPEScheFBack"; |
| 3804 | 3860 |
break; |
| 3805 | 3861 |
case 7: |
| 3806 | 3862 |
check_insn(env, ctx, ASE_MT); |
| 3807 |
gen_op_mfc0_vpeopt(); |
|
| 3863 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_VPEOpt)); |
|
| 3864 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3808 | 3865 |
rn = "VPEOpt"; |
| 3809 | 3866 |
break; |
| 3810 | 3867 |
default: |
| ... | ... | |
| 3814 | 3871 |
case 2: |
| 3815 | 3872 |
switch (sel) {
|
| 3816 | 3873 |
case 0: |
| 3817 |
gen_op_dmfc0_entrylo0();
|
|
| 3874 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo0));
|
|
| 3818 | 3875 |
rn = "EntryLo0"; |
| 3819 | 3876 |
break; |
| 3820 | 3877 |
case 1: |
| ... | ... | |
| 3859 | 3916 |
case 3: |
| 3860 | 3917 |
switch (sel) {
|
| 3861 | 3918 |
case 0: |
| 3862 |
gen_op_dmfc0_entrylo1();
|
|
| 3919 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryLo1));
|
|
| 3863 | 3920 |
rn = "EntryLo1"; |
| 3864 | 3921 |
break; |
| 3865 | 3922 |
default: |
| ... | ... | |
| 3869 | 3926 |
case 4: |
| 3870 | 3927 |
switch (sel) {
|
| 3871 | 3928 |
case 0: |
| 3872 |
gen_op_dmfc0_context();
|
|
| 3929 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_Context));
|
|
| 3873 | 3930 |
rn = "Context"; |
| 3874 | 3931 |
break; |
| 3875 | 3932 |
case 1: |
| ... | ... | |
| 3883 | 3940 |
case 5: |
| 3884 | 3941 |
switch (sel) {
|
| 3885 | 3942 |
case 0: |
| 3886 |
gen_op_mfc0_pagemask(); |
|
| 3943 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageMask)); |
|
| 3944 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3887 | 3945 |
rn = "PageMask"; |
| 3888 | 3946 |
break; |
| 3889 | 3947 |
case 1: |
| 3890 | 3948 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3891 |
gen_op_mfc0_pagegrain(); |
|
| 3949 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PageGrain)); |
|
| 3950 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3892 | 3951 |
rn = "PageGrain"; |
| 3893 | 3952 |
break; |
| 3894 | 3953 |
default: |
| ... | ... | |
| 3898 | 3957 |
case 6: |
| 3899 | 3958 |
switch (sel) {
|
| 3900 | 3959 |
case 0: |
| 3901 |
gen_op_mfc0_wired(); |
|
| 3960 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Wired)); |
|
| 3961 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3902 | 3962 |
rn = "Wired"; |
| 3903 | 3963 |
break; |
| 3904 | 3964 |
case 1: |
| 3905 | 3965 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3906 |
gen_op_mfc0_srsconf0(); |
|
| 3966 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf0)); |
|
| 3967 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3907 | 3968 |
rn = "SRSConf0"; |
| 3908 | 3969 |
break; |
| 3909 | 3970 |
case 2: |
| 3910 | 3971 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3911 |
gen_op_mfc0_srsconf1(); |
|
| 3972 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf1)); |
|
| 3973 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3912 | 3974 |
rn = "SRSConf1"; |
| 3913 | 3975 |
break; |
| 3914 | 3976 |
case 3: |
| 3915 | 3977 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3916 |
gen_op_mfc0_srsconf2(); |
|
| 3978 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf2)); |
|
| 3979 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3917 | 3980 |
rn = "SRSConf2"; |
| 3918 | 3981 |
break; |
| 3919 | 3982 |
case 4: |
| 3920 | 3983 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3921 |
gen_op_mfc0_srsconf3(); |
|
| 3984 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf3)); |
|
| 3985 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3922 | 3986 |
rn = "SRSConf3"; |
| 3923 | 3987 |
break; |
| 3924 | 3988 |
case 5: |
| 3925 | 3989 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3926 |
gen_op_mfc0_srsconf4(); |
|
| 3990 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSConf4)); |
|
| 3991 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3927 | 3992 |
rn = "SRSConf4"; |
| 3928 | 3993 |
break; |
| 3929 | 3994 |
default: |
| ... | ... | |
| 3934 | 3999 |
switch (sel) {
|
| 3935 | 4000 |
case 0: |
| 3936 | 4001 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3937 |
gen_op_mfc0_hwrena(); |
|
| 4002 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_HWREna)); |
|
| 4003 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3938 | 4004 |
rn = "HWREna"; |
| 3939 | 4005 |
break; |
| 3940 | 4006 |
default: |
| ... | ... | |
| 3944 | 4010 |
case 8: |
| 3945 | 4011 |
switch (sel) {
|
| 3946 | 4012 |
case 0: |
| 3947 |
gen_op_dmfc0_badvaddr();
|
|
| 3948 |
rn = "BadVaddr";
|
|
| 4013 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr));
|
|
| 4014 |
rn = "BadVAddr";
|
|
| 3949 | 4015 |
break; |
| 3950 | 4016 |
default: |
| 3951 | 4017 |
goto die; |
| ... | ... | |
| 3965 | 4031 |
case 10: |
| 3966 | 4032 |
switch (sel) {
|
| 3967 | 4033 |
case 0: |
| 3968 |
gen_op_dmfc0_entryhi();
|
|
| 4034 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EntryHi));
|
|
| 3969 | 4035 |
rn = "EntryHi"; |
| 3970 | 4036 |
break; |
| 3971 | 4037 |
default: |
| ... | ... | |
| 3975 | 4041 |
case 11: |
| 3976 | 4042 |
switch (sel) {
|
| 3977 | 4043 |
case 0: |
| 3978 |
gen_op_mfc0_compare(); |
|
| 4044 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Compare)); |
|
| 4045 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3979 | 4046 |
rn = "Compare"; |
| 3980 | 4047 |
break; |
| 3981 | 4048 |
/* 6,7 are implementation dependent */ |
| ... | ... | |
| 3986 | 4053 |
case 12: |
| 3987 | 4054 |
switch (sel) {
|
| 3988 | 4055 |
case 0: |
| 3989 |
gen_op_mfc0_status(); |
|
| 4056 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status)); |
|
| 4057 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3990 | 4058 |
rn = "Status"; |
| 3991 | 4059 |
break; |
| 3992 | 4060 |
case 1: |
| 3993 | 4061 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3994 |
gen_op_mfc0_intctl(); |
|
| 4062 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_IntCtl)); |
|
| 4063 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 3995 | 4064 |
rn = "IntCtl"; |
| 3996 | 4065 |
break; |
| 3997 | 4066 |
case 2: |
| 3998 | 4067 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3999 |
gen_op_mfc0_srsctl(); |
|
| 4068 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl)); |
|
| 4069 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4000 | 4070 |
rn = "SRSCtl"; |
| 4001 | 4071 |
break; |
| 4002 | 4072 |
case 3: |
| 4003 | 4073 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 4004 |
gen_op_mfc0_srsmap(); |
|
| 4074 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSMap)); |
|
| 4075 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4005 | 4076 |
rn = "SRSMap"; |
| 4006 | 4077 |
break; |
| 4007 | 4078 |
default: |
| ... | ... | |
| 4011 | 4082 |
case 13: |
| 4012 | 4083 |
switch (sel) {
|
| 4013 | 4084 |
case 0: |
| 4014 |
gen_op_mfc0_cause(); |
|
| 4085 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Cause)); |
|
| 4086 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4015 | 4087 |
rn = "Cause"; |
| 4016 | 4088 |
break; |
| 4017 | 4089 |
default: |
| ... | ... | |
| 4021 | 4093 |
case 14: |
| 4022 | 4094 |
switch (sel) {
|
| 4023 | 4095 |
case 0: |
| 4024 |
gen_op_dmfc0_epc();
|
|
| 4096 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
|
|
| 4025 | 4097 |
rn = "EPC"; |
| 4026 | 4098 |
break; |
| 4027 | 4099 |
default: |
| ... | ... | |
| 4031 | 4103 |
case 15: |
| 4032 | 4104 |
switch (sel) {
|
| 4033 | 4105 |
case 0: |
| 4034 |
gen_op_mfc0_prid(); |
|
| 4106 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_PRid)); |
|
| 4107 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4035 | 4108 |
rn = "PRid"; |
| 4036 | 4109 |
break; |
| 4037 | 4110 |
case 1: |
| 4038 | 4111 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 4039 |
gen_op_mfc0_ebase(); |
|
| 4112 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_EBase)); |
|
| 4113 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4040 | 4114 |
rn = "EBase"; |
| 4041 | 4115 |
break; |
| 4042 | 4116 |
default: |
| ... | ... | |
| 4046 | 4120 |
case 16: |
| 4047 | 4121 |
switch (sel) {
|
| 4048 | 4122 |
case 0: |
| 4049 |
gen_op_mfc0_config0(); |
|
| 4123 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config0)); |
|
| 4124 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4050 | 4125 |
rn = "Config"; |
| 4051 | 4126 |
break; |
| 4052 | 4127 |
case 1: |
| 4053 |
gen_op_mfc0_config1(); |
|
| 4128 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config1)); |
|
| 4129 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4054 | 4130 |
rn = "Config1"; |
| 4055 | 4131 |
break; |
| 4056 | 4132 |
case 2: |
| 4057 |
gen_op_mfc0_config2(); |
|
| 4133 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config2)); |
|
| 4134 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4058 | 4135 |
rn = "Config2"; |
| 4059 | 4136 |
break; |
| 4060 | 4137 |
case 3: |
| 4061 |
gen_op_mfc0_config3(); |
|
| 4138 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config3)); |
|
| 4139 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4062 | 4140 |
rn = "Config3"; |
| 4063 | 4141 |
break; |
| 4064 | 4142 |
/* 6,7 are implementation dependent */ |
| 4143 |
case 6: |
|
| 4144 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config6)); |
|
| 4145 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4146 |
rn = "Config6"; |
|
| 4147 |
break; |
|
| 4148 |
case 7: |
|
| 4149 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Config7)); |
|
| 4150 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4151 |
rn = "Config7"; |
|
| 4152 |
break; |
|
| 4065 | 4153 |
default: |
| 4066 | 4154 |
goto die; |
| 4067 | 4155 |
} |
| ... | ... | |
| 4100 | 4188 |
switch (sel) {
|
| 4101 | 4189 |
case 0: |
| 4102 | 4190 |
check_insn(env, ctx, ISA_MIPS3); |
| 4103 |
gen_op_dmfc0_xcontext();
|
|
| 4191 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_XContext));
|
|
| 4104 | 4192 |
rn = "XContext"; |
| 4105 | 4193 |
break; |
| 4106 | 4194 |
default: |
| ... | ... | |
| 4111 | 4199 |
/* Officially reserved, but sel 0 is used for R1x000 framemask */ |
| 4112 | 4200 |
switch (sel) {
|
| 4113 | 4201 |
case 0: |
| 4114 |
gen_op_mfc0_framemask(); |
|
| 4202 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Framemask)); |
|
| 4203 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4115 | 4204 |
rn = "Framemask"; |
| 4116 | 4205 |
break; |
| 4117 | 4206 |
default: |
| ... | ... | |
| 4151 | 4240 |
case 24: |
| 4152 | 4241 |
switch (sel) {
|
| 4153 | 4242 |
case 0: |
| 4154 |
gen_op_dmfc0_depc(); /* EJTAG support */ |
|
| 4243 |
/* EJTAG support */ |
|
| 4244 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC)); |
|
| 4155 | 4245 |
rn = "DEPC"; |
| 4156 | 4246 |
break; |
| 4157 | 4247 |
default: |
| ... | ... | |
| 4161 | 4251 |
case 25: |
| 4162 | 4252 |
switch (sel) {
|
| 4163 | 4253 |
case 0: |
| 4164 |
gen_op_mfc0_performance0(); |
|
| 4254 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Performance0)); |
|
| 4255 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4165 | 4256 |
rn = "Performance0"; |
| 4166 | 4257 |
break; |
| 4167 | 4258 |
case 1: |
| ... | ... | |
| 4215 | 4306 |
case 2: |
| 4216 | 4307 |
case 4: |
| 4217 | 4308 |
case 6: |
| 4218 |
gen_op_mfc0_taglo(); |
|
| 4309 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagLo)); |
|
| 4310 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4219 | 4311 |
rn = "TagLo"; |
| 4220 | 4312 |
break; |
| 4221 | 4313 |
case 1: |
| 4222 | 4314 |
case 3: |
| 4223 | 4315 |
case 5: |
| 4224 | 4316 |
case 7: |
| 4225 |
gen_op_mfc0_datalo(); |
|
| 4317 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataLo)); |
|
| 4318 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4226 | 4319 |
rn = "DataLo"; |
| 4227 | 4320 |
break; |
| 4228 | 4321 |
default: |
| ... | ... | |
| 4235 | 4328 |
case 2: |
| 4236 | 4329 |
case 4: |
| 4237 | 4330 |
case 6: |
| 4238 |
gen_op_mfc0_taghi(); |
|
| 4331 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_TagHi)); |
|
| 4332 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4239 | 4333 |
rn = "TagHi"; |
| 4240 | 4334 |
break; |
| 4241 | 4335 |
case 1: |
| 4242 | 4336 |
case 3: |
| 4243 | 4337 |
case 5: |
| 4244 | 4338 |
case 7: |
| 4245 |
gen_op_mfc0_datahi(); |
|
| 4339 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DataHi)); |
|
| 4340 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4246 | 4341 |
rn = "DataHi"; |
| 4247 | 4342 |
break; |
| 4248 | 4343 |
default: |
| ... | ... | |
| 4252 | 4347 |
case 30: |
| 4253 | 4348 |
switch (sel) {
|
| 4254 | 4349 |
case 0: |
| 4255 |
gen_op_dmfc0_errorepc();
|
|
| 4350 |
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
|
|
| 4256 | 4351 |
rn = "ErrorEPC"; |
| 4257 | 4352 |
break; |
| 4258 | 4353 |
default: |
| ... | ... | |
| 4262 | 4357 |
case 31: |
| 4263 | 4358 |
switch (sel) {
|
| 4264 | 4359 |
case 0: |
| 4265 |
gen_op_mfc0_desave(); /* EJTAG support */ |
|
| 4360 |
/* EJTAG support */ |
|
| 4361 |
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_DESAVE)); |
|
| 4362 |
tcg_gen_ext_i32_tl(cpu_T[0], r_tmp); |
|
| 4266 | 4363 |
rn = "DESAVE"; |
| 4267 | 4364 |
break; |
| 4268 | 4365 |
default: |
| ... | ... | |
| 4500 | 4597 |
break; |
| 4501 | 4598 |
case 8: |
| 4502 | 4599 |
/* ignored */ |
| 4503 |
rn = "BadVaddr";
|
|
| 4600 |
rn = "BadVAddr";
|
|
| 4504 | 4601 |
break; |
| 4505 | 4602 |
case 9: |
| 4506 | 4603 |
switch (sel) {
|
Also available in: Unified diff