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/*
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* QEMU model of Xilinx AXI-Ethernet.
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*
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* Copyright (c) 2011 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h" |
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#include "qemu/log.h" |
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#include "net/net.h" |
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#include "net/checksum.h" |
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#include "qapi/qmp/qerror.h" |
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#include "hw/stream.h" |
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#define DPHY(x)
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#define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" |
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#define XILINX_AXI_ENET(obj) \
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OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET) |
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|
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/* Advertisement control register. */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ |
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ |
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ |
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ |
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struct PHY {
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uint32_t regs[32];
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int link;
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|
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unsigned int (*read)(struct PHY *phy, unsigned int req); |
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void (*write)(struct PHY *phy, unsigned int req, |
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unsigned int data); |
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}; |
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|
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static unsigned int tdk_read(struct PHY *phy, unsigned int req) |
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{ |
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int regnum;
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unsigned r = 0; |
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regnum = req & 0x1f;
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switch (regnum) {
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case 1: |
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if (!phy->link) {
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break;
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} |
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/* MR1. */
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/* Speeds and modes. */
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r |= (1 << 13) | (1 << 14); |
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r |= (1 << 11) | (1 << 12); |
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r |= (1 << 5); /* Autoneg complete. */ |
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r |= (1 << 3); /* Autoneg able. */ |
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r |= (1 << 2); /* link. */ |
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r |= (1 << 1); /* link. */ |
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break;
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case 5: |
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/* Link partner ability.
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We are kind; always agree with whatever best mode
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the guest advertises. */
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r = 1 << 14; /* Success. */ |
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/* Copy advertised modes. */
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r |= phy->regs[4] & (15 << 5); |
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/* Autoneg support. */
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r |= 1;
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break;
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case 17: |
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/* Marvel PHY on many xilinx boards. */
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r = 0x8000; /* 1000Mb */ |
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break;
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case 18: |
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{ |
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/* Diagnostics reg. */
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int duplex = 0; |
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int speed_100 = 0; |
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|
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if (!phy->link) {
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break;
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} |
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/* Are we advertising 100 half or 100 duplex ? */
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speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
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speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
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/* Are we advertising 10 duplex or 100 duplex ? */
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duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
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duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
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r = (speed_100 << 10) | (duplex << 11); |
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} |
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break;
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default:
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r = phy->regs[regnum]; |
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break;
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} |
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DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
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return r;
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} |
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static void |
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tdk_write(struct PHY *phy, unsigned int req, unsigned int data) |
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{ |
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int regnum;
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regnum = req & 0x1f;
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DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
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switch (regnum) {
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default:
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phy->regs[regnum] = data; |
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break;
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} |
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} |
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static void |
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tdk_init(struct PHY *phy)
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{ |
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phy->regs[0] = 0x3100; |
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/* PHY Id. */
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phy->regs[2] = 0x0300; |
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phy->regs[3] = 0xe400; |
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/* Autonegotiation advertisement reg. */
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phy->regs[4] = 0x01E1; |
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phy->link = 1;
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phy->read = tdk_read; |
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phy->write = tdk_write; |
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} |
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struct MDIOBus {
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/* bus. */
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int mdc;
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int mdio;
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/* decoder. */
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enum {
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PREAMBLE, |
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SOF, |
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OPC, |
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ADDR, |
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REQ, |
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TURNAROUND, |
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DATA |
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} state; |
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unsigned int drive; |
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unsigned int cnt; |
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unsigned int addr; |
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unsigned int opc; |
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unsigned int req; |
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unsigned int data; |
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struct PHY *devs[32]; |
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}; |
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static void |
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mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) |
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{ |
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bus->devs[addr & 0x1f] = phy;
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} |
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#ifdef USE_THIS_DEAD_CODE
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static void |
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mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) |
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{ |
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bus->devs[addr & 0x1f] = NULL; |
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} |
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#endif
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static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, |
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unsigned int reg) |
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{ |
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struct PHY *phy;
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uint16_t data; |
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phy = bus->devs[addr]; |
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if (phy && phy->read) {
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data = phy->read(phy, reg); |
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} else {
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data = 0xffff;
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} |
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DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
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return data;
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} |
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static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, |
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unsigned int reg, uint16_t data) |
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{ |
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struct PHY *phy;
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DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
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phy = bus->devs[addr]; |
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if (phy && phy->write) {
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phy->write(phy, reg, data); |
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} |
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} |
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#define DENET(x)
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#define R_RAF (0x000 / 4) |
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enum {
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RAF_MCAST_REJ = (1 << 1), |
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RAF_BCAST_REJ = (1 << 2), |
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RAF_EMCF_EN = (1 << 12), |
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RAF_NEWFUNC_EN = (1 << 11) |
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}; |
226 |
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#define R_IS (0x00C / 4) |
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enum {
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IS_HARD_ACCESS_COMPLETE = 1,
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IS_AUTONEG = (1 << 1), |
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IS_RX_COMPLETE = (1 << 2), |
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IS_RX_REJECT = (1 << 3), |
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IS_TX_COMPLETE = (1 << 5), |
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IS_RX_DCM_LOCK = (1 << 6), |
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IS_MGM_RDY = (1 << 7), |
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IS_PHY_RST_DONE = (1 << 8), |
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}; |
238 |
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#define R_IP (0x010 / 4) |
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#define R_IE (0x014 / 4) |
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#define R_UAWL (0x020 / 4) |
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#define R_UAWU (0x024 / 4) |
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#define R_PPST (0x030 / 4) |
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enum {
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PPST_LINKSTATUS = (1 << 0), |
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PPST_PHY_LINKSTATUS = (1 << 7), |
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}; |
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#define R_STATS_RX_BYTESL (0x200 / 4) |
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#define R_STATS_RX_BYTESH (0x204 / 4) |
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#define R_STATS_TX_BYTESL (0x208 / 4) |
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#define R_STATS_TX_BYTESH (0x20C / 4) |
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#define R_STATS_RXL (0x290 / 4) |
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#define R_STATS_RXH (0x294 / 4) |
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#define R_STATS_RX_BCASTL (0x2a0 / 4) |
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#define R_STATS_RX_BCASTH (0x2a4 / 4) |
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#define R_STATS_RX_MCASTL (0x2a8 / 4) |
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#define R_STATS_RX_MCASTH (0x2ac / 4) |
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#define R_RCW0 (0x400 / 4) |
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#define R_RCW1 (0x404 / 4) |
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enum {
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RCW1_VLAN = (1 << 27), |
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RCW1_RX = (1 << 28), |
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RCW1_FCS = (1 << 29), |
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RCW1_JUM = (1 << 30), |
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RCW1_RST = (1 << 31), |
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}; |
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|
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#define R_TC (0x408 / 4) |
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enum {
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TC_VLAN = (1 << 27), |
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TC_TX = (1 << 28), |
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TC_FCS = (1 << 29), |
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TC_JUM = (1 << 30), |
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TC_RST = (1 << 31), |
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}; |
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#define R_EMMC (0x410 / 4) |
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enum {
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EMMC_LINKSPEED_10MB = (0 << 30), |
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EMMC_LINKSPEED_100MB = (1 << 30), |
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EMMC_LINKSPEED_1000MB = (2 << 30), |
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}; |
285 |
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#define R_PHYC (0x414 / 4) |
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#define R_MC (0x500 / 4) |
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#define MC_EN (1 << 6) |
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|
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#define R_MCR (0x504 / 4) |
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#define R_MWD (0x508 / 4) |
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#define R_MRD (0x50c / 4) |
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#define R_MIS (0x600 / 4) |
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#define R_MIP (0x620 / 4) |
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#define R_MIE (0x640 / 4) |
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#define R_MIC (0x640 / 4) |
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|
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#define R_UAW0 (0x700 / 4) |
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#define R_UAW1 (0x704 / 4) |
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#define R_FMI (0x708 / 4) |
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#define R_AF0 (0x710 / 4) |
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#define R_AF1 (0x714 / 4) |
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#define R_MAX (0x34 / 4) |
305 |
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/* Indirect registers. */
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struct TEMAC {
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struct MDIOBus mdio_bus;
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struct PHY phy;
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void *parent;
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}; |
313 |
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typedef struct XilinxAXIEnet XilinxAXIEnet; |
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struct XilinxAXIEnet {
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SysBusDevice busdev; |
318 |
MemoryRegion iomem; |
319 |
qemu_irq irq; |
320 |
StreamSlave *tx_dev; |
321 |
NICState *nic; |
322 |
NICConf conf; |
323 |
|
324 |
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uint32_t c_rxmem; |
326 |
uint32_t c_txmem; |
327 |
uint32_t c_phyaddr; |
328 |
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struct TEMAC TEMAC;
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|
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/* MII regs. */
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union {
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uint32_t regs[4];
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struct {
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uint32_t mc; |
336 |
uint32_t mcr; |
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uint32_t mwd; |
338 |
uint32_t mrd; |
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}; |
340 |
} mii; |
341 |
|
342 |
struct {
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uint64_t rx_bytes; |
344 |
uint64_t tx_bytes; |
345 |
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uint64_t rx; |
347 |
uint64_t rx_bcast; |
348 |
uint64_t rx_mcast; |
349 |
} stats; |
350 |
|
351 |
/* Receive configuration words. */
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352 |
uint32_t rcw[2];
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/* Transmit config. */
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uint32_t tc; |
355 |
uint32_t emmc; |
356 |
uint32_t phyc; |
357 |
|
358 |
/* Unicast Address Word. */
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359 |
uint32_t uaw[2];
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360 |
/* Unicast address filter used with extended mcast. */
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361 |
uint32_t ext_uaw[2];
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362 |
uint32_t fmi; |
363 |
|
364 |
uint32_t regs[R_MAX]; |
365 |
|
366 |
/* Multicast filter addrs. */
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367 |
uint32_t maddr[4][2]; |
368 |
/* 32K x 1 lookup filter. */
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369 |
uint32_t ext_mtable[1024];
|
370 |
|
371 |
|
372 |
uint8_t *rxmem; |
373 |
}; |
374 |
|
375 |
static void axienet_rx_reset(XilinxAXIEnet *s) |
376 |
{ |
377 |
s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
|
378 |
} |
379 |
|
380 |
static void axienet_tx_reset(XilinxAXIEnet *s) |
381 |
{ |
382 |
s->tc = TC_JUM | TC_TX | TC_VLAN; |
383 |
} |
384 |
|
385 |
static inline int axienet_rx_resetting(XilinxAXIEnet *s) |
386 |
{ |
387 |
return s->rcw[1] & RCW1_RST; |
388 |
} |
389 |
|
390 |
static inline int axienet_rx_enabled(XilinxAXIEnet *s) |
391 |
{ |
392 |
return s->rcw[1] & RCW1_RX; |
393 |
} |
394 |
|
395 |
static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) |
396 |
{ |
397 |
return !!(s->regs[R_RAF] & RAF_EMCF_EN);
|
398 |
} |
399 |
|
400 |
static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) |
401 |
{ |
402 |
return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
|
403 |
} |
404 |
|
405 |
static void axienet_reset(XilinxAXIEnet *s) |
406 |
{ |
407 |
axienet_rx_reset(s); |
408 |
axienet_tx_reset(s); |
409 |
|
410 |
s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; |
411 |
s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; |
412 |
|
413 |
s->emmc = EMMC_LINKSPEED_100MB; |
414 |
} |
415 |
|
416 |
static void enet_update_irq(XilinxAXIEnet *s) |
417 |
{ |
418 |
s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; |
419 |
qemu_set_irq(s->irq, !!s->regs[R_IP]); |
420 |
} |
421 |
|
422 |
static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) |
423 |
{ |
424 |
XilinxAXIEnet *s = opaque; |
425 |
uint32_t r = 0;
|
426 |
addr >>= 2;
|
427 |
|
428 |
switch (addr) {
|
429 |
case R_RCW0:
|
430 |
case R_RCW1:
|
431 |
r = s->rcw[addr & 1];
|
432 |
break;
|
433 |
|
434 |
case R_TC:
|
435 |
r = s->tc; |
436 |
break;
|
437 |
|
438 |
case R_EMMC:
|
439 |
r = s->emmc; |
440 |
break;
|
441 |
|
442 |
case R_PHYC:
|
443 |
r = s->phyc; |
444 |
break;
|
445 |
|
446 |
case R_MCR:
|
447 |
r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ |
448 |
break;
|
449 |
|
450 |
case R_STATS_RX_BYTESL:
|
451 |
case R_STATS_RX_BYTESH:
|
452 |
r = s->stats.rx_bytes >> (32 * (addr & 1)); |
453 |
break;
|
454 |
|
455 |
case R_STATS_TX_BYTESL:
|
456 |
case R_STATS_TX_BYTESH:
|
457 |
r = s->stats.tx_bytes >> (32 * (addr & 1)); |
458 |
break;
|
459 |
|
460 |
case R_STATS_RXL:
|
461 |
case R_STATS_RXH:
|
462 |
r = s->stats.rx >> (32 * (addr & 1)); |
463 |
break;
|
464 |
case R_STATS_RX_BCASTL:
|
465 |
case R_STATS_RX_BCASTH:
|
466 |
r = s->stats.rx_bcast >> (32 * (addr & 1)); |
467 |
break;
|
468 |
case R_STATS_RX_MCASTL:
|
469 |
case R_STATS_RX_MCASTH:
|
470 |
r = s->stats.rx_mcast >> (32 * (addr & 1)); |
471 |
break;
|
472 |
|
473 |
case R_MC:
|
474 |
case R_MWD:
|
475 |
case R_MRD:
|
476 |
r = s->mii.regs[addr & 3];
|
477 |
break;
|
478 |
|
479 |
case R_UAW0:
|
480 |
case R_UAW1:
|
481 |
r = s->uaw[addr & 1];
|
482 |
break;
|
483 |
|
484 |
case R_UAWU:
|
485 |
case R_UAWL:
|
486 |
r = s->ext_uaw[addr & 1];
|
487 |
break;
|
488 |
|
489 |
case R_FMI:
|
490 |
r = s->fmi; |
491 |
break;
|
492 |
|
493 |
case R_AF0:
|
494 |
case R_AF1:
|
495 |
r = s->maddr[s->fmi & 3][addr & 1]; |
496 |
break;
|
497 |
|
498 |
case 0x8000 ... 0x83ff: |
499 |
r = s->ext_mtable[addr - 0x8000];
|
500 |
break;
|
501 |
|
502 |
default:
|
503 |
if (addr < ARRAY_SIZE(s->regs)) {
|
504 |
r = s->regs[addr]; |
505 |
} |
506 |
DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", |
507 |
__func__, addr * 4, r));
|
508 |
break;
|
509 |
} |
510 |
return r;
|
511 |
} |
512 |
|
513 |
static void enet_write(void *opaque, hwaddr addr, |
514 |
uint64_t value, unsigned size)
|
515 |
{ |
516 |
XilinxAXIEnet *s = opaque; |
517 |
struct TEMAC *t = &s->TEMAC;
|
518 |
|
519 |
addr >>= 2;
|
520 |
switch (addr) {
|
521 |
case R_RCW0:
|
522 |
case R_RCW1:
|
523 |
s->rcw[addr & 1] = value;
|
524 |
if ((addr & 1) && value & RCW1_RST) { |
525 |
axienet_rx_reset(s); |
526 |
} else {
|
527 |
qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
528 |
} |
529 |
break;
|
530 |
|
531 |
case R_TC:
|
532 |
s->tc = value; |
533 |
if (value & TC_RST) {
|
534 |
axienet_tx_reset(s); |
535 |
} |
536 |
break;
|
537 |
|
538 |
case R_EMMC:
|
539 |
s->emmc = value; |
540 |
break;
|
541 |
|
542 |
case R_PHYC:
|
543 |
s->phyc = value; |
544 |
break;
|
545 |
|
546 |
case R_MC:
|
547 |
value &= ((1 < 7) - 1); |
548 |
|
549 |
/* Enable the MII. */
|
550 |
if (value & MC_EN) {
|
551 |
unsigned int miiclkdiv = value & ((1 << 6) - 1); |
552 |
if (!miiclkdiv) {
|
553 |
qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
|
554 |
} |
555 |
} |
556 |
s->mii.mc = value; |
557 |
break;
|
558 |
|
559 |
case R_MCR: {
|
560 |
unsigned int phyaddr = (value >> 24) & 0x1f; |
561 |
unsigned int regaddr = (value >> 16) & 0x1f; |
562 |
unsigned int op = (value >> 14) & 3; |
563 |
unsigned int initiate = (value >> 11) & 1; |
564 |
|
565 |
if (initiate) {
|
566 |
if (op == 1) { |
567 |
mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); |
568 |
} else if (op == 2) { |
569 |
s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); |
570 |
} else {
|
571 |
qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
|
572 |
} |
573 |
} |
574 |
s->mii.mcr = value; |
575 |
break;
|
576 |
} |
577 |
|
578 |
case R_MWD:
|
579 |
case R_MRD:
|
580 |
s->mii.regs[addr & 3] = value;
|
581 |
break;
|
582 |
|
583 |
|
584 |
case R_UAW0:
|
585 |
case R_UAW1:
|
586 |
s->uaw[addr & 1] = value;
|
587 |
break;
|
588 |
|
589 |
case R_UAWL:
|
590 |
case R_UAWU:
|
591 |
s->ext_uaw[addr & 1] = value;
|
592 |
break;
|
593 |
|
594 |
case R_FMI:
|
595 |
s->fmi = value; |
596 |
break;
|
597 |
|
598 |
case R_AF0:
|
599 |
case R_AF1:
|
600 |
s->maddr[s->fmi & 3][addr & 1] = value; |
601 |
break;
|
602 |
|
603 |
case R_IS:
|
604 |
s->regs[addr] &= ~value; |
605 |
break;
|
606 |
|
607 |
case 0x8000 ... 0x83ff: |
608 |
s->ext_mtable[addr - 0x8000] = value;
|
609 |
break;
|
610 |
|
611 |
default:
|
612 |
DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", |
613 |
__func__, addr * 4, (unsigned)value)); |
614 |
if (addr < ARRAY_SIZE(s->regs)) {
|
615 |
s->regs[addr] = value; |
616 |
} |
617 |
break;
|
618 |
} |
619 |
enet_update_irq(s); |
620 |
} |
621 |
|
622 |
static const MemoryRegionOps enet_ops = { |
623 |
.read = enet_read, |
624 |
.write = enet_write, |
625 |
.endianness = DEVICE_LITTLE_ENDIAN, |
626 |
}; |
627 |
|
628 |
static int eth_can_rx(NetClientState *nc) |
629 |
{ |
630 |
XilinxAXIEnet *s = qemu_get_nic_opaque(nc); |
631 |
|
632 |
/* RX enabled? */
|
633 |
return !axienet_rx_resetting(s) && axienet_rx_enabled(s);
|
634 |
} |
635 |
|
636 |
static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) |
637 |
{ |
638 |
int match = 1; |
639 |
|
640 |
if (memcmp(buf, &f0, 4)) { |
641 |
match = 0;
|
642 |
} |
643 |
|
644 |
if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { |
645 |
match = 0;
|
646 |
} |
647 |
|
648 |
return match;
|
649 |
} |
650 |
|
651 |
static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) |
652 |
{ |
653 |
XilinxAXIEnet *s = qemu_get_nic_opaque(nc); |
654 |
static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, |
655 |
0xff, 0xff, 0xff}; |
656 |
static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; |
657 |
uint32_t app[6] = {0}; |
658 |
int promisc = s->fmi & (1 << 31); |
659 |
int unicast, broadcast, multicast, ip_multicast = 0; |
660 |
uint32_t csum32; |
661 |
uint16_t csum16; |
662 |
int i;
|
663 |
|
664 |
DENET(qemu_log("%s: %zd bytes\n", __func__, size));
|
665 |
|
666 |
unicast = ~buf[0] & 0x1; |
667 |
broadcast = memcmp(buf, sa_bcast, 6) == 0; |
668 |
multicast = !unicast && !broadcast; |
669 |
if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { |
670 |
ip_multicast = 1;
|
671 |
} |
672 |
|
673 |
/* Jumbo or vlan sizes ? */
|
674 |
if (!(s->rcw[1] & RCW1_JUM)) { |
675 |
if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { |
676 |
return size;
|
677 |
} |
678 |
} |
679 |
|
680 |
/* Basic Address filters. If you want to use the extended filters
|
681 |
you'll generally have to place the ethernet mac into promiscuous mode
|
682 |
to avoid the basic filtering from dropping most frames. */
|
683 |
if (!promisc) {
|
684 |
if (unicast) {
|
685 |
if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { |
686 |
return size;
|
687 |
} |
688 |
} else {
|
689 |
if (broadcast) {
|
690 |
/* Broadcast. */
|
691 |
if (s->regs[R_RAF] & RAF_BCAST_REJ) {
|
692 |
return size;
|
693 |
} |
694 |
} else {
|
695 |
int drop = 1; |
696 |
|
697 |
/* Multicast. */
|
698 |
if (s->regs[R_RAF] & RAF_MCAST_REJ) {
|
699 |
return size;
|
700 |
} |
701 |
|
702 |
for (i = 0; i < 4; i++) { |
703 |
if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { |
704 |
drop = 0;
|
705 |
break;
|
706 |
} |
707 |
} |
708 |
|
709 |
if (drop) {
|
710 |
return size;
|
711 |
} |
712 |
} |
713 |
} |
714 |
} |
715 |
|
716 |
/* Extended mcast filtering enabled? */
|
717 |
if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
|
718 |
if (unicast) {
|
719 |
if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { |
720 |
return size;
|
721 |
} |
722 |
} else {
|
723 |
if (broadcast) {
|
724 |
/* Broadcast. ??? */
|
725 |
if (s->regs[R_RAF] & RAF_BCAST_REJ) {
|
726 |
return size;
|
727 |
} |
728 |
} else {
|
729 |
int idx, bit;
|
730 |
|
731 |
/* Multicast. */
|
732 |
if (!memcmp(buf, sa_ipmcast, 3)) { |
733 |
return size;
|
734 |
} |
735 |
|
736 |
idx = (buf[4] & 0x7f) << 8; |
737 |
idx |= buf[5];
|
738 |
|
739 |
bit = 1 << (idx & 0x1f); |
740 |
idx >>= 5;
|
741 |
|
742 |
if (!(s->ext_mtable[idx] & bit)) {
|
743 |
return size;
|
744 |
} |
745 |
} |
746 |
} |
747 |
} |
748 |
|
749 |
if (size < 12) { |
750 |
s->regs[R_IS] |= IS_RX_REJECT; |
751 |
enet_update_irq(s); |
752 |
return -1; |
753 |
} |
754 |
|
755 |
if (size > (s->c_rxmem - 4)) { |
756 |
size = s->c_rxmem - 4;
|
757 |
} |
758 |
|
759 |
memcpy(s->rxmem, buf, size); |
760 |
memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ |
761 |
|
762 |
if (s->rcw[1] & RCW1_FCS) { |
763 |
size += 4; /* fcs is inband. */ |
764 |
} |
765 |
|
766 |
app[0] = 5 << 28; |
767 |
csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); |
768 |
/* Fold it once. */
|
769 |
csum32 = (csum32 & 0xffff) + (csum32 >> 16); |
770 |
/* And twice to get rid of possible carries. */
|
771 |
csum16 = (csum32 & 0xffff) + (csum32 >> 16); |
772 |
app[3] = csum16;
|
773 |
app[4] = size & 0xffff; |
774 |
|
775 |
s->stats.rx_bytes += size; |
776 |
s->stats.rx++; |
777 |
if (multicast) {
|
778 |
s->stats.rx_mcast++; |
779 |
app[2] |= 1 | (ip_multicast << 1); |
780 |
} else if (broadcast) { |
781 |
s->stats.rx_bcast++; |
782 |
app[2] |= 1 << 3; |
783 |
} |
784 |
|
785 |
/* Good frame. */
|
786 |
app[2] |= 1 << 6; |
787 |
|
788 |
stream_push(s->tx_dev, (void *)s->rxmem, size, app);
|
789 |
|
790 |
s->regs[R_IS] |= IS_RX_COMPLETE; |
791 |
enet_update_irq(s); |
792 |
return size;
|
793 |
} |
794 |
|
795 |
static void eth_cleanup(NetClientState *nc) |
796 |
{ |
797 |
/* FIXME. */
|
798 |
XilinxAXIEnet *s = qemu_get_nic_opaque(nc); |
799 |
g_free(s->rxmem); |
800 |
g_free(s); |
801 |
} |
802 |
|
803 |
static void |
804 |
axienet_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t *hdr) |
805 |
{ |
806 |
XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj)); |
807 |
|
808 |
/* TX enable ? */
|
809 |
if (!(s->tc & TC_TX)) {
|
810 |
return;
|
811 |
} |
812 |
|
813 |
/* Jumbo or vlan sizes ? */
|
814 |
if (!(s->tc & TC_JUM)) {
|
815 |
if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) { |
816 |
return;
|
817 |
} |
818 |
} |
819 |
|
820 |
if (hdr[0] & 1) { |
821 |
unsigned int start_off = hdr[1] >> 16; |
822 |
unsigned int write_off = hdr[1] & 0xffff; |
823 |
uint32_t tmp_csum; |
824 |
uint16_t csum; |
825 |
|
826 |
tmp_csum = net_checksum_add(size - start_off, |
827 |
(uint8_t *)buf + start_off); |
828 |
/* Accumulate the seed. */
|
829 |
tmp_csum += hdr[2] & 0xffff; |
830 |
|
831 |
/* Fold the 32bit partial checksum. */
|
832 |
csum = net_checksum_finish(tmp_csum); |
833 |
|
834 |
/* Writeback. */
|
835 |
buf[write_off] = csum >> 8;
|
836 |
buf[write_off + 1] = csum & 0xff; |
837 |
} |
838 |
|
839 |
qemu_send_packet(qemu_get_queue(s->nic), buf, size); |
840 |
|
841 |
s->stats.tx_bytes += size; |
842 |
s->regs[R_IS] |= IS_TX_COMPLETE; |
843 |
enet_update_irq(s); |
844 |
} |
845 |
|
846 |
static NetClientInfo net_xilinx_enet_info = {
|
847 |
.type = NET_CLIENT_OPTIONS_KIND_NIC, |
848 |
.size = sizeof(NICState),
|
849 |
.can_receive = eth_can_rx, |
850 |
.receive = eth_rx, |
851 |
.cleanup = eth_cleanup, |
852 |
}; |
853 |
|
854 |
static int xilinx_enet_init(SysBusDevice *dev) |
855 |
{ |
856 |
XilinxAXIEnet *s = XILINX_AXI_ENET(dev); |
857 |
|
858 |
sysbus_init_irq(dev, &s->irq); |
859 |
|
860 |
memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000); |
861 |
sysbus_init_mmio(dev, &s->iomem); |
862 |
|
863 |
qemu_macaddr_default_if_unset(&s->conf.macaddr); |
864 |
s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, |
865 |
object_get_typename(OBJECT(dev)), dev->qdev.id, s); |
866 |
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
867 |
|
868 |
tdk_init(&s->TEMAC.phy); |
869 |
mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); |
870 |
|
871 |
s->TEMAC.parent = s; |
872 |
|
873 |
s->rxmem = g_malloc(s->c_rxmem); |
874 |
axienet_reset(s); |
875 |
|
876 |
return 0; |
877 |
} |
878 |
|
879 |
static void xilinx_enet_initfn(Object *obj) |
880 |
{ |
881 |
XilinxAXIEnet *s = XILINX_AXI_ENET(obj); |
882 |
Error *errp = NULL;
|
883 |
|
884 |
object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
|
885 |
(Object **) &s->tx_dev, &errp); |
886 |
assert_no_error(errp); |
887 |
} |
888 |
|
889 |
static Property xilinx_enet_properties[] = {
|
890 |
DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), |
891 |
DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), |
892 |
DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), |
893 |
DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), |
894 |
DEFINE_PROP_END_OF_LIST(), |
895 |
}; |
896 |
|
897 |
static void xilinx_enet_class_init(ObjectClass *klass, void *data) |
898 |
{ |
899 |
DeviceClass *dc = DEVICE_CLASS(klass); |
900 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
901 |
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); |
902 |
|
903 |
k->init = xilinx_enet_init; |
904 |
dc->props = xilinx_enet_properties; |
905 |
ssc->push = axienet_stream_push; |
906 |
} |
907 |
|
908 |
static const TypeInfo xilinx_enet_info = { |
909 |
.name = TYPE_XILINX_AXI_ENET, |
910 |
.parent = TYPE_SYS_BUS_DEVICE, |
911 |
.instance_size = sizeof(XilinxAXIEnet),
|
912 |
.class_init = xilinx_enet_class_init, |
913 |
.instance_init = xilinx_enet_initfn, |
914 |
.interfaces = (InterfaceInfo[]) { |
915 |
{ TYPE_STREAM_SLAVE }, |
916 |
{ } |
917 |
} |
918 |
}; |
919 |
|
920 |
static void xilinx_enet_register_types(void) |
921 |
{ |
922 |
type_register_static(&xilinx_enet_info); |
923 |
} |
924 |
|
925 |
type_init(xilinx_enet_register_types) |