Revision f0f26a06 qemu-tech.texi
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Lazy evaluation of CPU condition codes (@code{EFLAGS} register on x86)
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is important for CPUs where every instruction sets the condition |
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codes. It tends to be less important on conventional RISC systems |
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where condition codes are only updated when explicitly requested. |
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where condition codes are only updated when explicitly requested. On |
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Sparc64, costly update of both 32 and 64 bit condition codes can be |
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avoided with lazy evaluation. |
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Instead of computing the condition codes after each x86 instruction, |
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QEMU just stores one operand (called @code{CC_SRC}), the result
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@code{CC_OP} is almost never explicitly set in the generated code
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because it is known at translation time. |
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The lazy condition code evaluation is used on x86, m68k and cris. ARM
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uses a simplified variant for the N and Z flags. |
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The lazy condition code evaluation is used on x86, m68k, cris and
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Sparc. ARM uses a simplified variant for the N and Z flags.
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@node CPU state optimisations |
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@section CPU state optimisations |
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