root / hw / mips_r4k.c @ f0fc6f8f
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1 | e16fe40c | ths | /*
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2 | e16fe40c | ths | * QEMU/MIPS pseudo-board
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3 | e16fe40c | ths | *
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4 | e16fe40c | ths | * emulates a simple machine with ISA-like bus.
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5 | e16fe40c | ths | * ISA IO space mapped to the 0x14000000 (PHYS) and
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6 | e16fe40c | ths | * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
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7 | e16fe40c | ths | * All peripherial devices are attached to this "bus" with
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8 | e16fe40c | ths | * the standard PC ISA addresses.
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9 | e16fe40c | ths | */
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10 | 6af0bf9c | bellard | #include "vl.h" |
11 | 6af0bf9c | bellard | |
12 | 2909b29a | ths | #ifdef TARGET_WORDS_BIGENDIAN
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13 | 6af0bf9c | bellard | #define BIOS_FILENAME "mips_bios.bin" |
14 | f7bcd4e3 | ths | #else
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15 | f7bcd4e3 | ths | #define BIOS_FILENAME "mipsel_bios.bin" |
16 | f7bcd4e3 | ths | #endif
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17 | 44cbbf18 | ths | |
18 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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19 | 74287114 | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) |
20 | 5dc4b744 | ths | #else
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21 | 74287114 | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) |
22 | 5dc4b744 | ths | #endif
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23 | 6af0bf9c | bellard | |
24 | 5dc4b744 | ths | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
25 | 66a93e0f | bellard | |
26 | 58126404 | pbrook | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
27 | 58126404 | pbrook | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
28 | 58126404 | pbrook | static const int ide_irq[2] = { 14, 15 }; |
29 | 58126404 | pbrook | |
30 | eddbd288 | ths | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
31 | eddbd288 | ths | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
32 | eddbd288 | ths | |
33 | 6af0bf9c | bellard | extern FILE *logfile;
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34 | 6af0bf9c | bellard | |
35 | e16fe40c | ths | static PITState *pit; /* PIT i8254 */ |
36 | 697584ab | bellard | |
37 | e16fe40c | ths | /*i8254 PIT is attached to the IRQ0 at PIC i8259 */
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38 | 6af0bf9c | bellard | |
39 | 6ae81775 | ths | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |
40 | 6ae81775 | ths | uint32_t val) |
41 | 6ae81775 | ths | { |
42 | 6ae81775 | ths | if ((addr & 0xffff) == 0 && val == 42) |
43 | 6ae81775 | ths | qemu_system_reset_request (); |
44 | 6ae81775 | ths | else if ((addr & 0xffff) == 4 && val == 42) |
45 | 6ae81775 | ths | qemu_system_shutdown_request (); |
46 | 6ae81775 | ths | } |
47 | 6ae81775 | ths | |
48 | 6ae81775 | ths | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) |
49 | 6ae81775 | ths | { |
50 | 6ae81775 | ths | return 0; |
51 | 6ae81775 | ths | } |
52 | 6ae81775 | ths | |
53 | 6ae81775 | ths | static CPUWriteMemoryFunc *mips_qemu_write[] = {
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54 | 6ae81775 | ths | &mips_qemu_writel, |
55 | 6ae81775 | ths | &mips_qemu_writel, |
56 | 6ae81775 | ths | &mips_qemu_writel, |
57 | 6ae81775 | ths | }; |
58 | 6ae81775 | ths | |
59 | 6ae81775 | ths | static CPUReadMemoryFunc *mips_qemu_read[] = {
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60 | 6ae81775 | ths | &mips_qemu_readl, |
61 | 6ae81775 | ths | &mips_qemu_readl, |
62 | 6ae81775 | ths | &mips_qemu_readl, |
63 | 6ae81775 | ths | }; |
64 | 6ae81775 | ths | |
65 | 6ae81775 | ths | static int mips_qemu_iomemtype = 0; |
66 | 6ae81775 | ths | |
67 | ea6fd42f | ths | static void load_kernel (CPUState *env, int ram_size, |
68 | ea6fd42f | ths | const char *kernel_filename, |
69 | ea6fd42f | ths | const char *kernel_cmdline, |
70 | ea6fd42f | ths | const char *initrd_filename) |
71 | 6ae81775 | ths | { |
72 | 74287114 | ths | int64_t entry, kernel_low, kernel_high; |
73 | 6ae81775 | ths | long kernel_size, initrd_size;
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74 | 74287114 | ths | ram_addr_t initrd_offset; |
75 | 6ae81775 | ths | |
76 | 74287114 | ths | kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, |
77 | 74287114 | ths | &entry, &kernel_low, &kernel_high); |
78 | c570fd16 | ths | if (kernel_size >= 0) { |
79 | c570fd16 | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
80 | 5dc4b744 | ths | entry = (int32_t)entry; |
81 | ead9360e | ths | env->PC[env->current_tc] = entry; |
82 | c570fd16 | ths | } else {
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83 | 9042c0e2 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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84 | 9042c0e2 | ths | kernel_filename); |
85 | 9042c0e2 | ths | exit(1);
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86 | 6ae81775 | ths | } |
87 | 6ae81775 | ths | |
88 | 6ae81775 | ths | /* load initrd */
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89 | 6ae81775 | ths | initrd_size = 0;
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90 | 74287114 | ths | initrd_offset = 0;
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91 | 6ae81775 | ths | if (initrd_filename) {
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92 | 74287114 | ths | initrd_size = get_image_size (initrd_filename); |
93 | 74287114 | ths | if (initrd_size > 0) { |
94 | 74287114 | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
95 | 74287114 | ths | if (initrd_offset + initrd_size > ram_size) {
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96 | 74287114 | ths | fprintf(stderr, |
97 | 74287114 | ths | "qemu: memory too small for initial ram disk '%s'\n",
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98 | 74287114 | ths | initrd_filename); |
99 | 74287114 | ths | exit(1);
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100 | 74287114 | ths | } |
101 | 74287114 | ths | initrd_size = load_image(initrd_filename, |
102 | 74287114 | ths | phys_ram_base + initrd_offset); |
103 | 74287114 | ths | } |
104 | 6ae81775 | ths | if (initrd_size == (target_ulong) -1) { |
105 | 6ae81775 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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106 | 6ae81775 | ths | initrd_filename); |
107 | 6ae81775 | ths | exit(1);
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108 | 6ae81775 | ths | } |
109 | 6ae81775 | ths | } |
110 | 6ae81775 | ths | |
111 | 6ae81775 | ths | /* Store command line. */
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112 | 6ae81775 | ths | if (initrd_size > 0) { |
113 | 6ae81775 | ths | int ret;
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114 | 6ae81775 | ths | ret = sprintf(phys_ram_base + (16 << 20) - 256, |
115 | 3594c774 | ths | "rd_start=0x" TARGET_FMT_lx " rd_size=%li ", |
116 | 74287114 | ths | PHYS_TO_VIRT((uint32_t)initrd_offset), |
117 | 6ae81775 | ths | initrd_size); |
118 | 6ae81775 | ths | strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline); |
119 | 6ae81775 | ths | } |
120 | 6ae81775 | ths | else {
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121 | 6ae81775 | ths | strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); |
122 | 6ae81775 | ths | } |
123 | 6ae81775 | ths | |
124 | 44cbbf18 | ths | *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
125 | 44cbbf18 | ths | *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); |
126 | 6ae81775 | ths | } |
127 | 6ae81775 | ths | |
128 | 6ae81775 | ths | static void main_cpu_reset(void *opaque) |
129 | 6ae81775 | ths | { |
130 | 6ae81775 | ths | CPUState *env = opaque; |
131 | 6ae81775 | ths | cpu_reset(env); |
132 | 51b2772f | ths | cpu_mips_register(env, NULL);
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133 | 6ae81775 | ths | |
134 | 6ae81775 | ths | if (env->kernel_filename)
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135 | 6ae81775 | ths | load_kernel (env, env->ram_size, env->kernel_filename, |
136 | 6ae81775 | ths | env->kernel_cmdline, env->initrd_filename); |
137 | 6ae81775 | ths | } |
138 | 66a93e0f | bellard | |
139 | 70705261 | ths | static
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140 | 6af0bf9c | bellard | void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
141 | 6af0bf9c | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
142 | 6af0bf9c | bellard | const char *kernel_filename, const char *kernel_cmdline, |
143 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
144 | 6af0bf9c | bellard | { |
145 | 6af0bf9c | bellard | char buf[1024]; |
146 | 6af0bf9c | bellard | unsigned long bios_offset; |
147 | f7bcd4e3 | ths | int bios_size;
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148 | c68ea704 | bellard | CPUState *env; |
149 | 153a08db | ths | RTCState *rtc_state; |
150 | 58126404 | pbrook | int i;
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151 | 33d68b5f | ths | mips_def_t *def; |
152 | d537cf6c | pbrook | qemu_irq *i8259; |
153 | c68ea704 | bellard | |
154 | 33d68b5f | ths | /* init CPUs */
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155 | 33d68b5f | ths | if (cpu_model == NULL) { |
156 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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157 | 33d68b5f | ths | cpu_model = "R4000";
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158 | 33d68b5f | ths | #else
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159 | 1c32f43e | ths | cpu_model = "24Kf";
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160 | 33d68b5f | ths | #endif
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161 | 33d68b5f | ths | } |
162 | 33d68b5f | ths | if (mips_find_by_name(cpu_model, &def) != 0) |
163 | 33d68b5f | ths | def = NULL;
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164 | c68ea704 | bellard | env = cpu_init(); |
165 | 33d68b5f | ths | cpu_mips_register(env, def); |
166 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
167 | 6ae81775 | ths | qemu_register_reset(main_cpu_reset, env); |
168 | c68ea704 | bellard | |
169 | 6af0bf9c | bellard | /* allocate RAM */
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170 | 6af0bf9c | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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171 | 66a93e0f | bellard | |
172 | 6ae81775 | ths | if (!mips_qemu_iomemtype) {
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173 | 6ae81775 | ths | mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
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174 | 33d68b5f | ths | mips_qemu_write, NULL);
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175 | 6ae81775 | ths | } |
176 | 6ae81775 | ths | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); |
177 | 6ae81775 | ths | |
178 | 66a93e0f | bellard | /* Try to load a BIOS image. If this fails, we continue regardless,
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179 | 66a93e0f | bellard | but initialize the hardware ourselves. When a kernel gets
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180 | 66a93e0f | bellard | preloaded we also initialize the hardware, since the BIOS wasn't
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181 | 66a93e0f | bellard | run. */
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182 | 6af0bf9c | bellard | bios_offset = ram_size + vga_ram_size; |
183 | 1192dad8 | j_mayer | if (bios_name == NULL) |
184 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
185 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
186 | f7bcd4e3 | ths | bios_size = load_image(buf, phys_ram_base + bios_offset); |
187 | 2909b29a | ths | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { |
188 | 44cbbf18 | ths | cpu_register_physical_memory(0x1fc00000,
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189 | 66a93e0f | bellard | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
190 | 66a93e0f | bellard | } else {
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191 | 66a93e0f | bellard | /* not fatal */
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192 | 66a93e0f | bellard | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
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193 | 66a93e0f | bellard | buf); |
194 | 6af0bf9c | bellard | } |
195 | 66a93e0f | bellard | |
196 | 66a93e0f | bellard | if (kernel_filename) {
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197 | 6ae81775 | ths | load_kernel (env, ram_size, kernel_filename, kernel_cmdline, |
198 | 6ae81775 | ths | initrd_filename); |
199 | 6ae81775 | ths | env->ram_size = ram_size; |
200 | 6ae81775 | ths | env->kernel_filename = kernel_filename; |
201 | 6ae81775 | ths | env->kernel_cmdline = kernel_cmdline; |
202 | 6ae81775 | ths | env->initrd_filename = initrd_filename; |
203 | 6af0bf9c | bellard | } |
204 | 6af0bf9c | bellard | |
205 | e16fe40c | ths | /* Init CPU internal devices */
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206 | d537cf6c | pbrook | cpu_mips_irq_init_cpu(env); |
207 | c68ea704 | bellard | cpu_mips_clock_init(env); |
208 | 6af0bf9c | bellard | cpu_mips_irqctrl_init(); |
209 | 6af0bf9c | bellard | |
210 | d537cf6c | pbrook | /* The PIC is attached to the MIPS CPU INT0 pin */
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211 | d537cf6c | pbrook | i8259 = i8259_init(env->irq[2]);
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212 | d537cf6c | pbrook | |
213 | d537cf6c | pbrook | rtc_state = rtc_init(0x70, i8259[8]); |
214 | afdfa781 | ths | |
215 | 0699b548 | bellard | /* Register 64 KB of ISA IO space at 0x14000000 */
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216 | aef445bd | pbrook | isa_mmio_init(0x14000000, 0x00010000); |
217 | 0699b548 | bellard | isa_mem_base = 0x10000000;
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218 | 0699b548 | bellard | |
219 | d537cf6c | pbrook | pit = pit_init(0x40, i8259[0]); |
220 | afdfa781 | ths | |
221 | eddbd288 | ths | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
222 | eddbd288 | ths | if (serial_hds[i]) {
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223 | d537cf6c | pbrook | serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]); |
224 | eddbd288 | ths | } |
225 | eddbd288 | ths | } |
226 | eddbd288 | ths | |
227 | 5fafdf24 | ths | isa_vga_init(ds, phys_ram_base + ram_size, ram_size, |
228 | 89b6b508 | bellard | vga_ram_size); |
229 | 9827e95c | bellard | |
230 | a41b2ff2 | pbrook | if (nd_table[0].vlan) { |
231 | a41b2ff2 | pbrook | if (nd_table[0].model == NULL |
232 | a41b2ff2 | pbrook | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
233 | d537cf6c | pbrook | isa_ne2000_init(0x300, i8259[9], &nd_table[0]); |
234 | c4a7060c | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
235 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n");
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236 | c4a7060c | blueswir1 | exit (1);
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237 | a41b2ff2 | pbrook | } else {
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238 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
239 | a41b2ff2 | pbrook | exit (1);
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240 | a41b2ff2 | pbrook | } |
241 | a41b2ff2 | pbrook | } |
242 | 58126404 | pbrook | |
243 | 58126404 | pbrook | for(i = 0; i < 2; i++) |
244 | d537cf6c | pbrook | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
245 | 58126404 | pbrook | bs_table[2 * i], bs_table[2 * i + 1]); |
246 | 70705261 | ths | |
247 | d537cf6c | pbrook | i8042_init(i8259[1], i8259[12], 0x60); |
248 | 9542611a | ths | ds1225y_init(0x9000, "nvram"); |
249 | 6af0bf9c | bellard | } |
250 | 6af0bf9c | bellard | |
251 | 6af0bf9c | bellard | QEMUMachine mips_machine = { |
252 | 6af0bf9c | bellard | "mips",
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253 | 6af0bf9c | bellard | "mips r4k platform",
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254 | 6af0bf9c | bellard | mips_r4k_init, |
255 | 6af0bf9c | bellard | }; |