Revision f1698408

b/Makefile.objs
143 143
hw-obj-$(CONFIG_I8254) += i8254.o
144 144
hw-obj-$(CONFIG_PCSPK) += pcspk.o
145 145
hw-obj-$(CONFIG_USB_UHCI) += usb-uhci.o
146
hw-obj-$(CONFIG_USB_OHCI) += usb-ohci.o
146 147
hw-obj-$(CONFIG_FDC) += fdc.o
147 148

  
148 149
# PCI watchdog devices
b/Makefile.target
186 186
# xen backend driver support
187 187
obj-$(CONFIG_XEN) += xen_machine_pv.o xen_domainbuild.o
188 188

  
189
# USB layer
190
obj-$(CONFIG_USB_OHCI) += usb-ohci.o
191

  
192 189
# PCI network cards
193 190
obj-y += rtl8139.o
194 191
obj-y += e1000.o
b/hw/devices.h
69 69

  
70 70
/* usb-ohci.c */
71 71
void usb_ohci_init_sm501(uint32_t mmio_base, uint32_t localmem_base,
72
                         int num_ports, int devfn, qemu_irq irq);
72
                         int num_ports, int devfn, qemu_irq irq, int be);
73 73
#endif
b/hw/ppc_newworld.c
387 387
               escc_mem_index);
388 388

  
389 389
    if (usb_enabled) {
390
        usb_ohci_init_pci(pci_bus, -1);
390
        usb_ohci_init_pci(pci_bus, -1, 1);
391 391
    }
392 392

  
393 393
    /* U3 needs to use USB for input because Linux doesn't support via-cuda
b/hw/ppc_oldworld.c
370 370
               escc_mem_index);
371 371

  
372 372
    if (usb_enabled) {
373
        usb_ohci_init_pci(pci_bus, -1);
373
        usb_ohci_init_pci(pci_bus, -1, 1);
374 374
    }
375 375

  
376 376
    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
b/hw/ppc_prep.c
750 750
#endif
751 751

  
752 752
    if (usb_enabled) {
753
        usb_ohci_init_pci(pci_bus, -1);
753
        usb_ohci_init_pci(pci_bus, -1, 1);
754 754
    }
755 755

  
756 756
    m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
b/hw/pxa.h
213 213
PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
214 214
PXA2xxState *pxa255_init(unsigned int sdram_size);
215 215

  
216
/* usb-ohci.c */
217
void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
218
                       qemu_irq irq);
219

  
220 216
#endif	/* PXA_H */
b/hw/pxa2xx.c
9 9

  
10 10
#include "sysbus.h"
11 11
#include "pxa.h"
12
#include "usb-ohci.h"
12 13
#include "sysemu.h"
13 14
#include "pc.h"
14 15
#include "i2c.h"
......
2128 2129
    }
2129 2130

  
2130 2131
    if (usb_enabled) {
2131
        usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2132
#ifdef TARGET_WORDS_BIGENDIAN
2133
        usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1], 1);
2134
#else
2135
        usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1], 0);
2136
#endif
2132 2137
    }
2133 2138

  
2134 2139
    s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
......
2247 2252
    }
2248 2253

  
2249 2254
    if (usb_enabled) {
2250
        usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
2255
#ifdef TARGET_WORDS_BIGENDIAN
2256
        usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1], 1);
2257
#else
2258
        usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1], 0);
2259
#endif
2251 2260
    }
2252 2261

  
2253 2262
    s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
b/hw/realview.c
266 266
                                    pic[48], pic[49], pic[50], pic[51], NULL);
267 267
        pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
268 268
        if (usb_enabled) {
269
            usb_ohci_init_pci(pci_bus, -1);
269
#ifdef TARGET_WORDS_BIGENDIAN
270
            usb_ohci_init_pci(pci_bus, -1, 1);
271
#else
272
            usb_ohci_init_pci(pci_bus, -1, 0);
273
#endif
270 274
        }
271 275
        n = drive_get_max_bus(IF_SCSI);
272 276
        while (n >= 0) {
b/hw/sm501.c
1222 1222
                                 0x1000, sm501_disp_ctrl_index);
1223 1223

  
1224 1224
    /* bridge to usb host emulation module */
1225
#ifdef TARGET_WORDS_BIGENDIAN
1226
    usb_ohci_init_sm501(base + MMIO_BASE_OFFSET + SM501_USB_HOST, base,
1227
                        2, -1, irq, 1);
1228
#else
1225 1229
    usb_ohci_init_sm501(base + MMIO_BASE_OFFSET + SM501_USB_HOST, base,
1226
                        2, -1, irq);
1230
                        2, -1, irq, 0);
1231
#endif
1227 1232

  
1228 1233
    /* bridge to serial emulation module */
1229 1234
    if (chr) {
b/hw/usb-ohci.c
30 30
#include "qemu-timer.h"
31 31
#include "usb.h"
32 32
#include "pci.h"
33
#include "pxa.h"
34 33
#include "devices.h"
35 34
#include "usb-ohci.h"
36 35

  
......
1399 1398
    return;
1400 1399
}
1401 1400

  
1402
static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1401
static uint32_t ohci_mem_read_le(void *ptr, target_phys_addr_t addr)
1403 1402
{
1404 1403
    OHCIState *ohci = ptr;
1405 1404
    uint32_t retval;
......
1516 1515
            retval = 0xffffffff;
1517 1516
        }
1518 1517
    }
1518
    return retval;
1519
}
1520

  
1521
static uint32_t ohci_mem_read_be(void *ptr, target_phys_addr_t addr)
1522
{
1523
    uint32_t retval;
1519 1524

  
1520
#ifdef TARGET_WORDS_BIGENDIAN
1525
    retval = ohci_mem_read_le(ptr, addr);
1521 1526
    retval = bswap32(retval);
1522
#endif
1523 1527
    return retval;
1524 1528
}
1525 1529

  
1526
static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1530
static void ohci_mem_write_le(void *ptr, target_phys_addr_t addr, uint32_t val)
1527 1531
{
1528 1532
    OHCIState *ohci = ptr;
1529 1533

  
1530
#ifdef TARGET_WORDS_BIGENDIAN
1531
    val = bswap32(val);
1532
#endif
1533

  
1534 1534
    /* Only aligned reads are allowed on OHCI */
1535 1535
    if (addr & 3) {
1536 1536
        fprintf(stderr, "usb-ohci: Mis-aligned write\n");
......
1647 1647
    }
1648 1648
}
1649 1649

  
1650
static void ohci_mem_write_be(void *ptr, target_phys_addr_t addr, uint32_t val)
1651
{
1652
    val = bswap32(val);
1653
    ohci_mem_write_le(ptr, addr, val);
1654
}
1655

  
1650 1656
/* Only dword reads are defined on OHCI register space */
1651
static CPUReadMemoryFunc * const ohci_readfn[3]={
1652
    ohci_mem_read,
1653
    ohci_mem_read,
1654
    ohci_mem_read
1657
static CPUReadMemoryFunc * const ohci_readfn_be[3]={
1658
    ohci_mem_read_be,
1659
    ohci_mem_read_be,
1660
    ohci_mem_read_be
1655 1661
};
1656 1662

  
1657 1663
/* Only dword writes are defined on OHCI register space */
1658
static CPUWriteMemoryFunc * const ohci_writefn[3]={
1659
    ohci_mem_write,
1660
    ohci_mem_write,
1661
    ohci_mem_write
1664
static CPUWriteMemoryFunc * const ohci_writefn_be[3]={
1665
    ohci_mem_write_be,
1666
    ohci_mem_write_be,
1667
    ohci_mem_write_be
1668
};
1669

  
1670
static CPUReadMemoryFunc * const ohci_readfn_le[3]={
1671
    ohci_mem_read_le,
1672
    ohci_mem_read_le,
1673
    ohci_mem_read_le
1674
};
1675

  
1676
static CPUWriteMemoryFunc * const ohci_writefn_le[3]={
1677
    ohci_mem_write_le,
1678
    ohci_mem_write_le,
1679
    ohci_mem_write_le
1662 1680
};
1663 1681

  
1664 1682
static void usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1665 1683
                          int num_ports, int devfn,
1666 1684
                          qemu_irq irq, enum ohci_type type,
1667
                          const char *name, uint32_t localmem_base)
1685
                          const char *name, uint32_t localmem_base,
1686
                          int be)
1668 1687
{
1669 1688
    int i;
1670 1689

  
......
1684 1703
                usb_frame_time, usb_bit_time);
1685 1704
    }
1686 1705

  
1687
    ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci);
1706
    if (be) {
1707
        ohci->mem = cpu_register_io_memory(ohci_readfn_be, ohci_writefn_be,
1708
                                           ohci);
1709
    } else {
1710
        ohci->mem = cpu_register_io_memory(ohci_readfn_le, ohci_writefn_le,
1711
                                           ohci);
1712
    }
1688 1713
    ohci->localmem_base = localmem_base;
1689 1714
    ohci->name = name;
1690 1715

  
......
1704 1729
typedef struct {
1705 1730
    PCIDevice pci_dev;
1706 1731
    OHCIState state;
1732
    uint32_t be;
1707 1733
} OHCIPCIState;
1708 1734

  
1709 1735
static void ohci_mapfunc(PCIDevice *pci_dev, int i,
......
1728 1754

  
1729 1755
    usb_ohci_init(&ohci->state, &dev->qdev, num_ports,
1730 1756
                  ohci->pci_dev.devfn, ohci->pci_dev.irq[0],
1731
                  OHCI_TYPE_PCI, ohci->pci_dev.name, 0);
1757
                  OHCI_TYPE_PCI, ohci->pci_dev.name, 0, ohci->be);
1732 1758

  
1733 1759
    /* TODO: avoid cast below by using dev */
1734 1760
    pci_register_bar((struct PCIDevice *)ohci, 0, 256,
......
1736 1762
    return 0;
1737 1763
}
1738 1764

  
1739
void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1765
void usb_ohci_init_pci(struct PCIBus *bus, int devfn, int be)
1740 1766
{
1741
    pci_create_simple(bus, devfn, "pci-ohci");
1767
    PCIDevice *dev;
1768

  
1769
    dev = pci_create(bus, devfn, "pci-ohci");
1770
    qdev_prop_set_uint32(&dev->qdev, "be", be);
1771
    qdev_init_nofail(&dev->qdev);
1742 1772
}
1743 1773

  
1744 1774
void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
1745
                       qemu_irq irq)
1775
                       qemu_irq irq, int be)
1746 1776
{
1747 1777
    OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
1748 1778

  
1749 1779
    usb_ohci_init(ohci, NULL /* FIXME */, num_ports, devfn, irq,
1750
                  OHCI_TYPE_PXA, "OHCI USB", 0);
1780
                  OHCI_TYPE_PXA, "OHCI USB", 0, be);
1751 1781

  
1752 1782
    cpu_register_physical_memory(base, 0x1000, ohci->mem);
1753 1783
}
1754 1784

  
1755 1785
void usb_ohci_init_sm501(uint32_t mmio_base, uint32_t localmem_base,
1756
                         int num_ports, int devfn, qemu_irq irq)
1786
                         int num_ports, int devfn, qemu_irq irq, int be)
1757 1787
{
1758 1788
    OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
1759 1789

  
1760 1790
    usb_ohci_init(ohci, NULL /* FIXME */, num_ports, devfn, irq,
1761
                  OHCI_TYPE_SM501, "OHCI USB", localmem_base);
1791
                  OHCI_TYPE_SM501, "OHCI USB", localmem_base, be);
1762 1792

  
1763 1793
    cpu_register_physical_memory(mmio_base, 0x1000, ohci->mem);
1764 1794
}
......
1768 1798
    .qdev.desc    = "Apple USB Controller",
1769 1799
    .qdev.size    = sizeof(OHCIPCIState),
1770 1800
    .init         = usb_ohci_initfn_pci,
1801
    .qdev.props   = (Property[]) {
1802
        DEFINE_PROP_HEX32("be", OHCIPCIState, be, 0),
1803
        DEFINE_PROP_END_OF_LIST(),
1804
    }
1771 1805
};
1772 1806

  
1773 1807
static void ohci_register(void)
b/hw/usb-ohci.h
3 3

  
4 4
#include "qemu-common.h"
5 5

  
6
void usb_ohci_init_pci(struct PCIBus *bus, int devfn);
7

  
6
void usb_ohci_init_pci(struct PCIBus *bus, int devfn, int be);
7
void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
8
                       qemu_irq irq, int be);
8 9
#endif
9 10

  
b/hw/versatilepb.c
218 218
        }
219 219
    }
220 220
    if (usb_enabled) {
221
        usb_ohci_init_pci(pci_bus, -1);
221
#ifdef TARGET_WORDS_BIGENDIAN
222
        usb_ohci_init_pci(pci_bus, -1, 1);
223
#else
224
        usb_ohci_init_pci(pci_bus, -1, 0);
225
#endif
222 226
    }
223 227
    n = drive_get_max_bus(IF_SCSI);
224 228
    while (n >= 0) {

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