Archipelago » qemu

/*

 *  MIPS emulation helpers for qemu.

 *

 *  Copyright (c) 2004-2005 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include <stdlib.h>

#include "cpu.h"

#include "qemu/host-utils.h"

#include "helper.h"

#if !defined(CONFIG_USER_ONLY)

#include "exec/softmmu_exec.h"

#endif /* !defined(CONFIG_USER_ONLY) */

#ifndef CONFIG_USER_ONLY

static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);

#endif

/*****************************************************************************/

/* Exceptions processing helpers */

static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,

                                                        uint32_t exception,

                                                        int error_code,

                                                        uintptr_t pc)

{

    if (exception < EXCP_SC) {

        qemu_log("%s: %d %d\n", __func__, exception, error_code);

    }

    env->exception_index = exception;

    env->error_code = error_code;

    if (pc) {

        /* now we have a real cpu fault */

        cpu_restore_state(env, pc);

    }

    cpu_loop_exit(env);

}

static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,

                                                    uint32_t exception,

                                                    uintptr_t pc)

{

    do_raise_exception_err(env, exception, 0, pc);

}

void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,

                                int error_code)

{

    do_raise_exception_err(env, exception, error_code, 0);

}

void helper_raise_exception(CPUMIPSState *env, uint32_t exception)

{

    do_raise_exception(env, exception, 0);

}

#if defined(CONFIG_USER_ONLY)

#define HELPER_LD(name, insn, type)                                     \

static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \

                             int mem_idx)                               \

{                                                                       \

    return (type) insn##_raw(addr);                                     \

}

#else

#define HELPER_LD(name, insn, type)                                     \

static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \

                             int mem_idx)                               \

{                                                                       \

    switch (mem_idx)                                                    \

    {                                                                   \

    case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \

    case 1: return (type) cpu_##insn##_super(env, addr); break;         \

    default:                                                            \

    case 2: return (type) cpu_##insn##_user(env, addr); break;          \

    }                                                                   \

}

#endif

HELPER_LD(lbu, ldub, uint8_t)

HELPER_LD(lw, ldl, int32_t)

#ifdef TARGET_MIPS64

HELPER_LD(ld, ldq, int64_t)

#endif

#undef HELPER_LD

#if defined(CONFIG_USER_ONLY)

#define HELPER_ST(name, insn, type)                                     \

static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \

                             type val, int mem_idx)                     \

{                                                                       \

    insn##_raw(addr, val);                                              \

}

#else

#define HELPER_ST(name, insn, type)                                     \

static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \

                             type val, int mem_idx)                     \

{                                                                       \

    switch (mem_idx)                                                    \

    {                                                                   \

    case 0: cpu_##insn##_kernel(env, addr, val); break;                 \

    case 1: cpu_##insn##_super(env, addr, val); break;                  \

    default:                                                            \

    case 2: cpu_##insn##_user(env, addr, val); break;                   \

    }                                                                   \

}

#endif

HELPER_ST(sb, stb, uint8_t)

HELPER_ST(sw, stl, uint32_t)

#ifdef TARGET_MIPS64

HELPER_ST(sd, stq, uint64_t)

#endif

#undef HELPER_ST

target_ulong helper_clo (target_ulong arg1)

{

    return clo32(arg1);

}

target_ulong helper_clz (target_ulong arg1)

{

    return clz32(arg1);

}

#if defined(TARGET_MIPS64)

target_ulong helper_dclo (target_ulong arg1)

{

    return clo64(arg1);

}

target_ulong helper_dclz (target_ulong arg1)

{

    return clz64(arg1);

}

#endif /* TARGET_MIPS64 */

/* 64 bits arithmetic for 32 bits hosts */

static inline uint64_t get_HILO(CPUMIPSState *env)

{

    return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];

}

static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)

{

    target_ulong tmp;

    env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);

    tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);

    return tmp;

}

static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)

{

    target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);

    env->active_tc.HI[0] = (int32_t)(HILO >> 32);

    return tmp;

}

/* Multiplication variants of the vr54xx. */

target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,

                         target_ulong arg2)

{

    return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *

                                 (int64_t)(int32_t)arg2));

}

target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,

                          target_ulong arg2)

{

    return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *

                       (uint64_t)(uint32_t)arg2);

}

target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,

                         target_ulong arg2)

{

    return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *

                       (int64_t)(int32_t)arg2);

}

target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,

                           target_ulong arg2)

{

    return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *

                       (int64_t)(int32_t)arg2);

}

target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,

                          target_ulong arg2)

{

    return set_HI_LOT0(env, (uint64_t)get_HILO(env) +

                       (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);

}

target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,

                            target_ulong arg2)

{

    return set_HIT0_LO(env, (uint64_t)get_HILO(env) +

                       (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);

}

target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,

                         target_ulong arg2)

{

    return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *

                       (int64_t)(int32_t)arg2);

}

target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,

                           target_ulong arg2)

{

    return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *

                       (int64_t)(int32_t)arg2);

}

target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,

                          target_ulong arg2)

{

    return set_HI_LOT0(env, (uint64_t)get_HILO(env) -

                       (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);

}

target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,

                            target_ulong arg2)

{

    return set_HIT0_LO(env, (uint64_t)get_HILO(env) -

                       (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);

}

target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,

                          target_ulong arg2)

{

    return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);

}

target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,

                           target_ulong arg2)

{

    return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *

                       (uint64_t)(uint32_t)arg2);

}

target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,

                           target_ulong arg2)

{

    return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *

                       (int64_t)(int32_t)arg2);

}

target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,

                            target_ulong arg2)

{

    return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *

                       (uint64_t)(uint32_t)arg2);

}

#ifndef CONFIG_USER_ONLY

static inline hwaddr do_translate_address(CPUMIPSState *env,

                                                      target_ulong address,

                                                      int rw)

{

    hwaddr lladdr;

    lladdr = cpu_mips_translate_address(env, address, rw);

    if (lladdr == -1LL) {

        cpu_loop_exit(env);

    } else {

        return lladdr;

    }

}

#define HELPER_LD_ATOMIC(name, insn)                                          \

target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \

{                                                                             \

    env->lladdr = do_translate_address(env, arg, 0);                          \

    env->llval = do_##insn(env, arg, mem_idx);                                \

    return env->llval;                                                        \

}

HELPER_LD_ATOMIC(ll, lw)

#ifdef TARGET_MIPS64

HELPER_LD_ATOMIC(lld, ld)

#endif

#undef HELPER_LD_ATOMIC

#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \

target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \

                           target_ulong arg2, int mem_idx)                    \

{                                                                             \

    target_long tmp;                                                          \

                                                                              \

    if (arg2 & almask) {                                                      \

        env->CP0_BadVAddr = arg2;                                             \

        helper_raise_exception(env, EXCP_AdES);                               \

    }                                                                         \

    if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \

        tmp = do_##ld_insn(env, arg2, mem_idx);                               \

        if (tmp == env->llval) {                                              \

            do_##st_insn(env, arg2, arg1, mem_idx);                           \

            return 1;                                                         \

        }                                                                     \

    }                                                                         \

    return 0;                                                                 \

}

HELPER_ST_ATOMIC(sc, lw, sw, 0x3)

#ifdef TARGET_MIPS64

HELPER_ST_ATOMIC(scd, ld, sd, 0x7)

#endif

#undef HELPER_ST_ATOMIC

#endif

#ifdef TARGET_WORDS_BIGENDIAN

#define GET_LMASK(v) ((v) & 3)

#define GET_OFFSET(addr, offset) (addr + (offset))

#else

#define GET_LMASK(v) (((v) & 3) ^ 3)

#define GET_OFFSET(addr, offset) (addr - (offset))

#endif

void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,

                int mem_idx)

{

    do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);

    if (GET_LMASK(arg2) <= 2)

        do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);

    if (GET_LMASK(arg2) <= 1)

        do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);

    if (GET_LMASK(arg2) == 0)

        do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);

}

void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,

                int mem_idx)

{

    do_sb(env, arg2, (uint8_t)arg1, mem_idx);

    if (GET_LMASK(arg2) >= 1)

        do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);

    if (GET_LMASK(arg2) >= 2)

        do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);

    if (GET_LMASK(arg2) == 3)

        do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);

}

#if defined(TARGET_MIPS64)

/* "half" load and stores.  We must do the memory access inline,

   or fault handling won't work.  */

#ifdef TARGET_WORDS_BIGENDIAN

#define GET_LMASK64(v) ((v) & 7)

#else

#define GET_LMASK64(v) (((v) & 7) ^ 7)

#endif

void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,

                int mem_idx)

{

    do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);

    if (GET_LMASK64(arg2) <= 6)

        do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);

    if (GET_LMASK64(arg2) <= 5)

        do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);

    if (GET_LMASK64(arg2) <= 4)

        do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);

    if (GET_LMASK64(arg2) <= 3)

        do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);

    if (GET_LMASK64(arg2) <= 2)

        do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);

    if (GET_LMASK64(arg2) <= 1)

        do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);

    if (GET_LMASK64(arg2) <= 0)

        do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);

}

void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,

                int mem_idx)

{

    do_sb(env, arg2, (uint8_t)arg1, mem_idx);

    if (GET_LMASK64(arg2) >= 1)

        do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);

    if (GET_LMASK64(arg2) >= 2)

        do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);

    if (GET_LMASK64(arg2) >= 3)

        do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);

    if (GET_LMASK64(arg2) >= 4)

        do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);

    if (GET_LMASK64(arg2) >= 5)

        do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);

    if (GET_LMASK64(arg2) >= 6)

        do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);

    if (GET_LMASK64(arg2) == 7)

        do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);

}

#endif /* TARGET_MIPS64 */

static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };

void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,

                uint32_t mem_idx)

{

    target_ulong base_reglist = reglist & 0xf;

    target_ulong do_r31 = reglist & 0x10;

    if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {

        target_ulong i;

        for (i = 0; i < base_reglist; i++) {

            env->active_tc.gpr[multiple_regs[i]] =

                (target_long)do_lw(env, addr, mem_idx);

            addr += 4;

        }

    }

    if (do_r31) {

        env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);

    }

}

void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,

                uint32_t mem_idx)

{

    target_ulong base_reglist = reglist & 0xf;

    target_ulong do_r31 = reglist & 0x10;

    if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {

        target_ulong i;

        for (i = 0; i < base_reglist; i++) {

            do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);

            addr += 4;

        }

    }

    if (do_r31) {

        do_sw(env, addr, env->active_tc.gpr[31], mem_idx);

    }

}

#if defined(TARGET_MIPS64)

void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,

                uint32_t mem_idx)

{

    target_ulong base_reglist = reglist & 0xf;

    target_ulong do_r31 = reglist & 0x10;

    if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {

        target_ulong i;

        for (i = 0; i < base_reglist; i++) {

            env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);

            addr += 8;

        }

    }

    if (do_r31) {

        env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);

    }

}

void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,

                uint32_t mem_idx)

{

    target_ulong base_reglist = reglist & 0xf;

    target_ulong do_r31 = reglist & 0x10;

    if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {

        target_ulong i;

        for (i = 0; i < base_reglist; i++) {

            do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);

            addr += 8;

        }

    }

    if (do_r31) {

        do_sd(env, addr, env->active_tc.gpr[31], mem_idx);

    }

}

#endif

#ifndef CONFIG_USER_ONLY

/* SMP helpers.  */

static bool mips_vpe_is_wfi(MIPSCPU *c)

{

    CPUState *cpu = CPU(c);

    CPUMIPSState *env = &c->env;

    /* If the VPE is halted but otherwise active, it means it's waiting for

       an interrupt.  */

    return cpu->halted && mips_vpe_active(env);

}

static inline void mips_vpe_wake(MIPSCPU *c)

{

    /* Dont set ->halted = 0 directly, let it be done via cpu_has_work

       because there might be other conditions that state that c should

       be sleeping.  */

    cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);

}

static inline void mips_vpe_sleep(MIPSCPU *cpu)

{

    CPUState *cs = CPU(cpu);

    /* The VPE was shut off, really go to bed.

       Reset any old _WAKE requests.  */

    cs->halted = 1;

    cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);

}

static inline void mips_tc_wake(MIPSCPU *cpu, int tc)

{

    CPUMIPSState *c = &cpu->env;

    /* FIXME: TC reschedule.  */

    if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {

        mips_vpe_wake(cpu);

    }

}

static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)

{

    CPUMIPSState *c = &cpu->env;

    /* FIXME: TC reschedule.  */

    if (!mips_vpe_active(c)) {

        mips_vpe_sleep(cpu);

    }

}

/**

 * mips_cpu_map_tc:

 * @env: CPU from which mapping is performed.

 * @tc: Should point to an int with the value of the global TC index.

 *

 * This function will transform @tc into a local index within the

 * returned #CPUMIPSState.

 */

/* FIXME: This code assumes that all VPEs have the same number of TCs,

          which depends on runtime setup. Can probably be fixed by

          walking the list of CPUMIPSStates.  */

static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)

{

    MIPSCPU *cpu;

    CPUState *cs;

    CPUState *other_cs;

    int vpe_idx;

    int tc_idx = *tc;

    if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {

        /* Not allowed to address other CPUs.  */

        *tc = env->current_tc;

        return env;

    }

    cs = CPU(mips_env_get_cpu(env));

    vpe_idx = tc_idx / cs->nr_threads;

    *tc = tc_idx % cs->nr_threads;

    other_cs = qemu_get_cpu(vpe_idx);

    if (other_cs == NULL) {

        return env;

    }

    cpu = MIPS_CPU(other_cs);

    return &cpu->env;

}

/* The per VPE CP0_Status register shares some fields with the per TC

   CP0_TCStatus registers. These fields are wired to the same registers,

   so changes to either of them should be reflected on both registers.

   Also, EntryHi shares the bottom 8 bit ASID with TCStauts.

   These helper call synchronizes the regs for a given cpu.  */

/* Called for updates to CP0_Status.  */

static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)

{

    int32_t tcstatus, *tcst;

    uint32_t v = cpu->CP0_Status;

    uint32_t cu, mx, asid, ksu;

    uint32_t mask = ((1 << CP0TCSt_TCU3)

                       | (1 << CP0TCSt_TCU2)

                       | (1 << CP0TCSt_TCU1)

                       | (1 << CP0TCSt_TCU0)

                       | (1 << CP0TCSt_TMX)

                       | (3 << CP0TCSt_TKSU)

                       | (0xff << CP0TCSt_TASID));

    cu = (v >> CP0St_CU0) & 0xf;

    mx = (v >> CP0St_MX) & 0x1;

    ksu = (v >> CP0St_KSU) & 0x3;

    asid = env->CP0_EntryHi & 0xff;

    tcstatus = cu << CP0TCSt_TCU0;

    tcstatus |= mx << CP0TCSt_TMX;

    tcstatus |= ksu << CP0TCSt_TKSU;

    tcstatus |= asid;

    if (tc == cpu->current_tc) {

        tcst = &cpu->active_tc.CP0_TCStatus;

    } else {

        tcst = &cpu->tcs[tc].CP0_TCStatus;

    }

    *tcst &= ~mask;

    *tcst |= tcstatus;

    compute_hflags(cpu);

}

/* Called for updates to CP0_TCStatus.  */

static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,

                             target_ulong v)

{

    uint32_t status;

    uint32_t tcu, tmx, tasid, tksu;

    uint32_t mask = ((1 << CP0St_CU3)

                       | (1 << CP0St_CU2)

                       | (1 << CP0St_CU1)

                       | (1 << CP0St_CU0)

                       | (1 << CP0St_MX)

                       | (3 << CP0St_KSU));

    tcu = (v >> CP0TCSt_TCU0) & 0xf;

    tmx = (v >> CP0TCSt_TMX) & 0x1;

    tasid = v & 0xff;

    tksu = (v >> CP0TCSt_TKSU) & 0x3;

    status = tcu << CP0St_CU0;

    status |= tmx << CP0St_MX;

    status |= tksu << CP0St_KSU;

    cpu->CP0_Status &= ~mask;

    cpu->CP0_Status |= status;

    /* Sync the TASID with EntryHi.  */

    cpu->CP0_EntryHi &= ~0xff;

    cpu->CP0_EntryHi = tasid;

    compute_hflags(cpu);

}

/* Called for updates to CP0_EntryHi.  */

static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)

{

    int32_t *tcst;

    uint32_t asid, v = cpu->CP0_EntryHi;

    asid = v & 0xff;

    if (tc == cpu->current_tc) {

        tcst = &cpu->active_tc.CP0_TCStatus;

    } else {

        tcst = &cpu->tcs[tc].CP0_TCStatus;

    }

    *tcst &= ~0xff;

    *tcst |= asid;

}

/* CP0 helpers */

target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)

{

    return env->mvp->CP0_MVPControl;

}

target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)

{

    return env->mvp->CP0_MVPConf0;

}

target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)

{

    return env->mvp->CP0_MVPConf1;

}

target_ulong helper_mfc0_random(CPUMIPSState *env)

{

    return (int32_t)cpu_mips_get_random(env);

}

target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)

{

    return env->active_tc.CP0_TCStatus;

}

target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    if (other_tc == other->current_tc)

        return other->active_tc.CP0_TCStatus;

    else

        return other->tcs[other_tc].CP0_TCStatus;

}

target_ulong helper_mfc0_tcbind(CPUMIPSState *env)

{

    return env->active_tc.CP0_TCBind;

}

target_ulong helper_mftc0_tcbind(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    if (other_tc == other->current_tc)

        return other->active_tc.CP0_TCBind;

    else

        return other->tcs[other_tc].CP0_TCBind;

}

target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)

{

    return env->active_tc.PC;

}

target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    if (other_tc == other->current_tc)

        return other->active_tc.PC;

    else

        return other->tcs[other_tc].PC;

}

target_ulong helper_mfc0_tchalt(CPUMIPSState *env)

{

    return env->active_tc.CP0_TCHalt;

}

target_ulong helper_mftc0_tchalt(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    if (other_tc == other->current_tc)

        return other->active_tc.CP0_TCHalt;

    else

        return other->tcs[other_tc].CP0_TCHalt;

}

target_ulong helper_mfc0_tccontext(CPUMIPSState *env)

{

    return env->active_tc.CP0_TCContext;

}

target_ulong helper_mftc0_tccontext(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    if (other_tc == other->current_tc)

        return other->active_tc.CP0_TCContext;

    else

        return other->tcs[other_tc].CP0_TCContext;

}

target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)

{

    return env->active_tc.CP0_TCSchedule;

}

target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    if (other_tc == other->current_tc)

        return other->active_tc.CP0_TCSchedule;

    else

        return other->tcs[other_tc].CP0_TCSchedule;

}

target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)

{

    return env->active_tc.CP0_TCScheFBack;

}

target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    if (other_tc == other->current_tc)

        return other->active_tc.CP0_TCScheFBack;

    else

        return other->tcs[other_tc].CP0_TCScheFBack;

}

target_ulong helper_mfc0_count(CPUMIPSState *env)

{

    return (int32_t)cpu_mips_get_count(env);

}

target_ulong helper_mftc0_entryhi(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    return other->CP0_EntryHi;

}

target_ulong helper_mftc0_cause(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    int32_t tccause;

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    if (other_tc == other->current_tc) {

        tccause = other->CP0_Cause;

    } else {

        tccause = other->CP0_Cause;

    }

    return tccause;

}

target_ulong helper_mftc0_status(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    return other->CP0_Status;

}

target_ulong helper_mfc0_lladdr(CPUMIPSState *env)

{

    return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);

}

target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)

{

    return (int32_t)env->CP0_WatchLo[sel];

}

target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)

{

    return env->CP0_WatchHi[sel];

}

target_ulong helper_mfc0_debug(CPUMIPSState *env)

{

    target_ulong t0 = env->CP0_Debug;

    if (env->hflags & MIPS_HFLAG_DM)

        t0 |= 1 << CP0DB_DM;

    return t0;

}

target_ulong helper_mftc0_debug(CPUMIPSState *env)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    int32_t tcstatus;

    CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);

    if (other_tc == other->current_tc)

        tcstatus = other->active_tc.CP0_Debug_tcstatus;

    else

        tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;

    /* XXX: Might be wrong, check with EJTAG spec. */

    return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |

            (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));

}

#if defined(TARGET_MIPS64)

target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)

{

    return env->active_tc.PC;

}

target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)

{

    return env->active_tc.CP0_TCHalt;

}

target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)

{

    return env->active_tc.CP0_TCContext;

}