root / hw / spapr.c @ f28359d8
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/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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* Copyright (c) 2010 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "sysemu.h" |
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#include "hw.h" |
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#include "elf.h" |
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#include "net.h" |
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#include "blockdev.h" |
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#include "cpus.h" |
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#include "kvm.h" |
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#include "kvm_ppc.h" |
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#include "hw/boards.h" |
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#include "hw/ppc.h" |
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#include "hw/loader.h" |
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#include "hw/spapr.h" |
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#include "hw/spapr_vio.h" |
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#include "hw/spapr_pci.h" |
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#include "hw/xics.h" |
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#include "kvm.h" |
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#include "kvm_ppc.h" |
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#include "pci.h" |
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#include "vga-pci.h" |
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#include "exec-memory.h" |
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#include <libfdt.h> |
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/* SLOF memory layout:
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*
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* SLOF raw image loaded at 0, copies its romfs right below the flat
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* device-tree, then position SLOF itself 31M below that
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*
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* So we set FW_OVERHEAD to 40MB which should account for all of that
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* and more
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*
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* We load our kernel at 4M, leaving space for SLOF initial image
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*/
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#define FDT_MAX_SIZE 0x10000 |
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#define RTAS_MAX_SIZE 0x10000 |
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#define FW_MAX_SIZE 0x400000 |
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#define FW_FILE_NAME "slof.bin" |
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#define FW_OVERHEAD 0x2800000 |
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#define KERNEL_LOAD_ADDR FW_MAX_SIZE
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#define MIN_RMA_SLOF 128UL |
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#define TIMEBASE_FREQ 512000000ULL |
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#define MAX_CPUS 256 |
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#define XICS_IRQS 1024 |
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#define SPAPR_PCI_BUID 0x800000020000001ULL |
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#define SPAPR_PCI_MEM_WIN_ADDR (0x10000000000ULL + 0xA0000000) |
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#define SPAPR_PCI_MEM_WIN_SIZE 0x20000000 |
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#define SPAPR_PCI_IO_WIN_ADDR (0x10000000000ULL + 0x80000000) |
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#define PHANDLE_XICP 0x00001111 |
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sPAPREnvironment *spapr; |
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bool spapr_has_graphics;
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qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num, |
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enum xics_irq_type type)
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{ |
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uint32_t irq; |
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qemu_irq qirq; |
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if (hint) {
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irq = hint; |
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/* FIXME: we should probably check for collisions somehow */
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} else {
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irq = spapr->next_irq++; |
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} |
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qirq = xics_assign_irq(spapr->icp, irq, type); |
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if (!qirq) {
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return NULL; |
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} |
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if (irq_num) {
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*irq_num = irq; |
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} |
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return qirq;
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} |
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static int spapr_set_associativity(void *fdt, sPAPREnvironment *spapr) |
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{ |
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int ret = 0, offset; |
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CPUPPCState *env; |
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char cpu_model[32]; |
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int smt = kvmppc_smt_threads();
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assert(spapr->cpu_model); |
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for (env = first_cpu; env != NULL; env = env->next_cpu) { |
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uint32_t associativity[] = {cpu_to_be32(0x5),
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cpu_to_be32(0x0),
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cpu_to_be32(0x0),
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cpu_to_be32(0x0),
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cpu_to_be32(env->numa_node), |
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cpu_to_be32(env->cpu_index)}; |
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if ((env->cpu_index % smt) != 0) { |
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continue;
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} |
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snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model, |
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env->cpu_index); |
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offset = fdt_path_offset(fdt, cpu_model); |
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if (offset < 0) { |
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return offset;
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} |
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ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
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sizeof(associativity));
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if (ret < 0) { |
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return ret;
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} |
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} |
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return ret;
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} |
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static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
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size_t maxsize) |
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{ |
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size_t maxcells = maxsize / sizeof(uint32_t);
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int i, j, count;
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uint32_t *p = prop; |
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for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
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struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
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if (!sps->page_shift) {
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break;
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} |
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for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { |
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if (sps->enc[count].page_shift == 0) { |
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break;
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} |
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} |
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if ((p - prop) >= (maxcells - 3 - count * 2)) { |
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break;
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} |
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*(p++) = cpu_to_be32(sps->page_shift); |
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*(p++) = cpu_to_be32(sps->slb_enc); |
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*(p++) = cpu_to_be32(count); |
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for (j = 0; j < count; j++) { |
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*(p++) = cpu_to_be32(sps->enc[j].page_shift); |
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*(p++) = cpu_to_be32(sps->enc[j].pte_enc); |
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} |
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} |
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return (p - prop) * sizeof(uint32_t); |
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} |
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static void *spapr_create_fdt_skel(const char *cpu_model, |
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target_phys_addr_t rma_size, |
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target_phys_addr_t initrd_base, |
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target_phys_addr_t initrd_size, |
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target_phys_addr_t kernel_size, |
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const char *boot_device, |
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const char *kernel_cmdline, |
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long hash_shift)
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{ |
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void *fdt;
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CPUPPCState *env; |
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uint64_t mem_reg_property[2];
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uint32_t start_prop = cpu_to_be32(initrd_base); |
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uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); |
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uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
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char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" |
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"\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
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char qemu_hypertas_prop[] = "hcall-memop1"; |
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uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
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int i;
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char *modelname;
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int smt = kvmppc_smt_threads();
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unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; |
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uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; |
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uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), |
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cpu_to_be32(0x0), cpu_to_be32(0x0), |
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cpu_to_be32(0x0)};
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char mem_name[32]; |
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target_phys_addr_t node0_size, mem_start; |
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#define _FDT(exp) \
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do { \
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int ret = (exp); \
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if (ret < 0) { \ |
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fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
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#exp, fdt_strerror(ret)); \
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exit(1); \
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} \ |
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} while (0) |
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fdt = g_malloc0(FDT_MAX_SIZE); |
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_FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
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if (kernel_size) {
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_FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); |
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} |
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if (initrd_size) {
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_FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); |
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} |
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_FDT((fdt_finish_reservemap(fdt))); |
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/* Root node */
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_FDT((fdt_begin_node(fdt, "")));
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_FDT((fdt_property_string(fdt, "device_type", "chrp"))); |
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_FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
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_FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); |
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_FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); |
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/* /chosen */
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_FDT((fdt_begin_node(fdt, "chosen")));
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/* Set Form1_affinity */
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_FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); |
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_FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
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_FDT((fdt_property(fdt, "linux,initrd-start",
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&start_prop, sizeof(start_prop))));
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_FDT((fdt_property(fdt, "linux,initrd-end",
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&end_prop, sizeof(end_prop))));
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if (kernel_size) {
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uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
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cpu_to_be64(kernel_size) }; |
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_FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); |
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} |
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_FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
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_FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
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_FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
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_FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
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_FDT((fdt_end_node(fdt))); |
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/* memory node(s) */
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node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; |
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if (rma_size > node0_size) {
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rma_size = node0_size; |
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} |
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/* RMA */
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mem_reg_property[0] = 0; |
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mem_reg_property[1] = cpu_to_be64(rma_size);
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_FDT((fdt_begin_node(fdt, "memory@0")));
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_FDT((fdt_property_string(fdt, "device_type", "memory"))); |
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_FDT((fdt_property(fdt, "reg", mem_reg_property,
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sizeof(mem_reg_property))));
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_FDT((fdt_property(fdt, "ibm,associativity", associativity,
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sizeof(associativity))));
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_FDT((fdt_end_node(fdt))); |
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/* RAM: Node 0 */
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if (node0_size > rma_size) {
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mem_reg_property[0] = cpu_to_be64(rma_size);
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mem_reg_property[1] = cpu_to_be64(node0_size - rma_size);
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sprintf(mem_name, "memory@" TARGET_FMT_lx, rma_size);
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_FDT((fdt_begin_node(fdt, mem_name))); |
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_FDT((fdt_property_string(fdt, "device_type", "memory"))); |
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_FDT((fdt_property(fdt, "reg", mem_reg_property,
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sizeof(mem_reg_property))));
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_FDT((fdt_property(fdt, "ibm,associativity", associativity,
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sizeof(associativity))));
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_FDT((fdt_end_node(fdt))); |
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} |
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/* RAM: Node 1 and beyond */
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mem_start = node0_size; |
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for (i = 1; i < nb_numa_nodes; i++) { |
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mem_reg_property[0] = cpu_to_be64(mem_start);
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mem_reg_property[1] = cpu_to_be64(node_mem[i]);
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associativity[3] = associativity[4] = cpu_to_be32(i); |
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sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start);
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_FDT((fdt_begin_node(fdt, mem_name))); |
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_FDT((fdt_property_string(fdt, "device_type", "memory"))); |
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_FDT((fdt_property(fdt, "reg", mem_reg_property,
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sizeof(mem_reg_property))));
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_FDT((fdt_property(fdt, "ibm,associativity", associativity,
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sizeof(associativity))));
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_FDT((fdt_end_node(fdt))); |
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mem_start += node_mem[i]; |
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} |
316 |
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/* cpus */
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_FDT((fdt_begin_node(fdt, "cpus")));
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|
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_FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
321 |
_FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
322 |
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modelname = g_strdup(cpu_model); |
324 |
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for (i = 0; i < strlen(modelname); i++) { |
326 |
modelname[i] = toupper(modelname[i]); |
327 |
} |
328 |
|
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/* This is needed during FDT finalization */
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spapr->cpu_model = g_strdup(modelname); |
331 |
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for (env = first_cpu; env != NULL; env = env->next_cpu) { |
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int index = env->cpu_index;
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uint32_t servers_prop[smp_threads]; |
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uint32_t gservers_prop[smp_threads * 2];
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char *nodename;
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uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
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0xffffffff, 0xffffffff}; |
339 |
uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; |
340 |
uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
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uint32_t page_sizes_prop[64];
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size_t page_sizes_prop_size; |
343 |
|
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if ((index % smt) != 0) { |
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continue;
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} |
347 |
|
348 |
if (asprintf(&nodename, "%s@%x", modelname, index) < 0) { |
349 |
fprintf(stderr, "Allocation failure\n");
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exit(1);
|
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} |
352 |
|
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_FDT((fdt_begin_node(fdt, nodename))); |
354 |
|
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free(nodename); |
356 |
|
357 |
_FDT((fdt_property_cell(fdt, "reg", index)));
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_FDT((fdt_property_string(fdt, "device_type", "cpu"))); |
359 |
|
360 |
_FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
|
361 |
_FDT((fdt_property_cell(fdt, "dcache-block-size",
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env->dcache_line_size))); |
363 |
_FDT((fdt_property_cell(fdt, "icache-block-size",
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env->icache_line_size))); |
365 |
_FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
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_FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
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_FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
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368 |
_FDT((fdt_property(fdt, "ibm,pft-size",
|
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pft_size_prop, sizeof(pft_size_prop))));
|
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_FDT((fdt_property_string(fdt, "status", "okay"))); |
371 |
_FDT((fdt_property(fdt, "64-bit", NULL, 0))); |
372 |
|
373 |
/* Build interrupt servers and gservers properties */
|
374 |
for (i = 0; i < smp_threads; i++) { |
375 |
servers_prop[i] = cpu_to_be32(index + i); |
376 |
/* Hack, direct the group queues back to cpu 0 */
|
377 |
gservers_prop[i*2] = cpu_to_be32(index + i);
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gservers_prop[i*2 + 1] = 0; |
379 |
} |
380 |
_FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s",
|
381 |
servers_prop, sizeof(servers_prop))));
|
382 |
_FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
|
383 |
gservers_prop, sizeof(gservers_prop))));
|
384 |
|
385 |
if (env->mmu_model & POWERPC_MMU_1TSEG) {
|
386 |
_FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
|
387 |
segs, sizeof(segs))));
|
388 |
} |
389 |
|
390 |
/* Advertise VMX/VSX (vector extensions) if available
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* 0 / no property == no vector extensions
|
392 |
* 1 == VMX / Altivec available
|
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* 2 == VSX available */
|
394 |
if (env->insns_flags & PPC_ALTIVEC) {
|
395 |
uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; |
396 |
|
397 |
_FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
|
398 |
} |
399 |
|
400 |
/* Advertise DFP (Decimal Floating Point) if available
|
401 |
* 0 / no property == no DFP
|
402 |
* 1 == DFP available */
|
403 |
if (env->insns_flags2 & PPC2_DFP) {
|
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_FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); |
405 |
} |
406 |
|
407 |
page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, |
408 |
sizeof(page_sizes_prop));
|
409 |
if (page_sizes_prop_size) {
|
410 |
_FDT((fdt_property(fdt, "ibm,segment-page-sizes",
|
411 |
page_sizes_prop, page_sizes_prop_size))); |
412 |
} |
413 |
|
414 |
_FDT((fdt_end_node(fdt))); |
415 |
} |
416 |
|
417 |
g_free(modelname); |
418 |
|
419 |
_FDT((fdt_end_node(fdt))); |
420 |
|
421 |
/* RTAS */
|
422 |
_FDT((fdt_begin_node(fdt, "rtas")));
|
423 |
|
424 |
_FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
|
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sizeof(hypertas_prop))));
|
426 |
_FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop,
|
427 |
sizeof(qemu_hypertas_prop))));
|
428 |
|
429 |
_FDT((fdt_property(fdt, "ibm,associativity-reference-points",
|
430 |
refpoints, sizeof(refpoints))));
|
431 |
|
432 |
_FDT((fdt_end_node(fdt))); |
433 |
|
434 |
/* interrupt controller */
|
435 |
_FDT((fdt_begin_node(fdt, "interrupt-controller")));
|
436 |
|
437 |
_FDT((fdt_property_string(fdt, "device_type",
|
438 |
"PowerPC-External-Interrupt-Presentation")));
|
439 |
_FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); |
440 |
_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
441 |
_FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
|
442 |
interrupt_server_ranges_prop, |
443 |
sizeof(interrupt_server_ranges_prop))));
|
444 |
_FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); |
445 |
_FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
|
446 |
_FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
|
447 |
|
448 |
_FDT((fdt_end_node(fdt))); |
449 |
|
450 |
/* vdevice */
|
451 |
_FDT((fdt_begin_node(fdt, "vdevice")));
|
452 |
|
453 |
_FDT((fdt_property_string(fdt, "device_type", "vdevice"))); |
454 |
_FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); |
455 |
_FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
456 |
_FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
457 |
_FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
458 |
_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
459 |
|
460 |
_FDT((fdt_end_node(fdt))); |
461 |
|
462 |
_FDT((fdt_end_node(fdt))); /* close root node */
|
463 |
_FDT((fdt_finish(fdt))); |
464 |
|
465 |
return fdt;
|
466 |
} |
467 |
|
468 |
static void spapr_finalize_fdt(sPAPREnvironment *spapr, |
469 |
target_phys_addr_t fdt_addr, |
470 |
target_phys_addr_t rtas_addr, |
471 |
target_phys_addr_t rtas_size) |
472 |
{ |
473 |
int ret;
|
474 |
void *fdt;
|
475 |
sPAPRPHBState *phb; |
476 |
|
477 |
fdt = g_malloc(FDT_MAX_SIZE); |
478 |
|
479 |
/* open out the base tree into a temp buffer for the final tweaks */
|
480 |
_FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); |
481 |
|
482 |
ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
483 |
if (ret < 0) { |
484 |
fprintf(stderr, "couldn't setup vio devices in fdt\n");
|
485 |
exit(1);
|
486 |
} |
487 |
|
488 |
QLIST_FOREACH(phb, &spapr->phbs, list) { |
489 |
ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
490 |
} |
491 |
|
492 |
if (ret < 0) { |
493 |
fprintf(stderr, "couldn't setup PCI devices in fdt\n");
|
494 |
exit(1);
|
495 |
} |
496 |
|
497 |
/* RTAS */
|
498 |
ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); |
499 |
if (ret < 0) { |
500 |
fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
|
501 |
} |
502 |
|
503 |
/* Advertise NUMA via ibm,associativity */
|
504 |
if (nb_numa_nodes > 1) { |
505 |
ret = spapr_set_associativity(fdt, spapr); |
506 |
if (ret < 0) { |
507 |
fprintf(stderr, "Couldn't set up NUMA device tree properties\n");
|
508 |
} |
509 |
} |
510 |
|
511 |
if (!spapr_has_graphics) {
|
512 |
spapr_populate_chosen_stdout(fdt, spapr->vio_bus); |
513 |
} |
514 |
|
515 |
_FDT((fdt_pack(fdt))); |
516 |
|
517 |
if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
|
518 |
hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
|
519 |
fdt_totalsize(fdt), FDT_MAX_SIZE); |
520 |
exit(1);
|
521 |
} |
522 |
|
523 |
cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
524 |
|
525 |
g_free(fdt); |
526 |
} |
527 |
|
528 |
static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
529 |
{ |
530 |
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; |
531 |
} |
532 |
|
533 |
static void emulate_spapr_hypercall(CPUPPCState *env) |
534 |
{ |
535 |
env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); |
536 |
} |
537 |
|
538 |
static void spapr_reset(void *opaque) |
539 |
{ |
540 |
sPAPREnvironment *spapr = (sPAPREnvironment *)opaque; |
541 |
|
542 |
fprintf(stderr, "sPAPR reset\n");
|
543 |
|
544 |
/* flush out the hash table */
|
545 |
memset(spapr->htab, 0, spapr->htab_size);
|
546 |
|
547 |
/* Load the fdt */
|
548 |
spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, |
549 |
spapr->rtas_size); |
550 |
|
551 |
/* Set up the entry state */
|
552 |
first_cpu->gpr[3] = spapr->fdt_addr;
|
553 |
first_cpu->gpr[5] = 0; |
554 |
first_cpu->halted = 0;
|
555 |
first_cpu->nip = spapr->entry_point; |
556 |
|
557 |
} |
558 |
|
559 |
static void spapr_cpu_reset(void *opaque) |
560 |
{ |
561 |
PowerPCCPU *cpu = opaque; |
562 |
|
563 |
cpu_reset(CPU(cpu)); |
564 |
} |
565 |
|
566 |
static int spapr_vga_init(PCIBus *pci_bus) |
567 |
{ |
568 |
if (std_vga_enabled) {
|
569 |
pci_vga_init(pci_bus); |
570 |
} else {
|
571 |
fprintf(stderr, "This vga model is not supported,"
|
572 |
"currently it only supports -vga std\n");
|
573 |
return 0; |
574 |
} |
575 |
return 1; |
576 |
} |
577 |
|
578 |
/* pSeries LPAR / sPAPR hardware init */
|
579 |
static void ppc_spapr_init(ram_addr_t ram_size, |
580 |
const char *boot_device, |
581 |
const char *kernel_filename, |
582 |
const char *kernel_cmdline, |
583 |
const char *initrd_filename, |
584 |
const char *cpu_model) |
585 |
{ |
586 |
PowerPCCPU *cpu; |
587 |
CPUPPCState *env; |
588 |
int i;
|
589 |
MemoryRegion *sysmem = get_system_memory(); |
590 |
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
591 |
target_phys_addr_t rma_alloc_size, rma_size; |
592 |
uint32_t initrd_base = 0;
|
593 |
long kernel_size = 0, initrd_size = 0; |
594 |
long load_limit, rtas_limit, fw_size;
|
595 |
long pteg_shift = 17; |
596 |
char *filename;
|
597 |
|
598 |
spapr = g_malloc0(sizeof(*spapr));
|
599 |
QLIST_INIT(&spapr->phbs); |
600 |
|
601 |
cpu_ppc_hypercall = emulate_spapr_hypercall; |
602 |
|
603 |
/* Allocate RMA if necessary */
|
604 |
rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem);
|
605 |
|
606 |
if (rma_alloc_size == -1) { |
607 |
hw_error("qemu: Unable to create RMA\n");
|
608 |
exit(1);
|
609 |
} |
610 |
if (rma_alloc_size && (rma_alloc_size < ram_size)) {
|
611 |
rma_size = rma_alloc_size; |
612 |
} else {
|
613 |
rma_size = ram_size; |
614 |
} |
615 |
|
616 |
/* We place the device tree and RTAS just below either the top of the RMA,
|
617 |
* or just below 2GB, whichever is lowere, so that it can be
|
618 |
* processed with 32-bit real mode code if necessary */
|
619 |
rtas_limit = MIN(rma_size, 0x80000000);
|
620 |
spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
621 |
spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; |
622 |
load_limit = spapr->fdt_addr - FW_OVERHEAD; |
623 |
|
624 |
/* init CPUs */
|
625 |
if (cpu_model == NULL) { |
626 |
cpu_model = kvm_enabled() ? "host" : "POWER7"; |
627 |
} |
628 |
for (i = 0; i < smp_cpus; i++) { |
629 |
cpu = cpu_ppc_init(cpu_model); |
630 |
if (cpu == NULL) { |
631 |
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
632 |
exit(1);
|
633 |
} |
634 |
env = &cpu->env; |
635 |
|
636 |
/* Set time-base frequency to 512 MHz */
|
637 |
cpu_ppc_tb_init(env, TIMEBASE_FREQ); |
638 |
qemu_register_reset(spapr_cpu_reset, cpu); |
639 |
|
640 |
env->hreset_vector = 0x60;
|
641 |
env->hreset_excp_prefix = 0;
|
642 |
env->gpr[3] = env->cpu_index;
|
643 |
} |
644 |
|
645 |
/* allocate RAM */
|
646 |
spapr->ram_limit = ram_size; |
647 |
if (spapr->ram_limit > rma_alloc_size) {
|
648 |
ram_addr_t nonrma_base = rma_alloc_size; |
649 |
ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; |
650 |
|
651 |
memory_region_init_ram(ram, "ppc_spapr.ram", nonrma_size);
|
652 |
vmstate_register_ram_global(ram); |
653 |
memory_region_add_subregion(sysmem, nonrma_base, ram); |
654 |
} |
655 |
|
656 |
/* allocate hash page table. For now we always make this 16mb,
|
657 |
* later we should probably make it scale to the size of guest
|
658 |
* RAM */
|
659 |
spapr->htab_size = 1ULL << (pteg_shift + 7); |
660 |
spapr->htab = qemu_memalign(spapr->htab_size, spapr->htab_size); |
661 |
|
662 |
for (env = first_cpu; env != NULL; env = env->next_cpu) { |
663 |
env->external_htab = spapr->htab; |
664 |
env->htab_base = -1;
|
665 |
env->htab_mask = spapr->htab_size - 1;
|
666 |
|
667 |
/* Tell KVM that we're in PAPR mode */
|
668 |
env->spr[SPR_SDR1] = (unsigned long)spapr->htab | |
669 |
((pteg_shift + 7) - 18); |
670 |
env->spr[SPR_HIOR] = 0;
|
671 |
|
672 |
if (kvm_enabled()) {
|
673 |
kvmppc_set_papr(env); |
674 |
} |
675 |
} |
676 |
|
677 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
|
678 |
spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, |
679 |
rtas_limit - spapr->rtas_addr); |
680 |
if (spapr->rtas_size < 0) { |
681 |
hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
|
682 |
exit(1);
|
683 |
} |
684 |
if (spapr->rtas_size > RTAS_MAX_SIZE) {
|
685 |
hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
|
686 |
spapr->rtas_size, RTAS_MAX_SIZE); |
687 |
exit(1);
|
688 |
} |
689 |
g_free(filename); |
690 |
|
691 |
|
692 |
/* Set up Interrupt Controller */
|
693 |
spapr->icp = xics_system_init(XICS_IRQS); |
694 |
spapr->next_irq = 16;
|
695 |
|
696 |
/* Set up IOMMU */
|
697 |
spapr_iommu_init(); |
698 |
|
699 |
/* Set up VIO bus */
|
700 |
spapr->vio_bus = spapr_vio_bus_init(); |
701 |
|
702 |
for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
703 |
if (serial_hds[i]) {
|
704 |
spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
705 |
} |
706 |
} |
707 |
|
708 |
/* Set up PCI */
|
709 |
spapr_create_phb(spapr, "pci", SPAPR_PCI_BUID,
|
710 |
SPAPR_PCI_MEM_WIN_ADDR, |
711 |
SPAPR_PCI_MEM_WIN_SIZE, |
712 |
SPAPR_PCI_IO_WIN_ADDR); |
713 |
|
714 |
for (i = 0; i < nb_nics; i++) { |
715 |
NICInfo *nd = &nd_table[i]; |
716 |
|
717 |
if (!nd->model) {
|
718 |
nd->model = g_strdup("ibmveth");
|
719 |
} |
720 |
|
721 |
if (strcmp(nd->model, "ibmveth") == 0) { |
722 |
spapr_vlan_create(spapr->vio_bus, nd); |
723 |
} else {
|
724 |
pci_nic_init_nofail(&nd_table[i], nd->model, NULL);
|
725 |
} |
726 |
} |
727 |
|
728 |
for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
729 |
spapr_vscsi_create(spapr->vio_bus); |
730 |
} |
731 |
|
732 |
/* Graphics */
|
733 |
if (spapr_vga_init(QLIST_FIRST(&spapr->phbs)->host_state.bus)) {
|
734 |
spapr_has_graphics = true;
|
735 |
} |
736 |
|
737 |
if (rma_size < (MIN_RMA_SLOF << 20)) { |
738 |
fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
|
739 |
"%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
|
740 |
exit(1);
|
741 |
} |
742 |
|
743 |
fprintf(stderr, "sPAPR memory map:\n");
|
744 |
fprintf(stderr, "RTAS : 0x%08lx..%08lx\n",
|
745 |
(unsigned long)spapr->rtas_addr, |
746 |
(unsigned long)(spapr->rtas_addr + spapr->rtas_size - 1)); |
747 |
fprintf(stderr, "FDT : 0x%08lx..%08lx\n",
|
748 |
(unsigned long)spapr->fdt_addr, |
749 |
(unsigned long)(spapr->fdt_addr + FDT_MAX_SIZE - 1)); |
750 |
|
751 |
if (kernel_filename) {
|
752 |
uint64_t lowaddr = 0;
|
753 |
|
754 |
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
|
755 |
NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); |
756 |
if (kernel_size < 0) { |
757 |
kernel_size = load_image_targphys(kernel_filename, |
758 |
KERNEL_LOAD_ADDR, |
759 |
load_limit - KERNEL_LOAD_ADDR); |
760 |
} |
761 |
if (kernel_size < 0) { |
762 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
763 |
kernel_filename); |
764 |
exit(1);
|
765 |
} |
766 |
fprintf(stderr, "Kernel : 0x%08x..%08lx\n",
|
767 |
KERNEL_LOAD_ADDR, KERNEL_LOAD_ADDR + kernel_size - 1);
|
768 |
|
769 |
/* load initrd */
|
770 |
if (initrd_filename) {
|
771 |
/* Try to locate the initrd in the gap between the kernel
|
772 |
* and the firmware. Add a bit of space just in case
|
773 |
*/
|
774 |
initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; |
775 |
initrd_size = load_image_targphys(initrd_filename, initrd_base, |
776 |
load_limit - initrd_base); |
777 |
if (initrd_size < 0) { |
778 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
779 |
initrd_filename); |
780 |
exit(1);
|
781 |
} |
782 |
fprintf(stderr, "Ramdisk : 0x%08lx..%08lx\n",
|
783 |
(long)initrd_base, (long)(initrd_base + initrd_size - 1)); |
784 |
} else {
|
785 |
initrd_base = 0;
|
786 |
initrd_size = 0;
|
787 |
} |
788 |
} |
789 |
|
790 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME); |
791 |
fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
|
792 |
if (fw_size < 0) { |
793 |
hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
|
794 |
exit(1);
|
795 |
} |
796 |
g_free(filename); |
797 |
fprintf(stderr, "Firmware load : 0x%08x..%08lx\n",
|
798 |
0, fw_size);
|
799 |
fprintf(stderr, "Firmware runtime : 0x%08lx..%08lx\n",
|
800 |
load_limit, (unsigned long)spapr->fdt_addr); |
801 |
|
802 |
spapr->entry_point = 0x100;
|
803 |
|
804 |
/* SLOF will startup the secondary CPUs using RTAS */
|
805 |
for (env = first_cpu; env != NULL; env = env->next_cpu) { |
806 |
env->halted = 1;
|
807 |
} |
808 |
|
809 |
/* Prepare the device tree */
|
810 |
spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, rma_size, |
811 |
initrd_base, initrd_size, |
812 |
kernel_size, |
813 |
boot_device, kernel_cmdline, |
814 |
pteg_shift + 7);
|
815 |
assert(spapr->fdt_skel != NULL);
|
816 |
|
817 |
qemu_register_reset(spapr_reset, spapr); |
818 |
} |
819 |
|
820 |
static QEMUMachine spapr_machine = {
|
821 |
.name = "pseries",
|
822 |
.desc = "pSeries Logical Partition (PAPR compliant)",
|
823 |
.init = ppc_spapr_init, |
824 |
.max_cpus = MAX_CPUS, |
825 |
.no_parallel = 1,
|
826 |
.use_scsi = 1,
|
827 |
}; |
828 |
|
829 |
static void spapr_machine_init(void) |
830 |
{ |
831 |
qemu_register_machine(&spapr_machine); |
832 |
} |
833 |
|
834 |
machine_init(spapr_machine_init); |