Archipelago » qemu

    int access_type; /* when a memory exception occurs, the access

                        type is stored here */

    /* Address space register */

    target_ulong asr;

    /* segment registers */

    target_ulong sdr1;

    target_ulong sr[16];

    int nb_BATs;

    target_ulong DBAT[2][8];

    target_ulong IBAT[2][8];

    /* Other registers */

    /* Special purpose registers */

    target_ulong spr[1024];

    /* Altivec registers */

    ppc_avr_t avr[32];

    uint32_t vscr;

    /* SPE registers */

    ppc_gpr_t spe_acc;

    float_status spe_status;

    uint32_t spe_fscr;

    /* Internal devices resources */

    /* Time base and decrementer */

    /* Device control registers */

    ppc_dcr_t *dcr_env;

    int dcache_line_size;

    int icache_line_size;

    /* Those resources are used only during code translation */

    /* Next instruction pointer */

    target_ulong nip;

    /* opcode handlers */

    opc_handler_t *opcodes[0x40];

        if ((i & (RFPL - 1)) == (RFPL - 1))

            cpu_fprintf(f, "\n");

    }

    cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX "         " FILL FILL FILL

                "SDR1 " REGX "\n",

                env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);

#undef RGPL

#undef RFPL

/* BATs 0-3 */

static void gen_low_BATs (CPUPPCState *env)

{

    spr_register(env, SPR_IBAT0U, "IBAT0U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat, &spr_write_ibatu,

                 &spr_read_dbat, &spr_write_dbatl,

                 0x00000000);

    env->nb_BATs += 4;

}

/* BATs 4-7 */

static void gen_high_BATs (CPUPPCState *env)

{

    spr_register(env, SPR_IBAT4U, "IBAT4U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_ibat_h, &spr_write_ibatu_h,

                 &spr_read_dbat_h, &spr_write_dbatl_h,

                 0x00000000);

    env->nb_BATs += 4;

}

/* Generic PowerPC time base */

/* Softare table search registers */

static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)

{

    env->nb_tlb = nb_tlbs;

    env->nb_ways = nb_ways;

    env->id_tlbs = 1;

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

}

/* SPR common to MPC755 and G2 */

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Memory management */

    spr_register(env, SPR_IBAT0U, "IBAT0U",

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_601_ubat, &spr_write_601_ubatu,

                 &spr_read_601_ubat, &spr_write_601_ubatl,

                 0x00000000);

    env->nb_BATs = 4;

}

static void gen_spr_74xx (CPUPPCState *env)

static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)

{

    env->nb_tlb = nb_tlbs;

    env->nb_ways = nb_ways;

    env->id_tlbs = 1;

                 SPR_NOACCESS, SPR_NOACCESS,

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

}

/* PowerPC BookE SPR */

/* FSL storage control registers */

static void gen_spr_BookE_FSL (CPUPPCState *env)

{

    /* TLB assist registers */

    /* XXX : not implemented */

    spr_register(env, SPR_BOOKE_MAS0, "MAS0",

    default:

        break;

    }

}

/* SPR specific to PowerPC 440 implementation */

    gen_spr_401x2(env);

    gen_spr_compress(env);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_4xx_softmmu(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

    gen_spr_401x2(env);

    gen_spr_compress(env);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_4xx_softmmu(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_4xx_softmmu(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_4xx_softmmu(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_BookE(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

    gen_spr_BookE(env);

    gen_spr_440(env);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_BookE(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

    gen_spr_BookE(env);

    gen_spr_440(env);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_BookE(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_BookE(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_BookE(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_BookE(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

    gen_spr_BookE(env);

    /* Memory management */

    gen_spr_BookE_FSL(env);

    env->nb_tlb = 64;

    env->nb_ways = 1;

    env->id_tlbs = 0;

    init_excp_BookE(env);

    env->dcache_line_size = 32;

    env->icache_line_size = 32;

                 &spr_read_generic, &spr_write_generic,

                 0x00000000);

    /* Memory management */

    env->nb_tlb = 64;

    env->nb_ways = 2;

    env->id_tlbs = 0;

    init_excp_601(env);

    env->dcache_line_size = 64;

    env->icache_line_size = 64;

#if !defined(CONFIG_USER_ONLY)

    env->excp_prefix = 0xFFF00000;

#endif

    env->slb_nr = 32;

    init_excp_970(env);

    env->dcache_line_size = 128;

    env->icache_line_size = 128;

#if !defined(CONFIG_USER_ONLY)

    env->excp_prefix = 0xFFF00000;

#endif

    env->slb_nr = 32;

    init_excp_970(env);

    env->dcache_line_size = 128;

    env->icache_line_size = 128;

#if !defined(CONFIG_USER_ONLY)

    env->excp_prefix = 0xFFF00000;

#endif

    env->slb_nr = 32;

    init_excp_970(env);

    env->dcache_line_size = 128;

    env->icache_line_size = 128;

    env->excp_prefix = 0x00000000;

    env->ivor_mask = 0x00000000;

    env->ivpr_mask = 0x00000000;

    /* Default MMU definitions */

    env->nb_BATs = 0;

    env->nb_tlb = 0;

    env->nb_ways = 0;

    /* Register SPR common to all PowerPC implementations */

    gen_spr_generic(env);

    spr_register(env, SPR_PVR, "PVR",

    /* PowerPC implementation specific initialisations (SPRs, timers, ...) */

    (*def->init_proc)(env);

    /* Allocate TLBs buffer when needed */

    if (env->nb_tlb != 0) {

        int nb_tlb = env->nb_tlb;

        if (env->id_tlbs != 0)

        /* Pre-compute some useful values */

        env->tlb_per_way = env->nb_tlb / env->nb_ways;

    }

    if (env->irq_inputs == NULL) {

        fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"

                " Attempt Qemu to crash very soon !\n");

        printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"

               "    MMU model        : %s\n",

               def->name, def->pvr, def->msr_mask, mmu_model);

        if (env->tlb != NULL) {

            printf("                       %d %s TLB in %d ways\n",

                   env->nb_tlb, env->id_tlbs ? "splitted" : "merged",

                   env->nb_ways);

        }

        printf("    Exceptions model : %s\n"

               "    Bus model        : %s\n",

               excp_model, bus_model);