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1 | 05c2a3e7 | bellard | /*
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2 | 05c2a3e7 | bellard | * KQEMU header
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3 | da260249 | bellard | *
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4 | da260249 | bellard | * Copyright (c) 2004-2008 Fabrice Bellard
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5 | da260249 | bellard | *
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6 | 05c2a3e7 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 05c2a3e7 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 05c2a3e7 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 05c2a3e7 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 05c2a3e7 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 05c2a3e7 | bellard | * furnished to do so, subject to the following conditions:
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12 | 05c2a3e7 | bellard | *
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13 | 05c2a3e7 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 05c2a3e7 | bellard | * all copies or substantial portions of the Software.
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15 | 05c2a3e7 | bellard | *
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16 | 05c2a3e7 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 05c2a3e7 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 05c2a3e7 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 05c2a3e7 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 05c2a3e7 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 05c2a3e7 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 05c2a3e7 | bellard | * THE SOFTWARE.
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23 | 05c2a3e7 | bellard | */
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24 | 05c2a3e7 | bellard | #ifndef KQEMU_H
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25 | 05c2a3e7 | bellard | #define KQEMU_H
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26 | 05c2a3e7 | bellard | |
27 | da260249 | bellard | #if defined(__i386__)
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28 | da260249 | bellard | #define KQEMU_PAD32(x) x
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29 | da260249 | bellard | #else
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30 | da260249 | bellard | #define KQEMU_PAD32(x)
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31 | da260249 | bellard | #endif
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32 | da260249 | bellard | |
33 | da260249 | bellard | #define KQEMU_VERSION 0x010400 |
34 | 05c2a3e7 | bellard | |
35 | 05c2a3e7 | bellard | struct kqemu_segment_cache {
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36 | da260249 | bellard | uint16_t selector; |
37 | da260249 | bellard | uint16_t padding1; |
38 | 05c2a3e7 | bellard | uint32_t flags; |
39 | da260249 | bellard | uint64_t base; |
40 | da260249 | bellard | uint32_t limit; |
41 | da260249 | bellard | uint32_t padding2; |
42 | 05c2a3e7 | bellard | }; |
43 | 05c2a3e7 | bellard | |
44 | 05c2a3e7 | bellard | struct kqemu_cpu_state {
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45 | da260249 | bellard | uint64_t regs[16];
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46 | da260249 | bellard | uint64_t eip; |
47 | da260249 | bellard | uint64_t eflags; |
48 | 05c2a3e7 | bellard | |
49 | 05c2a3e7 | bellard | struct kqemu_segment_cache segs[6]; /* selector values */ |
50 | 05c2a3e7 | bellard | struct kqemu_segment_cache ldt;
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51 | 05c2a3e7 | bellard | struct kqemu_segment_cache tr;
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52 | 05c2a3e7 | bellard | struct kqemu_segment_cache gdt; /* only base and limit are used */ |
53 | 05c2a3e7 | bellard | struct kqemu_segment_cache idt; /* only base and limit are used */ |
54 | 05c2a3e7 | bellard | |
55 | da260249 | bellard | uint64_t cr0; |
56 | da260249 | bellard | uint64_t cr2; |
57 | da260249 | bellard | uint64_t cr3; |
58 | da260249 | bellard | uint64_t cr4; |
59 | da260249 | bellard | uint64_t a20_mask; |
60 | 05c2a3e7 | bellard | |
61 | 05c2a3e7 | bellard | /* sysenter registers */
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62 | da260249 | bellard | uint64_t sysenter_cs; |
63 | da260249 | bellard | uint64_t sysenter_esp; |
64 | da260249 | bellard | uint64_t sysenter_eip; |
65 | da260249 | bellard | uint64_t efer; |
66 | 05c2a3e7 | bellard | uint64_t star; |
67 | da260249 | bellard | |
68 | da260249 | bellard | uint64_t lstar; |
69 | da260249 | bellard | uint64_t cstar; |
70 | da260249 | bellard | uint64_t fmask; |
71 | da260249 | bellard | uint64_t kernelgsbase; |
72 | da260249 | bellard | |
73 | 05c2a3e7 | bellard | uint64_t tsc_offset; |
74 | 05c2a3e7 | bellard | |
75 | da260249 | bellard | uint64_t dr0; |
76 | da260249 | bellard | uint64_t dr1; |
77 | da260249 | bellard | uint64_t dr2; |
78 | da260249 | bellard | uint64_t dr3; |
79 | da260249 | bellard | uint64_t dr6; |
80 | da260249 | bellard | uint64_t dr7; |
81 | 05c2a3e7 | bellard | |
82 | 05c2a3e7 | bellard | uint8_t cpl; |
83 | 05c2a3e7 | bellard | uint8_t user_only; |
84 | da260249 | bellard | uint16_t padding1; |
85 | 05c2a3e7 | bellard | |
86 | 05c2a3e7 | bellard | uint32_t error_code; /* error_code when exiting with an exception */
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87 | da260249 | bellard | uint64_t next_eip; /* next eip value when exiting with an interrupt */
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88 | da260249 | bellard | uint32_t nb_pages_to_flush; /* number of pages to flush,
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89 | 05c2a3e7 | bellard | KQEMU_FLUSH_ALL means full flush */
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90 | 05c2a3e7 | bellard | #define KQEMU_MAX_PAGES_TO_FLUSH 512 |
91 | 05c2a3e7 | bellard | #define KQEMU_FLUSH_ALL (KQEMU_MAX_PAGES_TO_FLUSH + 1) |
92 | 05c2a3e7 | bellard | |
93 | da260249 | bellard | int32_t retval; |
94 | 05c2a3e7 | bellard | |
95 | 05c2a3e7 | bellard | /* number of ram_dirty entries to update */
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96 | da260249 | bellard | uint32_t nb_ram_pages_to_update; |
97 | 05c2a3e7 | bellard | #define KQEMU_MAX_RAM_PAGES_TO_UPDATE 512 |
98 | 05c2a3e7 | bellard | #define KQEMU_RAM_PAGES_UPDATE_ALL (KQEMU_MAX_RAM_PAGES_TO_UPDATE + 1) |
99 | 05c2a3e7 | bellard | |
100 | 05c2a3e7 | bellard | #define KQEMU_MAX_MODIFIED_RAM_PAGES 512 |
101 | da260249 | bellard | uint32_t nb_modified_ram_pages; |
102 | 05c2a3e7 | bellard | }; |
103 | 05c2a3e7 | bellard | |
104 | 05c2a3e7 | bellard | struct kqemu_init {
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105 | 05c2a3e7 | bellard | uint8_t *ram_base; /* must be page aligned */
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106 | da260249 | bellard | KQEMU_PAD32(uint32_t padding1;) |
107 | da260249 | bellard | uint64_t ram_size; /* must be multiple of 4 KB */
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108 | 05c2a3e7 | bellard | uint8_t *ram_dirty; /* must be page aligned */
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109 | da260249 | bellard | KQEMU_PAD32(uint32_t padding2;) |
110 | da260249 | bellard | uint64_t *pages_to_flush; /* must be page aligned */
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111 | da260249 | bellard | KQEMU_PAD32(uint32_t padding4;) |
112 | da260249 | bellard | uint64_t *ram_pages_to_update; /* must be page aligned */
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113 | da260249 | bellard | KQEMU_PAD32(uint32_t padding5;) |
114 | da260249 | bellard | uint64_t *modified_ram_pages; /* must be page aligned */
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115 | da260249 | bellard | KQEMU_PAD32(uint32_t padding6;) |
116 | da260249 | bellard | }; |
117 | da260249 | bellard | |
118 | da260249 | bellard | #define KQEMU_IO_MEM_RAM 0 |
119 | da260249 | bellard | #define KQEMU_IO_MEM_ROM 1 |
120 | da260249 | bellard | #define KQEMU_IO_MEM_COMM 2 /* kqemu communication page */ |
121 | da260249 | bellard | #define KQEMU_IO_MEM_UNASSIGNED 3 /* any device: return to application */ |
122 | da260249 | bellard | |
123 | da260249 | bellard | struct kqemu_phys_mem {
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124 | da260249 | bellard | uint64_t phys_addr; /* physical address range: phys_addr,
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125 | da260249 | bellard | phys_addr + size */
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126 | da260249 | bellard | uint64_t size; |
127 | da260249 | bellard | uint64_t ram_addr; /* corresponding ram address */
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128 | da260249 | bellard | uint32_t io_index; /* memory type: see KQEMU_IO_MEM_xxx */
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129 | da260249 | bellard | uint32_t padding1; |
130 | 05c2a3e7 | bellard | }; |
131 | 05c2a3e7 | bellard | |
132 | 05c2a3e7 | bellard | #define KQEMU_RET_ABORT (-1) |
133 | 05c2a3e7 | bellard | #define KQEMU_RET_EXCEPTION 0x0000 /* 8 low order bit are the exception */ |
134 | 05c2a3e7 | bellard | #define KQEMU_RET_INT 0x0100 /* 8 low order bit are the interrupt */ |
135 | 05c2a3e7 | bellard | #define KQEMU_RET_SOFTMMU 0x0200 /* emulation needed (I/O or |
136 | 05c2a3e7 | bellard | unsupported INSN) */
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137 | 05c2a3e7 | bellard | #define KQEMU_RET_INTR 0x0201 /* interrupted by a signal */ |
138 | 05c2a3e7 | bellard | #define KQEMU_RET_SYSCALL 0x0300 /* syscall insn */ |
139 | 05c2a3e7 | bellard | |
140 | 05c2a3e7 | bellard | #ifdef _WIN32
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141 | 05c2a3e7 | bellard | #define KQEMU_EXEC CTL_CODE(FILE_DEVICE_UNKNOWN, 1, METHOD_BUFFERED, FILE_READ_ACCESS | FILE_WRITE_ACCESS) |
142 | 05c2a3e7 | bellard | #define KQEMU_INIT CTL_CODE(FILE_DEVICE_UNKNOWN, 2, METHOD_BUFFERED, FILE_WRITE_ACCESS) |
143 | 05c2a3e7 | bellard | #define KQEMU_GET_VERSION CTL_CODE(FILE_DEVICE_UNKNOWN, 3, METHOD_BUFFERED, FILE_READ_ACCESS) |
144 | 05c2a3e7 | bellard | #define KQEMU_MODIFY_RAM_PAGES CTL_CODE(FILE_DEVICE_UNKNOWN, 4, METHOD_BUFFERED, FILE_WRITE_ACCESS) |
145 | da260249 | bellard | #define KQEMU_SET_PHYS_MEM CTL_CODE(FILE_DEVICE_UNKNOWN, 5, METHOD_BUFFERED, FILE_WRITE_ACCESS) |
146 | 05c2a3e7 | bellard | #else
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147 | 05c2a3e7 | bellard | #define KQEMU_EXEC _IOWR('q', 1, struct kqemu_cpu_state) |
148 | 05c2a3e7 | bellard | #define KQEMU_INIT _IOW('q', 2, struct kqemu_init) |
149 | 05c2a3e7 | bellard | #define KQEMU_GET_VERSION _IOR('q', 3, int) |
150 | 05c2a3e7 | bellard | #define KQEMU_MODIFY_RAM_PAGES _IOW('q', 4, int) |
151 | da260249 | bellard | #define KQEMU_SET_PHYS_MEM _IOW('q', 5, struct kqemu_phys_mem) |
152 | 05c2a3e7 | bellard | #endif
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153 | 05c2a3e7 | bellard | |
154 | 05c2a3e7 | bellard | #endif /* KQEMU_H */ |