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1 | 8f860bb8 | ths | /* s390-dis.c -- Disassemble S390 instructions
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2 | a4fc08ff | ths | Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
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3 | 8f860bb8 | ths | Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
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4 | 8f860bb8 | ths | |
5 | a4fc08ff | ths | This file is part of GDB, GAS and the GNU binutils.
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6 | 8f860bb8 | ths | |
7 | a4fc08ff | ths | This program is free software; you can redistribute it and/or modify
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8 | 8f860bb8 | ths | it under the terms of the GNU General Public License as published by
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9 | a4fc08ff | ths | the Free Software Foundation; either version 2 of the License, or
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10 | a4fc08ff | ths | (at your option) any later version.
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11 | 8f860bb8 | ths | |
12 | a4fc08ff | ths | This program is distributed in the hope that it will be useful,
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13 | a4fc08ff | ths | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | a4fc08ff | ths | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | a4fc08ff | ths | GNU General Public License for more details.
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16 | 8f860bb8 | ths | |
17 | 8f860bb8 | ths | You should have received a copy of the GNU General Public License
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18 | a4fc08ff | ths | along with this program; if not, write to the Free Software
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19 | a4fc08ff | ths | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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20 | a4fc08ff | ths | 02110-1301, USA. */
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21 | 8f860bb8 | ths | |
22 | 8f860bb8 | ths | #include <stdio.h> |
23 | 8f860bb8 | ths | #include "dis-asm.h" |
24 | 8f860bb8 | ths | |
25 | 8f860bb8 | ths | /* s390.h -- Header file for S390 opcode table
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26 | 8f860bb8 | ths | Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
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27 | 8f860bb8 | ths | Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
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28 | 8f860bb8 | ths | |
29 | 8f860bb8 | ths | This file is part of BFD, the Binary File Descriptor library.
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30 | 8f860bb8 | ths | |
31 | 8f860bb8 | ths | This program is free software; you can redistribute it and/or modify
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32 | 8f860bb8 | ths | it under the terms of the GNU General Public License as published by
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33 | 8f860bb8 | ths | the Free Software Foundation; either version 2 of the License, or
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34 | 8f860bb8 | ths | (at your option) any later version.
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35 | 8f860bb8 | ths | |
36 | 8f860bb8 | ths | This program is distributed in the hope that it will be useful,
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37 | 8f860bb8 | ths | but WITHOUT ANY WARRANTY; without even the implied warranty of
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38 | 8f860bb8 | ths | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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39 | 8f860bb8 | ths | GNU General Public License for more details.
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40 | 8f860bb8 | ths | |
41 | 8f860bb8 | ths | You should have received a copy of the GNU General Public License
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42 | 8f860bb8 | ths | along with this program; if not, write to the Free Software
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43 | 8f860bb8 | ths | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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44 | 8f860bb8 | ths | 02110-1301, USA. */
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45 | 8f860bb8 | ths | |
46 | 8f860bb8 | ths | #ifndef S390_H
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47 | 8f860bb8 | ths | #define S390_H
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48 | 8f860bb8 | ths | |
49 | 8f860bb8 | ths | /* List of instruction sets variations. */
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50 | 8f860bb8 | ths | |
51 | 8f860bb8 | ths | enum s390_opcode_mode_val
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52 | 8f860bb8 | ths | { |
53 | 8f860bb8 | ths | S390_OPCODE_ESA = 0,
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54 | 8f860bb8 | ths | S390_OPCODE_ZARCH |
55 | 8f860bb8 | ths | }; |
56 | 8f860bb8 | ths | |
57 | 8f860bb8 | ths | enum s390_opcode_cpu_val
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58 | 8f860bb8 | ths | { |
59 | 8f860bb8 | ths | S390_OPCODE_G5 = 0,
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60 | 8f860bb8 | ths | S390_OPCODE_G6, |
61 | 8f860bb8 | ths | S390_OPCODE_Z900, |
62 | 8f860bb8 | ths | S390_OPCODE_Z990, |
63 | 8f860bb8 | ths | S390_OPCODE_Z9_109, |
64 | 8f860bb8 | ths | S390_OPCODE_Z9_EC |
65 | 8f860bb8 | ths | }; |
66 | 8f860bb8 | ths | |
67 | 8f860bb8 | ths | /* The opcode table is an array of struct s390_opcode. */
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68 | 8f860bb8 | ths | |
69 | 8f860bb8 | ths | struct s390_opcode
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70 | 8f860bb8 | ths | { |
71 | 8f860bb8 | ths | /* The opcode name. */
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72 | 8f860bb8 | ths | const char * name; |
73 | 8f860bb8 | ths | |
74 | 8f860bb8 | ths | /* The opcode itself. Those bits which will be filled in with
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75 | 8f860bb8 | ths | operands are zeroes. */
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76 | 8f860bb8 | ths | unsigned char opcode[6]; |
77 | 8f860bb8 | ths | |
78 | 8f860bb8 | ths | /* The opcode mask. This is used by the disassembler. This is a
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79 | 8f860bb8 | ths | mask containing ones indicating those bits which must match the
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80 | 8f860bb8 | ths | opcode field, and zeroes indicating those bits which need not
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81 | 8f860bb8 | ths | match (and are presumably filled in by operands). */
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82 | 8f860bb8 | ths | unsigned char mask[6]; |
83 | 8f860bb8 | ths | |
84 | 8f860bb8 | ths | /* The opcode length in bytes. */
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85 | 8f860bb8 | ths | int oplen;
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86 | 8f860bb8 | ths | |
87 | 8f860bb8 | ths | /* An array of operand codes. Each code is an index into the
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88 | 8f860bb8 | ths | operand table. They appear in the order which the operands must
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89 | 8f860bb8 | ths | appear in assembly code, and are terminated by a zero. */
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90 | 8f860bb8 | ths | unsigned char operands[6]; |
91 | 8f860bb8 | ths | |
92 | 8f860bb8 | ths | /* Bitmask of execution modes this opcode is available for. */
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93 | 8f860bb8 | ths | unsigned int modes; |
94 | 8f860bb8 | ths | |
95 | 8f860bb8 | ths | /* First cpu this opcode is available for. */
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96 | 8f860bb8 | ths | enum s390_opcode_cpu_val min_cpu;
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97 | 8f860bb8 | ths | }; |
98 | 8f860bb8 | ths | |
99 | 8f860bb8 | ths | /* The table itself is sorted by major opcode number, and is otherwise
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100 | 8f860bb8 | ths | in the order in which the disassembler should consider
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101 | 8f860bb8 | ths | instructions. */
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102 | 8f860bb8 | ths | extern const struct s390_opcode s390_opcodes[]; |
103 | 8f860bb8 | ths | extern const int s390_num_opcodes; |
104 | 8f860bb8 | ths | |
105 | 8f860bb8 | ths | /* A opcode format table for the .insn pseudo mnemonic. */
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106 | 8f860bb8 | ths | extern const struct s390_opcode s390_opformats[]; |
107 | 8f860bb8 | ths | extern const int s390_num_opformats; |
108 | 8f860bb8 | ths | |
109 | 8f860bb8 | ths | /* Values defined for the flags field of a struct powerpc_opcode. */
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110 | 8f860bb8 | ths | |
111 | 8f860bb8 | ths | /* The operands table is an array of struct s390_operand. */
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112 | 8f860bb8 | ths | |
113 | 8f860bb8 | ths | struct s390_operand
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114 | 8f860bb8 | ths | { |
115 | 8f860bb8 | ths | /* The number of bits in the operand. */
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116 | 8f860bb8 | ths | int bits;
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117 | 8f860bb8 | ths | |
118 | 8f860bb8 | ths | /* How far the operand is left shifted in the instruction. */
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119 | 8f860bb8 | ths | int shift;
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120 | 8f860bb8 | ths | |
121 | 8f860bb8 | ths | /* One bit syntax flags. */
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122 | 8f860bb8 | ths | unsigned long flags; |
123 | 8f860bb8 | ths | }; |
124 | 8f860bb8 | ths | |
125 | 8f860bb8 | ths | /* Elements in the table are retrieved by indexing with values from
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126 | 8f860bb8 | ths | the operands field of the powerpc_opcodes table. */
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127 | 8f860bb8 | ths | |
128 | 8f860bb8 | ths | extern const struct s390_operand s390_operands[]; |
129 | 8f860bb8 | ths | |
130 | 8f860bb8 | ths | /* Values defined for the flags field of a struct s390_operand. */
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131 | 8f860bb8 | ths | |
132 | 8f860bb8 | ths | /* This operand names a register. The disassembler uses this to print
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133 | 8f860bb8 | ths | register names with a leading 'r'. */
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134 | 8f860bb8 | ths | #define S390_OPERAND_GPR 0x1 |
135 | 8f860bb8 | ths | |
136 | 8f860bb8 | ths | /* This operand names a floating point register. The disassembler
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137 | 8f860bb8 | ths | prints these with a leading 'f'. */
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138 | 8f860bb8 | ths | #define S390_OPERAND_FPR 0x2 |
139 | 8f860bb8 | ths | |
140 | 8f860bb8 | ths | /* This operand names an access register. The disassembler
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141 | 8f860bb8 | ths | prints these with a leading 'a'. */
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142 | 8f860bb8 | ths | #define S390_OPERAND_AR 0x4 |
143 | 8f860bb8 | ths | |
144 | 8f860bb8 | ths | /* This operand names a control register. The disassembler
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145 | 8f860bb8 | ths | prints these with a leading 'c'. */
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146 | 8f860bb8 | ths | #define S390_OPERAND_CR 0x8 |
147 | 8f860bb8 | ths | |
148 | 8f860bb8 | ths | /* This operand is a displacement. */
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149 | 8f860bb8 | ths | #define S390_OPERAND_DISP 0x10 |
150 | 8f860bb8 | ths | |
151 | 8f860bb8 | ths | /* This operand names a base register. */
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152 | 8f860bb8 | ths | #define S390_OPERAND_BASE 0x20 |
153 | 8f860bb8 | ths | |
154 | 8f860bb8 | ths | /* This operand names an index register, it can be skipped. */
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155 | 8f860bb8 | ths | #define S390_OPERAND_INDEX 0x40 |
156 | 8f860bb8 | ths | |
157 | 8f860bb8 | ths | /* This operand is a relative branch displacement. The disassembler
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158 | 8f860bb8 | ths | prints these symbolically if possible. */
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159 | 8f860bb8 | ths | #define S390_OPERAND_PCREL 0x80 |
160 | 8f860bb8 | ths | |
161 | 8f860bb8 | ths | /* This operand takes signed values. */
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162 | 8f860bb8 | ths | #define S390_OPERAND_SIGNED 0x100 |
163 | 8f860bb8 | ths | |
164 | 8f860bb8 | ths | /* This operand is a length. */
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165 | 8f860bb8 | ths | #define S390_OPERAND_LENGTH 0x200 |
166 | 8f860bb8 | ths | |
167 | 8f860bb8 | ths | /* This operand is optional. Only a single operand at the end of
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168 | 8f860bb8 | ths | the instruction may be optional. */
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169 | 8f860bb8 | ths | #define S390_OPERAND_OPTIONAL 0x400 |
170 | 8f860bb8 | ths | |
171 | 8f860bb8 | ths | #endif /* S390_H */ |
172 | 8f860bb8 | ths | |
173 | 8f860bb8 | ths | |
174 | 8f860bb8 | ths | static int init_flag = 0; |
175 | 8f860bb8 | ths | static int opc_index[256]; |
176 | 8f860bb8 | ths | static int current_arch_mask = 0; |
177 | 8f860bb8 | ths | |
178 | 8f860bb8 | ths | /* Set up index table for first opcode byte. */
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179 | 8f860bb8 | ths | |
180 | 8f860bb8 | ths | static void |
181 | 8f860bb8 | ths | init_disasm (struct disassemble_info *info)
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182 | 8f860bb8 | ths | { |
183 | 8f860bb8 | ths | const struct s390_opcode *opcode; |
184 | 8f860bb8 | ths | const struct s390_opcode *opcode_end; |
185 | 8f860bb8 | ths | |
186 | 8f860bb8 | ths | memset (opc_index, 0, sizeof (opc_index)); |
187 | 8f860bb8 | ths | opcode_end = s390_opcodes + s390_num_opcodes; |
188 | 8f860bb8 | ths | for (opcode = s390_opcodes; opcode < opcode_end; opcode++)
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189 | 8f860bb8 | ths | { |
190 | 8f860bb8 | ths | opc_index[(int) opcode->opcode[0]] = opcode - s390_opcodes; |
191 | 8f860bb8 | ths | while ((opcode < opcode_end) &&
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192 | 8f860bb8 | ths | (opcode[1].opcode[0] == opcode->opcode[0])) |
193 | 8f860bb8 | ths | opcode++; |
194 | 8f860bb8 | ths | } |
195 | 8f860bb8 | ths | // switch (info->mach)
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196 | 8f860bb8 | ths | // {
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197 | 8f860bb8 | ths | // case bfd_mach_s390_31:
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198 | 8f860bb8 | ths | current_arch_mask = 1 << S390_OPCODE_ESA;
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199 | 8f860bb8 | ths | // break;
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200 | 8f860bb8 | ths | // case bfd_mach_s390_64:
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201 | 8f860bb8 | ths | // current_arch_mask = 1 << S390_OPCODE_ZARCH;
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202 | 8f860bb8 | ths | // break;
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203 | 8f860bb8 | ths | // default:
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204 | 8f860bb8 | ths | // abort ();
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205 | 8f860bb8 | ths | // }
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206 | 8f860bb8 | ths | init_flag = 1;
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207 | 8f860bb8 | ths | } |
208 | 8f860bb8 | ths | |
209 | 8f860bb8 | ths | /* Extracts an operand value from an instruction. */
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210 | 8f860bb8 | ths | |
211 | 8f860bb8 | ths | static inline unsigned int |
212 | 8f860bb8 | ths | s390_extract_operand (unsigned char *insn, const struct s390_operand *operand) |
213 | 8f860bb8 | ths | { |
214 | 8f860bb8 | ths | unsigned int val; |
215 | 8f860bb8 | ths | int bits;
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216 | 8f860bb8 | ths | |
217 | 8f860bb8 | ths | /* Extract fragments of the operand byte for byte. */
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218 | 8f860bb8 | ths | insn += operand->shift / 8;
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219 | 8f860bb8 | ths | bits = (operand->shift & 7) + operand->bits;
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220 | 8f860bb8 | ths | val = 0;
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221 | 8f860bb8 | ths | do
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222 | 8f860bb8 | ths | { |
223 | 8f860bb8 | ths | val <<= 8;
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224 | 8f860bb8 | ths | val |= (unsigned int) *insn++; |
225 | 8f860bb8 | ths | bits -= 8;
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226 | 8f860bb8 | ths | } |
227 | 8f860bb8 | ths | while (bits > 0); |
228 | 8f860bb8 | ths | val >>= -bits; |
229 | 8f860bb8 | ths | val &= ((1U << (operand->bits - 1)) << 1) - 1; |
230 | 8f860bb8 | ths | |
231 | 8f860bb8 | ths | /* Check for special long displacement case. */
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232 | 8f860bb8 | ths | if (operand->bits == 20 && operand->shift == 20) |
233 | 8f860bb8 | ths | val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; |
234 | 8f860bb8 | ths | |
235 | 8f860bb8 | ths | /* Sign extend value if the operand is signed or pc relative. */
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236 | 8f860bb8 | ths | if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL))
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237 | 8f860bb8 | ths | && (val & (1U << (operand->bits - 1)))) |
238 | 8f860bb8 | ths | val |= (-1U << (operand->bits - 1)) << 1; |
239 | 8f860bb8 | ths | |
240 | 8f860bb8 | ths | /* Double value if the operand is pc relative. */
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241 | 8f860bb8 | ths | if (operand->flags & S390_OPERAND_PCREL)
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242 | 8f860bb8 | ths | val <<= 1;
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243 | 8f860bb8 | ths | |
244 | 8f860bb8 | ths | /* Length x in an instructions has real length x + 1. */
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245 | 8f860bb8 | ths | if (operand->flags & S390_OPERAND_LENGTH)
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246 | 8f860bb8 | ths | val++; |
247 | 8f860bb8 | ths | return val;
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248 | 8f860bb8 | ths | } |
249 | 8f860bb8 | ths | |
250 | 8f860bb8 | ths | /* Print a S390 instruction. */
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251 | 8f860bb8 | ths | |
252 | 8f860bb8 | ths | int
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253 | 8f860bb8 | ths | print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
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254 | 8f860bb8 | ths | { |
255 | 8f860bb8 | ths | bfd_byte buffer[6];
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256 | 8f860bb8 | ths | const struct s390_opcode *opcode; |
257 | 8f860bb8 | ths | const struct s390_opcode *opcode_end; |
258 | 8f860bb8 | ths | unsigned int value; |
259 | 8f860bb8 | ths | int status, opsize, bufsize;
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260 | 8f860bb8 | ths | char separator;
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261 | 8f860bb8 | ths | |
262 | 8f860bb8 | ths | if (init_flag == 0) |
263 | 8f860bb8 | ths | init_disasm (info); |
264 | 8f860bb8 | ths | |
265 | 8f860bb8 | ths | /* The output looks better if we put 6 bytes on a line. */
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266 | 8f860bb8 | ths | info->bytes_per_line = 6;
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267 | 8f860bb8 | ths | |
268 | 8f860bb8 | ths | /* Every S390 instruction is max 6 bytes long. */
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269 | 8f860bb8 | ths | memset (buffer, 0, 6); |
270 | 8f860bb8 | ths | status = (*info->read_memory_func) (memaddr, buffer, 6, info);
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271 | 8f860bb8 | ths | if (status != 0) |
272 | 8f860bb8 | ths | { |
273 | 8f860bb8 | ths | for (bufsize = 0; bufsize < 6; bufsize++) |
274 | 8f860bb8 | ths | if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0) |
275 | 8f860bb8 | ths | break;
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276 | 8f860bb8 | ths | if (bufsize <= 0) |
277 | 8f860bb8 | ths | { |
278 | 8f860bb8 | ths | (*info->memory_error_func) (status, memaddr, info); |
279 | 8f860bb8 | ths | return -1; |
280 | 8f860bb8 | ths | } |
281 | 8f860bb8 | ths | /* Opsize calculation looks strange but it works
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282 | 8f860bb8 | ths | 00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes,
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283 | 8f860bb8 | ths | 11xxxxxx -> 6 bytes. */
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284 | 8f860bb8 | ths | opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; |
285 | 8f860bb8 | ths | status = opsize > bufsize; |
286 | 8f860bb8 | ths | } |
287 | 8f860bb8 | ths | else
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288 | 8f860bb8 | ths | { |
289 | 8f860bb8 | ths | bufsize = 6;
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290 | 8f860bb8 | ths | opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; |
291 | 8f860bb8 | ths | } |
292 | 8f860bb8 | ths | |
293 | 8f860bb8 | ths | if (status == 0) |
294 | 8f860bb8 | ths | { |
295 | 8f860bb8 | ths | /* Find the first match in the opcode table. */
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296 | 8f860bb8 | ths | opcode_end = s390_opcodes + s390_num_opcodes; |
297 | 8f860bb8 | ths | for (opcode = s390_opcodes + opc_index[(int) buffer[0]]; |
298 | 8f860bb8 | ths | (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]); |
299 | 8f860bb8 | ths | opcode++) |
300 | 8f860bb8 | ths | { |
301 | 8f860bb8 | ths | const struct s390_operand *operand; |
302 | 8f860bb8 | ths | const unsigned char *opindex; |
303 | 8f860bb8 | ths | |
304 | 8f860bb8 | ths | /* Check architecture. */
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305 | 8f860bb8 | ths | if (!(opcode->modes & current_arch_mask))
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306 | 8f860bb8 | ths | continue;
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307 | 8f860bb8 | ths | /* Check signature of the opcode. */
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308 | 8f860bb8 | ths | if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1] |
309 | 8f860bb8 | ths | || (buffer[2] & opcode->mask[2]) != opcode->opcode[2] |
310 | 8f860bb8 | ths | || (buffer[3] & opcode->mask[3]) != opcode->opcode[3] |
311 | 8f860bb8 | ths | || (buffer[4] & opcode->mask[4]) != opcode->opcode[4] |
312 | 8f860bb8 | ths | || (buffer[5] & opcode->mask[5]) != opcode->opcode[5]) |
313 | 8f860bb8 | ths | continue;
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314 | 8f860bb8 | ths | |
315 | 8f860bb8 | ths | /* The instruction is valid. */
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316 | 8f860bb8 | ths | if (opcode->operands[0] != 0) |
317 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, "%s\t", opcode->name);
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318 | 8f860bb8 | ths | else
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319 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, "%s", opcode->name);
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320 | 8f860bb8 | ths | |
321 | 8f860bb8 | ths | /* Extract the operands. */
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322 | 8f860bb8 | ths | separator = 0;
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323 | 8f860bb8 | ths | for (opindex = opcode->operands; *opindex != 0; opindex++) |
324 | 8f860bb8 | ths | { |
325 | 8f860bb8 | ths | unsigned int value; |
326 | 8f860bb8 | ths | |
327 | 8f860bb8 | ths | operand = s390_operands + *opindex; |
328 | 8f860bb8 | ths | value = s390_extract_operand (buffer, operand); |
329 | 8f860bb8 | ths | |
330 | 8f860bb8 | ths | if ((operand->flags & S390_OPERAND_INDEX) && value == 0) |
331 | 8f860bb8 | ths | continue;
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332 | 8f860bb8 | ths | if ((operand->flags & S390_OPERAND_BASE) &&
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333 | 8f860bb8 | ths | value == 0 && separator == '(') |
334 | 8f860bb8 | ths | { |
335 | 8f860bb8 | ths | separator = ',';
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336 | 8f860bb8 | ths | continue;
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337 | 8f860bb8 | ths | } |
338 | 8f860bb8 | ths | |
339 | 8f860bb8 | ths | if (separator)
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340 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, "%c", separator);
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341 | 8f860bb8 | ths | |
342 | 8f860bb8 | ths | if (operand->flags & S390_OPERAND_GPR)
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343 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, "%%r%i", value);
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344 | 8f860bb8 | ths | else if (operand->flags & S390_OPERAND_FPR) |
345 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, "%%f%i", value);
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346 | 8f860bb8 | ths | else if (operand->flags & S390_OPERAND_AR) |
347 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, "%%a%i", value);
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348 | 8f860bb8 | ths | else if (operand->flags & S390_OPERAND_CR) |
349 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, "%%c%i", value);
|
350 | 8f860bb8 | ths | else if (operand->flags & S390_OPERAND_PCREL) |
351 | 8f860bb8 | ths | (*info->print_address_func) (memaddr + (int) value, info);
|
352 | 8f860bb8 | ths | else if (operand->flags & S390_OPERAND_SIGNED) |
353 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, "%i", (int) value); |
354 | 8f860bb8 | ths | else
|
355 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, "%u", value);
|
356 | 8f860bb8 | ths | |
357 | 8f860bb8 | ths | if (operand->flags & S390_OPERAND_DISP)
|
358 | 8f860bb8 | ths | { |
359 | 8f860bb8 | ths | separator = '(';
|
360 | 8f860bb8 | ths | } |
361 | 8f860bb8 | ths | else if (operand->flags & S390_OPERAND_BASE) |
362 | 8f860bb8 | ths | { |
363 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, ")");
|
364 | 8f860bb8 | ths | separator = ',';
|
365 | 8f860bb8 | ths | } |
366 | 8f860bb8 | ths | else
|
367 | 8f860bb8 | ths | separator = ',';
|
368 | 8f860bb8 | ths | } |
369 | 8f860bb8 | ths | |
370 | 8f860bb8 | ths | /* Found instruction, printed it, return its size. */
|
371 | 8f860bb8 | ths | return opsize;
|
372 | 8f860bb8 | ths | } |
373 | 8f860bb8 | ths | /* No matching instruction found, fall through to hex print. */
|
374 | 8f860bb8 | ths | } |
375 | 8f860bb8 | ths | |
376 | 8f860bb8 | ths | if (bufsize >= 4) |
377 | 8f860bb8 | ths | { |
378 | 8f860bb8 | ths | value = (unsigned int) buffer[0]; |
379 | 8f860bb8 | ths | value = (value << 8) + (unsigned int) buffer[1]; |
380 | 8f860bb8 | ths | value = (value << 8) + (unsigned int) buffer[2]; |
381 | 8f860bb8 | ths | value = (value << 8) + (unsigned int) buffer[3]; |
382 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, ".long\t0x%08x", value);
|
383 | 8f860bb8 | ths | return 4; |
384 | 8f860bb8 | ths | } |
385 | 8f860bb8 | ths | else if (bufsize >= 2) |
386 | 8f860bb8 | ths | { |
387 | 8f860bb8 | ths | value = (unsigned int) buffer[0]; |
388 | 8f860bb8 | ths | value = (value << 8) + (unsigned int) buffer[1]; |
389 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, ".short\t0x%04x", value);
|
390 | 8f860bb8 | ths | return 2; |
391 | 8f860bb8 | ths | } |
392 | 8f860bb8 | ths | else
|
393 | 8f860bb8 | ths | { |
394 | 8f860bb8 | ths | value = (unsigned int) buffer[0]; |
395 | 8f860bb8 | ths | (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value);
|
396 | 8f860bb8 | ths | return 1; |
397 | 8f860bb8 | ths | } |
398 | 8f860bb8 | ths | } |
399 | 8f860bb8 | ths | /* s390-opc.c -- S390 opcode list
|
400 | a4fc08ff | ths | Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
|
401 | 8f860bb8 | ths | Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
|
402 | 8f860bb8 | ths | |
403 | a4fc08ff | ths | This file is part of GDB, GAS, and the GNU binutils.
|
404 | 8f860bb8 | ths | |
405 | a4fc08ff | ths | This program is free software; you can redistribute it and/or modify
|
406 | 8f860bb8 | ths | it under the terms of the GNU General Public License as published by
|
407 | a4fc08ff | ths | the Free Software Foundation; either version 2 of the License, or
|
408 | a4fc08ff | ths | (at your option) any later version.
|
409 | 8f860bb8 | ths | |
410 | a4fc08ff | ths | This program is distributed in the hope that it will be useful,
|
411 | a4fc08ff | ths | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
412 | a4fc08ff | ths | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
413 | a4fc08ff | ths | GNU General Public License for more details.
|
414 | 8f860bb8 | ths | |
415 | 8f860bb8 | ths | You should have received a copy of the GNU General Public License
|
416 | a4fc08ff | ths | along with this program; if not, write to the Free Software
|
417 | a4fc08ff | ths | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
|
418 | a4fc08ff | ths | 02110-1301, USA. */
|
419 | 8f860bb8 | ths | |
420 | 8f860bb8 | ths | #include <stdio.h> |
421 | 8f860bb8 | ths | |
422 | 8f860bb8 | ths | /* This file holds the S390 opcode table. The opcode table
|
423 | 8f860bb8 | ths | includes almost all of the extended instruction mnemonics. This
|
424 | 8f860bb8 | ths | permits the disassembler to use them, and simplifies the assembler
|
425 | 8f860bb8 | ths | logic, at the cost of increasing the table size. The table is
|
426 | 8f860bb8 | ths | strictly constant data, so the compiler should be able to put it in
|
427 | 8f860bb8 | ths | the .text section.
|
428 | 8f860bb8 | ths | |
429 | 8f860bb8 | ths | This file also holds the operand table. All knowledge about
|
430 | 8f860bb8 | ths | inserting operands into instructions and vice-versa is kept in this
|
431 | 8f860bb8 | ths | file. */
|
432 | 8f860bb8 | ths | |
433 | 8f860bb8 | ths | /* The operands table.
|
434 | 8f860bb8 | ths | The fields are bits, shift, insert, extract, flags. */
|
435 | 8f860bb8 | ths | |
436 | 8f860bb8 | ths | const struct s390_operand s390_operands[] = |
437 | 8f860bb8 | ths | { |
438 | 8f860bb8 | ths | #define UNUSED 0 |
439 | 8f860bb8 | ths | { 0, 0, 0 }, /* Indicates the end of the operand list */ |
440 | 8f860bb8 | ths | |
441 | 8f860bb8 | ths | #define R_8 1 /* GPR starting at position 8 */ |
442 | 8f860bb8 | ths | { 4, 8, S390_OPERAND_GPR }, |
443 | 8f860bb8 | ths | #define R_12 2 /* GPR starting at position 12 */ |
444 | 8f860bb8 | ths | { 4, 12, S390_OPERAND_GPR }, |
445 | 8f860bb8 | ths | #define R_16 3 /* GPR starting at position 16 */ |
446 | 8f860bb8 | ths | { 4, 16, S390_OPERAND_GPR }, |
447 | 8f860bb8 | ths | #define R_20 4 /* GPR starting at position 20 */ |
448 | 8f860bb8 | ths | { 4, 20, S390_OPERAND_GPR }, |
449 | 8f860bb8 | ths | #define R_24 5 /* GPR starting at position 24 */ |
450 | 8f860bb8 | ths | { 4, 24, S390_OPERAND_GPR }, |
451 | 8f860bb8 | ths | #define R_28 6 /* GPR starting at position 28 */ |
452 | 8f860bb8 | ths | { 4, 28, S390_OPERAND_GPR }, |
453 | 8f860bb8 | ths | #define R_32 7 /* GPR starting at position 32 */ |
454 | 8f860bb8 | ths | { 4, 32, S390_OPERAND_GPR }, |
455 | 8f860bb8 | ths | |
456 | 8f860bb8 | ths | #define F_8 8 /* FPR starting at position 8 */ |
457 | 8f860bb8 | ths | { 4, 8, S390_OPERAND_FPR }, |
458 | 8f860bb8 | ths | #define F_12 9 /* FPR starting at position 12 */ |
459 | 8f860bb8 | ths | { 4, 12, S390_OPERAND_FPR }, |
460 | 8f860bb8 | ths | #define F_16 10 /* FPR starting at position 16 */ |
461 | 8f860bb8 | ths | { 4, 16, S390_OPERAND_FPR }, |
462 | 8f860bb8 | ths | #define F_20 11 /* FPR starting at position 16 */ |
463 | 8f860bb8 | ths | { 4, 16, S390_OPERAND_FPR }, |
464 | 8f860bb8 | ths | #define F_24 12 /* FPR starting at position 24 */ |
465 | 8f860bb8 | ths | { 4, 24, S390_OPERAND_FPR }, |
466 | 8f860bb8 | ths | #define F_28 13 /* FPR starting at position 28 */ |
467 | 8f860bb8 | ths | { 4, 28, S390_OPERAND_FPR }, |
468 | 8f860bb8 | ths | #define F_32 14 /* FPR starting at position 32 */ |
469 | 8f860bb8 | ths | { 4, 32, S390_OPERAND_FPR }, |
470 | 8f860bb8 | ths | |
471 | 8f860bb8 | ths | #define A_8 15 /* Access reg. starting at position 8 */ |
472 | 8f860bb8 | ths | { 4, 8, S390_OPERAND_AR }, |
473 | 8f860bb8 | ths | #define A_12 16 /* Access reg. starting at position 12 */ |
474 | 8f860bb8 | ths | { 4, 12, S390_OPERAND_AR }, |
475 | 8f860bb8 | ths | #define A_24 17 /* Access reg. starting at position 24 */ |
476 | 8f860bb8 | ths | { 4, 24, S390_OPERAND_AR }, |
477 | 8f860bb8 | ths | #define A_28 18 /* Access reg. starting at position 28 */ |
478 | 8f860bb8 | ths | { 4, 28, S390_OPERAND_AR }, |
479 | 8f860bb8 | ths | |
480 | 8f860bb8 | ths | #define C_8 19 /* Control reg. starting at position 8 */ |
481 | 8f860bb8 | ths | { 4, 8, S390_OPERAND_CR }, |
482 | 8f860bb8 | ths | #define C_12 20 /* Control reg. starting at position 12 */ |
483 | 8f860bb8 | ths | { 4, 12, S390_OPERAND_CR }, |
484 | 8f860bb8 | ths | |
485 | 8f860bb8 | ths | #define B_16 21 /* Base register starting at position 16 */ |
486 | 8f860bb8 | ths | { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, |
487 | 8f860bb8 | ths | #define B_32 22 /* Base register starting at position 32 */ |
488 | 8f860bb8 | ths | { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, |
489 | 8f860bb8 | ths | |
490 | 8f860bb8 | ths | #define X_12 23 /* Index register starting at position 12 */ |
491 | 8f860bb8 | ths | { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, |
492 | 8f860bb8 | ths | |
493 | 8f860bb8 | ths | #define D_20 24 /* Displacement starting at position 20 */ |
494 | 8f860bb8 | ths | { 12, 20, S390_OPERAND_DISP }, |
495 | 8f860bb8 | ths | #define D_36 25 /* Displacement starting at position 36 */ |
496 | 8f860bb8 | ths | { 12, 36, S390_OPERAND_DISP }, |
497 | 8f860bb8 | ths | #define D20_20 26 /* 20 bit displacement starting at 20 */ |
498 | 8f860bb8 | ths | { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, |
499 | 8f860bb8 | ths | |
500 | 8f860bb8 | ths | #define L4_8 27 /* 4 bit length starting at position 8 */ |
501 | 8f860bb8 | ths | { 4, 8, S390_OPERAND_LENGTH }, |
502 | 8f860bb8 | ths | #define L4_12 28 /* 4 bit length starting at position 12 */ |
503 | 8f860bb8 | ths | { 4, 12, S390_OPERAND_LENGTH }, |
504 | 8f860bb8 | ths | #define L8_8 29 /* 8 bit length starting at position 8 */ |
505 | 8f860bb8 | ths | { 8, 8, S390_OPERAND_LENGTH }, |
506 | 8f860bb8 | ths | |
507 | 8f860bb8 | ths | #define U4_8 30 /* 4 bit unsigned value starting at 8 */ |
508 | 8f860bb8 | ths | { 4, 8, 0 }, |
509 | 8f860bb8 | ths | #define U4_12 31 /* 4 bit unsigned value starting at 12 */ |
510 | 8f860bb8 | ths | { 4, 12, 0 }, |
511 | 8f860bb8 | ths | #define U4_16 32 /* 4 bit unsigned value starting at 16 */ |
512 | 8f860bb8 | ths | { 4, 16, 0 }, |
513 | 8f860bb8 | ths | #define U4_20 33 /* 4 bit unsigned value starting at 20 */ |
514 | 8f860bb8 | ths | { 4, 20, 0 }, |
515 | 8f860bb8 | ths | #define U8_8 34 /* 8 bit unsigned value starting at 8 */ |
516 | 8f860bb8 | ths | { 8, 8, 0 }, |
517 | 8f860bb8 | ths | #define U8_16 35 /* 8 bit unsigned value starting at 16 */ |
518 | 8f860bb8 | ths | { 8, 16, 0 }, |
519 | 8f860bb8 | ths | #define I16_16 36 /* 16 bit signed value starting at 16 */ |
520 | 8f860bb8 | ths | { 16, 16, S390_OPERAND_SIGNED }, |
521 | 8f860bb8 | ths | #define U16_16 37 /* 16 bit unsigned value starting at 16 */ |
522 | 8f860bb8 | ths | { 16, 16, 0 }, |
523 | 8f860bb8 | ths | #define J16_16 38 /* PC relative jump offset at 16 */ |
524 | 8f860bb8 | ths | { 16, 16, S390_OPERAND_PCREL }, |
525 | 8f860bb8 | ths | #define J32_16 39 /* PC relative long offset at 16 */ |
526 | 8f860bb8 | ths | { 32, 16, S390_OPERAND_PCREL }, |
527 | 8f860bb8 | ths | #define I32_16 40 /* 32 bit signed value starting at 16 */ |
528 | 8f860bb8 | ths | { 32, 16, S390_OPERAND_SIGNED }, |
529 | 8f860bb8 | ths | #define U32_16 41 /* 32 bit unsigned value starting at 16 */ |
530 | 8f860bb8 | ths | { 32, 16, 0 }, |
531 | 8f860bb8 | ths | #define M_16 42 /* 4 bit optional mask starting at 16 */ |
532 | 8f860bb8 | ths | { 4, 16, S390_OPERAND_OPTIONAL }, |
533 | 8f860bb8 | ths | #define RO_28 43 /* optional GPR starting at position 28 */ |
534 | 8f860bb8 | ths | { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) } |
535 | 8f860bb8 | ths | |
536 | 8f860bb8 | ths | }; |
537 | 8f860bb8 | ths | |
538 | 8f860bb8 | ths | |
539 | 8f860bb8 | ths | /* Macros used to form opcodes. */
|
540 | 8f860bb8 | ths | |
541 | 8f860bb8 | ths | /* 8/16/48 bit opcodes. */
|
542 | 8f860bb8 | ths | #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } |
543 | 8f860bb8 | ths | #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } |
544 | 8f860bb8 | ths | #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ |
545 | 8f860bb8 | ths | (x >> 16) & 255, (x >> 8) & 255, x & 255} |
546 | 8f860bb8 | ths | |
547 | 8f860bb8 | ths | /* The new format of the INSTR_x_y and MASK_x_y defines is based
|
548 | 8f860bb8 | ths | on the following rules:
|
549 | 8f860bb8 | ths | 1) the middle part of the definition (x in INSTR_x_y) is the official
|
550 | 8f860bb8 | ths | names of the instruction format that you can find in the principals
|
551 | 8f860bb8 | ths | of operation.
|
552 | 8f860bb8 | ths | 2) the last part of the definition (y in INSTR_x_y) gives you an idea
|
553 | 8f860bb8 | ths | which operands the binary represenation of the instruction has.
|
554 | 8f860bb8 | ths | The meanings of the letters in y are:
|
555 | 8f860bb8 | ths | a - access register
|
556 | 8f860bb8 | ths | c - control register
|
557 | 8f860bb8 | ths | d - displacement, 12 bit
|
558 | 8f860bb8 | ths | f - floating pointer register
|
559 | 8f860bb8 | ths | i - signed integer, 4, 8, 16 or 32 bit
|
560 | 8f860bb8 | ths | l - length, 4 or 8 bit
|
561 | 8f860bb8 | ths | p - pc relative
|
562 | 8f860bb8 | ths | r - general purpose register
|
563 | 8f860bb8 | ths | u - unsigned integer, 4, 8, 16 or 32 bit
|
564 | 8f860bb8 | ths | m - mode field, 4 bit
|
565 | 8f860bb8 | ths | 0 - operand skipped.
|
566 | 8f860bb8 | ths | The order of the letters reflects the layout of the format in
|
567 | 8f860bb8 | ths | storage and not the order of the paramaters of the instructions.
|
568 | 8f860bb8 | ths | The use of the letters is not a 100% match with the PoP but it is
|
569 | 8f860bb8 | ths | quite close.
|
570 | 8f860bb8 | ths | |
571 | 8f860bb8 | ths | For example the instruction "mvo" is defined in the PoP as follows:
|
572 | 3b46e624 | ths | |
573 | 8f860bb8 | ths | MVO D1(L1,B1),D2(L2,B2) [SS]
|
574 | 8f860bb8 | ths | |
575 | 8f860bb8 | ths | --------------------------------------
|
576 | 8f860bb8 | ths | | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
|
577 | 8f860bb8 | ths | --------------------------------------
|
578 | 8f860bb8 | ths | 0 8 12 16 20 32 36
|
579 | 8f860bb8 | ths | |
580 | 8f860bb8 | ths | The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */
|
581 | 8f860bb8 | ths | |
582 | 8f860bb8 | ths | #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ |
583 | 8f860bb8 | ths | #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ |
584 | 8f860bb8 | ths | #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ |
585 | 8f860bb8 | ths | #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ |
586 | 8f860bb8 | ths | #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ |
587 | 8f860bb8 | ths | #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ |
588 | 8f860bb8 | ths | #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ |
589 | 8f860bb8 | ths | #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ |
590 | 8f860bb8 | ths | #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ |
591 | 8f860bb8 | ths | #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ |
592 | 8f860bb8 | ths | #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ |
593 | 8f860bb8 | ths | #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ |
594 | 8f860bb8 | ths | #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ |
595 | 8f860bb8 | ths | #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ |
596 | 8f860bb8 | ths | #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ |
597 | 8f860bb8 | ths | #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ |
598 | 8f860bb8 | ths | #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ |
599 | 8f860bb8 | ths | #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ |
600 | 8f860bb8 | ths | #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ |
601 | 8f860bb8 | ths | #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ |
602 | 8f860bb8 | ths | #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ |
603 | 8f860bb8 | ths | #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ |
604 | 8f860bb8 | ths | #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ |
605 | 8f860bb8 | ths | /* Actually efpc and sfpc do not take an optional operand.
|
606 | 8f860bb8 | ths | This is just a workaround for existing code e.g. glibc. */
|
607 | 8f860bb8 | ths | #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ |
608 | 8f860bb8 | ths | #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ |
609 | 8f860bb8 | ths | #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ |
610 | 8f860bb8 | ths | #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ |
611 | 8f860bb8 | ths | #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ |
612 | 8f860bb8 | ths | #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ |
613 | 8f860bb8 | ths | #define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ |
614 | 8f860bb8 | ths | #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ |
615 | 8f860bb8 | ths | #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ |
616 | 8f860bb8 | ths | #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ |
617 | 8f860bb8 | ths | #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ |
618 | 8f860bb8 | ths | #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */ |
619 | 8f860bb8 | ths | #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ |
620 | 8f860bb8 | ths | #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ |
621 | 8f860bb8 | ths | #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ |
622 | 8f860bb8 | ths | #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ |
623 | 8f860bb8 | ths | #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ |
624 | 8f860bb8 | ths | #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ |
625 | 8f860bb8 | ths | #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ |
626 | 8f860bb8 | ths | #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ |
627 | 8f860bb8 | ths | #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ |
628 | 8f860bb8 | ths | #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ |
629 | 8f860bb8 | ths | #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ |
630 | 8f860bb8 | ths | #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ |
631 | 8f860bb8 | ths | #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ |
632 | 8f860bb8 | ths | #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ |
633 | 8f860bb8 | ths | #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ |
634 | 8f860bb8 | ths | #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
635 | 8f860bb8 | ths | #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
636 | 8f860bb8 | ths | #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ |
637 | 8f860bb8 | ths | #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ |
638 | 8f860bb8 | ths | #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ |
639 | 8f860bb8 | ths | #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ |
640 | 8f860bb8 | ths | #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ |
641 | 8f860bb8 | ths | #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ |
642 | 8f860bb8 | ths | #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ |
643 | 8f860bb8 | ths | #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ |
644 | 8f860bb8 | ths | #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ |
645 | 8f860bb8 | ths | #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ |
646 | 8f860bb8 | ths | #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ |
647 | 8f860bb8 | ths | #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ |
648 | 8f860bb8 | ths | #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ |
649 | 8f860bb8 | ths | #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ |
650 | 8f860bb8 | ths | #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ |
651 | 8f860bb8 | ths | #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ |
652 | 8f860bb8 | ths | #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ |
653 | 8f860bb8 | ths | #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ |
654 | 8f860bb8 | ths | #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ |
655 | 8f860bb8 | ths | #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ |
656 | 8f860bb8 | ths | #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ |
657 | 8f860bb8 | ths | #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ |
658 | 8f860bb8 | ths | #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ |
659 | 8f860bb8 | ths | #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ |
660 | 8f860bb8 | ths | #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ |
661 | 8f860bb8 | ths | #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ |
662 | 8f860bb8 | ths | #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ |
663 | 8f860bb8 | ths | #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ |
664 | 8f860bb8 | ths | |
665 | 8f860bb8 | ths | #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
666 | 8f860bb8 | ths | #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
667 | 8f860bb8 | ths | #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
668 | 8f860bb8 | ths | #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
669 | 8f860bb8 | ths | #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
670 | 8f860bb8 | ths | #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
671 | 8f860bb8 | ths | #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
672 | 8f860bb8 | ths | #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
673 | 8f860bb8 | ths | #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
674 | 8f860bb8 | ths | #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
675 | 8f860bb8 | ths | #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
676 | 8f860bb8 | ths | #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
677 | 8f860bb8 | ths | #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
678 | 8f860bb8 | ths | #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } |
679 | 8f860bb8 | ths | #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
680 | 8f860bb8 | ths | #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
681 | 8f860bb8 | ths | #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
682 | 8f860bb8 | ths | #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
683 | 8f860bb8 | ths | #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
684 | 8f860bb8 | ths | #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
685 | 8f860bb8 | ths | #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
686 | 8f860bb8 | ths | #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
687 | 8f860bb8 | ths | #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
688 | 8f860bb8 | ths | #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
689 | 8f860bb8 | ths | #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
690 | 8f860bb8 | ths | #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
691 | 8f860bb8 | ths | #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
692 | 8f860bb8 | ths | #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
693 | 8f860bb8 | ths | #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
694 | 8f860bb8 | ths | #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
695 | 8f860bb8 | ths | #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
696 | 8f860bb8 | ths | #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
697 | 8f860bb8 | ths | #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
698 | 8f860bb8 | ths | #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } |
699 | 8f860bb8 | ths | #define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
700 | 8f860bb8 | ths | #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
701 | 8f860bb8 | ths | #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
702 | 8f860bb8 | ths | #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
703 | 8f860bb8 | ths | #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
704 | 8f860bb8 | ths | #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
705 | 8f860bb8 | ths | #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
706 | 8f860bb8 | ths | #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
707 | 8f860bb8 | ths | #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
708 | 8f860bb8 | ths | #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
709 | 8f860bb8 | ths | #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
710 | 8f860bb8 | ths | #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
711 | 8f860bb8 | ths | #define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
712 | 8f860bb8 | ths | #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
713 | 8f860bb8 | ths | #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
714 | 8f860bb8 | ths | #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
715 | 8f860bb8 | ths | #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
716 | 8f860bb8 | ths | #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
717 | 8f860bb8 | ths | #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
718 | 8f860bb8 | ths | #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
719 | 8f860bb8 | ths | #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
720 | 8f860bb8 | ths | #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
721 | 8f860bb8 | ths | #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
722 | 8f860bb8 | ths | #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
723 | 8f860bb8 | ths | #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
724 | 8f860bb8 | ths | #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
725 | 8f860bb8 | ths | #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
726 | 8f860bb8 | ths | #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
727 | 8f860bb8 | ths | #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
728 | 8f860bb8 | ths | #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
729 | 8f860bb8 | ths | #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
730 | 8f860bb8 | ths | #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
731 | 8f860bb8 | ths | #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
732 | 8f860bb8 | ths | #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
733 | 8f860bb8 | ths | #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
734 | 8f860bb8 | ths | #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
735 | 8f860bb8 | ths | #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
736 | 8f860bb8 | ths | #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
737 | 8f860bb8 | ths | #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
738 | 8f860bb8 | ths | #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
739 | 8f860bb8 | ths | #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
740 | 8f860bb8 | ths | #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
741 | 8f860bb8 | ths | #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
742 | 8f860bb8 | ths | #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
743 | 8f860bb8 | ths | #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
744 | 8f860bb8 | ths | #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
745 | 8f860bb8 | ths | |
746 | 8f860bb8 | ths | /* The opcode formats table (blueprints for .insn pseudo mnemonic). */
|
747 | 8f860bb8 | ths | |
748 | 8f860bb8 | ths | const struct s390_opcode s390_opformats[] = |
749 | 8f860bb8 | ths | { |
750 | 8f860bb8 | ths | { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, |
751 | 8f860bb8 | ths | { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, |
752 | 8f860bb8 | ths | { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, |
753 | 8f860bb8 | ths | { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, |
754 | 8f860bb8 | ths | { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, |
755 | 8f860bb8 | ths | { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, |
756 | 8f860bb8 | ths | { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, |
757 | 8f860bb8 | ths | { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, |
758 | 8f860bb8 | ths | { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, |
759 | 8f860bb8 | ths | { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, |
760 | 8f860bb8 | ths | { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, |
761 | 8f860bb8 | ths | { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, |
762 | 8f860bb8 | ths | { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, |
763 | 8f860bb8 | ths | { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, |
764 | 8f860bb8 | ths | { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, |
765 | 8f860bb8 | ths | { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, |
766 | 8f860bb8 | ths | { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, |
767 | 8f860bb8 | ths | { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, |
768 | 8f860bb8 | ths | { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, |
769 | 8f860bb8 | ths | { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, |
770 | 8f860bb8 | ths | { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, |
771 | 8f860bb8 | ths | { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, |
772 | 8f860bb8 | ths | }; |
773 | 8f860bb8 | ths | |
774 | 8f860bb8 | ths | const int s390_num_opformats = |
775 | 8f860bb8 | ths | sizeof (s390_opformats) / sizeof (s390_opformats[0]); |
776 | 8f860bb8 | ths | |
777 | 8f860bb8 | ths | /* The opcode table. This file was generated by s390-mkopc.
|
778 | 8f860bb8 | ths | |
779 | 8f860bb8 | ths | The format of the opcode table is:
|
780 | 8f860bb8 | ths | |
781 | 8f860bb8 | ths | NAME OPCODE MASK OPERANDS
|
782 | 8f860bb8 | ths | |
783 | 8f860bb8 | ths | Name is the name of the instruction.
|
784 | 8f860bb8 | ths | OPCODE is the instruction opcode.
|
785 | 8f860bb8 | ths | MASK is the opcode mask; this is used to tell the disassembler
|
786 | 8f860bb8 | ths | which bits in the actual opcode must match OPCODE.
|
787 | 8f860bb8 | ths | OPERANDS is the list of operands.
|
788 | 8f860bb8 | ths | |
789 | 8f860bb8 | ths | The disassembler reads the table in order and prints the first
|
790 | 8f860bb8 | ths | instruction which matches. */
|
791 | 8f860bb8 | ths | |
792 | 8f860bb8 | ths | const struct s390_opcode s390_opcodes[] = |
793 | 8f860bb8 | ths | { |
794 | 8f860bb8 | ths | { "dp", OP8(0xfdLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
795 | 8f860bb8 | ths | { "mp", OP8(0xfcLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
796 | 8f860bb8 | ths | { "sp", OP8(0xfbLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
797 | 8f860bb8 | ths | { "ap", OP8(0xfaLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
798 | 8f860bb8 | ths | { "cp", OP8(0xf9LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
799 | 8f860bb8 | ths | { "zap", OP8(0xf8LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
800 | 8f860bb8 | ths | { "unpk", OP8(0xf3LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
801 | 8f860bb8 | ths | { "pack", OP8(0xf2LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
802 | 8f860bb8 | ths | { "mvo", OP8(0xf1LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0}, |
803 | 8f860bb8 | ths | { "srp", OP8(0xf0LL), MASK_SS_LIRDRD, INSTR_SS_LIRDRD, 3, 0}, |
804 | 8f860bb8 | ths | { "lmd", OP8(0xefLL), MASK_SS_RRRDRD3, INSTR_SS_RRRDRD3, 2, 2}, |
805 | 8f860bb8 | ths | { "plo", OP8(0xeeLL), MASK_SS_RRRDRD2, INSTR_SS_RRRDRD2, 3, 0}, |
806 | 8f860bb8 | ths | { "stdy", OP48(0xed0000000067LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, |
807 | 8f860bb8 | ths | { "stey", OP48(0xed0000000066LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, |
808 | 8f860bb8 | ths | { "ldy", OP48(0xed0000000065LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, |
809 | 8f860bb8 | ths | { "ley", OP48(0xed0000000064LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3}, |
810 | 8f860bb8 | ths | { "tgxt", OP48(0xed0000000059LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
811 | 8f860bb8 | ths | { "tcxt", OP48(0xed0000000058LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
812 | 8f860bb8 | ths | { "tgdt", OP48(0xed0000000055LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
813 | 8f860bb8 | ths | { "tcdt", OP48(0xed0000000054LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
814 | 8f860bb8 | ths | { "tget", OP48(0xed0000000051LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
815 | 8f860bb8 | ths | { "tcet", OP48(0xed0000000050LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5}, |
816 | 8f860bb8 | ths | { "srxt", OP48(0xed0000000049LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, |
817 | 8f860bb8 | ths | { "slxt", OP48(0xed0000000048LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, |
818 | 8f860bb8 | ths | { "srdt", OP48(0xed0000000041LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, |
819 | 8f860bb8 | ths | { "sldt", OP48(0xed0000000040LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5}, |
820 | 8f860bb8 | ths | { "msd", OP48(0xed000000003fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3}, |
821 | 8f860bb8 | ths | { "mad", OP48(0xed000000003eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3}, |
822 | 8f860bb8 | ths | { "myh", OP48(0xed000000003dLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
823 | 8f860bb8 | ths | { "mayh", OP48(0xed000000003cLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
824 | 8f860bb8 | ths | { "my", OP48(0xed000000003bLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
825 | 8f860bb8 | ths | { "may", OP48(0xed000000003aLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
826 | 8f860bb8 | ths | { "myl", OP48(0xed0000000039LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
827 | 8f860bb8 | ths | { "mayl", OP48(0xed0000000038LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4}, |
828 | 8f860bb8 | ths | { "mee", OP48(0xed0000000037LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
829 | 8f860bb8 | ths | { "sqe", OP48(0xed0000000034LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
830 | 8f860bb8 | ths | { "mse", OP48(0xed000000002fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3}, |
831 | 8f860bb8 | ths | { "mae", OP48(0xed000000002eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3}, |
832 | 8f860bb8 | ths | { "lxe", OP48(0xed0000000026LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
833 | 8f860bb8 | ths | { "lxd", OP48(0xed0000000025LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
834 | 8f860bb8 | ths | { "lde", OP48(0xed0000000024LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
835 | 8f860bb8 | ths | { "msdb", OP48(0xed000000001fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0}, |
836 | 8f860bb8 | ths | { "madb", OP48(0xed000000001eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0}, |
837 | 8f860bb8 | ths | { "ddb", OP48(0xed000000001dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
838 | 8f860bb8 | ths | { "mdb", OP48(0xed000000001cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
839 | 8f860bb8 | ths | { "sdb", OP48(0xed000000001bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
840 | 8f860bb8 | ths | { "adb", OP48(0xed000000001aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
841 | 8f860bb8 | ths | { "cdb", OP48(0xed0000000019LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
842 | 8f860bb8 | ths | { "kdb", OP48(0xed0000000018LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
843 | 8f860bb8 | ths | { "meeb", OP48(0xed0000000017LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
844 | 8f860bb8 | ths | { "sqdb", OP48(0xed0000000015LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
845 | 8f860bb8 | ths | { "sqeb", OP48(0xed0000000014LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
846 | 8f860bb8 | ths | { "tcxb", OP48(0xed0000000012LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
847 | 8f860bb8 | ths | { "tcdb", OP48(0xed0000000011LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
848 | 8f860bb8 | ths | { "tceb", OP48(0xed0000000010LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
849 | 8f860bb8 | ths | { "mseb", OP48(0xed000000000fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0}, |
850 | 8f860bb8 | ths | { "maeb", OP48(0xed000000000eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0}, |
851 | 8f860bb8 | ths | { "deb", OP48(0xed000000000dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
852 | 8f860bb8 | ths | { "mdeb", OP48(0xed000000000cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
853 | 8f860bb8 | ths | { "seb", OP48(0xed000000000bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
854 | 8f860bb8 | ths | { "aeb", OP48(0xed000000000aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
855 | 8f860bb8 | ths | { "ceb", OP48(0xed0000000009LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
856 | 8f860bb8 | ths | { "keb", OP48(0xed0000000008LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
857 | 8f860bb8 | ths | { "mxdb", OP48(0xed0000000007LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
858 | 8f860bb8 | ths | { "lxeb", OP48(0xed0000000006LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
859 | 8f860bb8 | ths | { "lxdb", OP48(0xed0000000005LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
860 | 8f860bb8 | ths | { "ldeb", OP48(0xed0000000004LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0}, |
861 | 8f860bb8 | ths | { "brxlg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2}, |
862 | 8f860bb8 | ths | { "brxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2}, |
863 | 8f860bb8 | ths | { "tp", OP48(0xeb00000000c0LL), MASK_RSL_R0RD, INSTR_RSL_R0RD, 3, 0}, |
864 | 8f860bb8 | ths | { "stamy", OP48(0xeb000000009bLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3}, |
865 | 8f860bb8 | ths | { "lamy", OP48(0xeb000000009aLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3}, |
866 | 8f860bb8 | ths | { "lmy", OP48(0xeb0000000098LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
867 | 8f860bb8 | ths | { "lmh", OP48(0xeb0000000096LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
868 | 8f860bb8 | ths | { "lmh", OP48(0xeb0000000096LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
869 | 8f860bb8 | ths | { "stmy", OP48(0xeb0000000090LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
870 | 8f860bb8 | ths | { "clclu", OP48(0xeb000000008fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
871 | 8f860bb8 | ths | { "mvclu", OP48(0xeb000000008eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3}, |
872 | 8f860bb8 | ths | { "mvclu", OP48(0xeb000000008eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0}, |
873 | 8f860bb8 | ths | { "icmy", OP48(0xeb0000000081LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
874 | 8f860bb8 | ths | { "icmh", OP48(0xeb0000000080LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
875 | 8f860bb8 | ths | { "icmh", OP48(0xeb0000000080LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2}, |
876 | 8f860bb8 | ths | { "xiy", OP48(0xeb0000000057LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
877 | 8f860bb8 | ths | { "oiy", OP48(0xeb0000000056LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
878 | 8f860bb8 | ths | { "cliy", OP48(0xeb0000000055LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
879 | 8f860bb8 | ths | { "niy", OP48(0xeb0000000054LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
880 | 8f860bb8 | ths | { "mviy", OP48(0xeb0000000052LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
881 | 8f860bb8 | ths | { "tmy", OP48(0xeb0000000051LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3}, |
882 | 8f860bb8 | ths | { "bxleg", OP48(0xeb0000000045LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
883 | 8f860bb8 | ths | { "bxleg", OP48(0xeb0000000045LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
884 | 8f860bb8 | ths | { "bxhg", OP48(0xeb0000000044LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
885 | 8f860bb8 | ths | { "bxhg", OP48(0xeb0000000044LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
886 | 8f860bb8 | ths | { "cdsg", OP48(0xeb000000003eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
887 | 8f860bb8 | ths | { "cdsg", OP48(0xeb000000003eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
888 | 8f860bb8 | ths | { "cdsy", OP48(0xeb0000000031LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
889 | 8f860bb8 | ths | { "csg", OP48(0xeb0000000030LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
890 | 8f860bb8 | ths | { "csg", OP48(0xeb0000000030LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
891 | 8f860bb8 | ths | { "lctlg", OP48(0xeb000000002fLL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3}, |
892 | 8f860bb8 | ths | { "lctlg", OP48(0xeb000000002fLL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2}, |
893 | 8f860bb8 | ths | { "stcmy", OP48(0xeb000000002dLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
894 | 8f860bb8 | ths | { "stcmh", OP48(0xeb000000002cLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
895 | 8f860bb8 | ths | { "stcmh", OP48(0xeb000000002cLL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2}, |
896 | 8f860bb8 | ths | { "stmh", OP48(0xeb0000000026LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
897 | 8f860bb8 | ths | { "stmh", OP48(0xeb0000000026LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
898 | 8f860bb8 | ths | { "stctg", OP48(0xeb0000000025LL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3}, |
899 | 8f860bb8 | ths | { "stctg", OP48(0xeb0000000025LL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2}, |
900 | 8f860bb8 | ths | { "stmg", OP48(0xeb0000000024LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
901 | 8f860bb8 | ths | { "stmg", OP48(0xeb0000000024LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
902 | 8f860bb8 | ths | { "clmy", OP48(0xeb0000000021LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
903 | 8f860bb8 | ths | { "clmh", OP48(0xeb0000000020LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3}, |
904 | 8f860bb8 | ths | { "clmh", OP48(0xeb0000000020LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2}, |
905 | 8f860bb8 | ths | { "rll", OP48(0xeb000000001dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3}, |
906 | 8f860bb8 | ths | { "rll", OP48(0xeb000000001dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 2}, |
907 | 8f860bb8 | ths | { "rllg", OP48(0xeb000000001cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
908 | 8f860bb8 | ths | { "rllg", OP48(0xeb000000001cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
909 | 8f860bb8 | ths | { "csy", OP48(0xeb0000000014LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
910 | 8f860bb8 | ths | { "tracg", OP48(0xeb000000000fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
911 | 8f860bb8 | ths | { "tracg", OP48(0xeb000000000fLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
912 | 8f860bb8 | ths | { "sllg", OP48(0xeb000000000dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
913 | 8f860bb8 | ths | { "sllg", OP48(0xeb000000000dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
914 | 8f860bb8 | ths | { "srlg", OP48(0xeb000000000cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
915 | 8f860bb8 | ths | { "srlg", OP48(0xeb000000000cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
916 | 8f860bb8 | ths | { "slag", OP48(0xeb000000000bLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
917 | 8f860bb8 | ths | { "slag", OP48(0xeb000000000bLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
918 | 8f860bb8 | ths | { "srag", OP48(0xeb000000000aLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
919 | 8f860bb8 | ths | { "srag", OP48(0xeb000000000aLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
920 | 8f860bb8 | ths | { "lmg", OP48(0xeb0000000004LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3}, |
921 | 8f860bb8 | ths | { "lmg", OP48(0xeb0000000004LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2}, |
922 | 8f860bb8 | ths | { "unpka", OP8(0xeaLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
923 | 8f860bb8 | ths | { "pka", OP8(0xe9LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0}, |
924 | 8f860bb8 | ths | { "mvcin", OP8(0xe8LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
925 | 8f860bb8 | ths | { "mvcdk", OP16(0xe50fLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, |
926 | 8f860bb8 | ths | { "mvcsk", OP16(0xe50eLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, |
927 | 8f860bb8 | ths | { "tprot", OP16(0xe501LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, |
928 | 8f860bb8 | ths | { "strag", OP48(0xe50000000002LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 2}, |
929 | 8f860bb8 | ths | { "lasp", OP16(0xe500LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0}, |
930 | 8f860bb8 | ths | { "slb", OP48(0xe30000000099LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
931 | 8f860bb8 | ths | { "slb", OP48(0xe30000000099LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
932 | 8f860bb8 | ths | { "alc", OP48(0xe30000000098LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
933 | 8f860bb8 | ths | { "alc", OP48(0xe30000000098LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
934 | 8f860bb8 | ths | { "dl", OP48(0xe30000000097LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
935 | 8f860bb8 | ths | { "dl", OP48(0xe30000000097LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
936 | 8f860bb8 | ths | { "ml", OP48(0xe30000000096LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
937 | 8f860bb8 | ths | { "ml", OP48(0xe30000000096LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
938 | 8f860bb8 | ths | { "llh", OP48(0xe30000000095LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4}, |
939 | 8f860bb8 | ths | { "llc", OP48(0xe30000000094LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4}, |
940 | 8f860bb8 | ths | { "llgh", OP48(0xe30000000091LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
941 | 8f860bb8 | ths | { "llgh", OP48(0xe30000000091LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
942 | 8f860bb8 | ths | { "llgc", OP48(0xe30000000090LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
943 | 8f860bb8 | ths | { "llgc", OP48(0xe30000000090LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
944 | 8f860bb8 | ths | { "lpq", OP48(0xe3000000008fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
945 | 8f860bb8 | ths | { "lpq", OP48(0xe3000000008fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
946 | 8f860bb8 | ths | { "stpq", OP48(0xe3000000008eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
947 | 8f860bb8 | ths | { "stpq", OP48(0xe3000000008eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
948 | 8f860bb8 | ths | { "slbg", OP48(0xe30000000089LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
949 | 8f860bb8 | ths | { "slbg", OP48(0xe30000000089LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
950 | 8f860bb8 | ths | { "alcg", OP48(0xe30000000088LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
951 | 8f860bb8 | ths | { "alcg", OP48(0xe30000000088LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
952 | 8f860bb8 | ths | { "dlg", OP48(0xe30000000087LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
953 | 8f860bb8 | ths | { "dlg", OP48(0xe30000000087LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
954 | 8f860bb8 | ths | { "mlg", OP48(0xe30000000086LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
955 | 8f860bb8 | ths | { "mlg", OP48(0xe30000000086LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
956 | 8f860bb8 | ths | { "xg", OP48(0xe30000000082LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
957 | 8f860bb8 | ths | { "xg", OP48(0xe30000000082LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
958 | 8f860bb8 | ths | { "og", OP48(0xe30000000081LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
959 | 8f860bb8 | ths | { "og", OP48(0xe30000000081LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
960 | 8f860bb8 | ths | { "ng", OP48(0xe30000000080LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
961 | 8f860bb8 | ths | { "ng", OP48(0xe30000000080LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
962 | 8f860bb8 | ths | { "shy", OP48(0xe3000000007bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
963 | 8f860bb8 | ths | { "ahy", OP48(0xe3000000007aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
964 | 8f860bb8 | ths | { "chy", OP48(0xe30000000079LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
965 | 8f860bb8 | ths | { "lhy", OP48(0xe30000000078LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
966 | 8f860bb8 | ths | { "lgb", OP48(0xe30000000077LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
967 | 8f860bb8 | ths | { "lb", OP48(0xe30000000076LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
968 | 8f860bb8 | ths | { "icy", OP48(0xe30000000073LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
969 | 8f860bb8 | ths | { "stcy", OP48(0xe30000000072LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
970 | 8f860bb8 | ths | { "lay", OP48(0xe30000000071LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
971 | 8f860bb8 | ths | { "sthy", OP48(0xe30000000070LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
972 | 8f860bb8 | ths | { "sly", OP48(0xe3000000005fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
973 | 8f860bb8 | ths | { "aly", OP48(0xe3000000005eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
974 | 8f860bb8 | ths | { "sy", OP48(0xe3000000005bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
975 | 8f860bb8 | ths | { "ay", OP48(0xe3000000005aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
976 | 8f860bb8 | ths | { "cy", OP48(0xe30000000059LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
977 | 8f860bb8 | ths | { "ly", OP48(0xe30000000058LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
978 | 8f860bb8 | ths | { "xy", OP48(0xe30000000057LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
979 | 8f860bb8 | ths | { "oy", OP48(0xe30000000056LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
980 | 8f860bb8 | ths | { "cly", OP48(0xe30000000055LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
981 | 8f860bb8 | ths | { "ny", OP48(0xe30000000054LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
982 | 8f860bb8 | ths | { "msy", OP48(0xe30000000051LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
983 | 8f860bb8 | ths | { "sty", OP48(0xe30000000050LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
984 | 8f860bb8 | ths | { "bctg", OP48(0xe30000000046LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
985 | 8f860bb8 | ths | { "bctg", OP48(0xe30000000046LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
986 | 8f860bb8 | ths | { "strvh", OP48(0xe3000000003fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
987 | 8f860bb8 | ths | { "strvh", OP48(0xe3000000003fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
988 | 8f860bb8 | ths | { "strv", OP48(0xe3000000003eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
989 | 8f860bb8 | ths | { "strv", OP48(0xe3000000003eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
990 | 8f860bb8 | ths | { "clgf", OP48(0xe30000000031LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
991 | 8f860bb8 | ths | { "clgf", OP48(0xe30000000031LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
992 | 8f860bb8 | ths | { "cgf", OP48(0xe30000000030LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
993 | 8f860bb8 | ths | { "cgf", OP48(0xe30000000030LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
994 | 8f860bb8 | ths | { "strvg", OP48(0xe3000000002fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
995 | 8f860bb8 | ths | { "strvg", OP48(0xe3000000002fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
996 | 8f860bb8 | ths | { "cvdg", OP48(0xe3000000002eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
997 | 8f860bb8 | ths | { "cvdg", OP48(0xe3000000002eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
998 | 8f860bb8 | ths | { "cvdy", OP48(0xe30000000026LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
999 | 8f860bb8 | ths | { "stg", OP48(0xe30000000024LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1000 | 8f860bb8 | ths | { "stg", OP48(0xe30000000024LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1001 | 8f860bb8 | ths | { "clg", OP48(0xe30000000021LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1002 | 8f860bb8 | ths | { "clg", OP48(0xe30000000021LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1003 | 8f860bb8 | ths | { "cg", OP48(0xe30000000020LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1004 | 8f860bb8 | ths | { "cg", OP48(0xe30000000020LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1005 | 8f860bb8 | ths | { "lrvh", OP48(0xe3000000001fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
1006 | 8f860bb8 | ths | { "lrvh", OP48(0xe3000000001fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
1007 | 8f860bb8 | ths | { "lrv", OP48(0xe3000000001eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3}, |
1008 | 8f860bb8 | ths | { "lrv", OP48(0xe3000000001eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2}, |
1009 | 8f860bb8 | ths | { "dsgf", OP48(0xe3000000001dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1010 | 8f860bb8 | ths | { "dsgf", OP48(0xe3000000001dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1011 | 8f860bb8 | ths | { "msgf", OP48(0xe3000000001cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1012 | 8f860bb8 | ths | { "msgf", OP48(0xe3000000001cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1013 | 8f860bb8 | ths | { "slgf", OP48(0xe3000000001bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1014 | 8f860bb8 | ths | { "slgf", OP48(0xe3000000001bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1015 | 8f860bb8 | ths | { "algf", OP48(0xe3000000001aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1016 | 8f860bb8 | ths | { "algf", OP48(0xe3000000001aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1017 | 8f860bb8 | ths | { "sgf", OP48(0xe30000000019LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1018 | 8f860bb8 | ths | { "sgf", OP48(0xe30000000019LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1019 | 8f860bb8 | ths | { "agf", OP48(0xe30000000018LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1020 | 8f860bb8 | ths | { "agf", OP48(0xe30000000018LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1021 | 8f860bb8 | ths | { "llgt", OP48(0xe30000000017LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1022 | 8f860bb8 | ths | { "llgt", OP48(0xe30000000017LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1023 | 8f860bb8 | ths | { "llgf", OP48(0xe30000000016LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1024 | 8f860bb8 | ths | { "llgf", OP48(0xe30000000016LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1025 | 8f860bb8 | ths | { "lgh", OP48(0xe30000000015LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1026 | 8f860bb8 | ths | { "lgh", OP48(0xe30000000015LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1027 | 8f860bb8 | ths | { "lgf", OP48(0xe30000000014LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1028 | 8f860bb8 | ths | { "lgf", OP48(0xe30000000014LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1029 | 8f860bb8 | ths | { "lray", OP48(0xe30000000013LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1030 | 8f860bb8 | ths | { "lt", OP48(0xe30000000012LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4}, |
1031 | 8f860bb8 | ths | { "lrvg", OP48(0xe3000000000fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1032 | 8f860bb8 | ths | { "lrvg", OP48(0xe3000000000fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1033 | 8f860bb8 | ths | { "cvbg", OP48(0xe3000000000eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1034 | 8f860bb8 | ths | { "cvbg", OP48(0xe3000000000eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1035 | 8f860bb8 | ths | { "dsg", OP48(0xe3000000000dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1036 | 8f860bb8 | ths | { "dsg", OP48(0xe3000000000dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1037 | 8f860bb8 | ths | { "msg", OP48(0xe3000000000cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1038 | 8f860bb8 | ths | { "msg", OP48(0xe3000000000cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1039 | 8f860bb8 | ths | { "slg", OP48(0xe3000000000bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1040 | 8f860bb8 | ths | { "slg", OP48(0xe3000000000bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1041 | 8f860bb8 | ths | { "alg", OP48(0xe3000000000aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1042 | 8f860bb8 | ths | { "alg", OP48(0xe3000000000aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1043 | 8f860bb8 | ths | { "sg", OP48(0xe30000000009LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1044 | 8f860bb8 | ths | { "sg", OP48(0xe30000000009LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1045 | 8f860bb8 | ths | { "ag", OP48(0xe30000000008LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1046 | 8f860bb8 | ths | { "ag", OP48(0xe30000000008LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1047 | 8f860bb8 | ths | { "cvby", OP48(0xe30000000006LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1048 | 8f860bb8 | ths | { "lg", OP48(0xe30000000004LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1049 | 8f860bb8 | ths | { "lg", OP48(0xe30000000004LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1050 | 8f860bb8 | ths | { "lrag", OP48(0xe30000000003LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3}, |
1051 | 8f860bb8 | ths | { "lrag", OP48(0xe30000000003LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2}, |
1052 | 8f860bb8 | ths | { "ltg", OP48(0xe30000000002LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4}, |
1053 | 8f860bb8 | ths | { "unpku", OP8(0xe2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1054 | 8f860bb8 | ths | { "pku", OP8(0xe1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1055 | 8f860bb8 | ths | { "edmk", OP8(0xdfLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1056 | 8f860bb8 | ths | { "ed", OP8(0xdeLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1057 | 8f860bb8 | ths | { "trt", OP8(0xddLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1058 | 8f860bb8 | ths | { "tr", OP8(0xdcLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1059 | 8f860bb8 | ths | { "mvcs", OP8(0xdbLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0}, |
1060 | 8f860bb8 | ths | { "mvcp", OP8(0xdaLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0}, |
1061 | 8f860bb8 | ths | { "mvck", OP8(0xd9LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0}, |
1062 | 8f860bb8 | ths | { "xc", OP8(0xd7LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1063 | 8f860bb8 | ths | { "oc", OP8(0xd6LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1064 | 8f860bb8 | ths | { "clc", OP8(0xd5LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1065 | 8f860bb8 | ths | { "nc", OP8(0xd4LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1066 | 8f860bb8 | ths | { "mvz", OP8(0xd3LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1067 | 8f860bb8 | ths | { "mvc", OP8(0xd2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1068 | 8f860bb8 | ths | { "mvn", OP8(0xd1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0}, |
1069 | 8f860bb8 | ths | { "csst", OP16(0xc802LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5}, |
1070 | 8f860bb8 | ths | { "ectg", OP16(0xc801LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5}, |
1071 | 8f860bb8 | ths | { "mvcos", OP16(0xc800LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 4}, |
1072 | 8f860bb8 | ths | { "clfi", OP16(0xc20fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1073 | 8f860bb8 | ths | { "clgfi", OP16(0xc20eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1074 | 8f860bb8 | ths | { "cfi", OP16(0xc20dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, |
1075 | 8f860bb8 | ths | { "cgfi", OP16(0xc20cLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, |
1076 | 8f860bb8 | ths | { "alfi", OP16(0xc20bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1077 | 8f860bb8 | ths | { "algfi", OP16(0xc20aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1078 | 8f860bb8 | ths | { "afi", OP16(0xc209LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, |
1079 | 8f860bb8 | ths | { "agfi", OP16(0xc208LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, |
1080 | 8f860bb8 | ths | { "slfi", OP16(0xc205LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1081 | 8f860bb8 | ths | { "slgfi", OP16(0xc204LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1082 | 8f860bb8 | ths | { "jg", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1083 | 8f860bb8 | ths | { "jgno", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1084 | 8f860bb8 | ths | { "jgnh", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1085 | 8f860bb8 | ths | { "jgnp", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1086 | 8f860bb8 | ths | { "jgle", OP16(0xc0c4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1087 | 8f860bb8 | ths | { "jgnl", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1088 | 8f860bb8 | ths | { "jgnm", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1089 | 8f860bb8 | ths | { "jghe", OP16(0xc0a4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1090 | 8f860bb8 | ths | { "jgnlh", OP16(0xc094LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1091 | 8f860bb8 | ths | { "jge", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1092 | 8f860bb8 | ths | { "jgz", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1093 | 8f860bb8 | ths | { "jgne", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1094 | 8f860bb8 | ths | { "jgnz", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1095 | 8f860bb8 | ths | { "jglh", OP16(0xc064LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1096 | 8f860bb8 | ths | { "jgnhe", OP16(0xc054LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1097 | 8f860bb8 | ths | { "jgl", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1098 | 8f860bb8 | ths | { "jgm", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1099 | 8f860bb8 | ths | { "jgnle", OP16(0xc034LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1100 | 8f860bb8 | ths | { "jgh", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1101 | 8f860bb8 | ths | { "jgp", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1102 | 8f860bb8 | ths | { "jgo", OP16(0xc014LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2}, |
1103 | 8f860bb8 | ths | { "llilf", OP16(0xc00fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1104 | 8f860bb8 | ths | { "llihf", OP16(0xc00eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1105 | 8f860bb8 | ths | { "oilf", OP16(0xc00dLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1106 | 8f860bb8 | ths | { "oihf", OP16(0xc00cLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1107 | 8f860bb8 | ths | { "nilf", OP16(0xc00bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1108 | 8f860bb8 | ths | { "nihf", OP16(0xc00aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1109 | 8f860bb8 | ths | { "iilf", OP16(0xc009LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1110 | 8f860bb8 | ths | { "iihf", OP16(0xc008LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1111 | 8f860bb8 | ths | { "xilf", OP16(0xc007LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1112 | 8f860bb8 | ths | { "xihf", OP16(0xc006LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4}, |
1113 | 8f860bb8 | ths | { "brasl", OP16(0xc005LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2}, |
1114 | 8f860bb8 | ths | { "brcl", OP16(0xc004LL), MASK_RIL_UP, INSTR_RIL_UP, 3, 2}, |
1115 | 8f860bb8 | ths | { "lgfi", OP16(0xc001LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4}, |
1116 | 8f860bb8 | ths | { "larl", OP16(0xc000LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2}, |
1117 | 8f860bb8 | ths | { "icm", OP8(0xbfLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0}, |
1118 | 8f860bb8 | ths | { "stcm", OP8(0xbeLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0}, |
1119 | 8f860bb8 | ths | { "clm", OP8(0xbdLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0}, |
1120 | 8f860bb8 | ths | { "cds", OP8(0xbbLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1121 | 8f860bb8 | ths | { "cs", OP8(0xbaLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1122 | 8f860bb8 | ths | { "cu42", OP16(0xb9b3LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
1123 | 8f860bb8 | ths | { "cu41", OP16(0xb9b2LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
1124 | 8f860bb8 | ths | { "cu24", OP16(0xb9b1LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
1125 | 8f860bb8 | ths | { "cu14", OP16(0xb9b0LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
1126 | 8f860bb8 | ths | { "lptea", OP16(0xb9aaLL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 4}, |
1127 | 8f860bb8 | ths | { "esea", OP16(0xb99dLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 2}, |
1128 | 8f860bb8 | ths | { "slbr", OP16(0xb999LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
1129 | 8f860bb8 | ths | { "alcr", OP16(0xb998LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
1130 | 8f860bb8 | ths | { "dlr", OP16(0xb997LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
1131 | 8f860bb8 | ths | { "mlr", OP16(0xb996LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
1132 | 8f860bb8 | ths | { "llhr", OP16(0xb995LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
1133 | 8f860bb8 | ths | { "llcr", OP16(0xb994LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
1134 | 8f860bb8 | ths | { "troo", OP16(0xb993LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4}, |
1135 | 8f860bb8 | ths | { "troo", OP16(0xb993LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1136 | 8f860bb8 | ths | { "trot", OP16(0xb992LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4}, |
1137 | 8f860bb8 | ths | { "trot", OP16(0xb992LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1138 | 8f860bb8 | ths | { "trto", OP16(0xb991LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4}, |
1139 | 8f860bb8 | ths | { "trto", OP16(0xb991LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1140 | 8f860bb8 | ths | { "trtt", OP16(0xb990LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4}, |
1141 | 8f860bb8 | ths | { "trtt", OP16(0xb990LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1142 | 8f860bb8 | ths | { "idte", OP16(0xb98eLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 2, 3}, |
1143 | 8f860bb8 | ths | { "epsw", OP16(0xb98dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
1144 | 8f860bb8 | ths | { "cspg", OP16(0xb98aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 3}, |
1145 | 8f860bb8 | ths | { "slbgr", OP16(0xb989LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1146 | 8f860bb8 | ths | { "alcgr", OP16(0xb988LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1147 | 8f860bb8 | ths | { "dlgr", OP16(0xb987LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1148 | 8f860bb8 | ths | { "mlgr", OP16(0xb986LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1149 | 8f860bb8 | ths | { "llghr", OP16(0xb985LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
1150 | 8f860bb8 | ths | { "llgcr", OP16(0xb984LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
1151 | 8f860bb8 | ths | { "flogr", OP16(0xb983LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
1152 | 8f860bb8 | ths | { "xgr", OP16(0xb982LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1153 | 8f860bb8 | ths | { "ogr", OP16(0xb981LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1154 | 8f860bb8 | ths | { "ngr", OP16(0xb980LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1155 | 8f860bb8 | ths | { "bctgr", OP16(0xb946LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1156 | 8f860bb8 | ths | { "klmd", OP16(0xb93fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, |
1157 | 8f860bb8 | ths | { "kimd", OP16(0xb93eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, |
1158 | 8f860bb8 | ths | { "clgfr", OP16(0xb931LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1159 | 8f860bb8 | ths | { "cgfr", OP16(0xb930LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1160 | 8f860bb8 | ths | { "kmc", OP16(0xb92fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, |
1161 | 8f860bb8 | ths | { "km", OP16(0xb92eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, |
1162 | 8f860bb8 | ths | { "lhr", OP16(0xb927LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
1163 | 8f860bb8 | ths | { "lbr", OP16(0xb926LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
1164 | 8f860bb8 | ths | { "sturg", OP16(0xb925LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1165 | 8f860bb8 | ths | { "clgr", OP16(0xb921LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1166 | 8f860bb8 | ths | { "cgr", OP16(0xb920LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1167 | 8f860bb8 | ths | { "lrvr", OP16(0xb91fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2}, |
1168 | 8f860bb8 | ths | { "kmac", OP16(0xb91eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3}, |
1169 | 8f860bb8 | ths | { "dsgfr", OP16(0xb91dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1170 | 8f860bb8 | ths | { "msgfr", OP16(0xb91cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1171 | 8f860bb8 | ths | { "slgfr", OP16(0xb91bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1172 | 8f860bb8 | ths | { "algfr", OP16(0xb91aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1173 | 8f860bb8 | ths | { "sgfr", OP16(0xb919LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1174 | 8f860bb8 | ths | { "agfr", OP16(0xb918LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1175 | 8f860bb8 | ths | { "llgtr", OP16(0xb917LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1176 | 8f860bb8 | ths | { "llgfr", OP16(0xb916LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1177 | 8f860bb8 | ths | { "lgfr", OP16(0xb914LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1178 | 8f860bb8 | ths | { "lcgfr", OP16(0xb913LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1179 | 8f860bb8 | ths | { "ltgfr", OP16(0xb912LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1180 | 8f860bb8 | ths | { "lngfr", OP16(0xb911LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1181 | 8f860bb8 | ths | { "lpgfr", OP16(0xb910LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1182 | 8f860bb8 | ths | { "lrvgr", OP16(0xb90fLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1183 | 8f860bb8 | ths | { "eregg", OP16(0xb90eLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1184 | 8f860bb8 | ths | { "dsgr", OP16(0xb90dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1185 | 8f860bb8 | ths | { "msgr", OP16(0xb90cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1186 | 8f860bb8 | ths | { "slgr", OP16(0xb90bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1187 | 8f860bb8 | ths | { "algr", OP16(0xb90aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1188 | 8f860bb8 | ths | { "sgr", OP16(0xb909LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1189 | 8f860bb8 | ths | { "agr", OP16(0xb908LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1190 | 8f860bb8 | ths | { "lghr", OP16(0xb907LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
1191 | 8f860bb8 | ths | { "lgbr", OP16(0xb906LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4}, |
1192 | 8f860bb8 | ths | { "lurag", OP16(0xb905LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1193 | 8f860bb8 | ths | { "lgr", OP16(0xb904LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1194 | 8f860bb8 | ths | { "lcgr", OP16(0xb903LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1195 | 8f860bb8 | ths | { "ltgr", OP16(0xb902LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1196 | 8f860bb8 | ths | { "lngr", OP16(0xb901LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1197 | 8f860bb8 | ths | { "lpgr", OP16(0xb900LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1198 | 8f860bb8 | ths | { "lctl", OP8(0xb7LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0}, |
1199 | 8f860bb8 | ths | { "stctl", OP8(0xb6LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0}, |
1200 | 8f860bb8 | ths | { "rrxtr", OP16(0xb3ffLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, |
1201 | 8f860bb8 | ths | { "iextr", OP16(0xb3feLL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5}, |
1202 | 8f860bb8 | ths | { "qaxtr", OP16(0xb3fdLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, |
1203 | 8f860bb8 | ths | { "cextr", OP16(0xb3fcLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1204 | 8f860bb8 | ths | { "cxstr", OP16(0xb3fbLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
1205 | 8f860bb8 | ths | { "cxutr", OP16(0xb3faLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
1206 | 8f860bb8 | ths | { "cxgtr", OP16(0xb3f9LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
1207 | 8f860bb8 | ths | { "rrdtr", OP16(0xb3f7LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, |
1208 | 8f860bb8 | ths | { "iedtr", OP16(0xb3f6LL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5}, |
1209 | 8f860bb8 | ths | { "qadtr", OP16(0xb3f5LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5}, |
1210 | 8f860bb8 | ths | { "cedtr", OP16(0xb3f4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1211 | 8f860bb8 | ths | { "cdstr", OP16(0xb3f3LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
1212 | 8f860bb8 | ths | { "cdutr", OP16(0xb3f2LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
1213 | 8f860bb8 | ths | { "cdgtr", OP16(0xb3f1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
1214 | 8f860bb8 | ths | { "esxtr", OP16(0xb3efLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
1215 | 8f860bb8 | ths | { "eextr", OP16(0xb3edLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
1216 | 8f860bb8 | ths | { "cxtr", OP16(0xb3ecLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1217 | 8f860bb8 | ths | { "csxtr", OP16(0xb3ebLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
1218 | 8f860bb8 | ths | { "cuxtr", OP16(0xb3eaLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
1219 | 8f860bb8 | ths | { "cgxtr", OP16(0xb3e9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5}, |
1220 | 8f860bb8 | ths | { "kxtr", OP16(0xb3e8LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1221 | 8f860bb8 | ths | { "esdtr", OP16(0xb3e7LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
1222 | 8f860bb8 | ths | { "eedtr", OP16(0xb3e5LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
1223 | 8f860bb8 | ths | { "cdtr", OP16(0xb3e4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1224 | 8f860bb8 | ths | { "csdtr", OP16(0xb3e3LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
1225 | 8f860bb8 | ths | { "cudtr", OP16(0xb3e2LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
1226 | 8f860bb8 | ths | { "cgdtr", OP16(0xb3e1LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5}, |
1227 | 8f860bb8 | ths | { "kdtr", OP16(0xb3e0LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1228 | 8f860bb8 | ths | { "fixtr", OP16(0xb3dfLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5}, |
1229 | 8f860bb8 | ths | { "ltxtr", OP16(0xb3deLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1230 | 8f860bb8 | ths | { "ldxtr", OP16(0xb3ddLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5}, |
1231 | 8f860bb8 | ths | { "lxdtr", OP16(0xb3dcLL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5}, |
1232 | 8f860bb8 | ths | { "sxtr", OP16(0xb3dbLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
1233 | 8f860bb8 | ths | { "axtr", OP16(0xb3daLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
1234 | 8f860bb8 | ths | { "dxtr", OP16(0xb3d9LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
1235 | 8f860bb8 | ths | { "mxtr", OP16(0xb3d8LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
1236 | 8f860bb8 | ths | { "fidtr", OP16(0xb3d7LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5}, |
1237 | 8f860bb8 | ths | { "ltdtr", OP16(0xb3d6LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1238 | 8f860bb8 | ths | { "ledtr", OP16(0xb3d5LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5}, |
1239 | 8f860bb8 | ths | { "ldetr", OP16(0xb3d4LL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5}, |
1240 | 8f860bb8 | ths | { "sdtr", OP16(0xb3d3LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
1241 | 8f860bb8 | ths | { "adtr", OP16(0xb3d2LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
1242 | 8f860bb8 | ths | { "ddtr", OP16(0xb3d1LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
1243 | 8f860bb8 | ths | { "mdtr", OP16(0xb3d0LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5}, |
1244 | 8f860bb8 | ths | { "lgdr", OP16(0xb3cdLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5}, |
1245 | 8f860bb8 | ths | { "cgxr", OP16(0xb3caLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
1246 | 8f860bb8 | ths | { "cgdr", OP16(0xb3c9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
1247 | 8f860bb8 | ths | { "cger", OP16(0xb3c8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
1248 | 8f860bb8 | ths | { "cxgr", OP16(0xb3c6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1249 | 8f860bb8 | ths | { "cdgr", OP16(0xb3c5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1250 | 8f860bb8 | ths | { "cegr", OP16(0xb3c4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1251 | 8f860bb8 | ths | { "ldgr", OP16(0xb3c1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5}, |
1252 | 8f860bb8 | ths | { "cfxr", OP16(0xb3baLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
1253 | 8f860bb8 | ths | { "cfdr", OP16(0xb3b9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
1254 | 8f860bb8 | ths | { "cfer", OP16(0xb3b8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
1255 | 8f860bb8 | ths | { "cxfr", OP16(0xb3b6LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
1256 | 8f860bb8 | ths | { "cdfr", OP16(0xb3b5LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
1257 | 8f860bb8 | ths | { "cefr", OP16(0xb3b4LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
1258 | 8f860bb8 | ths | { "cgxbr", OP16(0xb3aaLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
1259 | 8f860bb8 | ths | { "cgdbr", OP16(0xb3a9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
1260 | 8f860bb8 | ths | { "cgebr", OP16(0xb3a8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2}, |
1261 | 8f860bb8 | ths | { "cxgbr", OP16(0xb3a6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1262 | 8f860bb8 | ths | { "cdgbr", OP16(0xb3a5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1263 | 8f860bb8 | ths | { "cegbr", OP16(0xb3a4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2}, |
1264 | 8f860bb8 | ths | { "cfxbr", OP16(0xb39aLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0}, |
1265 | 8f860bb8 | ths | { "cfdbr", OP16(0xb399LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0}, |
1266 | 8f860bb8 | ths | { "cfebr", OP16(0xb398LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0}, |
1267 | 8f860bb8 | ths | { "cxfbr", OP16(0xb396LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
1268 | 8f860bb8 | ths | { "cdfbr", OP16(0xb395LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
1269 | 8f860bb8 | ths | { "cefbr", OP16(0xb394LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0}, |
1270 | 8f860bb8 | ths | { "efpc", OP16(0xb38cLL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0}, |
1271 | 8f860bb8 | ths | { "sfasr", OP16(0xb385LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 5}, |
1272 | 8f860bb8 | ths | { "sfpc", OP16(0xb384LL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0}, |
1273 | 8f860bb8 | ths | { "fidr", OP16(0xb37fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
1274 | 8f860bb8 | ths | { "fier", OP16(0xb377LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
1275 | 8f860bb8 | ths | { "lzxr", OP16(0xb376LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
1276 | 8f860bb8 | ths | { "lzdr", OP16(0xb375LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
1277 | 8f860bb8 | ths | { "lzer", OP16(0xb374LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
1278 | 8f860bb8 | ths | { "lcdfr", OP16(0xb373LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1279 | 8f860bb8 | ths | { "cpsdr", OP16(0xb372LL), MASK_RRF_F0FF2, INSTR_RRF_F0FF2, 2, 5}, |
1280 | 8f860bb8 | ths | { "lndfr", OP16(0xb371LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1281 | 8f860bb8 | ths | { "lpdfr", OP16(0xb370LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5}, |
1282 | 8f860bb8 | ths | { "cxr", OP16(0xb369LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1283 | 8f860bb8 | ths | { "fixr", OP16(0xb367LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
1284 | 8f860bb8 | ths | { "lexr", OP16(0xb366LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1285 | 8f860bb8 | ths | { "lxr", OP16(0xb365LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1286 | 8f860bb8 | ths | { "lcxr", OP16(0xb363LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1287 | 8f860bb8 | ths | { "ltxr", OP16(0xb362LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1288 | 8f860bb8 | ths | { "lnxr", OP16(0xb361LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1289 | 8f860bb8 | ths | { "lpxr", OP16(0xb360LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1290 | 8f860bb8 | ths | { "fidbr", OP16(0xb35fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
1291 | 8f860bb8 | ths | { "didbr", OP16(0xb35bLL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0}, |
1292 | 8f860bb8 | ths | { "thdr", OP16(0xb359LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1293 | 8f860bb8 | ths | { "thder", OP16(0xb358LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1294 | 8f860bb8 | ths | { "fiebr", OP16(0xb357LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
1295 | 8f860bb8 | ths | { "diebr", OP16(0xb353LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0}, |
1296 | 8f860bb8 | ths | { "tbdr", OP16(0xb351LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
1297 | 8f860bb8 | ths | { "tbedr", OP16(0xb350LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
1298 | 8f860bb8 | ths | { "dxbr", OP16(0xb34dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1299 | 8f860bb8 | ths | { "mxbr", OP16(0xb34cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1300 | 8f860bb8 | ths | { "sxbr", OP16(0xb34bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1301 | 8f860bb8 | ths | { "axbr", OP16(0xb34aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1302 | 8f860bb8 | ths | { "cxbr", OP16(0xb349LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1303 | 8f860bb8 | ths | { "kxbr", OP16(0xb348LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1304 | 8f860bb8 | ths | { "fixbr", OP16(0xb347LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0}, |
1305 | 8f860bb8 | ths | { "lexbr", OP16(0xb346LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1306 | 8f860bb8 | ths | { "ldxbr", OP16(0xb345LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1307 | 8f860bb8 | ths | { "ledbr", OP16(0xb344LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1308 | 8f860bb8 | ths | { "lcxbr", OP16(0xb343LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1309 | 8f860bb8 | ths | { "ltxbr", OP16(0xb342LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1310 | 8f860bb8 | ths | { "lnxbr", OP16(0xb341LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1311 | 8f860bb8 | ths | { "lpxbr", OP16(0xb340LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1312 | 8f860bb8 | ths | { "msdr", OP16(0xb33fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3}, |
1313 | 8f860bb8 | ths | { "madr", OP16(0xb33eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3}, |
1314 | 8f860bb8 | ths | { "myhr", OP16(0xb33dLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
1315 | 8f860bb8 | ths | { "mayhr", OP16(0xb33cLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
1316 | 8f860bb8 | ths | { "myr", OP16(0xb33bLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
1317 | 8f860bb8 | ths | { "mayr", OP16(0xb33aLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
1318 | 8f860bb8 | ths | { "mylr", OP16(0xb339LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
1319 | 8f860bb8 | ths | { "maylr", OP16(0xb338LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4}, |
1320 | 8f860bb8 | ths | { "meer", OP16(0xb337LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1321 | 8f860bb8 | ths | { "sqxr", OP16(0xb336LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1322 | 8f860bb8 | ths | { "mser", OP16(0xb32fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3}, |
1323 | 8f860bb8 | ths | { "maer", OP16(0xb32eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3}, |
1324 | 8f860bb8 | ths | { "lxer", OP16(0xb326LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1325 | 8f860bb8 | ths | { "lxdr", OP16(0xb325LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1326 | 8f860bb8 | ths | { "lder", OP16(0xb324LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1327 | 8f860bb8 | ths | { "msdbr", OP16(0xb31fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0}, |
1328 | 8f860bb8 | ths | { "madbr", OP16(0xb31eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0}, |
1329 | 8f860bb8 | ths | { "ddbr", OP16(0xb31dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1330 | 8f860bb8 | ths | { "mdbr", OP16(0xb31cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1331 | 8f860bb8 | ths | { "sdbr", OP16(0xb31bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1332 | 8f860bb8 | ths | { "adbr", OP16(0xb31aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1333 | 8f860bb8 | ths | { "cdbr", OP16(0xb319LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1334 | 8f860bb8 | ths | { "kdbr", OP16(0xb318LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1335 | 8f860bb8 | ths | { "meebr", OP16(0xb317LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1336 | 8f860bb8 | ths | { "sqxbr", OP16(0xb316LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1337 | 8f860bb8 | ths | { "sqdbr", OP16(0xb315LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1338 | 8f860bb8 | ths | { "sqebr", OP16(0xb314LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1339 | 8f860bb8 | ths | { "lcdbr", OP16(0xb313LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1340 | 8f860bb8 | ths | { "ltdbr", OP16(0xb312LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1341 | 8f860bb8 | ths | { "lndbr", OP16(0xb311LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1342 | 8f860bb8 | ths | { "lpdbr", OP16(0xb310LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1343 | 8f860bb8 | ths | { "msebr", OP16(0xb30fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0}, |
1344 | 8f860bb8 | ths | { "maebr", OP16(0xb30eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0}, |
1345 | 8f860bb8 | ths | { "debr", OP16(0xb30dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1346 | 8f860bb8 | ths | { "mdebr", OP16(0xb30cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1347 | 8f860bb8 | ths | { "sebr", OP16(0xb30bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1348 | 8f860bb8 | ths | { "aebr", OP16(0xb30aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1349 | 8f860bb8 | ths | { "cebr", OP16(0xb309LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1350 | 8f860bb8 | ths | { "kebr", OP16(0xb308LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1351 | 8f860bb8 | ths | { "mxdbr", OP16(0xb307LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1352 | 8f860bb8 | ths | { "lxebr", OP16(0xb306LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1353 | 8f860bb8 | ths | { "lxdbr", OP16(0xb305LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1354 | 8f860bb8 | ths | { "ldebr", OP16(0xb304LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1355 | 8f860bb8 | ths | { "lcebr", OP16(0xb303LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1356 | 8f860bb8 | ths | { "ltebr", OP16(0xb302LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1357 | 8f860bb8 | ths | { "lnebr", OP16(0xb301LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1358 | 8f860bb8 | ths | { "lpebr", OP16(0xb300LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0}, |
1359 | 8f860bb8 | ths | { "trap4", OP16(0xb2ffLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1360 | 8f860bb8 | ths | { "lfas", OP16(0xb2bdLL), MASK_S_RD, INSTR_S_RD, 2, 5}, |
1361 | 8f860bb8 | ths | { "srnmt", OP16(0xb2b9LL), MASK_S_RD, INSTR_S_RD, 2, 5}, |
1362 | 8f860bb8 | ths | { "lpswe", OP16(0xb2b2LL), MASK_S_RD, INSTR_S_RD, 2, 2}, |
1363 | 8f860bb8 | ths | { "stfl", OP16(0xb2b1LL), MASK_S_RD, INSTR_S_RD, 3, 2}, |
1364 | 8f860bb8 | ths | { "stfle", OP16(0xb2b0LL), MASK_S_RD, INSTR_S_RD, 2, 4}, |
1365 | 8f860bb8 | ths | { "cu12", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
1366 | 8f860bb8 | ths | { "cutfu", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
1367 | 8f860bb8 | ths | { "cutfu", OP16(0xb2a7LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1368 | 8f860bb8 | ths | { "cu21", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
1369 | 8f860bb8 | ths | { "cuutf", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
1370 | 8f860bb8 | ths | { "cuutf", OP16(0xb2a6LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1371 | 8f860bb8 | ths | { "tre", OP16(0xb2a5LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1372 | 8f860bb8 | ths | { "lfpc", OP16(0xb29dLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1373 | 8f860bb8 | ths | { "stfpc", OP16(0xb29cLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1374 | 8f860bb8 | ths | { "srnm", OP16(0xb299LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1375 | 8f860bb8 | ths | { "stsi", OP16(0xb27dLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1376 | 8f860bb8 | ths | { "stckf", OP16(0xb27cLL), MASK_S_RD, INSTR_S_RD, 2, 4}, |
1377 | 8f860bb8 | ths | { "sacf", OP16(0xb279LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1378 | 8f860bb8 | ths | { "stcke", OP16(0xb278LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1379 | 8f860bb8 | ths | { "rp", OP16(0xb277LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1380 | 8f860bb8 | ths | { "xsch", OP16(0xb276LL), MASK_S_00, INSTR_S_00, 3, 0}, |
1381 | 8f860bb8 | ths | { "siga", OP16(0xb274LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1382 | 8f860bb8 | ths | { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1383 | 8f860bb8 | ths | { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1384 | 8f860bb8 | ths | { "srst", OP16(0xb25eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1385 | 8f860bb8 | ths | { "clst", OP16(0xb25dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1386 | 8f860bb8 | ths | { "bsa", OP16(0xb25aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1387 | 8f860bb8 | ths | { "bsg", OP16(0xb258LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1388 | 8f860bb8 | ths | { "cuse", OP16(0xb257LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1389 | 8f860bb8 | ths | { "mvst", OP16(0xb255LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1390 | 8f860bb8 | ths | { "mvpg", OP16(0xb254LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1391 | 8f860bb8 | ths | { "msr", OP16(0xb252LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1392 | 8f860bb8 | ths | { "csp", OP16(0xb250LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1393 | 8f860bb8 | ths | { "ear", OP16(0xb24fLL), MASK_RRE_RA, INSTR_RRE_RA, 3, 0}, |
1394 | 8f860bb8 | ths | { "sar", OP16(0xb24eLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0}, |
1395 | 8f860bb8 | ths | { "cpya", OP16(0xb24dLL), MASK_RRE_AA, INSTR_RRE_AA, 3, 0}, |
1396 | 8f860bb8 | ths | { "tar", OP16(0xb24cLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0}, |
1397 | 8f860bb8 | ths | { "lura", OP16(0xb24bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1398 | 8f860bb8 | ths | { "esta", OP16(0xb24aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1399 | 8f860bb8 | ths | { "ereg", OP16(0xb249LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1400 | 8f860bb8 | ths | { "palb", OP16(0xb248LL), MASK_RRE_00, INSTR_RRE_00, 3, 0}, |
1401 | 8f860bb8 | ths | { "msta", OP16(0xb247LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
1402 | 8f860bb8 | ths | { "stura", OP16(0xb246LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1403 | 8f860bb8 | ths | { "sqer", OP16(0xb245LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, |
1404 | 8f860bb8 | ths | { "sqdr", OP16(0xb244LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, |
1405 | 8f860bb8 | ths | { "cksm", OP16(0xb241LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1406 | 8f860bb8 | ths | { "bakr", OP16(0xb240LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1407 | 8f860bb8 | ths | { "schm", OP16(0xb23cLL), MASK_S_00, INSTR_S_00, 3, 0}, |
1408 | 8f860bb8 | ths | { "rchp", OP16(0xb23bLL), MASK_S_00, INSTR_S_00, 3, 0}, |
1409 | 8f860bb8 | ths | { "stcps", OP16(0xb23aLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1410 | 8f860bb8 | ths | { "stcrw", OP16(0xb239LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1411 | 8f860bb8 | ths | { "rsch", OP16(0xb238LL), MASK_S_00, INSTR_S_00, 3, 0}, |
1412 | 8f860bb8 | ths | { "sal", OP16(0xb237LL), MASK_S_00, INSTR_S_00, 3, 0}, |
1413 | 8f860bb8 | ths | { "tpi", OP16(0xb236LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1414 | 8f860bb8 | ths | { "tsch", OP16(0xb235LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1415 | 8f860bb8 | ths | { "stsch", OP16(0xb234LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1416 | 8f860bb8 | ths | { "ssch", OP16(0xb233LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1417 | 8f860bb8 | ths | { "msch", OP16(0xb232LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1418 | 8f860bb8 | ths | { "hsch", OP16(0xb231LL), MASK_S_00, INSTR_S_00, 3, 0}, |
1419 | 8f860bb8 | ths | { "csch", OP16(0xb230LL), MASK_S_00, INSTR_S_00, 3, 0}, |
1420 | 8f860bb8 | ths | { "pgout", OP16(0xb22fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1421 | 8f860bb8 | ths | { "pgin", OP16(0xb22eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1422 | 8f860bb8 | ths | { "dxr", OP16(0xb22dLL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0}, |
1423 | 8f860bb8 | ths | { "tb", OP16(0xb22cLL), MASK_RRE_0R, INSTR_RRE_0R, 3, 0}, |
1424 | 8f860bb8 | ths | { "sske", OP16(0xb22bLL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4}, |
1425 | 8f860bb8 | ths | { "sske", OP16(0xb22bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1426 | 8f860bb8 | ths | { "rrbe", OP16(0xb22aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1427 | 8f860bb8 | ths | { "iske", OP16(0xb229LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1428 | 8f860bb8 | ths | { "pt", OP16(0xb228LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1429 | 8f860bb8 | ths | { "esar", OP16(0xb227LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
1430 | 8f860bb8 | ths | { "epar", OP16(0xb226LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
1431 | 8f860bb8 | ths | { "ssar", OP16(0xb225LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
1432 | 8f860bb8 | ths | { "iac", OP16(0xb224LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
1433 | 8f860bb8 | ths | { "ivsk", OP16(0xb223LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1434 | 8f860bb8 | ths | { "ipm", OP16(0xb222LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0}, |
1435 | 8f860bb8 | ths | { "ipte", OP16(0xb221LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0}, |
1436 | 8f860bb8 | ths | { "cfc", OP16(0xb21aLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1437 | 8f860bb8 | ths | { "sac", OP16(0xb219LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1438 | 8f860bb8 | ths | { "pc", OP16(0xb218LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1439 | 8f860bb8 | ths | { "sie", OP16(0xb214LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1440 | 8f860bb8 | ths | { "stap", OP16(0xb212LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1441 | 8f860bb8 | ths | { "stpx", OP16(0xb211LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1442 | 8f860bb8 | ths | { "spx", OP16(0xb210LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1443 | 8f860bb8 | ths | { "ptlb", OP16(0xb20dLL), MASK_S_00, INSTR_S_00, 3, 0}, |
1444 | 8f860bb8 | ths | { "ipk", OP16(0xb20bLL), MASK_S_00, INSTR_S_00, 3, 0}, |
1445 | 8f860bb8 | ths | { "spka", OP16(0xb20aLL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1446 | 8f860bb8 | ths | { "stpt", OP16(0xb209LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1447 | 8f860bb8 | ths | { "spt", OP16(0xb208LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1448 | 8f860bb8 | ths | { "stckc", OP16(0xb207LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1449 | 8f860bb8 | ths | { "sckc", OP16(0xb206LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1450 | 8f860bb8 | ths | { "stck", OP16(0xb205LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1451 | 8f860bb8 | ths | { "sck", OP16(0xb204LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1452 | 8f860bb8 | ths | { "stidp", OP16(0xb202LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1453 | 8f860bb8 | ths | { "lra", OP8(0xb1LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1454 | 8f860bb8 | ths | { "mc", OP8(0xafLL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
1455 | 8f860bb8 | ths | { "sigp", OP8(0xaeLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1456 | 8f860bb8 | ths | { "stosm", OP8(0xadLL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
1457 | 8f860bb8 | ths | { "stnsm", OP8(0xacLL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
1458 | 8f860bb8 | ths | { "clcle", OP8(0xa9LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1459 | 8f860bb8 | ths | { "mvcle", OP8(0xa8LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1460 | 8f860bb8 | ths | { "j", OP16(0xa7f4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1461 | 8f860bb8 | ths | { "jno", OP16(0xa7e4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1462 | 8f860bb8 | ths | { "jnh", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1463 | 8f860bb8 | ths | { "jnp", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1464 | 8f860bb8 | ths | { "jle", OP16(0xa7c4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1465 | 8f860bb8 | ths | { "jnl", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1466 | 8f860bb8 | ths | { "jnm", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1467 | 8f860bb8 | ths | { "jhe", OP16(0xa7a4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1468 | 8f860bb8 | ths | { "jnlh", OP16(0xa794LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1469 | 8f860bb8 | ths | { "je", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1470 | 8f860bb8 | ths | { "jz", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1471 | 8f860bb8 | ths | { "jne", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1472 | 8f860bb8 | ths | { "jnz", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1473 | 8f860bb8 | ths | { "jlh", OP16(0xa764LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1474 | 8f860bb8 | ths | { "jnhe", OP16(0xa754LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1475 | 8f860bb8 | ths | { "jl", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1476 | 8f860bb8 | ths | { "jm", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1477 | 8f860bb8 | ths | { "jnle", OP16(0xa734LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1478 | 8f860bb8 | ths | { "jh", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1479 | 8f860bb8 | ths | { "jp", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1480 | 8f860bb8 | ths | { "jo", OP16(0xa714LL), MASK_RI_0P, INSTR_RI_0P, 3, 0}, |
1481 | 8f860bb8 | ths | { "cghi", OP16(0xa70fLL), MASK_RI_RI, INSTR_RI_RI, 2, 2}, |
1482 | 8f860bb8 | ths | { "chi", OP16(0xa70eLL), MASK_RI_RI, INSTR_RI_RI, 3, 0}, |
1483 | 8f860bb8 | ths | { "mghi", OP16(0xa70dLL), MASK_RI_RI, INSTR_RI_RI, 2, 2}, |
1484 | 8f860bb8 | ths | { "mhi", OP16(0xa70cLL), MASK_RI_RI, INSTR_RI_RI, 3, 0}, |
1485 | 8f860bb8 | ths | { "aghi", OP16(0xa70bLL), MASK_RI_RI, INSTR_RI_RI, 2, 2}, |
1486 | 8f860bb8 | ths | { "ahi", OP16(0xa70aLL), MASK_RI_RI, INSTR_RI_RI, 3, 0}, |
1487 | 8f860bb8 | ths | { "lghi", OP16(0xa709LL), MASK_RI_RI, INSTR_RI_RI, 2, 2}, |
1488 | 8f860bb8 | ths | { "lhi", OP16(0xa708LL), MASK_RI_RI, INSTR_RI_RI, 3, 0}, |
1489 | 8f860bb8 | ths | { "brctg", OP16(0xa707LL), MASK_RI_RP, INSTR_RI_RP, 2, 2}, |
1490 | 8f860bb8 | ths | { "brct", OP16(0xa706LL), MASK_RI_RP, INSTR_RI_RP, 3, 0}, |
1491 | 8f860bb8 | ths | { "bras", OP16(0xa705LL), MASK_RI_RP, INSTR_RI_RP, 3, 0}, |
1492 | 8f860bb8 | ths | { "brc", OP16(0xa704LL), MASK_RI_UP, INSTR_RI_UP, 3, 0}, |
1493 | 8f860bb8 | ths | { "tmhl", OP16(0xa703LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1494 | 8f860bb8 | ths | { "tmhh", OP16(0xa702LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1495 | 8f860bb8 | ths | { "tml", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0}, |
1496 | 8f860bb8 | ths | { "tmll", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0}, |
1497 | 8f860bb8 | ths | { "tmh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0}, |
1498 | 8f860bb8 | ths | { "tmlh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0}, |
1499 | 8f860bb8 | ths | { "llill", OP16(0xa50fLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1500 | 8f860bb8 | ths | { "llilh", OP16(0xa50eLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1501 | 8f860bb8 | ths | { "llihl", OP16(0xa50dLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1502 | 8f860bb8 | ths | { "llihh", OP16(0xa50cLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1503 | 8f860bb8 | ths | { "oill", OP16(0xa50bLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1504 | 8f860bb8 | ths | { "oilh", OP16(0xa50aLL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1505 | 8f860bb8 | ths | { "oihl", OP16(0xa509LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1506 | 8f860bb8 | ths | { "oihh", OP16(0xa508LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1507 | 8f860bb8 | ths | { "nill", OP16(0xa507LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1508 | 8f860bb8 | ths | { "nilh", OP16(0xa506LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1509 | 8f860bb8 | ths | { "nihl", OP16(0xa505LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1510 | 8f860bb8 | ths | { "nihh", OP16(0xa504LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1511 | 8f860bb8 | ths | { "iill", OP16(0xa503LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1512 | 8f860bb8 | ths | { "iilh", OP16(0xa502LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1513 | 8f860bb8 | ths | { "iihl", OP16(0xa501LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1514 | 8f860bb8 | ths | { "iihh", OP16(0xa500LL), MASK_RI_RU, INSTR_RI_RU, 2, 2}, |
1515 | 8f860bb8 | ths | { "stam", OP8(0x9bLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0}, |
1516 | 8f860bb8 | ths | { "lam", OP8(0x9aLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0}, |
1517 | 8f860bb8 | ths | { "trace", OP8(0x99LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1518 | 8f860bb8 | ths | { "lm", OP8(0x98LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1519 | 8f860bb8 | ths | { "xi", OP8(0x97LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
1520 | 8f860bb8 | ths | { "oi", OP8(0x96LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
1521 | 8f860bb8 | ths | { "cli", OP8(0x95LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
1522 | 8f860bb8 | ths | { "ni", OP8(0x94LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
1523 | 8f860bb8 | ths | { "ts", OP8(0x93LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1524 | 8f860bb8 | ths | { "mvi", OP8(0x92LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
1525 | 8f860bb8 | ths | { "tm", OP8(0x91LL), MASK_SI_URD, INSTR_SI_URD, 3, 0}, |
1526 | 8f860bb8 | ths | { "stm", OP8(0x90LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1527 | 8f860bb8 | ths | { "slda", OP8(0x8fLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
1528 | 8f860bb8 | ths | { "srda", OP8(0x8eLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
1529 | 8f860bb8 | ths | { "sldl", OP8(0x8dLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
1530 | 8f860bb8 | ths | { "srdl", OP8(0x8cLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
1531 | 8f860bb8 | ths | { "sla", OP8(0x8bLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
1532 | 8f860bb8 | ths | { "sra", OP8(0x8aLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
1533 | 8f860bb8 | ths | { "sll", OP8(0x89LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
1534 | 8f860bb8 | ths | { "srl", OP8(0x88LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0}, |
1535 | 8f860bb8 | ths | { "bxle", OP8(0x87LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1536 | 8f860bb8 | ths | { "bxh", OP8(0x86LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1537 | 8f860bb8 | ths | { "brxle", OP8(0x85LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0}, |
1538 | 8f860bb8 | ths | { "brxh", OP8(0x84LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0}, |
1539 | 8f860bb8 | ths | { "diag", OP8(0x83LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0}, |
1540 | 8f860bb8 | ths | { "lpsw", OP8(0x82LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1541 | 8f860bb8 | ths | { "ssm", OP8(0x80LL), MASK_S_RD, INSTR_S_RD, 3, 0}, |
1542 | 8f860bb8 | ths | { "su", OP8(0x7fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1543 | 8f860bb8 | ths | { "au", OP8(0x7eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1544 | 8f860bb8 | ths | { "de", OP8(0x7dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1545 | 8f860bb8 | ths | { "me", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1546 | 8f860bb8 | ths | { "mde", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1547 | 8f860bb8 | ths | { "se", OP8(0x7bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1548 | 8f860bb8 | ths | { "ae", OP8(0x7aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1549 | 8f860bb8 | ths | { "ce", OP8(0x79LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1550 | 8f860bb8 | ths | { "le", OP8(0x78LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1551 | 8f860bb8 | ths | { "ms", OP8(0x71LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1552 | 8f860bb8 | ths | { "ste", OP8(0x70LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1553 | 8f860bb8 | ths | { "sw", OP8(0x6fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1554 | 8f860bb8 | ths | { "aw", OP8(0x6eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1555 | 8f860bb8 | ths | { "dd", OP8(0x6dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1556 | 8f860bb8 | ths | { "md", OP8(0x6cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1557 | 8f860bb8 | ths | { "sd", OP8(0x6bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1558 | 8f860bb8 | ths | { "ad", OP8(0x6aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1559 | 8f860bb8 | ths | { "cd", OP8(0x69LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1560 | 8f860bb8 | ths | { "ld", OP8(0x68LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1561 | 8f860bb8 | ths | { "mxd", OP8(0x67LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1562 | 8f860bb8 | ths | { "std", OP8(0x60LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0}, |
1563 | 8f860bb8 | ths | { "sl", OP8(0x5fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1564 | 8f860bb8 | ths | { "al", OP8(0x5eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1565 | 8f860bb8 | ths | { "d", OP8(0x5dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1566 | 8f860bb8 | ths | { "m", OP8(0x5cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1567 | 8f860bb8 | ths | { "s", OP8(0x5bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1568 | 8f860bb8 | ths | { "a", OP8(0x5aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1569 | 8f860bb8 | ths | { "c", OP8(0x59LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1570 | 8f860bb8 | ths | { "l", OP8(0x58LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1571 | 8f860bb8 | ths | { "x", OP8(0x57LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1572 | 8f860bb8 | ths | { "o", OP8(0x56LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1573 | 8f860bb8 | ths | { "cl", OP8(0x55LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1574 | 8f860bb8 | ths | { "n", OP8(0x54LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1575 | 8f860bb8 | ths | { "lae", OP8(0x51LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1576 | 8f860bb8 | ths | { "st", OP8(0x50LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1577 | 8f860bb8 | ths | { "cvb", OP8(0x4fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1578 | 8f860bb8 | ths | { "cvd", OP8(0x4eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1579 | 8f860bb8 | ths | { "bas", OP8(0x4dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1580 | 8f860bb8 | ths | { "mh", OP8(0x4cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1581 | 8f860bb8 | ths | { "sh", OP8(0x4bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1582 | 8f860bb8 | ths | { "ah", OP8(0x4aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1583 | 8f860bb8 | ths | { "ch", OP8(0x49LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1584 | 8f860bb8 | ths | { "lh", OP8(0x48LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1585 | 8f860bb8 | ths | { "b", OP16(0x47f0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1586 | 8f860bb8 | ths | { "bno", OP16(0x47e0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1587 | 8f860bb8 | ths | { "bnh", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1588 | 8f860bb8 | ths | { "bnp", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1589 | 8f860bb8 | ths | { "ble", OP16(0x47c0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1590 | 8f860bb8 | ths | { "bnl", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1591 | 8f860bb8 | ths | { "bnm", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1592 | 8f860bb8 | ths | { "bhe", OP16(0x47a0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1593 | 8f860bb8 | ths | { "bnlh", OP16(0x4790LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1594 | 8f860bb8 | ths | { "be", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1595 | 8f860bb8 | ths | { "bz", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1596 | 8f860bb8 | ths | { "bne", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1597 | 8f860bb8 | ths | { "bnz", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1598 | 8f860bb8 | ths | { "blh", OP16(0x4760LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1599 | 8f860bb8 | ths | { "bnhe", OP16(0x4750LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1600 | 8f860bb8 | ths | { "bl", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1601 | 8f860bb8 | ths | { "bm", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1602 | 8f860bb8 | ths | { "bnle", OP16(0x4730LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1603 | 8f860bb8 | ths | { "bh", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1604 | 8f860bb8 | ths | { "bp", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1605 | 8f860bb8 | ths | { "bo", OP16(0x4710LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1606 | 8f860bb8 | ths | { "bc", OP8(0x47LL), MASK_RX_URRD, INSTR_RX_URRD, 3, 0}, |
1607 | 8f860bb8 | ths | { "nop", OP16(0x4700LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0}, |
1608 | 8f860bb8 | ths | { "bct", OP8(0x46LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1609 | 8f860bb8 | ths | { "bal", OP8(0x45LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1610 | 8f860bb8 | ths | { "ex", OP8(0x44LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1611 | 8f860bb8 | ths | { "ic", OP8(0x43LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1612 | 8f860bb8 | ths | { "stc", OP8(0x42LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1613 | 8f860bb8 | ths | { "la", OP8(0x41LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1614 | 8f860bb8 | ths | { "sth", OP8(0x40LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0}, |
1615 | 8f860bb8 | ths | { "sur", OP8(0x3fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1616 | 8f860bb8 | ths | { "aur", OP8(0x3eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1617 | 8f860bb8 | ths | { "der", OP8(0x3dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1618 | 8f860bb8 | ths | { "mer", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1619 | 8f860bb8 | ths | { "mder", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1620 | 8f860bb8 | ths | { "ser", OP8(0x3bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1621 | 8f860bb8 | ths | { "aer", OP8(0x3aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1622 | 8f860bb8 | ths | { "cer", OP8(0x39LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1623 | 8f860bb8 | ths | { "ler", OP8(0x38LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1624 | 8f860bb8 | ths | { "sxr", OP8(0x37LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1625 | 8f860bb8 | ths | { "axr", OP8(0x36LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1626 | 8f860bb8 | ths | { "lrer", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1627 | 8f860bb8 | ths | { "ledr", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1628 | 8f860bb8 | ths | { "her", OP8(0x34LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1629 | 8f860bb8 | ths | { "lcer", OP8(0x33LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1630 | 8f860bb8 | ths | { "lter", OP8(0x32LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1631 | 8f860bb8 | ths | { "lner", OP8(0x31LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1632 | 8f860bb8 | ths | { "lper", OP8(0x30LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1633 | 8f860bb8 | ths | { "swr", OP8(0x2fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1634 | 8f860bb8 | ths | { "awr", OP8(0x2eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1635 | 8f860bb8 | ths | { "ddr", OP8(0x2dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1636 | 8f860bb8 | ths | { "mdr", OP8(0x2cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1637 | 8f860bb8 | ths | { "sdr", OP8(0x2bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1638 | 8f860bb8 | ths | { "adr", OP8(0x2aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1639 | 8f860bb8 | ths | { "cdr", OP8(0x29LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1640 | 8f860bb8 | ths | { "ldr", OP8(0x28LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1641 | 8f860bb8 | ths | { "mxdr", OP8(0x27LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1642 | 8f860bb8 | ths | { "mxr", OP8(0x26LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1643 | 8f860bb8 | ths | { "lrdr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1644 | 8f860bb8 | ths | { "ldxr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1645 | 8f860bb8 | ths | { "hdr", OP8(0x24LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1646 | 8f860bb8 | ths | { "lcdr", OP8(0x23LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1647 | 8f860bb8 | ths | { "ltdr", OP8(0x22LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1648 | 8f860bb8 | ths | { "lndr", OP8(0x21LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1649 | 8f860bb8 | ths | { "lpdr", OP8(0x20LL), MASK_RR_FF, INSTR_RR_FF, 3, 0}, |
1650 | 8f860bb8 | ths | { "slr", OP8(0x1fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1651 | 8f860bb8 | ths | { "alr", OP8(0x1eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1652 | 8f860bb8 | ths | { "dr", OP8(0x1dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1653 | 8f860bb8 | ths | { "mr", OP8(0x1cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1654 | 8f860bb8 | ths | { "sr", OP8(0x1bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1655 | 8f860bb8 | ths | { "ar", OP8(0x1aLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1656 | 8f860bb8 | ths | { "cr", OP8(0x19LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1657 | 8f860bb8 | ths | { "lr", OP8(0x18LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1658 | 8f860bb8 | ths | { "xr", OP8(0x17LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1659 | 8f860bb8 | ths | { "or", OP8(0x16LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1660 | 8f860bb8 | ths | { "clr", OP8(0x15LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1661 | 8f860bb8 | ths | { "nr", OP8(0x14LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1662 | 8f860bb8 | ths | { "lcr", OP8(0x13LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1663 | 8f860bb8 | ths | { "ltr", OP8(0x12LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1664 | 8f860bb8 | ths | { "lnr", OP8(0x11LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1665 | 8f860bb8 | ths | { "lpr", OP8(0x10LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1666 | 8f860bb8 | ths | { "clcl", OP8(0x0fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1667 | 8f860bb8 | ths | { "mvcl", OP8(0x0eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1668 | 8f860bb8 | ths | { "basr", OP8(0x0dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1669 | 8f860bb8 | ths | { "bassm", OP8(0x0cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1670 | 8f860bb8 | ths | { "bsm", OP8(0x0bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1671 | 8f860bb8 | ths | { "svc", OP8(0x0aLL), MASK_RR_U0, INSTR_RR_U0, 3, 0}, |
1672 | 8f860bb8 | ths | { "br", OP16(0x07f0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1673 | 8f860bb8 | ths | { "bnor", OP16(0x07e0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1674 | 8f860bb8 | ths | { "bnhr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1675 | 8f860bb8 | ths | { "bnpr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1676 | 8f860bb8 | ths | { "bler", OP16(0x07c0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1677 | 8f860bb8 | ths | { "bnlr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1678 | 8f860bb8 | ths | { "bnmr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1679 | 8f860bb8 | ths | { "bher", OP16(0x07a0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1680 | 8f860bb8 | ths | { "bnlhr", OP16(0x0790LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1681 | 8f860bb8 | ths | { "ber", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1682 | 8f860bb8 | ths | { "bzr", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1683 | 8f860bb8 | ths | { "bner", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1684 | 8f860bb8 | ths | { "bnzr", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1685 | 8f860bb8 | ths | { "blhr", OP16(0x0760LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1686 | 8f860bb8 | ths | { "bnher", OP16(0x0750LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1687 | 8f860bb8 | ths | { "blr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1688 | 8f860bb8 | ths | { "bmr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1689 | 8f860bb8 | ths | { "bnler", OP16(0x0730LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1690 | 8f860bb8 | ths | { "bhr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1691 | 8f860bb8 | ths | { "bpr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1692 | 8f860bb8 | ths | { "bor", OP16(0x0710LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1693 | 8f860bb8 | ths | { "bcr", OP8(0x07LL), MASK_RR_UR, INSTR_RR_UR, 3, 0}, |
1694 | 8f860bb8 | ths | { "nopr", OP16(0x0700LL), MASK_RR_0R, INSTR_RR_0R, 3, 0}, |
1695 | 8f860bb8 | ths | { "bctr", OP8(0x06LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1696 | 8f860bb8 | ths | { "balr", OP8(0x05LL), MASK_RR_RR, INSTR_RR_RR, 3, 0}, |
1697 | 8f860bb8 | ths | { "spm", OP8(0x04LL), MASK_RR_R0, INSTR_RR_R0, 3, 0}, |
1698 | 8f860bb8 | ths | { "trap2", OP16(0x01ffLL), MASK_E, INSTR_E, 3, 0}, |
1699 | 8f860bb8 | ths | { "sam64", OP16(0x010eLL), MASK_E, INSTR_E, 2, 2}, |
1700 | 8f860bb8 | ths | { "sam31", OP16(0x010dLL), MASK_E, INSTR_E, 3, 2}, |
1701 | 8f860bb8 | ths | { "sam24", OP16(0x010cLL), MASK_E, INSTR_E, 3, 2}, |
1702 | 8f860bb8 | ths | { "tam", OP16(0x010bLL), MASK_E, INSTR_E, 3, 2}, |
1703 | 8f860bb8 | ths | { "pfpo", OP16(0x010aLL), MASK_E, INSTR_E, 2, 5}, |
1704 | 8f860bb8 | ths | { "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0}, |
1705 | 8f860bb8 | ths | { "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0}, |
1706 | 8f860bb8 | ths | { "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0} |
1707 | 8f860bb8 | ths | }; |
1708 | 8f860bb8 | ths | |
1709 | 8f860bb8 | ths | const int s390_num_opcodes = |
1710 | 8f860bb8 | ths | sizeof (s390_opcodes) / sizeof (s390_opcodes[0]); |