Revision f3902383
| b/hw/ppc_chrp.c | ||
|---|---|---|
| 37 | 37 |
#define MAX_IDE_BUS 2 |
| 38 | 38 |
#define VGA_BIOS_SIZE 65536 |
| 39 | 39 |
|
| 40 |
/* debug UniNorth */ |
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//#define DEBUG_UNIN |
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#ifdef DEBUG_UNIN |
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#define UNIN_DPRINTF(fmt, args...) \ |
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do { printf("UNIN: " fmt , ##args); } while (0)
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#else |
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#define UNIN_DPRINTF(fmt, args...) |
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#endif |
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| 40 | 50 |
/* UniN device */ |
| 41 | 51 |
static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 42 | 52 |
{
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UNIN_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", addr, value);
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| 43 | 54 |
} |
| 44 | 55 |
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| 45 | 56 |
static uint32_t unin_readl (void *opaque, target_phys_addr_t addr) |
| 46 | 57 |
{
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return 0; |
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uint32_t value; |
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value = 0; |
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UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);
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return value; |
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| 48 | 64 |
} |
| 49 | 65 |
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| 50 | 66 |
static CPUWriteMemoryFunc *unin_write[] = {
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| b/hw/unin_pci.c | ||
|---|---|---|
| 25 | 25 |
#include "ppc_mac.h" |
| 26 | 26 |
#include "pci.h" |
| 27 | 27 |
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/* debug UniNorth */ |
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//#define DEBUG_UNIN |
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|
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#ifdef DEBUG_UNIN |
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#define UNIN_DPRINTF(fmt, args...) \ |
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do { printf("UNIN: " fmt , ##args); } while (0)
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#else |
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#define UNIN_DPRINTF(fmt, args...) |
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#endif |
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| 28 | 38 |
typedef target_phys_addr_t pci_addr_t; |
| 29 | 39 |
#include "pci_host.h" |
| 30 | 40 |
|
| ... | ... | |
| 36 | 46 |
UNINState *s = opaque; |
| 37 | 47 |
int i; |
| 38 | 48 |
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UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val);
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|
| 39 | 50 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 40 | 51 |
val = bswap32(val); |
| 41 | 52 |
#endif |
| ... | ... | |
| 63 | 74 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 64 | 75 |
val = bswap32(val); |
| 65 | 76 |
#endif |
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UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val);
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| 66 | 78 |
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return val; |
| 68 | 80 |
} |
| ... | ... | |
| 154 | 166 |
qemu_set_irq(pic[irq_num + 8], level); |
| 155 | 167 |
} |
| 156 | 168 |
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static void pci_unin_save(QEMUFile* f, void *opaque) |
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{
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PCIDevice *d = opaque; |
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pci_device_save(d, f); |
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} |
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static int pci_unin_load(QEMUFile* f, void *opaque, int version_id) |
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{
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PCIDevice *d = opaque; |
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if (version_id != 1) |
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return -EINVAL; |
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return pci_device_load(d, f); |
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} |
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static void pci_unin_reset(void *opaque) |
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{
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} |
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| 157 | 190 |
PCIBus *pci_pmac_init(qemu_irq *pic) |
| 158 | 191 |
{
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| 159 | 192 |
UNINState *s; |
| ... | ... | |
| 254 | 287 |
d->config[0x0E] = 0x00; // header_type |
| 255 | 288 |
d->config[0x34] = 0x00; // capabilities_pointer |
| 256 | 289 |
#endif |
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register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);
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qemu_register_reset(pci_unin_reset, d); |
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pci_unin_reset(d); |
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| 257 | 294 |
return s->bus; |
| 258 | 295 |
} |
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