Revision f44c9960

b/tcg/sparc/tcg-target.c
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/* Generate global QEMU prologue and epilogue code */
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static void tcg_target_qemu_prologue(TCGContext *s)
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{
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    tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_CALL_STACK_OFFSET,
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                  CPU_TEMP_BUF_NLONGS * (int)sizeof(long));
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    tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
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              INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
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              INSN_IMM13(-(TCG_TARGET_STACK_MINFRAME +
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                           CPU_TEMP_BUF_NLONGS * (int)sizeof(long))));
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    tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) |
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              INSN_RS2(TCG_REG_G0));
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    tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0);
......
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    tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
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    tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
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    tcg_add_target_add_op_defs(sparc_op_defs);
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    tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
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                  CPU_TEMP_BUF_NLONGS * sizeof(long));
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}
b/tcg/tcg.c
1439 1439 
{
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    TCGTemp *ts;
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    ts = &s->temps[temp];
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#ifndef __sparc_v9__ /* Sparc64 stack is accessed with offset of 2047 */
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    s->current_frame_offset = (s->current_frame_offset +
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                               (tcg_target_long)sizeof(tcg_target_long) - 1) &
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        ~(sizeof(tcg_target_long) - 1);
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#endif
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    if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) >
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        s->frame_end) {
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        tcg_abort();

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