root / target-i386 / translate.c @ f484d386
History | View | Annotate | Download (220.1 kB)
1 | 2c0262af | bellard | /*
|
---|---|---|---|
2 | 2c0262af | bellard | * i386 translation
|
3 | 5fafdf24 | ths | *
|
4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | 2c0262af | bellard | *
|
6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
|
7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
|
9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 2c0262af | bellard | *
|
11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 2c0262af | bellard | * Lesser General Public License for more details.
|
15 | 2c0262af | bellard | *
|
16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
|
18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | 2c0262af | bellard | */
|
20 | 2c0262af | bellard | #include <stdarg.h> |
21 | 2c0262af | bellard | #include <stdlib.h> |
22 | 2c0262af | bellard | #include <stdio.h> |
23 | 2c0262af | bellard | #include <string.h> |
24 | 2c0262af | bellard | #include <inttypes.h> |
25 | 2c0262af | bellard | #include <signal.h> |
26 | 2c0262af | bellard | #include <assert.h> |
27 | 2c0262af | bellard | |
28 | 2c0262af | bellard | #include "cpu.h" |
29 | 2c0262af | bellard | #include "exec-all.h" |
30 | 2c0262af | bellard | #include "disas.h" |
31 | 57fec1fe | bellard | #include "helper.h" |
32 | 57fec1fe | bellard | #include "tcg-op.h" |
33 | 2c0262af | bellard | |
34 | 2c0262af | bellard | #define PREFIX_REPZ 0x01 |
35 | 2c0262af | bellard | #define PREFIX_REPNZ 0x02 |
36 | 2c0262af | bellard | #define PREFIX_LOCK 0x04 |
37 | 2c0262af | bellard | #define PREFIX_DATA 0x08 |
38 | 2c0262af | bellard | #define PREFIX_ADR 0x10 |
39 | 2c0262af | bellard | |
40 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
41 | 14ce26e7 | bellard | #define X86_64_ONLY(x) x
|
42 | 14ce26e7 | bellard | #define X86_64_DEF(x...) x
|
43 | 14ce26e7 | bellard | #define CODE64(s) ((s)->code64)
|
44 | 14ce26e7 | bellard | #define REX_X(s) ((s)->rex_x)
|
45 | 14ce26e7 | bellard | #define REX_B(s) ((s)->rex_b)
|
46 | 14ce26e7 | bellard | /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
|
47 | 14ce26e7 | bellard | #if 1 |
48 | 14ce26e7 | bellard | #define BUGGY_64(x) NULL |
49 | 14ce26e7 | bellard | #endif
|
50 | 14ce26e7 | bellard | #else
|
51 | 14ce26e7 | bellard | #define X86_64_ONLY(x) NULL |
52 | 14ce26e7 | bellard | #define X86_64_DEF(x...)
|
53 | 14ce26e7 | bellard | #define CODE64(s) 0 |
54 | 14ce26e7 | bellard | #define REX_X(s) 0 |
55 | 14ce26e7 | bellard | #define REX_B(s) 0 |
56 | 14ce26e7 | bellard | #endif
|
57 | 14ce26e7 | bellard | |
58 | 57fec1fe | bellard | //#define MACRO_TEST 1
|
59 | 57fec1fe | bellard | |
60 | 57fec1fe | bellard | /* global register indexes */
|
61 | b6abf97d | bellard | static TCGv cpu_env, cpu_T[2], cpu_A0, cpu_cc_op, cpu_cc_src, cpu_cc_dst; |
62 | b6abf97d | bellard | static TCGv cpu_T3;
|
63 | 57fec1fe | bellard | /* local register indexes (only used inside old micro ops) */
|
64 | b6abf97d | bellard | static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1;
|
65 | b6abf97d | bellard | static TCGv cpu_tmp5, cpu_tmp6;
|
66 | 57fec1fe | bellard | |
67 | 57fec1fe | bellard | #ifdef TARGET_X86_64
|
68 | 57fec1fe | bellard | static int x86_64_hregs; |
69 | ae063a68 | bellard | #endif
|
70 | ae063a68 | bellard | |
71 | 2c0262af | bellard | typedef struct DisasContext { |
72 | 2c0262af | bellard | /* current insn context */
|
73 | 2c0262af | bellard | int override; /* -1 if no override */ |
74 | 2c0262af | bellard | int prefix;
|
75 | 2c0262af | bellard | int aflag, dflag;
|
76 | 14ce26e7 | bellard | target_ulong pc; /* pc = eip + cs_base */
|
77 | 2c0262af | bellard | int is_jmp; /* 1 = means jump (stop translation), 2 means CPU |
78 | 2c0262af | bellard | static state change (stop translation) */
|
79 | 2c0262af | bellard | /* current block context */
|
80 | 14ce26e7 | bellard | target_ulong cs_base; /* base of CS segment */
|
81 | 2c0262af | bellard | int pe; /* protected mode */ |
82 | 2c0262af | bellard | int code32; /* 32 bit code segment */ |
83 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
84 | 14ce26e7 | bellard | int lma; /* long mode active */ |
85 | 14ce26e7 | bellard | int code64; /* 64 bit code segment */ |
86 | 14ce26e7 | bellard | int rex_x, rex_b;
|
87 | 14ce26e7 | bellard | #endif
|
88 | 2c0262af | bellard | int ss32; /* 32 bit stack segment */ |
89 | 2c0262af | bellard | int cc_op; /* current CC operation */ |
90 | 2c0262af | bellard | int addseg; /* non zero if either DS/ES/SS have a non zero base */ |
91 | 2c0262af | bellard | int f_st; /* currently unused */ |
92 | 2c0262af | bellard | int vm86; /* vm86 mode */ |
93 | 2c0262af | bellard | int cpl;
|
94 | 2c0262af | bellard | int iopl;
|
95 | 2c0262af | bellard | int tf; /* TF cpu flag */ |
96 | 34865134 | bellard | int singlestep_enabled; /* "hardware" single step enabled */ |
97 | 2c0262af | bellard | int jmp_opt; /* use direct block chaining for direct jumps */ |
98 | 2c0262af | bellard | int mem_index; /* select memory access functions */ |
99 | c068688b | j_mayer | uint64_t flags; /* all execution flags */
|
100 | 2c0262af | bellard | struct TranslationBlock *tb;
|
101 | 2c0262af | bellard | int popl_esp_hack; /* for correct popl with esp base handling */ |
102 | 14ce26e7 | bellard | int rip_offset; /* only used in x86_64, but left for simplicity */ |
103 | 14ce26e7 | bellard | int cpuid_features;
|
104 | 3d7374c5 | bellard | int cpuid_ext_features;
|
105 | e771edab | aurel32 | int cpuid_ext2_features;
|
106 | 2c0262af | bellard | } DisasContext; |
107 | 2c0262af | bellard | |
108 | 2c0262af | bellard | static void gen_eob(DisasContext *s); |
109 | 14ce26e7 | bellard | static void gen_jmp(DisasContext *s, target_ulong eip); |
110 | 14ce26e7 | bellard | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); |
111 | 2c0262af | bellard | |
112 | 2c0262af | bellard | /* i386 arith/logic operations */
|
113 | 2c0262af | bellard | enum {
|
114 | 5fafdf24 | ths | OP_ADDL, |
115 | 5fafdf24 | ths | OP_ORL, |
116 | 5fafdf24 | ths | OP_ADCL, |
117 | 2c0262af | bellard | OP_SBBL, |
118 | 5fafdf24 | ths | OP_ANDL, |
119 | 5fafdf24 | ths | OP_SUBL, |
120 | 5fafdf24 | ths | OP_XORL, |
121 | 2c0262af | bellard | OP_CMPL, |
122 | 2c0262af | bellard | }; |
123 | 2c0262af | bellard | |
124 | 2c0262af | bellard | /* i386 shift ops */
|
125 | 2c0262af | bellard | enum {
|
126 | 5fafdf24 | ths | OP_ROL, |
127 | 5fafdf24 | ths | OP_ROR, |
128 | 5fafdf24 | ths | OP_RCL, |
129 | 5fafdf24 | ths | OP_RCR, |
130 | 5fafdf24 | ths | OP_SHL, |
131 | 5fafdf24 | ths | OP_SHR, |
132 | 2c0262af | bellard | OP_SHL1, /* undocumented */
|
133 | 2c0262af | bellard | OP_SAR = 7,
|
134 | 2c0262af | bellard | }; |
135 | 2c0262af | bellard | |
136 | 2c0262af | bellard | /* operand size */
|
137 | 2c0262af | bellard | enum {
|
138 | 2c0262af | bellard | OT_BYTE = 0,
|
139 | 2c0262af | bellard | OT_WORD, |
140 | 5fafdf24 | ths | OT_LONG, |
141 | 2c0262af | bellard | OT_QUAD, |
142 | 2c0262af | bellard | }; |
143 | 2c0262af | bellard | |
144 | 2c0262af | bellard | enum {
|
145 | 2c0262af | bellard | /* I386 int registers */
|
146 | 2c0262af | bellard | OR_EAX, /* MUST be even numbered */
|
147 | 2c0262af | bellard | OR_ECX, |
148 | 2c0262af | bellard | OR_EDX, |
149 | 2c0262af | bellard | OR_EBX, |
150 | 2c0262af | bellard | OR_ESP, |
151 | 2c0262af | bellard | OR_EBP, |
152 | 2c0262af | bellard | OR_ESI, |
153 | 2c0262af | bellard | OR_EDI, |
154 | 14ce26e7 | bellard | |
155 | 14ce26e7 | bellard | OR_TMP0 = 16, /* temporary operand register */ |
156 | 2c0262af | bellard | OR_TMP1, |
157 | 2c0262af | bellard | OR_A0, /* temporary register used when doing address evaluation */
|
158 | 2c0262af | bellard | }; |
159 | 2c0262af | bellard | |
160 | 57fec1fe | bellard | static inline void gen_op_movl_T0_0(void) |
161 | 57fec1fe | bellard | { |
162 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[0], 0); |
163 | 57fec1fe | bellard | } |
164 | 57fec1fe | bellard | |
165 | 57fec1fe | bellard | static inline void gen_op_movl_T0_im(int32_t val) |
166 | 57fec1fe | bellard | { |
167 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[0], val);
|
168 | 57fec1fe | bellard | } |
169 | 57fec1fe | bellard | |
170 | 57fec1fe | bellard | static inline void gen_op_movl_T0_imu(uint32_t val) |
171 | 57fec1fe | bellard | { |
172 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[0], val);
|
173 | 57fec1fe | bellard | } |
174 | 57fec1fe | bellard | |
175 | 57fec1fe | bellard | static inline void gen_op_movl_T1_im(int32_t val) |
176 | 57fec1fe | bellard | { |
177 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[1], val);
|
178 | 57fec1fe | bellard | } |
179 | 57fec1fe | bellard | |
180 | 57fec1fe | bellard | static inline void gen_op_movl_T1_imu(uint32_t val) |
181 | 57fec1fe | bellard | { |
182 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[1], val);
|
183 | 57fec1fe | bellard | } |
184 | 57fec1fe | bellard | |
185 | 57fec1fe | bellard | static inline void gen_op_movl_A0_im(uint32_t val) |
186 | 57fec1fe | bellard | { |
187 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_A0, val); |
188 | 57fec1fe | bellard | } |
189 | 57fec1fe | bellard | |
190 | 57fec1fe | bellard | #ifdef TARGET_X86_64
|
191 | 57fec1fe | bellard | static inline void gen_op_movq_A0_im(int64_t val) |
192 | 57fec1fe | bellard | { |
193 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_A0, val); |
194 | 57fec1fe | bellard | } |
195 | 57fec1fe | bellard | #endif
|
196 | 57fec1fe | bellard | |
197 | 57fec1fe | bellard | static inline void gen_movtl_T0_im(target_ulong val) |
198 | 57fec1fe | bellard | { |
199 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[0], val);
|
200 | 57fec1fe | bellard | } |
201 | 57fec1fe | bellard | |
202 | 57fec1fe | bellard | static inline void gen_movtl_T1_im(target_ulong val) |
203 | 57fec1fe | bellard | { |
204 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_T[1], val);
|
205 | 57fec1fe | bellard | } |
206 | 57fec1fe | bellard | |
207 | 57fec1fe | bellard | static inline void gen_op_andl_T0_ffff(void) |
208 | 57fec1fe | bellard | { |
209 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); |
210 | 57fec1fe | bellard | } |
211 | 57fec1fe | bellard | |
212 | 57fec1fe | bellard | static inline void gen_op_andl_T0_im(uint32_t val) |
213 | 57fec1fe | bellard | { |
214 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); |
215 | 57fec1fe | bellard | } |
216 | 57fec1fe | bellard | |
217 | 57fec1fe | bellard | static inline void gen_op_movl_T0_T1(void) |
218 | 57fec1fe | bellard | { |
219 | 57fec1fe | bellard | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); |
220 | 57fec1fe | bellard | } |
221 | 57fec1fe | bellard | |
222 | 57fec1fe | bellard | static inline void gen_op_andl_A0_ffff(void) |
223 | 57fec1fe | bellard | { |
224 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
|
225 | 57fec1fe | bellard | } |
226 | 57fec1fe | bellard | |
227 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
228 | 14ce26e7 | bellard | |
229 | 14ce26e7 | bellard | #define NB_OP_SIZES 4 |
230 | 14ce26e7 | bellard | |
231 | 14ce26e7 | bellard | #define DEF_REGS(prefix, suffix) \
|
232 | 14ce26e7 | bellard | prefix ## EAX ## suffix,\ |
233 | 14ce26e7 | bellard | prefix ## ECX ## suffix,\ |
234 | 14ce26e7 | bellard | prefix ## EDX ## suffix,\ |
235 | 14ce26e7 | bellard | prefix ## EBX ## suffix,\ |
236 | 14ce26e7 | bellard | prefix ## ESP ## suffix,\ |
237 | 14ce26e7 | bellard | prefix ## EBP ## suffix,\ |
238 | 14ce26e7 | bellard | prefix ## ESI ## suffix,\ |
239 | 14ce26e7 | bellard | prefix ## EDI ## suffix,\ |
240 | 14ce26e7 | bellard | prefix ## R8 ## suffix,\ |
241 | 14ce26e7 | bellard | prefix ## R9 ## suffix,\ |
242 | 14ce26e7 | bellard | prefix ## R10 ## suffix,\ |
243 | 14ce26e7 | bellard | prefix ## R11 ## suffix,\ |
244 | 14ce26e7 | bellard | prefix ## R12 ## suffix,\ |
245 | 14ce26e7 | bellard | prefix ## R13 ## suffix,\ |
246 | 14ce26e7 | bellard | prefix ## R14 ## suffix,\ |
247 | 14ce26e7 | bellard | prefix ## R15 ## suffix, |
248 | 14ce26e7 | bellard | |
249 | 14ce26e7 | bellard | #else /* !TARGET_X86_64 */ |
250 | 14ce26e7 | bellard | |
251 | 14ce26e7 | bellard | #define NB_OP_SIZES 3 |
252 | 14ce26e7 | bellard | |
253 | 14ce26e7 | bellard | #define DEF_REGS(prefix, suffix) \
|
254 | 14ce26e7 | bellard | prefix ## EAX ## suffix,\ |
255 | 14ce26e7 | bellard | prefix ## ECX ## suffix,\ |
256 | 14ce26e7 | bellard | prefix ## EDX ## suffix,\ |
257 | 14ce26e7 | bellard | prefix ## EBX ## suffix,\ |
258 | 14ce26e7 | bellard | prefix ## ESP ## suffix,\ |
259 | 14ce26e7 | bellard | prefix ## EBP ## suffix,\ |
260 | 14ce26e7 | bellard | prefix ## ESI ## suffix,\ |
261 | 14ce26e7 | bellard | prefix ## EDI ## suffix, |
262 | 14ce26e7 | bellard | |
263 | 14ce26e7 | bellard | #endif /* !TARGET_X86_64 */ |
264 | 14ce26e7 | bellard | |
265 | 57fec1fe | bellard | #if defined(WORDS_BIGENDIAN)
|
266 | 57fec1fe | bellard | #define REG_B_OFFSET (sizeof(target_ulong) - 1) |
267 | 57fec1fe | bellard | #define REG_H_OFFSET (sizeof(target_ulong) - 2) |
268 | 57fec1fe | bellard | #define REG_W_OFFSET (sizeof(target_ulong) - 2) |
269 | 57fec1fe | bellard | #define REG_L_OFFSET (sizeof(target_ulong) - 4) |
270 | 57fec1fe | bellard | #define REG_LH_OFFSET (sizeof(target_ulong) - 8) |
271 | 14ce26e7 | bellard | #else
|
272 | 57fec1fe | bellard | #define REG_B_OFFSET 0 |
273 | 57fec1fe | bellard | #define REG_H_OFFSET 1 |
274 | 57fec1fe | bellard | #define REG_W_OFFSET 0 |
275 | 57fec1fe | bellard | #define REG_L_OFFSET 0 |
276 | 57fec1fe | bellard | #define REG_LH_OFFSET 4 |
277 | 14ce26e7 | bellard | #endif
|
278 | 57fec1fe | bellard | |
279 | 57fec1fe | bellard | static inline void gen_op_mov_reg_TN(int ot, int t_index, int reg) |
280 | 57fec1fe | bellard | { |
281 | 57fec1fe | bellard | switch(ot) {
|
282 | 57fec1fe | bellard | case OT_BYTE:
|
283 | 57fec1fe | bellard | if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { |
284 | 57fec1fe | bellard | tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET); |
285 | 57fec1fe | bellard | } else {
|
286 | 57fec1fe | bellard | tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
|
287 | 57fec1fe | bellard | } |
288 | 57fec1fe | bellard | break;
|
289 | 57fec1fe | bellard | case OT_WORD:
|
290 | 57fec1fe | bellard | tcg_gen_st16_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); |
291 | 57fec1fe | bellard | break;
|
292 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
293 | 57fec1fe | bellard | case OT_LONG:
|
294 | 57fec1fe | bellard | tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
295 | 57fec1fe | bellard | /* high part of register set to zero */
|
296 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_tmp0, 0);
|
297 | 57fec1fe | bellard | tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); |
298 | 57fec1fe | bellard | break;
|
299 | 57fec1fe | bellard | default:
|
300 | 57fec1fe | bellard | case OT_QUAD:
|
301 | 57fec1fe | bellard | tcg_gen_st_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg])); |
302 | 57fec1fe | bellard | break;
|
303 | 57fec1fe | bellard | #else
|
304 | 57fec1fe | bellard | default:
|
305 | 57fec1fe | bellard | case OT_LONG:
|
306 | 57fec1fe | bellard | tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
307 | 57fec1fe | bellard | break;
|
308 | 14ce26e7 | bellard | #endif
|
309 | 57fec1fe | bellard | } |
310 | 57fec1fe | bellard | } |
311 | 2c0262af | bellard | |
312 | 57fec1fe | bellard | static inline void gen_op_mov_reg_T0(int ot, int reg) |
313 | 57fec1fe | bellard | { |
314 | 57fec1fe | bellard | gen_op_mov_reg_TN(ot, 0, reg);
|
315 | 57fec1fe | bellard | } |
316 | 57fec1fe | bellard | |
317 | 57fec1fe | bellard | static inline void gen_op_mov_reg_T1(int ot, int reg) |
318 | 57fec1fe | bellard | { |
319 | 57fec1fe | bellard | gen_op_mov_reg_TN(ot, 1, reg);
|
320 | 57fec1fe | bellard | } |
321 | 57fec1fe | bellard | |
322 | 57fec1fe | bellard | static inline void gen_op_mov_reg_A0(int size, int reg) |
323 | 57fec1fe | bellard | { |
324 | 57fec1fe | bellard | switch(size) {
|
325 | 57fec1fe | bellard | case 0: |
326 | 57fec1fe | bellard | tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); |
327 | 57fec1fe | bellard | break;
|
328 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
329 | 57fec1fe | bellard | case 1: |
330 | 57fec1fe | bellard | tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
331 | 57fec1fe | bellard | /* high part of register set to zero */
|
332 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_tmp0, 0);
|
333 | 57fec1fe | bellard | tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); |
334 | 57fec1fe | bellard | break;
|
335 | 57fec1fe | bellard | default:
|
336 | 57fec1fe | bellard | case 2: |
337 | 57fec1fe | bellard | tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg])); |
338 | 57fec1fe | bellard | break;
|
339 | 14ce26e7 | bellard | #else
|
340 | 57fec1fe | bellard | default:
|
341 | 57fec1fe | bellard | case 1: |
342 | 57fec1fe | bellard | tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
343 | 57fec1fe | bellard | break;
|
344 | 14ce26e7 | bellard | #endif
|
345 | 57fec1fe | bellard | } |
346 | 57fec1fe | bellard | } |
347 | 57fec1fe | bellard | |
348 | 57fec1fe | bellard | static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) |
349 | 57fec1fe | bellard | { |
350 | 57fec1fe | bellard | switch(ot) {
|
351 | 57fec1fe | bellard | case OT_BYTE:
|
352 | 57fec1fe | bellard | if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { |
353 | 57fec1fe | bellard | goto std_case;
|
354 | 57fec1fe | bellard | } else {
|
355 | 57fec1fe | bellard | tcg_gen_ld8u_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
|
356 | 57fec1fe | bellard | } |
357 | 57fec1fe | bellard | break;
|
358 | 57fec1fe | bellard | default:
|
359 | 57fec1fe | bellard | std_case:
|
360 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg])); |
361 | 57fec1fe | bellard | break;
|
362 | 57fec1fe | bellard | } |
363 | 57fec1fe | bellard | } |
364 | 57fec1fe | bellard | |
365 | 57fec1fe | bellard | static inline void gen_op_movl_A0_reg(int reg) |
366 | 57fec1fe | bellard | { |
367 | 57fec1fe | bellard | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); |
368 | 57fec1fe | bellard | } |
369 | 57fec1fe | bellard | |
370 | 57fec1fe | bellard | static inline void gen_op_addl_A0_im(int32_t val) |
371 | 57fec1fe | bellard | { |
372 | 57fec1fe | bellard | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); |
373 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
374 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
|
375 | 14ce26e7 | bellard | #endif
|
376 | 57fec1fe | bellard | } |
377 | 2c0262af | bellard | |
378 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
379 | 57fec1fe | bellard | static inline void gen_op_addq_A0_im(int64_t val) |
380 | 57fec1fe | bellard | { |
381 | 57fec1fe | bellard | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); |
382 | 57fec1fe | bellard | } |
383 | 14ce26e7 | bellard | #endif
|
384 | 57fec1fe | bellard | |
385 | 57fec1fe | bellard | static void gen_add_A0_im(DisasContext *s, int val) |
386 | 57fec1fe | bellard | { |
387 | 57fec1fe | bellard | #ifdef TARGET_X86_64
|
388 | 57fec1fe | bellard | if (CODE64(s))
|
389 | 57fec1fe | bellard | gen_op_addq_A0_im(val); |
390 | 57fec1fe | bellard | else
|
391 | 57fec1fe | bellard | #endif
|
392 | 57fec1fe | bellard | gen_op_addl_A0_im(val); |
393 | 57fec1fe | bellard | } |
394 | 2c0262af | bellard | |
395 | 57fec1fe | bellard | static inline void gen_op_addl_T0_T1(void) |
396 | 2c0262af | bellard | { |
397 | 57fec1fe | bellard | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
398 | 57fec1fe | bellard | } |
399 | 57fec1fe | bellard | |
400 | 57fec1fe | bellard | static inline void gen_op_jmp_T0(void) |
401 | 57fec1fe | bellard | { |
402 | 57fec1fe | bellard | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
|
403 | 57fec1fe | bellard | } |
404 | 57fec1fe | bellard | |
405 | 57fec1fe | bellard | static inline void gen_op_addw_ESP_im(int32_t val) |
406 | 57fec1fe | bellard | { |
407 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP])); |
408 | 57fec1fe | bellard | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); |
409 | 57fec1fe | bellard | tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]) + REG_W_OFFSET); |
410 | 57fec1fe | bellard | } |
411 | 57fec1fe | bellard | |
412 | 57fec1fe | bellard | static inline void gen_op_addl_ESP_im(int32_t val) |
413 | 57fec1fe | bellard | { |
414 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP])); |
415 | 57fec1fe | bellard | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); |
416 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
417 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
|
418 | 14ce26e7 | bellard | #endif
|
419 | 57fec1fe | bellard | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP])); |
420 | 57fec1fe | bellard | } |
421 | 57fec1fe | bellard | |
422 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
423 | 57fec1fe | bellard | static inline void gen_op_addq_ESP_im(int32_t val) |
424 | 57fec1fe | bellard | { |
425 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP])); |
426 | 57fec1fe | bellard | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); |
427 | 57fec1fe | bellard | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP])); |
428 | 57fec1fe | bellard | } |
429 | 14ce26e7 | bellard | #endif
|
430 | 57fec1fe | bellard | |
431 | 57fec1fe | bellard | static inline void gen_op_set_cc_op(int32_t val) |
432 | 57fec1fe | bellard | { |
433 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, val); |
434 | 57fec1fe | bellard | } |
435 | 57fec1fe | bellard | |
436 | 57fec1fe | bellard | static inline void gen_op_addl_A0_reg_sN(int shift, int reg) |
437 | 57fec1fe | bellard | { |
438 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
439 | 57fec1fe | bellard | if (shift != 0) |
440 | 57fec1fe | bellard | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
441 | 57fec1fe | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
442 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
443 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
|
444 | 14ce26e7 | bellard | #endif
|
445 | 57fec1fe | bellard | } |
446 | 2c0262af | bellard | |
447 | 57fec1fe | bellard | static inline void gen_op_movl_A0_seg(int reg) |
448 | 57fec1fe | bellard | { |
449 | 57fec1fe | bellard | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET); |
450 | 57fec1fe | bellard | } |
451 | 2c0262af | bellard | |
452 | 57fec1fe | bellard | static inline void gen_op_addl_A0_seg(int reg) |
453 | 57fec1fe | bellard | { |
454 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base)); |
455 | 57fec1fe | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
456 | 57fec1fe | bellard | #ifdef TARGET_X86_64
|
457 | 57fec1fe | bellard | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
|
458 | 57fec1fe | bellard | #endif
|
459 | 57fec1fe | bellard | } |
460 | 2c0262af | bellard | |
461 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
462 | 57fec1fe | bellard | static inline void gen_op_movq_A0_seg(int reg) |
463 | 57fec1fe | bellard | { |
464 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base)); |
465 | 57fec1fe | bellard | } |
466 | 14ce26e7 | bellard | |
467 | 57fec1fe | bellard | static inline void gen_op_addq_A0_seg(int reg) |
468 | 57fec1fe | bellard | { |
469 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base)); |
470 | 57fec1fe | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
471 | 57fec1fe | bellard | } |
472 | 57fec1fe | bellard | |
473 | 57fec1fe | bellard | static inline void gen_op_movq_A0_reg(int reg) |
474 | 57fec1fe | bellard | { |
475 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg])); |
476 | 57fec1fe | bellard | } |
477 | 57fec1fe | bellard | |
478 | 57fec1fe | bellard | static inline void gen_op_addq_A0_reg_sN(int shift, int reg) |
479 | 57fec1fe | bellard | { |
480 | 57fec1fe | bellard | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); |
481 | 57fec1fe | bellard | if (shift != 0) |
482 | 57fec1fe | bellard | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
483 | 57fec1fe | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
484 | 57fec1fe | bellard | } |
485 | 14ce26e7 | bellard | #endif
|
486 | 14ce26e7 | bellard | |
487 | 14ce26e7 | bellard | static GenOpFunc *gen_op_cmov_reg_T1_T0[NB_OP_SIZES - 1][CPU_NB_REGS] = { |
488 | 14ce26e7 | bellard | [0] = {
|
489 | 14ce26e7 | bellard | DEF_REGS(gen_op_cmovw_, _T1_T0) |
490 | 14ce26e7 | bellard | }, |
491 | 14ce26e7 | bellard | [1] = {
|
492 | 14ce26e7 | bellard | DEF_REGS(gen_op_cmovl_, _T1_T0) |
493 | 14ce26e7 | bellard | }, |
494 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
495 | 14ce26e7 | bellard | [2] = {
|
496 | 14ce26e7 | bellard | DEF_REGS(gen_op_cmovq_, _T1_T0) |
497 | 14ce26e7 | bellard | }, |
498 | 14ce26e7 | bellard | #endif
|
499 | 14ce26e7 | bellard | }; |
500 | 2c0262af | bellard | |
501 | 14ce26e7 | bellard | static GenOpFunc *gen_op_bsx_T0_cc[3][2] = { |
502 | 2c0262af | bellard | [0] = {
|
503 | 2c0262af | bellard | gen_op_bsfw_T0_cc, |
504 | 2c0262af | bellard | gen_op_bsrw_T0_cc, |
505 | 2c0262af | bellard | }, |
506 | 2c0262af | bellard | [1] = {
|
507 | 2c0262af | bellard | gen_op_bsfl_T0_cc, |
508 | 2c0262af | bellard | gen_op_bsrl_T0_cc, |
509 | 2c0262af | bellard | }, |
510 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
511 | 14ce26e7 | bellard | [2] = {
|
512 | 14ce26e7 | bellard | gen_op_bsfq_T0_cc, |
513 | 14ce26e7 | bellard | gen_op_bsrq_T0_cc, |
514 | 14ce26e7 | bellard | }, |
515 | 14ce26e7 | bellard | #endif
|
516 | 2c0262af | bellard | }; |
517 | 2c0262af | bellard | |
518 | 57fec1fe | bellard | static inline void gen_op_lds_T0_A0(int idx) |
519 | 57fec1fe | bellard | { |
520 | 57fec1fe | bellard | int mem_index = (idx >> 2) - 1; |
521 | 57fec1fe | bellard | switch(idx & 3) { |
522 | 57fec1fe | bellard | case 0: |
523 | 57fec1fe | bellard | tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
|
524 | 57fec1fe | bellard | break;
|
525 | 57fec1fe | bellard | case 1: |
526 | 57fec1fe | bellard | tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
|
527 | 57fec1fe | bellard | break;
|
528 | 57fec1fe | bellard | default:
|
529 | 57fec1fe | bellard | case 2: |
530 | 57fec1fe | bellard | tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
|
531 | 57fec1fe | bellard | break;
|
532 | 57fec1fe | bellard | } |
533 | 57fec1fe | bellard | } |
534 | 2c0262af | bellard | |
535 | 2c0262af | bellard | /* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
|
536 | 57fec1fe | bellard | static inline void gen_op_ld_T0_A0(int idx) |
537 | 57fec1fe | bellard | { |
538 | 57fec1fe | bellard | int mem_index = (idx >> 2) - 1; |
539 | 57fec1fe | bellard | switch(idx & 3) { |
540 | 57fec1fe | bellard | case 0: |
541 | 57fec1fe | bellard | tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, mem_index);
|
542 | 57fec1fe | bellard | break;
|
543 | 57fec1fe | bellard | case 1: |
544 | 57fec1fe | bellard | tcg_gen_qemu_ld16u(cpu_T[0], cpu_A0, mem_index);
|
545 | 57fec1fe | bellard | break;
|
546 | 57fec1fe | bellard | case 2: |
547 | 57fec1fe | bellard | tcg_gen_qemu_ld32u(cpu_T[0], cpu_A0, mem_index);
|
548 | 57fec1fe | bellard | break;
|
549 | 57fec1fe | bellard | default:
|
550 | 57fec1fe | bellard | case 3: |
551 | 57fec1fe | bellard | tcg_gen_qemu_ld64(cpu_T[0], cpu_A0, mem_index);
|
552 | 57fec1fe | bellard | break;
|
553 | 57fec1fe | bellard | } |
554 | 57fec1fe | bellard | } |
555 | 2c0262af | bellard | |
556 | 57fec1fe | bellard | static inline void gen_op_ldu_T0_A0(int idx) |
557 | 57fec1fe | bellard | { |
558 | 57fec1fe | bellard | gen_op_ld_T0_A0(idx); |
559 | 57fec1fe | bellard | } |
560 | 2c0262af | bellard | |
561 | 57fec1fe | bellard | static inline void gen_op_ld_T1_A0(int idx) |
562 | 57fec1fe | bellard | { |
563 | 57fec1fe | bellard | int mem_index = (idx >> 2) - 1; |
564 | 57fec1fe | bellard | switch(idx & 3) { |
565 | 57fec1fe | bellard | case 0: |
566 | 57fec1fe | bellard | tcg_gen_qemu_ld8u(cpu_T[1], cpu_A0, mem_index);
|
567 | 57fec1fe | bellard | break;
|
568 | 57fec1fe | bellard | case 1: |
569 | 57fec1fe | bellard | tcg_gen_qemu_ld16u(cpu_T[1], cpu_A0, mem_index);
|
570 | 57fec1fe | bellard | break;
|
571 | 57fec1fe | bellard | case 2: |
572 | 57fec1fe | bellard | tcg_gen_qemu_ld32u(cpu_T[1], cpu_A0, mem_index);
|
573 | 57fec1fe | bellard | break;
|
574 | 57fec1fe | bellard | default:
|
575 | 57fec1fe | bellard | case 3: |
576 | 57fec1fe | bellard | tcg_gen_qemu_ld64(cpu_T[1], cpu_A0, mem_index);
|
577 | 57fec1fe | bellard | break;
|
578 | 57fec1fe | bellard | } |
579 | 57fec1fe | bellard | } |
580 | 4f31916f | bellard | |
581 | 57fec1fe | bellard | static inline void gen_op_st_T0_A0(int idx) |
582 | 57fec1fe | bellard | { |
583 | 57fec1fe | bellard | int mem_index = (idx >> 2) - 1; |
584 | 57fec1fe | bellard | switch(idx & 3) { |
585 | 57fec1fe | bellard | case 0: |
586 | 57fec1fe | bellard | tcg_gen_qemu_st8(cpu_T[0], cpu_A0, mem_index);
|
587 | 57fec1fe | bellard | break;
|
588 | 57fec1fe | bellard | case 1: |
589 | 57fec1fe | bellard | tcg_gen_qemu_st16(cpu_T[0], cpu_A0, mem_index);
|
590 | 57fec1fe | bellard | break;
|
591 | 57fec1fe | bellard | case 2: |
592 | 57fec1fe | bellard | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, mem_index);
|
593 | 57fec1fe | bellard | break;
|
594 | 57fec1fe | bellard | default:
|
595 | 57fec1fe | bellard | case 3: |
596 | 57fec1fe | bellard | tcg_gen_qemu_st64(cpu_T[0], cpu_A0, mem_index);
|
597 | 57fec1fe | bellard | break;
|
598 | 57fec1fe | bellard | } |
599 | 57fec1fe | bellard | } |
600 | 4f31916f | bellard | |
601 | 57fec1fe | bellard | static inline void gen_op_st_T1_A0(int idx) |
602 | 57fec1fe | bellard | { |
603 | 57fec1fe | bellard | int mem_index = (idx >> 2) - 1; |
604 | 57fec1fe | bellard | switch(idx & 3) { |
605 | 57fec1fe | bellard | case 0: |
606 | 57fec1fe | bellard | tcg_gen_qemu_st8(cpu_T[1], cpu_A0, mem_index);
|
607 | 57fec1fe | bellard | break;
|
608 | 57fec1fe | bellard | case 1: |
609 | 57fec1fe | bellard | tcg_gen_qemu_st16(cpu_T[1], cpu_A0, mem_index);
|
610 | 57fec1fe | bellard | break;
|
611 | 57fec1fe | bellard | case 2: |
612 | 57fec1fe | bellard | tcg_gen_qemu_st32(cpu_T[1], cpu_A0, mem_index);
|
613 | 57fec1fe | bellard | break;
|
614 | 57fec1fe | bellard | default:
|
615 | 57fec1fe | bellard | case 3: |
616 | 57fec1fe | bellard | tcg_gen_qemu_st64(cpu_T[1], cpu_A0, mem_index);
|
617 | 57fec1fe | bellard | break;
|
618 | 57fec1fe | bellard | } |
619 | 57fec1fe | bellard | } |
620 | 4f31916f | bellard | |
621 | 14ce26e7 | bellard | static inline void gen_jmp_im(target_ulong pc) |
622 | 14ce26e7 | bellard | { |
623 | 57fec1fe | bellard | tcg_gen_movi_tl(cpu_tmp0, pc); |
624 | 57fec1fe | bellard | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip)); |
625 | 14ce26e7 | bellard | } |
626 | 14ce26e7 | bellard | |
627 | 2c0262af | bellard | static inline void gen_string_movl_A0_ESI(DisasContext *s) |
628 | 2c0262af | bellard | { |
629 | 2c0262af | bellard | int override;
|
630 | 2c0262af | bellard | |
631 | 2c0262af | bellard | override = s->override; |
632 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
633 | 14ce26e7 | bellard | if (s->aflag == 2) { |
634 | 14ce26e7 | bellard | if (override >= 0) { |
635 | 57fec1fe | bellard | gen_op_movq_A0_seg(override); |
636 | 57fec1fe | bellard | gen_op_addq_A0_reg_sN(0, R_ESI);
|
637 | 14ce26e7 | bellard | } else {
|
638 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_ESI); |
639 | 14ce26e7 | bellard | } |
640 | 14ce26e7 | bellard | } else
|
641 | 14ce26e7 | bellard | #endif
|
642 | 2c0262af | bellard | if (s->aflag) {
|
643 | 2c0262af | bellard | /* 32 bit address */
|
644 | 2c0262af | bellard | if (s->addseg && override < 0) |
645 | 2c0262af | bellard | override = R_DS; |
646 | 2c0262af | bellard | if (override >= 0) { |
647 | 57fec1fe | bellard | gen_op_movl_A0_seg(override); |
648 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_ESI);
|
649 | 2c0262af | bellard | } else {
|
650 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESI); |
651 | 2c0262af | bellard | } |
652 | 2c0262af | bellard | } else {
|
653 | 2c0262af | bellard | /* 16 address, always override */
|
654 | 2c0262af | bellard | if (override < 0) |
655 | 2c0262af | bellard | override = R_DS; |
656 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESI); |
657 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
658 | 57fec1fe | bellard | gen_op_addl_A0_seg(override); |
659 | 2c0262af | bellard | } |
660 | 2c0262af | bellard | } |
661 | 2c0262af | bellard | |
662 | 2c0262af | bellard | static inline void gen_string_movl_A0_EDI(DisasContext *s) |
663 | 2c0262af | bellard | { |
664 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
665 | 14ce26e7 | bellard | if (s->aflag == 2) { |
666 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_EDI); |
667 | 14ce26e7 | bellard | } else
|
668 | 14ce26e7 | bellard | #endif
|
669 | 2c0262af | bellard | if (s->aflag) {
|
670 | 2c0262af | bellard | if (s->addseg) {
|
671 | 57fec1fe | bellard | gen_op_movl_A0_seg(R_ES); |
672 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_EDI);
|
673 | 2c0262af | bellard | } else {
|
674 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EDI); |
675 | 2c0262af | bellard | } |
676 | 2c0262af | bellard | } else {
|
677 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EDI); |
678 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
679 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_ES); |
680 | 2c0262af | bellard | } |
681 | 2c0262af | bellard | } |
682 | 2c0262af | bellard | |
683 | 14ce26e7 | bellard | static GenOpFunc *gen_op_movl_T0_Dshift[4] = { |
684 | 2c0262af | bellard | gen_op_movl_T0_Dshiftb, |
685 | 2c0262af | bellard | gen_op_movl_T0_Dshiftw, |
686 | 2c0262af | bellard | gen_op_movl_T0_Dshiftl, |
687 | 14ce26e7 | bellard | X86_64_ONLY(gen_op_movl_T0_Dshiftq), |
688 | 2c0262af | bellard | }; |
689 | 2c0262af | bellard | |
690 | 14ce26e7 | bellard | static GenOpFunc1 *gen_op_jnz_ecx[3] = { |
691 | 14ce26e7 | bellard | gen_op_jnz_ecxw, |
692 | 14ce26e7 | bellard | gen_op_jnz_ecxl, |
693 | 14ce26e7 | bellard | X86_64_ONLY(gen_op_jnz_ecxq), |
694 | 2c0262af | bellard | }; |
695 | 3b46e624 | ths | |
696 | 14ce26e7 | bellard | static GenOpFunc1 *gen_op_jz_ecx[3] = { |
697 | 14ce26e7 | bellard | gen_op_jz_ecxw, |
698 | 14ce26e7 | bellard | gen_op_jz_ecxl, |
699 | 14ce26e7 | bellard | X86_64_ONLY(gen_op_jz_ecxq), |
700 | 2c0262af | bellard | }; |
701 | 2c0262af | bellard | |
702 | 14ce26e7 | bellard | static GenOpFunc *gen_op_dec_ECX[3] = { |
703 | 2c0262af | bellard | gen_op_decw_ECX, |
704 | 2c0262af | bellard | gen_op_decl_ECX, |
705 | 14ce26e7 | bellard | X86_64_ONLY(gen_op_decq_ECX), |
706 | 2c0262af | bellard | }; |
707 | 2c0262af | bellard | |
708 | 14ce26e7 | bellard | static GenOpFunc1 *gen_op_string_jnz_sub[2][4] = { |
709 | 2c0262af | bellard | { |
710 | 14ce26e7 | bellard | gen_op_jnz_subb, |
711 | 14ce26e7 | bellard | gen_op_jnz_subw, |
712 | 14ce26e7 | bellard | gen_op_jnz_subl, |
713 | 14ce26e7 | bellard | X86_64_ONLY(gen_op_jnz_subq), |
714 | 2c0262af | bellard | }, |
715 | 2c0262af | bellard | { |
716 | 14ce26e7 | bellard | gen_op_jz_subb, |
717 | 14ce26e7 | bellard | gen_op_jz_subw, |
718 | 14ce26e7 | bellard | gen_op_jz_subl, |
719 | 14ce26e7 | bellard | X86_64_ONLY(gen_op_jz_subq), |
720 | 2c0262af | bellard | }, |
721 | 2c0262af | bellard | }; |
722 | 2c0262af | bellard | |
723 | b8b6a50b | bellard | static void *helper_in_func[3] = { |
724 | b8b6a50b | bellard | helper_inb, |
725 | b8b6a50b | bellard | helper_inw, |
726 | b8b6a50b | bellard | helper_inl, |
727 | 2c0262af | bellard | }; |
728 | 2c0262af | bellard | |
729 | b8b6a50b | bellard | static void *helper_out_func[3] = { |
730 | b8b6a50b | bellard | helper_outb, |
731 | b8b6a50b | bellard | helper_outw, |
732 | b8b6a50b | bellard | helper_outl, |
733 | 2c0262af | bellard | }; |
734 | 2c0262af | bellard | |
735 | b8b6a50b | bellard | static void *gen_check_io_func[3] = { |
736 | b8b6a50b | bellard | helper_check_iob, |
737 | b8b6a50b | bellard | helper_check_iow, |
738 | b8b6a50b | bellard | helper_check_iol, |
739 | f115e911 | bellard | }; |
740 | f115e911 | bellard | |
741 | b8b6a50b | bellard | static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, |
742 | b8b6a50b | bellard | uint32_t svm_flags) |
743 | f115e911 | bellard | { |
744 | b8b6a50b | bellard | int state_saved;
|
745 | b8b6a50b | bellard | target_ulong next_eip; |
746 | b8b6a50b | bellard | |
747 | b8b6a50b | bellard | state_saved = 0;
|
748 | f115e911 | bellard | if (s->pe && (s->cpl > s->iopl || s->vm86)) {
|
749 | f115e911 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
750 | f115e911 | bellard | gen_op_set_cc_op(s->cc_op); |
751 | 14ce26e7 | bellard | gen_jmp_im(cur_eip); |
752 | b8b6a50b | bellard | state_saved = 1;
|
753 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
754 | b8b6a50b | bellard | tcg_gen_helper_0_1(gen_check_io_func[ot], |
755 | b6abf97d | bellard | cpu_tmp2_i32); |
756 | b8b6a50b | bellard | } |
757 | b8b6a50b | bellard | if(s->flags & (1ULL << INTERCEPT_IOIO_PROT)) { |
758 | b8b6a50b | bellard | if (!state_saved) {
|
759 | b8b6a50b | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
760 | b8b6a50b | bellard | gen_op_set_cc_op(s->cc_op); |
761 | b8b6a50b | bellard | gen_jmp_im(cur_eip); |
762 | b8b6a50b | bellard | state_saved = 1;
|
763 | b8b6a50b | bellard | } |
764 | b8b6a50b | bellard | svm_flags |= (1 << (4 + ot)); |
765 | b8b6a50b | bellard | next_eip = s->pc - s->cs_base; |
766 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
767 | b8b6a50b | bellard | tcg_gen_helper_0_3(helper_svm_check_io, |
768 | b6abf97d | bellard | cpu_tmp2_i32, |
769 | b8b6a50b | bellard | tcg_const_i32(svm_flags), |
770 | b8b6a50b | bellard | tcg_const_i32(next_eip - cur_eip)); |
771 | f115e911 | bellard | } |
772 | f115e911 | bellard | } |
773 | f115e911 | bellard | |
774 | 2c0262af | bellard | static inline void gen_movs(DisasContext *s, int ot) |
775 | 2c0262af | bellard | { |
776 | 2c0262af | bellard | gen_string_movl_A0_ESI(s); |
777 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
778 | 2c0262af | bellard | gen_string_movl_A0_EDI(s); |
779 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
780 | 2c0262af | bellard | gen_op_movl_T0_Dshift[ot](); |
781 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
782 | 14ce26e7 | bellard | if (s->aflag == 2) { |
783 | 14ce26e7 | bellard | gen_op_addq_ESI_T0(); |
784 | 14ce26e7 | bellard | gen_op_addq_EDI_T0(); |
785 | 5fafdf24 | ths | } else
|
786 | 14ce26e7 | bellard | #endif
|
787 | 2c0262af | bellard | if (s->aflag) {
|
788 | 2c0262af | bellard | gen_op_addl_ESI_T0(); |
789 | 2c0262af | bellard | gen_op_addl_EDI_T0(); |
790 | 2c0262af | bellard | } else {
|
791 | 2c0262af | bellard | gen_op_addw_ESI_T0(); |
792 | 2c0262af | bellard | gen_op_addw_EDI_T0(); |
793 | 2c0262af | bellard | } |
794 | 2c0262af | bellard | } |
795 | 2c0262af | bellard | |
796 | 2c0262af | bellard | static inline void gen_update_cc_op(DisasContext *s) |
797 | 2c0262af | bellard | { |
798 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
799 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
800 | 2c0262af | bellard | s->cc_op = CC_OP_DYNAMIC; |
801 | 2c0262af | bellard | } |
802 | 2c0262af | bellard | } |
803 | 2c0262af | bellard | |
804 | b6abf97d | bellard | static void gen_op_update1_cc(void) |
805 | b6abf97d | bellard | { |
806 | b6abf97d | bellard | tcg_gen_discard_tl(cpu_cc_src); |
807 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
808 | b6abf97d | bellard | } |
809 | b6abf97d | bellard | |
810 | b6abf97d | bellard | static void gen_op_update2_cc(void) |
811 | b6abf97d | bellard | { |
812 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
|
813 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
814 | b6abf97d | bellard | } |
815 | b6abf97d | bellard | |
816 | b6abf97d | bellard | static inline void gen_op_cmpl_T0_T1_cc(void) |
817 | b6abf97d | bellard | { |
818 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
|
819 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
820 | b6abf97d | bellard | } |
821 | b6abf97d | bellard | |
822 | b6abf97d | bellard | static inline void gen_op_testl_T0_T1_cc(void) |
823 | b6abf97d | bellard | { |
824 | b6abf97d | bellard | tcg_gen_discard_tl(cpu_cc_src); |
825 | b6abf97d | bellard | tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
826 | b6abf97d | bellard | } |
827 | b6abf97d | bellard | |
828 | b6abf97d | bellard | static void gen_op_update_neg_cc(void) |
829 | b6abf97d | bellard | { |
830 | b6abf97d | bellard | tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
|
831 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
832 | b6abf97d | bellard | } |
833 | b6abf97d | bellard | |
834 | 14ce26e7 | bellard | /* XXX: does not work with gdbstub "ice" single step - not a
|
835 | 14ce26e7 | bellard | serious problem */
|
836 | 14ce26e7 | bellard | static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) |
837 | 2c0262af | bellard | { |
838 | 14ce26e7 | bellard | int l1, l2;
|
839 | 14ce26e7 | bellard | |
840 | 14ce26e7 | bellard | l1 = gen_new_label(); |
841 | 14ce26e7 | bellard | l2 = gen_new_label(); |
842 | 14ce26e7 | bellard | gen_op_jnz_ecx[s->aflag](l1); |
843 | 14ce26e7 | bellard | gen_set_label(l2); |
844 | 14ce26e7 | bellard | gen_jmp_tb(s, next_eip, 1);
|
845 | 14ce26e7 | bellard | gen_set_label(l1); |
846 | 14ce26e7 | bellard | return l2;
|
847 | 2c0262af | bellard | } |
848 | 2c0262af | bellard | |
849 | 2c0262af | bellard | static inline void gen_stos(DisasContext *s, int ot) |
850 | 2c0262af | bellard | { |
851 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
|
852 | 2c0262af | bellard | gen_string_movl_A0_EDI(s); |
853 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
854 | 2c0262af | bellard | gen_op_movl_T0_Dshift[ot](); |
855 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
856 | 14ce26e7 | bellard | if (s->aflag == 2) { |
857 | 14ce26e7 | bellard | gen_op_addq_EDI_T0(); |
858 | 5fafdf24 | ths | } else
|
859 | 14ce26e7 | bellard | #endif
|
860 | 2c0262af | bellard | if (s->aflag) {
|
861 | 2c0262af | bellard | gen_op_addl_EDI_T0(); |
862 | 2c0262af | bellard | } else {
|
863 | 2c0262af | bellard | gen_op_addw_EDI_T0(); |
864 | 2c0262af | bellard | } |
865 | 2c0262af | bellard | } |
866 | 2c0262af | bellard | |
867 | 2c0262af | bellard | static inline void gen_lods(DisasContext *s, int ot) |
868 | 2c0262af | bellard | { |
869 | 2c0262af | bellard | gen_string_movl_A0_ESI(s); |
870 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
871 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, R_EAX); |
872 | 2c0262af | bellard | gen_op_movl_T0_Dshift[ot](); |
873 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
874 | 14ce26e7 | bellard | if (s->aflag == 2) { |
875 | 14ce26e7 | bellard | gen_op_addq_ESI_T0(); |
876 | 5fafdf24 | ths | } else
|
877 | 14ce26e7 | bellard | #endif
|
878 | 2c0262af | bellard | if (s->aflag) {
|
879 | 2c0262af | bellard | gen_op_addl_ESI_T0(); |
880 | 2c0262af | bellard | } else {
|
881 | 2c0262af | bellard | gen_op_addw_ESI_T0(); |
882 | 2c0262af | bellard | } |
883 | 2c0262af | bellard | } |
884 | 2c0262af | bellard | |
885 | 2c0262af | bellard | static inline void gen_scas(DisasContext *s, int ot) |
886 | 2c0262af | bellard | { |
887 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
|
888 | 2c0262af | bellard | gen_string_movl_A0_EDI(s); |
889 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
890 | 2c0262af | bellard | gen_op_cmpl_T0_T1_cc(); |
891 | 2c0262af | bellard | gen_op_movl_T0_Dshift[ot](); |
892 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
893 | 14ce26e7 | bellard | if (s->aflag == 2) { |
894 | 14ce26e7 | bellard | gen_op_addq_EDI_T0(); |
895 | 5fafdf24 | ths | } else
|
896 | 14ce26e7 | bellard | #endif
|
897 | 2c0262af | bellard | if (s->aflag) {
|
898 | 2c0262af | bellard | gen_op_addl_EDI_T0(); |
899 | 2c0262af | bellard | } else {
|
900 | 2c0262af | bellard | gen_op_addw_EDI_T0(); |
901 | 2c0262af | bellard | } |
902 | 2c0262af | bellard | } |
903 | 2c0262af | bellard | |
904 | 2c0262af | bellard | static inline void gen_cmps(DisasContext *s, int ot) |
905 | 2c0262af | bellard | { |
906 | 2c0262af | bellard | gen_string_movl_A0_ESI(s); |
907 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
908 | 2c0262af | bellard | gen_string_movl_A0_EDI(s); |
909 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
910 | 2c0262af | bellard | gen_op_cmpl_T0_T1_cc(); |
911 | 2c0262af | bellard | gen_op_movl_T0_Dshift[ot](); |
912 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
913 | 14ce26e7 | bellard | if (s->aflag == 2) { |
914 | 14ce26e7 | bellard | gen_op_addq_ESI_T0(); |
915 | 14ce26e7 | bellard | gen_op_addq_EDI_T0(); |
916 | 5fafdf24 | ths | } else
|
917 | 14ce26e7 | bellard | #endif
|
918 | 2c0262af | bellard | if (s->aflag) {
|
919 | 2c0262af | bellard | gen_op_addl_ESI_T0(); |
920 | 2c0262af | bellard | gen_op_addl_EDI_T0(); |
921 | 2c0262af | bellard | } else {
|
922 | 2c0262af | bellard | gen_op_addw_ESI_T0(); |
923 | 2c0262af | bellard | gen_op_addw_EDI_T0(); |
924 | 2c0262af | bellard | } |
925 | 2c0262af | bellard | } |
926 | 2c0262af | bellard | |
927 | 2c0262af | bellard | static inline void gen_ins(DisasContext *s, int ot) |
928 | 2c0262af | bellard | { |
929 | 2c0262af | bellard | gen_string_movl_A0_EDI(s); |
930 | 9772c73b | bellard | gen_op_movl_T0_0(); |
931 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
932 | b8b6a50b | bellard | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
|
933 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
|
934 | b6abf97d | bellard | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
935 | b6abf97d | bellard | tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[0], cpu_tmp2_i32);
|
936 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
937 | 2c0262af | bellard | gen_op_movl_T0_Dshift[ot](); |
938 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
939 | 14ce26e7 | bellard | if (s->aflag == 2) { |
940 | 14ce26e7 | bellard | gen_op_addq_EDI_T0(); |
941 | 5fafdf24 | ths | } else
|
942 | 14ce26e7 | bellard | #endif
|
943 | 2c0262af | bellard | if (s->aflag) {
|
944 | 2c0262af | bellard | gen_op_addl_EDI_T0(); |
945 | 2c0262af | bellard | } else {
|
946 | 2c0262af | bellard | gen_op_addw_EDI_T0(); |
947 | 2c0262af | bellard | } |
948 | 2c0262af | bellard | } |
949 | 2c0262af | bellard | |
950 | 2c0262af | bellard | static inline void gen_outs(DisasContext *s, int ot) |
951 | 2c0262af | bellard | { |
952 | 2c0262af | bellard | gen_string_movl_A0_ESI(s); |
953 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
954 | b8b6a50b | bellard | |
955 | b8b6a50b | bellard | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
|
956 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
|
957 | b6abf97d | bellard | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
958 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
|
959 | b6abf97d | bellard | tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32); |
960 | b8b6a50b | bellard | |
961 | 2c0262af | bellard | gen_op_movl_T0_Dshift[ot](); |
962 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
963 | 14ce26e7 | bellard | if (s->aflag == 2) { |
964 | 14ce26e7 | bellard | gen_op_addq_ESI_T0(); |
965 | 5fafdf24 | ths | } else
|
966 | 14ce26e7 | bellard | #endif
|
967 | 2c0262af | bellard | if (s->aflag) {
|
968 | 2c0262af | bellard | gen_op_addl_ESI_T0(); |
969 | 2c0262af | bellard | } else {
|
970 | 2c0262af | bellard | gen_op_addw_ESI_T0(); |
971 | 2c0262af | bellard | } |
972 | 2c0262af | bellard | } |
973 | 2c0262af | bellard | |
974 | 2c0262af | bellard | /* same method as Valgrind : we generate jumps to current or next
|
975 | 2c0262af | bellard | instruction */
|
976 | 2c0262af | bellard | #define GEN_REPZ(op) \
|
977 | 2c0262af | bellard | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ |
978 | 14ce26e7 | bellard | target_ulong cur_eip, target_ulong next_eip) \ |
979 | 2c0262af | bellard | { \ |
980 | 14ce26e7 | bellard | int l2;\
|
981 | 2c0262af | bellard | gen_update_cc_op(s); \ |
982 | 14ce26e7 | bellard | l2 = gen_jz_ecx_string(s, next_eip); \ |
983 | 2c0262af | bellard | gen_ ## op(s, ot); \ |
984 | 2c0262af | bellard | gen_op_dec_ECX[s->aflag](); \ |
985 | 2c0262af | bellard | /* a loop would cause two single step exceptions if ECX = 1 \
|
986 | 2c0262af | bellard | before rep string_insn */ \
|
987 | 2c0262af | bellard | if (!s->jmp_opt) \
|
988 | 14ce26e7 | bellard | gen_op_jz_ecx[s->aflag](l2); \ |
989 | 2c0262af | bellard | gen_jmp(s, cur_eip); \ |
990 | 2c0262af | bellard | } |
991 | 2c0262af | bellard | |
992 | 2c0262af | bellard | #define GEN_REPZ2(op) \
|
993 | 2c0262af | bellard | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ |
994 | 14ce26e7 | bellard | target_ulong cur_eip, \ |
995 | 14ce26e7 | bellard | target_ulong next_eip, \ |
996 | 2c0262af | bellard | int nz) \
|
997 | 2c0262af | bellard | { \ |
998 | 14ce26e7 | bellard | int l2;\
|
999 | 2c0262af | bellard | gen_update_cc_op(s); \ |
1000 | 14ce26e7 | bellard | l2 = gen_jz_ecx_string(s, next_eip); \ |
1001 | 2c0262af | bellard | gen_ ## op(s, ot); \ |
1002 | 2c0262af | bellard | gen_op_dec_ECX[s->aflag](); \ |
1003 | 2c0262af | bellard | gen_op_set_cc_op(CC_OP_SUBB + ot); \ |
1004 | 14ce26e7 | bellard | gen_op_string_jnz_sub[nz][ot](l2);\ |
1005 | 2c0262af | bellard | if (!s->jmp_opt) \
|
1006 | 14ce26e7 | bellard | gen_op_jz_ecx[s->aflag](l2); \ |
1007 | 2c0262af | bellard | gen_jmp(s, cur_eip); \ |
1008 | 2c0262af | bellard | } |
1009 | 2c0262af | bellard | |
1010 | 2c0262af | bellard | GEN_REPZ(movs) |
1011 | 2c0262af | bellard | GEN_REPZ(stos) |
1012 | 2c0262af | bellard | GEN_REPZ(lods) |
1013 | 2c0262af | bellard | GEN_REPZ(ins) |
1014 | 2c0262af | bellard | GEN_REPZ(outs) |
1015 | 2c0262af | bellard | GEN_REPZ2(scas) |
1016 | 2c0262af | bellard | GEN_REPZ2(cmps) |
1017 | 2c0262af | bellard | |
1018 | 2c0262af | bellard | enum {
|
1019 | 2c0262af | bellard | JCC_O, |
1020 | 2c0262af | bellard | JCC_B, |
1021 | 2c0262af | bellard | JCC_Z, |
1022 | 2c0262af | bellard | JCC_BE, |
1023 | 2c0262af | bellard | JCC_S, |
1024 | 2c0262af | bellard | JCC_P, |
1025 | 2c0262af | bellard | JCC_L, |
1026 | 2c0262af | bellard | JCC_LE, |
1027 | 2c0262af | bellard | }; |
1028 | 2c0262af | bellard | |
1029 | 14ce26e7 | bellard | static GenOpFunc1 *gen_jcc_sub[4][8] = { |
1030 | 2c0262af | bellard | [OT_BYTE] = { |
1031 | 2c0262af | bellard | NULL,
|
1032 | 2c0262af | bellard | gen_op_jb_subb, |
1033 | 2c0262af | bellard | gen_op_jz_subb, |
1034 | 2c0262af | bellard | gen_op_jbe_subb, |
1035 | 2c0262af | bellard | gen_op_js_subb, |
1036 | 2c0262af | bellard | NULL,
|
1037 | 2c0262af | bellard | gen_op_jl_subb, |
1038 | 2c0262af | bellard | gen_op_jle_subb, |
1039 | 2c0262af | bellard | }, |
1040 | 2c0262af | bellard | [OT_WORD] = { |
1041 | 2c0262af | bellard | NULL,
|
1042 | 2c0262af | bellard | gen_op_jb_subw, |
1043 | 2c0262af | bellard | gen_op_jz_subw, |
1044 | 2c0262af | bellard | gen_op_jbe_subw, |
1045 | 2c0262af | bellard | gen_op_js_subw, |
1046 | 2c0262af | bellard | NULL,
|
1047 | 2c0262af | bellard | gen_op_jl_subw, |
1048 | 2c0262af | bellard | gen_op_jle_subw, |
1049 | 2c0262af | bellard | }, |
1050 | 2c0262af | bellard | [OT_LONG] = { |
1051 | 2c0262af | bellard | NULL,
|
1052 | 2c0262af | bellard | gen_op_jb_subl, |
1053 | 2c0262af | bellard | gen_op_jz_subl, |
1054 | 2c0262af | bellard | gen_op_jbe_subl, |
1055 | 2c0262af | bellard | gen_op_js_subl, |
1056 | 2c0262af | bellard | NULL,
|
1057 | 2c0262af | bellard | gen_op_jl_subl, |
1058 | 2c0262af | bellard | gen_op_jle_subl, |
1059 | 2c0262af | bellard | }, |
1060 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
1061 | 14ce26e7 | bellard | [OT_QUAD] = { |
1062 | 14ce26e7 | bellard | NULL,
|
1063 | 14ce26e7 | bellard | BUGGY_64(gen_op_jb_subq), |
1064 | 14ce26e7 | bellard | gen_op_jz_subq, |
1065 | 14ce26e7 | bellard | BUGGY_64(gen_op_jbe_subq), |
1066 | 14ce26e7 | bellard | gen_op_js_subq, |
1067 | 14ce26e7 | bellard | NULL,
|
1068 | 14ce26e7 | bellard | BUGGY_64(gen_op_jl_subq), |
1069 | 14ce26e7 | bellard | BUGGY_64(gen_op_jle_subq), |
1070 | 14ce26e7 | bellard | }, |
1071 | 14ce26e7 | bellard | #endif
|
1072 | 2c0262af | bellard | }; |
1073 | 14ce26e7 | bellard | static GenOpFunc1 *gen_op_loop[3][4] = { |
1074 | 2c0262af | bellard | [0] = {
|
1075 | 2c0262af | bellard | gen_op_loopnzw, |
1076 | 2c0262af | bellard | gen_op_loopzw, |
1077 | 14ce26e7 | bellard | gen_op_jnz_ecxw, |
1078 | 2c0262af | bellard | }, |
1079 | 2c0262af | bellard | [1] = {
|
1080 | 2c0262af | bellard | gen_op_loopnzl, |
1081 | 2c0262af | bellard | gen_op_loopzl, |
1082 | 14ce26e7 | bellard | gen_op_jnz_ecxl, |
1083 | 14ce26e7 | bellard | }, |
1084 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
1085 | 14ce26e7 | bellard | [2] = {
|
1086 | 14ce26e7 | bellard | gen_op_loopnzq, |
1087 | 14ce26e7 | bellard | gen_op_loopzq, |
1088 | 14ce26e7 | bellard | gen_op_jnz_ecxq, |
1089 | 2c0262af | bellard | }, |
1090 | 14ce26e7 | bellard | #endif
|
1091 | 2c0262af | bellard | }; |
1092 | 2c0262af | bellard | |
1093 | 2c0262af | bellard | static GenOpFunc *gen_setcc_slow[8] = { |
1094 | 2c0262af | bellard | gen_op_seto_T0_cc, |
1095 | 2c0262af | bellard | gen_op_setb_T0_cc, |
1096 | 2c0262af | bellard | gen_op_setz_T0_cc, |
1097 | 2c0262af | bellard | gen_op_setbe_T0_cc, |
1098 | 2c0262af | bellard | gen_op_sets_T0_cc, |
1099 | 2c0262af | bellard | gen_op_setp_T0_cc, |
1100 | 2c0262af | bellard | gen_op_setl_T0_cc, |
1101 | 2c0262af | bellard | gen_op_setle_T0_cc, |
1102 | 2c0262af | bellard | }; |
1103 | 2c0262af | bellard | |
1104 | 14ce26e7 | bellard | static GenOpFunc *gen_setcc_sub[4][8] = { |
1105 | 2c0262af | bellard | [OT_BYTE] = { |
1106 | 2c0262af | bellard | NULL,
|
1107 | 2c0262af | bellard | gen_op_setb_T0_subb, |
1108 | 2c0262af | bellard | gen_op_setz_T0_subb, |
1109 | 2c0262af | bellard | gen_op_setbe_T0_subb, |
1110 | 2c0262af | bellard | gen_op_sets_T0_subb, |
1111 | 2c0262af | bellard | NULL,
|
1112 | 2c0262af | bellard | gen_op_setl_T0_subb, |
1113 | 2c0262af | bellard | gen_op_setle_T0_subb, |
1114 | 2c0262af | bellard | }, |
1115 | 2c0262af | bellard | [OT_WORD] = { |
1116 | 2c0262af | bellard | NULL,
|
1117 | 2c0262af | bellard | gen_op_setb_T0_subw, |
1118 | 2c0262af | bellard | gen_op_setz_T0_subw, |
1119 | 2c0262af | bellard | gen_op_setbe_T0_subw, |
1120 | 2c0262af | bellard | gen_op_sets_T0_subw, |
1121 | 2c0262af | bellard | NULL,
|
1122 | 2c0262af | bellard | gen_op_setl_T0_subw, |
1123 | 2c0262af | bellard | gen_op_setle_T0_subw, |
1124 | 2c0262af | bellard | }, |
1125 | 2c0262af | bellard | [OT_LONG] = { |
1126 | 2c0262af | bellard | NULL,
|
1127 | 2c0262af | bellard | gen_op_setb_T0_subl, |
1128 | 2c0262af | bellard | gen_op_setz_T0_subl, |
1129 | 2c0262af | bellard | gen_op_setbe_T0_subl, |
1130 | 2c0262af | bellard | gen_op_sets_T0_subl, |
1131 | 2c0262af | bellard | NULL,
|
1132 | 2c0262af | bellard | gen_op_setl_T0_subl, |
1133 | 2c0262af | bellard | gen_op_setle_T0_subl, |
1134 | 2c0262af | bellard | }, |
1135 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
1136 | 14ce26e7 | bellard | [OT_QUAD] = { |
1137 | 14ce26e7 | bellard | NULL,
|
1138 | 14ce26e7 | bellard | gen_op_setb_T0_subq, |
1139 | 14ce26e7 | bellard | gen_op_setz_T0_subq, |
1140 | 14ce26e7 | bellard | gen_op_setbe_T0_subq, |
1141 | 14ce26e7 | bellard | gen_op_sets_T0_subq, |
1142 | 14ce26e7 | bellard | NULL,
|
1143 | 14ce26e7 | bellard | gen_op_setl_T0_subq, |
1144 | 14ce26e7 | bellard | gen_op_setle_T0_subq, |
1145 | 14ce26e7 | bellard | }, |
1146 | 14ce26e7 | bellard | #endif
|
1147 | 2c0262af | bellard | }; |
1148 | 2c0262af | bellard | |
1149 | 19e6c4b8 | bellard | static void *helper_fp_arith_ST0_FT0[8] = { |
1150 | 19e6c4b8 | bellard | helper_fadd_ST0_FT0, |
1151 | 19e6c4b8 | bellard | helper_fmul_ST0_FT0, |
1152 | 19e6c4b8 | bellard | helper_fcom_ST0_FT0, |
1153 | 19e6c4b8 | bellard | helper_fcom_ST0_FT0, |
1154 | 19e6c4b8 | bellard | helper_fsub_ST0_FT0, |
1155 | 19e6c4b8 | bellard | helper_fsubr_ST0_FT0, |
1156 | 19e6c4b8 | bellard | helper_fdiv_ST0_FT0, |
1157 | 19e6c4b8 | bellard | helper_fdivr_ST0_FT0, |
1158 | 2c0262af | bellard | }; |
1159 | 2c0262af | bellard | |
1160 | 2c0262af | bellard | /* NOTE the exception in "r" op ordering */
|
1161 | 19e6c4b8 | bellard | static void *helper_fp_arith_STN_ST0[8] = { |
1162 | 19e6c4b8 | bellard | helper_fadd_STN_ST0, |
1163 | 19e6c4b8 | bellard | helper_fmul_STN_ST0, |
1164 | 2c0262af | bellard | NULL,
|
1165 | 2c0262af | bellard | NULL,
|
1166 | 19e6c4b8 | bellard | helper_fsubr_STN_ST0, |
1167 | 19e6c4b8 | bellard | helper_fsub_STN_ST0, |
1168 | 19e6c4b8 | bellard | helper_fdivr_STN_ST0, |
1169 | 19e6c4b8 | bellard | helper_fdiv_STN_ST0, |
1170 | 2c0262af | bellard | }; |
1171 | 2c0262af | bellard | |
1172 | cad3a37d | bellard | /* compute eflags.C to reg */
|
1173 | cad3a37d | bellard | static void gen_compute_eflags_c(TCGv reg) |
1174 | cad3a37d | bellard | { |
1175 | cad3a37d | bellard | #if TCG_TARGET_REG_BITS == 32 |
1176 | cad3a37d | bellard | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
|
1177 | cad3a37d | bellard | tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, |
1178 | cad3a37d | bellard | (long)cc_table + offsetof(CCTable, compute_c));
|
1179 | cad3a37d | bellard | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
|
1180 | cad3a37d | bellard | tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, |
1181 | cad3a37d | bellard | 1, &cpu_tmp2_i32, 0, NULL); |
1182 | cad3a37d | bellard | #else
|
1183 | cad3a37d | bellard | tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op); |
1184 | cad3a37d | bellard | tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
|
1185 | cad3a37d | bellard | tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, |
1186 | cad3a37d | bellard | (long)cc_table + offsetof(CCTable, compute_c));
|
1187 | cad3a37d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
|
1188 | cad3a37d | bellard | tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, |
1189 | cad3a37d | bellard | 1, &cpu_tmp2_i32, 0, NULL); |
1190 | cad3a37d | bellard | #endif
|
1191 | cad3a37d | bellard | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
1192 | cad3a37d | bellard | } |
1193 | cad3a37d | bellard | |
1194 | cad3a37d | bellard | /* compute all eflags to cc_src */
|
1195 | cad3a37d | bellard | static void gen_compute_eflags(TCGv reg) |
1196 | cad3a37d | bellard | { |
1197 | cad3a37d | bellard | #if TCG_TARGET_REG_BITS == 32 |
1198 | cad3a37d | bellard | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
|
1199 | cad3a37d | bellard | tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, |
1200 | cad3a37d | bellard | (long)cc_table + offsetof(CCTable, compute_all));
|
1201 | cad3a37d | bellard | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
|
1202 | cad3a37d | bellard | tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, |
1203 | cad3a37d | bellard | 1, &cpu_tmp2_i32, 0, NULL); |
1204 | cad3a37d | bellard | #else
|
1205 | cad3a37d | bellard | tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op); |
1206 | cad3a37d | bellard | tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
|
1207 | cad3a37d | bellard | tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, |
1208 | cad3a37d | bellard | (long)cc_table + offsetof(CCTable, compute_all));
|
1209 | cad3a37d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
|
1210 | cad3a37d | bellard | tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, |
1211 | cad3a37d | bellard | 1, &cpu_tmp2_i32, 0, NULL); |
1212 | cad3a37d | bellard | #endif
|
1213 | cad3a37d | bellard | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
1214 | cad3a37d | bellard | } |
1215 | cad3a37d | bellard | |
1216 | 2c0262af | bellard | /* if d == OR_TMP0, it means memory operand (address in A0) */
|
1217 | 2c0262af | bellard | static void gen_op(DisasContext *s1, int op, int ot, int d) |
1218 | 2c0262af | bellard | { |
1219 | 2c0262af | bellard | if (d != OR_TMP0) {
|
1220 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, d);
|
1221 | 2c0262af | bellard | } else {
|
1222 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s1->mem_index); |
1223 | 2c0262af | bellard | } |
1224 | 2c0262af | bellard | switch(op) {
|
1225 | 2c0262af | bellard | case OP_ADCL:
|
1226 | cad3a37d | bellard | if (s1->cc_op != CC_OP_DYNAMIC)
|
1227 | cad3a37d | bellard | gen_op_set_cc_op(s1->cc_op); |
1228 | cad3a37d | bellard | gen_compute_eflags_c(cpu_tmp4); |
1229 | cad3a37d | bellard | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1230 | cad3a37d | bellard | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4); |
1231 | cad3a37d | bellard | if (d != OR_TMP0)
|
1232 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1233 | cad3a37d | bellard | else
|
1234 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1235 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
|
1236 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
1237 | cad3a37d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); |
1238 | cad3a37d | bellard | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
|
1239 | cad3a37d | bellard | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot); |
1240 | cad3a37d | bellard | s1->cc_op = CC_OP_DYNAMIC; |
1241 | cad3a37d | bellard | break;
|
1242 | 2c0262af | bellard | case OP_SBBL:
|
1243 | 2c0262af | bellard | if (s1->cc_op != CC_OP_DYNAMIC)
|
1244 | 2c0262af | bellard | gen_op_set_cc_op(s1->cc_op); |
1245 | cad3a37d | bellard | gen_compute_eflags_c(cpu_tmp4); |
1246 | cad3a37d | bellard | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1247 | cad3a37d | bellard | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4); |
1248 | cad3a37d | bellard | if (d != OR_TMP0)
|
1249 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, d); |
1250 | cad3a37d | bellard | else
|
1251 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1252 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
|
1253 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
1254 | cad3a37d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); |
1255 | cad3a37d | bellard | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
|
1256 | cad3a37d | bellard | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot); |
1257 | 2c0262af | bellard | s1->cc_op = CC_OP_DYNAMIC; |
1258 | cad3a37d | bellard | break;
|
1259 | 2c0262af | bellard | case OP_ADDL:
|
1260 | 2c0262af | bellard | gen_op_addl_T0_T1(); |
1261 | cad3a37d | bellard | if (d != OR_TMP0)
|
1262 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1263 | cad3a37d | bellard | else
|
1264 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1265 | cad3a37d | bellard | gen_op_update2_cc(); |
1266 | 2c0262af | bellard | s1->cc_op = CC_OP_ADDB + ot; |
1267 | 2c0262af | bellard | break;
|
1268 | 2c0262af | bellard | case OP_SUBL:
|
1269 | 57fec1fe | bellard | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1270 | cad3a37d | bellard | if (d != OR_TMP0)
|
1271 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1272 | cad3a37d | bellard | else
|
1273 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1274 | cad3a37d | bellard | gen_op_update2_cc(); |
1275 | 2c0262af | bellard | s1->cc_op = CC_OP_SUBB + ot; |
1276 | 2c0262af | bellard | break;
|
1277 | 2c0262af | bellard | default:
|
1278 | 2c0262af | bellard | case OP_ANDL:
|
1279 | 57fec1fe | bellard | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1280 | cad3a37d | bellard | if (d != OR_TMP0)
|
1281 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1282 | cad3a37d | bellard | else
|
1283 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1284 | cad3a37d | bellard | gen_op_update1_cc(); |
1285 | 57fec1fe | bellard | s1->cc_op = CC_OP_LOGICB + ot; |
1286 | 57fec1fe | bellard | break;
|
1287 | 2c0262af | bellard | case OP_ORL:
|
1288 | 57fec1fe | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1289 | cad3a37d | bellard | if (d != OR_TMP0)
|
1290 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1291 | cad3a37d | bellard | else
|
1292 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1293 | cad3a37d | bellard | gen_op_update1_cc(); |
1294 | 57fec1fe | bellard | s1->cc_op = CC_OP_LOGICB + ot; |
1295 | 57fec1fe | bellard | break;
|
1296 | 2c0262af | bellard | case OP_XORL:
|
1297 | 57fec1fe | bellard | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1298 | cad3a37d | bellard | if (d != OR_TMP0)
|
1299 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, d); |
1300 | cad3a37d | bellard | else
|
1301 | cad3a37d | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1302 | cad3a37d | bellard | gen_op_update1_cc(); |
1303 | 2c0262af | bellard | s1->cc_op = CC_OP_LOGICB + ot; |
1304 | 2c0262af | bellard | break;
|
1305 | 2c0262af | bellard | case OP_CMPL:
|
1306 | 2c0262af | bellard | gen_op_cmpl_T0_T1_cc(); |
1307 | 2c0262af | bellard | s1->cc_op = CC_OP_SUBB + ot; |
1308 | 2c0262af | bellard | break;
|
1309 | 2c0262af | bellard | } |
1310 | b6abf97d | bellard | } |
1311 | b6abf97d | bellard | |
1312 | 2c0262af | bellard | /* if d == OR_TMP0, it means memory operand (address in A0) */
|
1313 | 2c0262af | bellard | static void gen_inc(DisasContext *s1, int ot, int d, int c) |
1314 | 2c0262af | bellard | { |
1315 | 2c0262af | bellard | if (d != OR_TMP0)
|
1316 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, d);
|
1317 | 2c0262af | bellard | else
|
1318 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s1->mem_index); |
1319 | 2c0262af | bellard | if (s1->cc_op != CC_OP_DYNAMIC)
|
1320 | 2c0262af | bellard | gen_op_set_cc_op(s1->cc_op); |
1321 | 2c0262af | bellard | if (c > 0) { |
1322 | b6abf97d | bellard | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); |
1323 | 2c0262af | bellard | s1->cc_op = CC_OP_INCB + ot; |
1324 | 2c0262af | bellard | } else {
|
1325 | b6abf97d | bellard | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1); |
1326 | 2c0262af | bellard | s1->cc_op = CC_OP_DECB + ot; |
1327 | 2c0262af | bellard | } |
1328 | 2c0262af | bellard | if (d != OR_TMP0)
|
1329 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, d); |
1330 | 2c0262af | bellard | else
|
1331 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s1->mem_index); |
1332 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
1333 | b6abf97d | bellard | gen_compute_eflags_c(cpu_cc_src); |
1334 | 2c0262af | bellard | } |
1335 | 2c0262af | bellard | |
1336 | cad3a37d | bellard | static void gen_extu(int ot, TCGv reg) |
1337 | cad3a37d | bellard | { |
1338 | cad3a37d | bellard | switch(ot) {
|
1339 | cad3a37d | bellard | case OT_BYTE:
|
1340 | cad3a37d | bellard | tcg_gen_ext8u_tl(reg, reg); |
1341 | cad3a37d | bellard | break;
|
1342 | cad3a37d | bellard | case OT_WORD:
|
1343 | cad3a37d | bellard | tcg_gen_ext16u_tl(reg, reg); |
1344 | cad3a37d | bellard | break;
|
1345 | cad3a37d | bellard | case OT_LONG:
|
1346 | cad3a37d | bellard | tcg_gen_ext32u_tl(reg, reg); |
1347 | cad3a37d | bellard | break;
|
1348 | cad3a37d | bellard | default:
|
1349 | cad3a37d | bellard | break;
|
1350 | cad3a37d | bellard | } |
1351 | cad3a37d | bellard | } |
1352 | cad3a37d | bellard | |
1353 | f484d386 | bellard | static void gen_exts(int ot, TCGv reg) |
1354 | f484d386 | bellard | { |
1355 | f484d386 | bellard | switch(ot) {
|
1356 | f484d386 | bellard | case OT_BYTE:
|
1357 | f484d386 | bellard | tcg_gen_ext8s_tl(reg, reg); |
1358 | f484d386 | bellard | break;
|
1359 | f484d386 | bellard | case OT_WORD:
|
1360 | f484d386 | bellard | tcg_gen_ext16s_tl(reg, reg); |
1361 | f484d386 | bellard | break;
|
1362 | f484d386 | bellard | case OT_LONG:
|
1363 | f484d386 | bellard | tcg_gen_ext32s_tl(reg, reg); |
1364 | f484d386 | bellard | break;
|
1365 | f484d386 | bellard | default:
|
1366 | f484d386 | bellard | break;
|
1367 | f484d386 | bellard | } |
1368 | f484d386 | bellard | } |
1369 | f484d386 | bellard | |
1370 | b6abf97d | bellard | /* XXX: add faster immediate case */
|
1371 | b6abf97d | bellard | static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
1372 | b6abf97d | bellard | int is_right, int is_arith) |
1373 | 2c0262af | bellard | { |
1374 | b6abf97d | bellard | target_ulong mask; |
1375 | b6abf97d | bellard | int shift_label;
|
1376 | b6abf97d | bellard | |
1377 | b6abf97d | bellard | if (ot == OT_QUAD)
|
1378 | b6abf97d | bellard | mask = 0x3f;
|
1379 | 2c0262af | bellard | else
|
1380 | b6abf97d | bellard | mask = 0x1f;
|
1381 | 3b46e624 | ths | |
1382 | b6abf97d | bellard | /* load */
|
1383 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1384 | b6abf97d | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1385 | 2c0262af | bellard | else
|
1386 | b6abf97d | bellard | gen_op_mov_TN_reg(ot, 0, op1);
|
1387 | b6abf97d | bellard | |
1388 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); |
1389 | b6abf97d | bellard | |
1390 | b6abf97d | bellard | tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1); |
1391 | b6abf97d | bellard | |
1392 | b6abf97d | bellard | if (is_right) {
|
1393 | b6abf97d | bellard | if (is_arith) {
|
1394 | f484d386 | bellard | gen_exts(ot, cpu_T[0]);
|
1395 | b6abf97d | bellard | tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
|
1396 | b6abf97d | bellard | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1397 | b6abf97d | bellard | } else {
|
1398 | cad3a37d | bellard | gen_extu(ot, cpu_T[0]);
|
1399 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
|
1400 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1401 | b6abf97d | bellard | } |
1402 | b6abf97d | bellard | } else {
|
1403 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
|
1404 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1405 | b6abf97d | bellard | } |
1406 | b6abf97d | bellard | |
1407 | b6abf97d | bellard | /* store */
|
1408 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1409 | b6abf97d | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1410 | b6abf97d | bellard | else
|
1411 | b6abf97d | bellard | gen_op_mov_reg_T0(ot, op1); |
1412 | b6abf97d | bellard | |
1413 | b6abf97d | bellard | /* update eflags if non zero shift */
|
1414 | b6abf97d | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
1415 | b6abf97d | bellard | gen_op_set_cc_op(s->cc_op); |
1416 | b6abf97d | bellard | |
1417 | b6abf97d | bellard | shift_label = gen_new_label(); |
1418 | b6abf97d | bellard | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), shift_label); |
1419 | b6abf97d | bellard | |
1420 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T3); |
1421 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
1422 | b6abf97d | bellard | if (is_right)
|
1423 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
1424 | b6abf97d | bellard | else
|
1425 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
1426 | b6abf97d | bellard | |
1427 | b6abf97d | bellard | gen_set_label(shift_label); |
1428 | b6abf97d | bellard | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
|
1429 | b6abf97d | bellard | } |
1430 | b6abf97d | bellard | |
1431 | b6abf97d | bellard | static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
1432 | b6abf97d | bellard | { |
1433 | b6abf97d | bellard | if (arg2 >= 0) |
1434 | b6abf97d | bellard | tcg_gen_shli_tl(ret, arg1, arg2); |
1435 | b6abf97d | bellard | else
|
1436 | b6abf97d | bellard | tcg_gen_shri_tl(ret, arg1, -arg2); |
1437 | b6abf97d | bellard | } |
1438 | b6abf97d | bellard | |
1439 | b6abf97d | bellard | /* XXX: add faster immediate case */
|
1440 | b6abf97d | bellard | static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, |
1441 | b6abf97d | bellard | int is_right)
|
1442 | b6abf97d | bellard | { |
1443 | b6abf97d | bellard | target_ulong mask; |
1444 | b6abf97d | bellard | int label1, label2, data_bits;
|
1445 | b6abf97d | bellard | |
1446 | b6abf97d | bellard | if (ot == OT_QUAD)
|
1447 | b6abf97d | bellard | mask = 0x3f;
|
1448 | b6abf97d | bellard | else
|
1449 | b6abf97d | bellard | mask = 0x1f;
|
1450 | b6abf97d | bellard | |
1451 | b6abf97d | bellard | /* load */
|
1452 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1453 | b6abf97d | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1454 | b6abf97d | bellard | else
|
1455 | b6abf97d | bellard | gen_op_mov_TN_reg(ot, 0, op1);
|
1456 | b6abf97d | bellard | |
1457 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); |
1458 | b6abf97d | bellard | |
1459 | b6abf97d | bellard | /* Must test zero case to avoid using undefined behaviour in TCG
|
1460 | b6abf97d | bellard | shifts. */
|
1461 | b6abf97d | bellard | label1 = gen_new_label(); |
1462 | b6abf97d | bellard | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label1); |
1463 | b6abf97d | bellard | |
1464 | b6abf97d | bellard | if (ot <= OT_WORD)
|
1465 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_T[1], (1 << (3 + ot)) - 1); |
1466 | b6abf97d | bellard | else
|
1467 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_tmp0, cpu_T[1]);
|
1468 | b6abf97d | bellard | |
1469 | cad3a37d | bellard | gen_extu(ot, cpu_T[0]);
|
1470 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_T3, cpu_T[0]);
|
1471 | b6abf97d | bellard | |
1472 | b6abf97d | bellard | data_bits = 8 << ot;
|
1473 | b6abf97d | bellard | /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
|
1474 | b6abf97d | bellard | fix TCG definition) */
|
1475 | b6abf97d | bellard | if (is_right) {
|
1476 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp0);
|
1477 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0); |
1478 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
1479 | b6abf97d | bellard | } else {
|
1480 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp0);
|
1481 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0); |
1482 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
1483 | b6abf97d | bellard | } |
1484 | b6abf97d | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp4); |
1485 | b6abf97d | bellard | |
1486 | b6abf97d | bellard | gen_set_label(label1); |
1487 | b6abf97d | bellard | /* store */
|
1488 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1489 | b6abf97d | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1490 | b6abf97d | bellard | else
|
1491 | b6abf97d | bellard | gen_op_mov_reg_T0(ot, op1); |
1492 | b6abf97d | bellard | |
1493 | b6abf97d | bellard | /* update eflags */
|
1494 | b6abf97d | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
1495 | b6abf97d | bellard | gen_op_set_cc_op(s->cc_op); |
1496 | b6abf97d | bellard | |
1497 | b6abf97d | bellard | label2 = gen_new_label(); |
1498 | b6abf97d | bellard | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label2); |
1499 | b6abf97d | bellard | |
1500 | b6abf97d | bellard | gen_compute_eflags(cpu_cc_src); |
1501 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); |
1502 | b6abf97d | bellard | tcg_gen_xor_tl(cpu_tmp0, cpu_T3, cpu_T[0]);
|
1503 | b6abf97d | bellard | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); |
1504 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); |
1505 | b6abf97d | bellard | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
1506 | b6abf97d | bellard | if (is_right) {
|
1507 | b6abf97d | bellard | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], data_bits - 1); |
1508 | b6abf97d | bellard | } |
1509 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_C); |
1510 | b6abf97d | bellard | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
|
1511 | b6abf97d | bellard | |
1512 | b6abf97d | bellard | tcg_gen_discard_tl(cpu_cc_dst); |
1513 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); |
1514 | b6abf97d | bellard | |
1515 | b6abf97d | bellard | gen_set_label(label2); |
1516 | b6abf97d | bellard | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
|
1517 | b6abf97d | bellard | } |
1518 | b6abf97d | bellard | |
1519 | b6abf97d | bellard | static void *helper_rotc[8] = { |
1520 | b6abf97d | bellard | helper_rclb, |
1521 | b6abf97d | bellard | helper_rclw, |
1522 | b6abf97d | bellard | helper_rcll, |
1523 | b6abf97d | bellard | X86_64_ONLY(helper_rclq), |
1524 | b6abf97d | bellard | helper_rcrb, |
1525 | b6abf97d | bellard | helper_rcrw, |
1526 | b6abf97d | bellard | helper_rcrl, |
1527 | b6abf97d | bellard | X86_64_ONLY(helper_rcrq), |
1528 | b6abf97d | bellard | }; |
1529 | b6abf97d | bellard | |
1530 | b6abf97d | bellard | /* XXX: add faster immediate = 1 case */
|
1531 | b6abf97d | bellard | static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, |
1532 | b6abf97d | bellard | int is_right)
|
1533 | b6abf97d | bellard | { |
1534 | b6abf97d | bellard | int label1;
|
1535 | b6abf97d | bellard | |
1536 | b6abf97d | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
1537 | b6abf97d | bellard | gen_op_set_cc_op(s->cc_op); |
1538 | b6abf97d | bellard | |
1539 | b6abf97d | bellard | /* load */
|
1540 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1541 | b6abf97d | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1542 | b6abf97d | bellard | else
|
1543 | b6abf97d | bellard | gen_op_mov_TN_reg(ot, 0, op1);
|
1544 | b6abf97d | bellard | |
1545 | b6abf97d | bellard | tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)],
|
1546 | b6abf97d | bellard | cpu_T[0], cpu_T[0], cpu_T[1]); |
1547 | b6abf97d | bellard | /* store */
|
1548 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1549 | b6abf97d | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1550 | b6abf97d | bellard | else
|
1551 | b6abf97d | bellard | gen_op_mov_reg_T0(ot, op1); |
1552 | b6abf97d | bellard | |
1553 | b6abf97d | bellard | /* update eflags */
|
1554 | b6abf97d | bellard | label1 = gen_new_label(); |
1555 | b6abf97d | bellard | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(-1), label1);
|
1556 | b6abf97d | bellard | |
1557 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T3); |
1558 | b6abf97d | bellard | tcg_gen_discard_tl(cpu_cc_dst); |
1559 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); |
1560 | b6abf97d | bellard | |
1561 | b6abf97d | bellard | gen_set_label(label1); |
1562 | b6abf97d | bellard | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
|
1563 | b6abf97d | bellard | } |
1564 | b6abf97d | bellard | |
1565 | b6abf97d | bellard | /* XXX: add faster immediate case */
|
1566 | b6abf97d | bellard | static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, |
1567 | b6abf97d | bellard | int is_right)
|
1568 | b6abf97d | bellard | { |
1569 | b6abf97d | bellard | int label1, label2, data_bits;
|
1570 | b6abf97d | bellard | target_ulong mask; |
1571 | b6abf97d | bellard | |
1572 | b6abf97d | bellard | if (ot == OT_QUAD)
|
1573 | b6abf97d | bellard | mask = 0x3f;
|
1574 | b6abf97d | bellard | else
|
1575 | b6abf97d | bellard | mask = 0x1f;
|
1576 | b6abf97d | bellard | |
1577 | b6abf97d | bellard | /* load */
|
1578 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1579 | b6abf97d | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1580 | b6abf97d | bellard | else
|
1581 | b6abf97d | bellard | gen_op_mov_TN_reg(ot, 0, op1);
|
1582 | b6abf97d | bellard | |
1583 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); |
1584 | b6abf97d | bellard | /* Must test zero case to avoid using undefined behaviour in TCG
|
1585 | b6abf97d | bellard | shifts. */
|
1586 | b6abf97d | bellard | label1 = gen_new_label(); |
1587 | b6abf97d | bellard | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1);
|
1588 | b6abf97d | bellard | |
1589 | b6abf97d | bellard | tcg_gen_addi_tl(cpu_tmp5, cpu_T3, -1);
|
1590 | b6abf97d | bellard | if (ot == OT_WORD) {
|
1591 | b6abf97d | bellard | /* Note: we implement the Intel behaviour for shift count > 16 */
|
1592 | b6abf97d | bellard | if (is_right) {
|
1593 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); |
1594 | b6abf97d | bellard | tcg_gen_shli_tl(cpu_tmp0, cpu_T[1], 16); |
1595 | b6abf97d | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
1596 | b6abf97d | bellard | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
1597 | b6abf97d | bellard | |
1598 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
|
1599 | b6abf97d | bellard | |
1600 | b6abf97d | bellard | /* only needed if count > 16, but a test would complicate */
|
1601 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3);
|
1602 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp5);
|
1603 | b6abf97d | bellard | |
1604 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3); |
1605 | b6abf97d | bellard | |
1606 | b6abf97d | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
1607 | b6abf97d | bellard | } else {
|
1608 | b6abf97d | bellard | /* XXX: not optimal */
|
1609 | b6abf97d | bellard | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); |
1610 | b6abf97d | bellard | tcg_gen_shli_tl(cpu_T[1], cpu_T[1], 16); |
1611 | b6abf97d | bellard | tcg_gen_or_tl(cpu_T[1], cpu_T[1], cpu_T[0]); |
1612 | b6abf97d | bellard | tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); |
1613 | b6abf97d | bellard | |
1614 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
|
1615 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);
|
1616 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_tmp6, cpu_T[1], cpu_tmp0);
|
1617 | b6abf97d | bellard | tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6); |
1618 | b6abf97d | bellard | |
1619 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3); |
1620 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3);
|
1621 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5); |
1622 | b6abf97d | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1623 | b6abf97d | bellard | } |
1624 | b6abf97d | bellard | } else {
|
1625 | b6abf97d | bellard | data_bits = 8 << ot;
|
1626 | b6abf97d | bellard | if (is_right) {
|
1627 | b6abf97d | bellard | if (ot == OT_LONG)
|
1628 | b6abf97d | bellard | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
1629 | b6abf97d | bellard | |
1630 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
|
1631 | b6abf97d | bellard | |
1632 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3); |
1633 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3); |
1634 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp5); |
1635 | b6abf97d | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1636 | b6abf97d | bellard | |
1637 | b6abf97d | bellard | } else {
|
1638 | b6abf97d | bellard | if (ot == OT_LONG)
|
1639 | b6abf97d | bellard | tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); |
1640 | b6abf97d | bellard | |
1641 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
|
1642 | b6abf97d | bellard | |
1643 | b6abf97d | bellard | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3); |
1644 | b6abf97d | bellard | tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3); |
1645 | b6abf97d | bellard | tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5); |
1646 | b6abf97d | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1647 | b6abf97d | bellard | } |
1648 | b6abf97d | bellard | } |
1649 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_T[1], cpu_tmp4);
|
1650 | b6abf97d | bellard | |
1651 | b6abf97d | bellard | gen_set_label(label1); |
1652 | b6abf97d | bellard | /* store */
|
1653 | b6abf97d | bellard | if (op1 == OR_TMP0)
|
1654 | b6abf97d | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1655 | b6abf97d | bellard | else
|
1656 | b6abf97d | bellard | gen_op_mov_reg_T0(ot, op1); |
1657 | b6abf97d | bellard | |
1658 | b6abf97d | bellard | /* update eflags */
|
1659 | b6abf97d | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
1660 | b6abf97d | bellard | gen_op_set_cc_op(s->cc_op); |
1661 | b6abf97d | bellard | |
1662 | b6abf97d | bellard | label2 = gen_new_label(); |
1663 | b6abf97d | bellard | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label2);
|
1664 | b6abf97d | bellard | |
1665 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
|
1666 | b6abf97d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
|
1667 | b6abf97d | bellard | if (is_right) {
|
1668 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
1669 | b6abf97d | bellard | } else {
|
1670 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
1671 | b6abf97d | bellard | } |
1672 | b6abf97d | bellard | gen_set_label(label2); |
1673 | b6abf97d | bellard | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
|
1674 | b6abf97d | bellard | } |
1675 | b6abf97d | bellard | |
1676 | b6abf97d | bellard | static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) |
1677 | b6abf97d | bellard | { |
1678 | b6abf97d | bellard | if (s != OR_TMP1)
|
1679 | b6abf97d | bellard | gen_op_mov_TN_reg(ot, 1, s);
|
1680 | b6abf97d | bellard | switch(op) {
|
1681 | b6abf97d | bellard | case OP_ROL:
|
1682 | b6abf97d | bellard | gen_rot_rm_T1(s1, ot, d, 0);
|
1683 | b6abf97d | bellard | break;
|
1684 | b6abf97d | bellard | case OP_ROR:
|
1685 | b6abf97d | bellard | gen_rot_rm_T1(s1, ot, d, 1);
|
1686 | b6abf97d | bellard | break;
|
1687 | b6abf97d | bellard | case OP_SHL:
|
1688 | b6abf97d | bellard | case OP_SHL1:
|
1689 | b6abf97d | bellard | gen_shift_rm_T1(s1, ot, d, 0, 0); |
1690 | b6abf97d | bellard | break;
|
1691 | b6abf97d | bellard | case OP_SHR:
|
1692 | b6abf97d | bellard | gen_shift_rm_T1(s1, ot, d, 1, 0); |
1693 | b6abf97d | bellard | break;
|
1694 | b6abf97d | bellard | case OP_SAR:
|
1695 | b6abf97d | bellard | gen_shift_rm_T1(s1, ot, d, 1, 1); |
1696 | b6abf97d | bellard | break;
|
1697 | b6abf97d | bellard | case OP_RCL:
|
1698 | b6abf97d | bellard | gen_rotc_rm_T1(s1, ot, d, 0);
|
1699 | b6abf97d | bellard | break;
|
1700 | b6abf97d | bellard | case OP_RCR:
|
1701 | b6abf97d | bellard | gen_rotc_rm_T1(s1, ot, d, 1);
|
1702 | b6abf97d | bellard | break;
|
1703 | b6abf97d | bellard | } |
1704 | 2c0262af | bellard | } |
1705 | 2c0262af | bellard | |
1706 | 2c0262af | bellard | static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) |
1707 | 2c0262af | bellard | { |
1708 | 2c0262af | bellard | /* currently not optimized */
|
1709 | 2c0262af | bellard | gen_op_movl_T1_im(c); |
1710 | 2c0262af | bellard | gen_shift(s1, op, ot, d, OR_TMP1); |
1711 | 2c0262af | bellard | } |
1712 | 2c0262af | bellard | |
1713 | 2c0262af | bellard | static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr) |
1714 | 2c0262af | bellard | { |
1715 | 14ce26e7 | bellard | target_long disp; |
1716 | 2c0262af | bellard | int havesib;
|
1717 | 14ce26e7 | bellard | int base;
|
1718 | 2c0262af | bellard | int index;
|
1719 | 2c0262af | bellard | int scale;
|
1720 | 2c0262af | bellard | int opreg;
|
1721 | 2c0262af | bellard | int mod, rm, code, override, must_add_seg;
|
1722 | 2c0262af | bellard | |
1723 | 2c0262af | bellard | override = s->override; |
1724 | 2c0262af | bellard | must_add_seg = s->addseg; |
1725 | 2c0262af | bellard | if (override >= 0) |
1726 | 2c0262af | bellard | must_add_seg = 1;
|
1727 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
1728 | 2c0262af | bellard | rm = modrm & 7;
|
1729 | 2c0262af | bellard | |
1730 | 2c0262af | bellard | if (s->aflag) {
|
1731 | 2c0262af | bellard | |
1732 | 2c0262af | bellard | havesib = 0;
|
1733 | 2c0262af | bellard | base = rm; |
1734 | 2c0262af | bellard | index = 0;
|
1735 | 2c0262af | bellard | scale = 0;
|
1736 | 3b46e624 | ths | |
1737 | 2c0262af | bellard | if (base == 4) { |
1738 | 2c0262af | bellard | havesib = 1;
|
1739 | 61382a50 | bellard | code = ldub_code(s->pc++); |
1740 | 2c0262af | bellard | scale = (code >> 6) & 3; |
1741 | 14ce26e7 | bellard | index = ((code >> 3) & 7) | REX_X(s); |
1742 | 14ce26e7 | bellard | base = (code & 7);
|
1743 | 2c0262af | bellard | } |
1744 | 14ce26e7 | bellard | base |= REX_B(s); |
1745 | 2c0262af | bellard | |
1746 | 2c0262af | bellard | switch (mod) {
|
1747 | 2c0262af | bellard | case 0: |
1748 | 14ce26e7 | bellard | if ((base & 7) == 5) { |
1749 | 2c0262af | bellard | base = -1;
|
1750 | 14ce26e7 | bellard | disp = (int32_t)ldl_code(s->pc); |
1751 | 2c0262af | bellard | s->pc += 4;
|
1752 | 14ce26e7 | bellard | if (CODE64(s) && !havesib) {
|
1753 | 14ce26e7 | bellard | disp += s->pc + s->rip_offset; |
1754 | 14ce26e7 | bellard | } |
1755 | 2c0262af | bellard | } else {
|
1756 | 2c0262af | bellard | disp = 0;
|
1757 | 2c0262af | bellard | } |
1758 | 2c0262af | bellard | break;
|
1759 | 2c0262af | bellard | case 1: |
1760 | 61382a50 | bellard | disp = (int8_t)ldub_code(s->pc++); |
1761 | 2c0262af | bellard | break;
|
1762 | 2c0262af | bellard | default:
|
1763 | 2c0262af | bellard | case 2: |
1764 | 61382a50 | bellard | disp = ldl_code(s->pc); |
1765 | 2c0262af | bellard | s->pc += 4;
|
1766 | 2c0262af | bellard | break;
|
1767 | 2c0262af | bellard | } |
1768 | 3b46e624 | ths | |
1769 | 2c0262af | bellard | if (base >= 0) { |
1770 | 2c0262af | bellard | /* for correct popl handling with esp */
|
1771 | 2c0262af | bellard | if (base == 4 && s->popl_esp_hack) |
1772 | 2c0262af | bellard | disp += s->popl_esp_hack; |
1773 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
1774 | 14ce26e7 | bellard | if (s->aflag == 2) { |
1775 | 57fec1fe | bellard | gen_op_movq_A0_reg(base); |
1776 | 14ce26e7 | bellard | if (disp != 0) { |
1777 | 57fec1fe | bellard | gen_op_addq_A0_im(disp); |
1778 | 14ce26e7 | bellard | } |
1779 | 5fafdf24 | ths | } else
|
1780 | 14ce26e7 | bellard | #endif
|
1781 | 14ce26e7 | bellard | { |
1782 | 57fec1fe | bellard | gen_op_movl_A0_reg(base); |
1783 | 14ce26e7 | bellard | if (disp != 0) |
1784 | 14ce26e7 | bellard | gen_op_addl_A0_im(disp); |
1785 | 14ce26e7 | bellard | } |
1786 | 2c0262af | bellard | } else {
|
1787 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
1788 | 14ce26e7 | bellard | if (s->aflag == 2) { |
1789 | 57fec1fe | bellard | gen_op_movq_A0_im(disp); |
1790 | 5fafdf24 | ths | } else
|
1791 | 14ce26e7 | bellard | #endif
|
1792 | 14ce26e7 | bellard | { |
1793 | 14ce26e7 | bellard | gen_op_movl_A0_im(disp); |
1794 | 14ce26e7 | bellard | } |
1795 | 2c0262af | bellard | } |
1796 | 2c0262af | bellard | /* XXX: index == 4 is always invalid */
|
1797 | 2c0262af | bellard | if (havesib && (index != 4 || scale != 0)) { |
1798 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
1799 | 14ce26e7 | bellard | if (s->aflag == 2) { |
1800 | 57fec1fe | bellard | gen_op_addq_A0_reg_sN(scale, index); |
1801 | 5fafdf24 | ths | } else
|
1802 | 14ce26e7 | bellard | #endif
|
1803 | 14ce26e7 | bellard | { |
1804 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(scale, index); |
1805 | 14ce26e7 | bellard | } |
1806 | 2c0262af | bellard | } |
1807 | 2c0262af | bellard | if (must_add_seg) {
|
1808 | 2c0262af | bellard | if (override < 0) { |
1809 | 2c0262af | bellard | if (base == R_EBP || base == R_ESP)
|
1810 | 2c0262af | bellard | override = R_SS; |
1811 | 2c0262af | bellard | else
|
1812 | 2c0262af | bellard | override = R_DS; |
1813 | 2c0262af | bellard | } |
1814 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
1815 | 14ce26e7 | bellard | if (s->aflag == 2) { |
1816 | 57fec1fe | bellard | gen_op_addq_A0_seg(override); |
1817 | 5fafdf24 | ths | } else
|
1818 | 14ce26e7 | bellard | #endif
|
1819 | 14ce26e7 | bellard | { |
1820 | 57fec1fe | bellard | gen_op_addl_A0_seg(override); |
1821 | 14ce26e7 | bellard | } |
1822 | 2c0262af | bellard | } |
1823 | 2c0262af | bellard | } else {
|
1824 | 2c0262af | bellard | switch (mod) {
|
1825 | 2c0262af | bellard | case 0: |
1826 | 2c0262af | bellard | if (rm == 6) { |
1827 | 61382a50 | bellard | disp = lduw_code(s->pc); |
1828 | 2c0262af | bellard | s->pc += 2;
|
1829 | 2c0262af | bellard | gen_op_movl_A0_im(disp); |
1830 | 2c0262af | bellard | rm = 0; /* avoid SS override */ |
1831 | 2c0262af | bellard | goto no_rm;
|
1832 | 2c0262af | bellard | } else {
|
1833 | 2c0262af | bellard | disp = 0;
|
1834 | 2c0262af | bellard | } |
1835 | 2c0262af | bellard | break;
|
1836 | 2c0262af | bellard | case 1: |
1837 | 61382a50 | bellard | disp = (int8_t)ldub_code(s->pc++); |
1838 | 2c0262af | bellard | break;
|
1839 | 2c0262af | bellard | default:
|
1840 | 2c0262af | bellard | case 2: |
1841 | 61382a50 | bellard | disp = lduw_code(s->pc); |
1842 | 2c0262af | bellard | s->pc += 2;
|
1843 | 2c0262af | bellard | break;
|
1844 | 2c0262af | bellard | } |
1845 | 2c0262af | bellard | switch(rm) {
|
1846 | 2c0262af | bellard | case 0: |
1847 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBX); |
1848 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_ESI);
|
1849 | 2c0262af | bellard | break;
|
1850 | 2c0262af | bellard | case 1: |
1851 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBX); |
1852 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_EDI);
|
1853 | 2c0262af | bellard | break;
|
1854 | 2c0262af | bellard | case 2: |
1855 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBP); |
1856 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_ESI);
|
1857 | 2c0262af | bellard | break;
|
1858 | 2c0262af | bellard | case 3: |
1859 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBP); |
1860 | 57fec1fe | bellard | gen_op_addl_A0_reg_sN(0, R_EDI);
|
1861 | 2c0262af | bellard | break;
|
1862 | 2c0262af | bellard | case 4: |
1863 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESI); |
1864 | 2c0262af | bellard | break;
|
1865 | 2c0262af | bellard | case 5: |
1866 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EDI); |
1867 | 2c0262af | bellard | break;
|
1868 | 2c0262af | bellard | case 6: |
1869 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBP); |
1870 | 2c0262af | bellard | break;
|
1871 | 2c0262af | bellard | default:
|
1872 | 2c0262af | bellard | case 7: |
1873 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBX); |
1874 | 2c0262af | bellard | break;
|
1875 | 2c0262af | bellard | } |
1876 | 2c0262af | bellard | if (disp != 0) |
1877 | 2c0262af | bellard | gen_op_addl_A0_im(disp); |
1878 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
1879 | 2c0262af | bellard | no_rm:
|
1880 | 2c0262af | bellard | if (must_add_seg) {
|
1881 | 2c0262af | bellard | if (override < 0) { |
1882 | 2c0262af | bellard | if (rm == 2 || rm == 3 || rm == 6) |
1883 | 2c0262af | bellard | override = R_SS; |
1884 | 2c0262af | bellard | else
|
1885 | 2c0262af | bellard | override = R_DS; |
1886 | 2c0262af | bellard | } |
1887 | 57fec1fe | bellard | gen_op_addl_A0_seg(override); |
1888 | 2c0262af | bellard | } |
1889 | 2c0262af | bellard | } |
1890 | 2c0262af | bellard | |
1891 | 2c0262af | bellard | opreg = OR_A0; |
1892 | 2c0262af | bellard | disp = 0;
|
1893 | 2c0262af | bellard | *reg_ptr = opreg; |
1894 | 2c0262af | bellard | *offset_ptr = disp; |
1895 | 2c0262af | bellard | } |
1896 | 2c0262af | bellard | |
1897 | e17a36ce | bellard | static void gen_nop_modrm(DisasContext *s, int modrm) |
1898 | e17a36ce | bellard | { |
1899 | e17a36ce | bellard | int mod, rm, base, code;
|
1900 | e17a36ce | bellard | |
1901 | e17a36ce | bellard | mod = (modrm >> 6) & 3; |
1902 | e17a36ce | bellard | if (mod == 3) |
1903 | e17a36ce | bellard | return;
|
1904 | e17a36ce | bellard | rm = modrm & 7;
|
1905 | e17a36ce | bellard | |
1906 | e17a36ce | bellard | if (s->aflag) {
|
1907 | e17a36ce | bellard | |
1908 | e17a36ce | bellard | base = rm; |
1909 | 3b46e624 | ths | |
1910 | e17a36ce | bellard | if (base == 4) { |
1911 | e17a36ce | bellard | code = ldub_code(s->pc++); |
1912 | e17a36ce | bellard | base = (code & 7);
|
1913 | e17a36ce | bellard | } |
1914 | 3b46e624 | ths | |
1915 | e17a36ce | bellard | switch (mod) {
|
1916 | e17a36ce | bellard | case 0: |
1917 | e17a36ce | bellard | if (base == 5) { |
1918 | e17a36ce | bellard | s->pc += 4;
|
1919 | e17a36ce | bellard | } |
1920 | e17a36ce | bellard | break;
|
1921 | e17a36ce | bellard | case 1: |
1922 | e17a36ce | bellard | s->pc++; |
1923 | e17a36ce | bellard | break;
|
1924 | e17a36ce | bellard | default:
|
1925 | e17a36ce | bellard | case 2: |
1926 | e17a36ce | bellard | s->pc += 4;
|
1927 | e17a36ce | bellard | break;
|
1928 | e17a36ce | bellard | } |
1929 | e17a36ce | bellard | } else {
|
1930 | e17a36ce | bellard | switch (mod) {
|
1931 | e17a36ce | bellard | case 0: |
1932 | e17a36ce | bellard | if (rm == 6) { |
1933 | e17a36ce | bellard | s->pc += 2;
|
1934 | e17a36ce | bellard | } |
1935 | e17a36ce | bellard | break;
|
1936 | e17a36ce | bellard | case 1: |
1937 | e17a36ce | bellard | s->pc++; |
1938 | e17a36ce | bellard | break;
|
1939 | e17a36ce | bellard | default:
|
1940 | e17a36ce | bellard | case 2: |
1941 | e17a36ce | bellard | s->pc += 2;
|
1942 | e17a36ce | bellard | break;
|
1943 | e17a36ce | bellard | } |
1944 | e17a36ce | bellard | } |
1945 | e17a36ce | bellard | } |
1946 | e17a36ce | bellard | |
1947 | 664e0f19 | bellard | /* used for LEA and MOV AX, mem */
|
1948 | 664e0f19 | bellard | static void gen_add_A0_ds_seg(DisasContext *s) |
1949 | 664e0f19 | bellard | { |
1950 | 664e0f19 | bellard | int override, must_add_seg;
|
1951 | 664e0f19 | bellard | must_add_seg = s->addseg; |
1952 | 664e0f19 | bellard | override = R_DS; |
1953 | 664e0f19 | bellard | if (s->override >= 0) { |
1954 | 664e0f19 | bellard | override = s->override; |
1955 | 664e0f19 | bellard | must_add_seg = 1;
|
1956 | 664e0f19 | bellard | } else {
|
1957 | 664e0f19 | bellard | override = R_DS; |
1958 | 664e0f19 | bellard | } |
1959 | 664e0f19 | bellard | if (must_add_seg) {
|
1960 | 8f091a59 | bellard | #ifdef TARGET_X86_64
|
1961 | 8f091a59 | bellard | if (CODE64(s)) {
|
1962 | 57fec1fe | bellard | gen_op_addq_A0_seg(override); |
1963 | 5fafdf24 | ths | } else
|
1964 | 8f091a59 | bellard | #endif
|
1965 | 8f091a59 | bellard | { |
1966 | 57fec1fe | bellard | gen_op_addl_A0_seg(override); |
1967 | 8f091a59 | bellard | } |
1968 | 664e0f19 | bellard | } |
1969 | 664e0f19 | bellard | } |
1970 | 664e0f19 | bellard | |
1971 | 2c0262af | bellard | /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
|
1972 | 2c0262af | bellard | OR_TMP0 */
|
1973 | 2c0262af | bellard | static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store) |
1974 | 2c0262af | bellard | { |
1975 | 2c0262af | bellard | int mod, rm, opreg, disp;
|
1976 | 2c0262af | bellard | |
1977 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
1978 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
1979 | 2c0262af | bellard | if (mod == 3) { |
1980 | 2c0262af | bellard | if (is_store) {
|
1981 | 2c0262af | bellard | if (reg != OR_TMP0)
|
1982 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
1983 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
1984 | 2c0262af | bellard | } else {
|
1985 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
1986 | 2c0262af | bellard | if (reg != OR_TMP0)
|
1987 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
1988 | 2c0262af | bellard | } |
1989 | 2c0262af | bellard | } else {
|
1990 | 2c0262af | bellard | gen_lea_modrm(s, modrm, &opreg, &disp); |
1991 | 2c0262af | bellard | if (is_store) {
|
1992 | 2c0262af | bellard | if (reg != OR_TMP0)
|
1993 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
1994 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
1995 | 2c0262af | bellard | } else {
|
1996 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
1997 | 2c0262af | bellard | if (reg != OR_TMP0)
|
1998 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
1999 | 2c0262af | bellard | } |
2000 | 2c0262af | bellard | } |
2001 | 2c0262af | bellard | } |
2002 | 2c0262af | bellard | |
2003 | 2c0262af | bellard | static inline uint32_t insn_get(DisasContext *s, int ot) |
2004 | 2c0262af | bellard | { |
2005 | 2c0262af | bellard | uint32_t ret; |
2006 | 2c0262af | bellard | |
2007 | 2c0262af | bellard | switch(ot) {
|
2008 | 2c0262af | bellard | case OT_BYTE:
|
2009 | 61382a50 | bellard | ret = ldub_code(s->pc); |
2010 | 2c0262af | bellard | s->pc++; |
2011 | 2c0262af | bellard | break;
|
2012 | 2c0262af | bellard | case OT_WORD:
|
2013 | 61382a50 | bellard | ret = lduw_code(s->pc); |
2014 | 2c0262af | bellard | s->pc += 2;
|
2015 | 2c0262af | bellard | break;
|
2016 | 2c0262af | bellard | default:
|
2017 | 2c0262af | bellard | case OT_LONG:
|
2018 | 61382a50 | bellard | ret = ldl_code(s->pc); |
2019 | 2c0262af | bellard | s->pc += 4;
|
2020 | 2c0262af | bellard | break;
|
2021 | 2c0262af | bellard | } |
2022 | 2c0262af | bellard | return ret;
|
2023 | 2c0262af | bellard | } |
2024 | 2c0262af | bellard | |
2025 | 14ce26e7 | bellard | static inline int insn_const_size(unsigned int ot) |
2026 | 14ce26e7 | bellard | { |
2027 | 14ce26e7 | bellard | if (ot <= OT_LONG)
|
2028 | 14ce26e7 | bellard | return 1 << ot; |
2029 | 14ce26e7 | bellard | else
|
2030 | 14ce26e7 | bellard | return 4; |
2031 | 14ce26e7 | bellard | } |
2032 | 14ce26e7 | bellard | |
2033 | 6e256c93 | bellard | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) |
2034 | 6e256c93 | bellard | { |
2035 | 6e256c93 | bellard | TranslationBlock *tb; |
2036 | 6e256c93 | bellard | target_ulong pc; |
2037 | 6e256c93 | bellard | |
2038 | 6e256c93 | bellard | pc = s->cs_base + eip; |
2039 | 6e256c93 | bellard | tb = s->tb; |
2040 | 6e256c93 | bellard | /* NOTE: we handle the case where the TB spans two pages here */
|
2041 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
|
2042 | 6e256c93 | bellard | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
|
2043 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
|
2044 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
2045 | 6e256c93 | bellard | gen_jmp_im(eip); |
2046 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
|
2047 | 6e256c93 | bellard | } else {
|
2048 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
|
2049 | 6e256c93 | bellard | gen_jmp_im(eip); |
2050 | 6e256c93 | bellard | gen_eob(s); |
2051 | 6e256c93 | bellard | } |
2052 | 6e256c93 | bellard | } |
2053 | 6e256c93 | bellard | |
2054 | 5fafdf24 | ths | static inline void gen_jcc(DisasContext *s, int b, |
2055 | 14ce26e7 | bellard | target_ulong val, target_ulong next_eip) |
2056 | 2c0262af | bellard | { |
2057 | 2c0262af | bellard | TranslationBlock *tb; |
2058 | 2c0262af | bellard | int inv, jcc_op;
|
2059 | 14ce26e7 | bellard | GenOpFunc1 *func; |
2060 | 14ce26e7 | bellard | target_ulong tmp; |
2061 | 14ce26e7 | bellard | int l1, l2;
|
2062 | 2c0262af | bellard | |
2063 | 2c0262af | bellard | inv = b & 1;
|
2064 | 2c0262af | bellard | jcc_op = (b >> 1) & 7; |
2065 | 3b46e624 | ths | |
2066 | 2c0262af | bellard | if (s->jmp_opt) {
|
2067 | 2c0262af | bellard | switch(s->cc_op) {
|
2068 | 2c0262af | bellard | /* we optimize the cmp/jcc case */
|
2069 | 2c0262af | bellard | case CC_OP_SUBB:
|
2070 | 2c0262af | bellard | case CC_OP_SUBW:
|
2071 | 2c0262af | bellard | case CC_OP_SUBL:
|
2072 | 14ce26e7 | bellard | case CC_OP_SUBQ:
|
2073 | 2c0262af | bellard | func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op]; |
2074 | 2c0262af | bellard | break;
|
2075 | 3b46e624 | ths | |
2076 | 2c0262af | bellard | /* some jumps are easy to compute */
|
2077 | 2c0262af | bellard | case CC_OP_ADDB:
|
2078 | 2c0262af | bellard | case CC_OP_ADDW:
|
2079 | 2c0262af | bellard | case CC_OP_ADDL:
|
2080 | 14ce26e7 | bellard | case CC_OP_ADDQ:
|
2081 | 14ce26e7 | bellard | |
2082 | 2c0262af | bellard | case CC_OP_ADCB:
|
2083 | 2c0262af | bellard | case CC_OP_ADCW:
|
2084 | 2c0262af | bellard | case CC_OP_ADCL:
|
2085 | 14ce26e7 | bellard | case CC_OP_ADCQ:
|
2086 | 14ce26e7 | bellard | |
2087 | 2c0262af | bellard | case CC_OP_SBBB:
|
2088 | 2c0262af | bellard | case CC_OP_SBBW:
|
2089 | 2c0262af | bellard | case CC_OP_SBBL:
|
2090 | 14ce26e7 | bellard | case CC_OP_SBBQ:
|
2091 | 14ce26e7 | bellard | |
2092 | 2c0262af | bellard | case CC_OP_LOGICB:
|
2093 | 2c0262af | bellard | case CC_OP_LOGICW:
|
2094 | 2c0262af | bellard | case CC_OP_LOGICL:
|
2095 | 14ce26e7 | bellard | case CC_OP_LOGICQ:
|
2096 | 14ce26e7 | bellard | |
2097 | 2c0262af | bellard | case CC_OP_INCB:
|
2098 | 2c0262af | bellard | case CC_OP_INCW:
|
2099 | 2c0262af | bellard | case CC_OP_INCL:
|
2100 | 14ce26e7 | bellard | case CC_OP_INCQ:
|
2101 | 14ce26e7 | bellard | |
2102 | 2c0262af | bellard | case CC_OP_DECB:
|
2103 | 2c0262af | bellard | case CC_OP_DECW:
|
2104 | 2c0262af | bellard | case CC_OP_DECL:
|
2105 | 14ce26e7 | bellard | case CC_OP_DECQ:
|
2106 | 14ce26e7 | bellard | |
2107 | 2c0262af | bellard | case CC_OP_SHLB:
|
2108 | 2c0262af | bellard | case CC_OP_SHLW:
|
2109 | 2c0262af | bellard | case CC_OP_SHLL:
|
2110 | 14ce26e7 | bellard | case CC_OP_SHLQ:
|
2111 | 14ce26e7 | bellard | |
2112 | 2c0262af | bellard | case CC_OP_SARB:
|
2113 | 2c0262af | bellard | case CC_OP_SARW:
|
2114 | 2c0262af | bellard | case CC_OP_SARL:
|
2115 | 14ce26e7 | bellard | case CC_OP_SARQ:
|
2116 | 2c0262af | bellard | switch(jcc_op) {
|
2117 | 2c0262af | bellard | case JCC_Z:
|
2118 | 14ce26e7 | bellard | func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
|
2119 | 2c0262af | bellard | break;
|
2120 | 2c0262af | bellard | case JCC_S:
|
2121 | 14ce26e7 | bellard | func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
|
2122 | 2c0262af | bellard | break;
|
2123 | 2c0262af | bellard | default:
|
2124 | 2c0262af | bellard | func = NULL;
|
2125 | 2c0262af | bellard | break;
|
2126 | 2c0262af | bellard | } |
2127 | 2c0262af | bellard | break;
|
2128 | 2c0262af | bellard | default:
|
2129 | 2c0262af | bellard | func = NULL;
|
2130 | 2c0262af | bellard | break;
|
2131 | 2c0262af | bellard | } |
2132 | 2c0262af | bellard | |
2133 | 6e256c93 | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
2134 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2135 | 6e256c93 | bellard | s->cc_op = CC_OP_DYNAMIC; |
2136 | 6e256c93 | bellard | } |
2137 | 2c0262af | bellard | |
2138 | 2c0262af | bellard | if (!func) {
|
2139 | 2c0262af | bellard | gen_setcc_slow[jcc_op](); |
2140 | 14ce26e7 | bellard | func = gen_op_jnz_T0_label; |
2141 | 2c0262af | bellard | } |
2142 | 3b46e624 | ths | |
2143 | 14ce26e7 | bellard | if (inv) {
|
2144 | 14ce26e7 | bellard | tmp = val; |
2145 | 14ce26e7 | bellard | val = next_eip; |
2146 | 14ce26e7 | bellard | next_eip = tmp; |
2147 | 2c0262af | bellard | } |
2148 | 14ce26e7 | bellard | tb = s->tb; |
2149 | 14ce26e7 | bellard | |
2150 | 14ce26e7 | bellard | l1 = gen_new_label(); |
2151 | 14ce26e7 | bellard | func(l1); |
2152 | 14ce26e7 | bellard | |
2153 | 6e256c93 | bellard | gen_goto_tb(s, 0, next_eip);
|
2154 | 14ce26e7 | bellard | |
2155 | 14ce26e7 | bellard | gen_set_label(l1); |
2156 | 6e256c93 | bellard | gen_goto_tb(s, 1, val);
|
2157 | 14ce26e7 | bellard | |
2158 | 2c0262af | bellard | s->is_jmp = 3;
|
2159 | 2c0262af | bellard | } else {
|
2160 | 14ce26e7 | bellard | |
2161 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
2162 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2163 | 2c0262af | bellard | s->cc_op = CC_OP_DYNAMIC; |
2164 | 2c0262af | bellard | } |
2165 | 2c0262af | bellard | gen_setcc_slow[jcc_op](); |
2166 | 14ce26e7 | bellard | if (inv) {
|
2167 | 14ce26e7 | bellard | tmp = val; |
2168 | 14ce26e7 | bellard | val = next_eip; |
2169 | 14ce26e7 | bellard | next_eip = tmp; |
2170 | 2c0262af | bellard | } |
2171 | 14ce26e7 | bellard | l1 = gen_new_label(); |
2172 | 14ce26e7 | bellard | l2 = gen_new_label(); |
2173 | 14ce26e7 | bellard | gen_op_jnz_T0_label(l1); |
2174 | 14ce26e7 | bellard | gen_jmp_im(next_eip); |
2175 | 14ce26e7 | bellard | gen_op_jmp_label(l2); |
2176 | 14ce26e7 | bellard | gen_set_label(l1); |
2177 | 14ce26e7 | bellard | gen_jmp_im(val); |
2178 | 14ce26e7 | bellard | gen_set_label(l2); |
2179 | 2c0262af | bellard | gen_eob(s); |
2180 | 2c0262af | bellard | } |
2181 | 2c0262af | bellard | } |
2182 | 2c0262af | bellard | |
2183 | 2c0262af | bellard | static void gen_setcc(DisasContext *s, int b) |
2184 | 2c0262af | bellard | { |
2185 | 2c0262af | bellard | int inv, jcc_op;
|
2186 | 2c0262af | bellard | GenOpFunc *func; |
2187 | 2c0262af | bellard | |
2188 | 2c0262af | bellard | inv = b & 1;
|
2189 | 2c0262af | bellard | jcc_op = (b >> 1) & 7; |
2190 | 2c0262af | bellard | switch(s->cc_op) {
|
2191 | 2c0262af | bellard | /* we optimize the cmp/jcc case */
|
2192 | 2c0262af | bellard | case CC_OP_SUBB:
|
2193 | 2c0262af | bellard | case CC_OP_SUBW:
|
2194 | 2c0262af | bellard | case CC_OP_SUBL:
|
2195 | 14ce26e7 | bellard | case CC_OP_SUBQ:
|
2196 | 2c0262af | bellard | func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op]; |
2197 | 2c0262af | bellard | if (!func)
|
2198 | 2c0262af | bellard | goto slow_jcc;
|
2199 | 2c0262af | bellard | break;
|
2200 | 3b46e624 | ths | |
2201 | 2c0262af | bellard | /* some jumps are easy to compute */
|
2202 | 2c0262af | bellard | case CC_OP_ADDB:
|
2203 | 2c0262af | bellard | case CC_OP_ADDW:
|
2204 | 2c0262af | bellard | case CC_OP_ADDL:
|
2205 | 14ce26e7 | bellard | case CC_OP_ADDQ:
|
2206 | 14ce26e7 | bellard | |
2207 | 2c0262af | bellard | case CC_OP_LOGICB:
|
2208 | 2c0262af | bellard | case CC_OP_LOGICW:
|
2209 | 2c0262af | bellard | case CC_OP_LOGICL:
|
2210 | 14ce26e7 | bellard | case CC_OP_LOGICQ:
|
2211 | 14ce26e7 | bellard | |
2212 | 2c0262af | bellard | case CC_OP_INCB:
|
2213 | 2c0262af | bellard | case CC_OP_INCW:
|
2214 | 2c0262af | bellard | case CC_OP_INCL:
|
2215 | 14ce26e7 | bellard | case CC_OP_INCQ:
|
2216 | 14ce26e7 | bellard | |
2217 | 2c0262af | bellard | case CC_OP_DECB:
|
2218 | 2c0262af | bellard | case CC_OP_DECW:
|
2219 | 2c0262af | bellard | case CC_OP_DECL:
|
2220 | 14ce26e7 | bellard | case CC_OP_DECQ:
|
2221 | 14ce26e7 | bellard | |
2222 | 2c0262af | bellard | case CC_OP_SHLB:
|
2223 | 2c0262af | bellard | case CC_OP_SHLW:
|
2224 | 2c0262af | bellard | case CC_OP_SHLL:
|
2225 | 14ce26e7 | bellard | case CC_OP_SHLQ:
|
2226 | 2c0262af | bellard | switch(jcc_op) {
|
2227 | 2c0262af | bellard | case JCC_Z:
|
2228 | 14ce26e7 | bellard | func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
|
2229 | 2c0262af | bellard | break;
|
2230 | 2c0262af | bellard | case JCC_S:
|
2231 | 14ce26e7 | bellard | func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
|
2232 | 2c0262af | bellard | break;
|
2233 | 2c0262af | bellard | default:
|
2234 | 2c0262af | bellard | goto slow_jcc;
|
2235 | 2c0262af | bellard | } |
2236 | 2c0262af | bellard | break;
|
2237 | 2c0262af | bellard | default:
|
2238 | 2c0262af | bellard | slow_jcc:
|
2239 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2240 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2241 | 2c0262af | bellard | func = gen_setcc_slow[jcc_op]; |
2242 | 2c0262af | bellard | break;
|
2243 | 2c0262af | bellard | } |
2244 | 2c0262af | bellard | func(); |
2245 | 2c0262af | bellard | if (inv) {
|
2246 | 2c0262af | bellard | gen_op_xor_T0_1(); |
2247 | 2c0262af | bellard | } |
2248 | 2c0262af | bellard | } |
2249 | 2c0262af | bellard | |
2250 | 2c0262af | bellard | /* move T0 to seg_reg and compute if the CPU state may change. Never
|
2251 | 2c0262af | bellard | call this function with seg_reg == R_CS */
|
2252 | 14ce26e7 | bellard | static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) |
2253 | 2c0262af | bellard | { |
2254 | 3415a4dd | bellard | if (s->pe && !s->vm86) {
|
2255 | 3415a4dd | bellard | /* XXX: optimize by finding processor state dynamically */
|
2256 | 3415a4dd | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2257 | 3415a4dd | bellard | gen_op_set_cc_op(s->cc_op); |
2258 | 14ce26e7 | bellard | gen_jmp_im(cur_eip); |
2259 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
2260 | b6abf97d | bellard | tcg_gen_helper_0_2(helper_load_seg, tcg_const_i32(seg_reg), cpu_tmp2_i32); |
2261 | dc196a57 | bellard | /* abort translation because the addseg value may change or
|
2262 | dc196a57 | bellard | because ss32 may change. For R_SS, translation must always
|
2263 | dc196a57 | bellard | stop as a special handling must be done to disable hardware
|
2264 | dc196a57 | bellard | interrupts for the next instruction */
|
2265 | dc196a57 | bellard | if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
|
2266 | dc196a57 | bellard | s->is_jmp = 3;
|
2267 | 3415a4dd | bellard | } else {
|
2268 | 2c0262af | bellard | gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg])); |
2269 | dc196a57 | bellard | if (seg_reg == R_SS)
|
2270 | dc196a57 | bellard | s->is_jmp = 3;
|
2271 | 3415a4dd | bellard | } |
2272 | 2c0262af | bellard | } |
2273 | 2c0262af | bellard | |
2274 | 0573fbfc | ths | static inline int svm_is_rep(int prefixes) |
2275 | 0573fbfc | ths | { |
2276 | 0573fbfc | ths | return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); |
2277 | 0573fbfc | ths | } |
2278 | 0573fbfc | ths | |
2279 | 0573fbfc | ths | static inline int |
2280 | 0573fbfc | ths | gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, |
2281 | b8b6a50b | bellard | uint32_t type, uint64_t param) |
2282 | 0573fbfc | ths | { |
2283 | 0573fbfc | ths | if(!(s->flags & (INTERCEPT_SVM_MASK)))
|
2284 | 0573fbfc | ths | /* no SVM activated */
|
2285 | 0573fbfc | ths | return 0; |
2286 | 0573fbfc | ths | switch(type) {
|
2287 | 0573fbfc | ths | /* CRx and DRx reads/writes */
|
2288 | 0573fbfc | ths | case SVM_EXIT_READ_CR0 ... SVM_EXIT_EXCP_BASE - 1: |
2289 | 0573fbfc | ths | if (s->cc_op != CC_OP_DYNAMIC) {
|
2290 | 0573fbfc | ths | gen_op_set_cc_op(s->cc_op); |
2291 | 0573fbfc | ths | } |
2292 | 0573fbfc | ths | gen_jmp_im(pc_start - s->cs_base); |
2293 | b8b6a50b | bellard | tcg_gen_helper_0_2(helper_svm_check_intercept_param, |
2294 | b8b6a50b | bellard | tcg_const_i32(type), tcg_const_i64(param)); |
2295 | 0573fbfc | ths | /* this is a special case as we do not know if the interception occurs
|
2296 | 0573fbfc | ths | so we assume there was none */
|
2297 | 0573fbfc | ths | return 0; |
2298 | 0573fbfc | ths | case SVM_EXIT_MSR:
|
2299 | 0573fbfc | ths | if(s->flags & (1ULL << INTERCEPT_MSR_PROT)) { |
2300 | 0573fbfc | ths | if (s->cc_op != CC_OP_DYNAMIC) {
|
2301 | 0573fbfc | ths | gen_op_set_cc_op(s->cc_op); |
2302 | 0573fbfc | ths | } |
2303 | 0573fbfc | ths | gen_jmp_im(pc_start - s->cs_base); |
2304 | b8b6a50b | bellard | tcg_gen_helper_0_2(helper_svm_check_intercept_param, |
2305 | b8b6a50b | bellard | tcg_const_i32(type), tcg_const_i64(param)); |
2306 | 0573fbfc | ths | /* this is a special case as we do not know if the interception occurs
|
2307 | 0573fbfc | ths | so we assume there was none */
|
2308 | 0573fbfc | ths | return 0; |
2309 | 0573fbfc | ths | } |
2310 | 0573fbfc | ths | break;
|
2311 | 0573fbfc | ths | default:
|
2312 | 0573fbfc | ths | if(s->flags & (1ULL << ((type - SVM_EXIT_INTR) + INTERCEPT_INTR))) { |
2313 | 0573fbfc | ths | if (s->cc_op != CC_OP_DYNAMIC) {
|
2314 | 0573fbfc | ths | gen_op_set_cc_op(s->cc_op); |
2315 | 0573fbfc | ths | } |
2316 | 0573fbfc | ths | gen_jmp_im(pc_start - s->cs_base); |
2317 | b8b6a50b | bellard | tcg_gen_helper_0_2(helper_vmexit, |
2318 | b8b6a50b | bellard | tcg_const_i32(type), tcg_const_i64(param)); |
2319 | 0573fbfc | ths | /* we can optimize this one so TBs don't get longer
|
2320 | 0573fbfc | ths | than up to vmexit */
|
2321 | 0573fbfc | ths | gen_eob(s); |
2322 | 0573fbfc | ths | return 1; |
2323 | 0573fbfc | ths | } |
2324 | 0573fbfc | ths | } |
2325 | 0573fbfc | ths | return 0; |
2326 | 0573fbfc | ths | } |
2327 | 0573fbfc | ths | |
2328 | 0573fbfc | ths | static inline int |
2329 | 0573fbfc | ths | gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) |
2330 | 0573fbfc | ths | { |
2331 | 0573fbfc | ths | return gen_svm_check_intercept_param(s, pc_start, type, 0); |
2332 | 0573fbfc | ths | } |
2333 | 0573fbfc | ths | |
2334 | 4f31916f | bellard | static inline void gen_stack_update(DisasContext *s, int addend) |
2335 | 4f31916f | bellard | { |
2336 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2337 | 14ce26e7 | bellard | if (CODE64(s)) {
|
2338 | 57fec1fe | bellard | gen_op_addq_ESP_im(addend); |
2339 | 14ce26e7 | bellard | } else
|
2340 | 14ce26e7 | bellard | #endif
|
2341 | 4f31916f | bellard | if (s->ss32) {
|
2342 | 57fec1fe | bellard | gen_op_addl_ESP_im(addend); |
2343 | 4f31916f | bellard | } else {
|
2344 | 57fec1fe | bellard | gen_op_addw_ESP_im(addend); |
2345 | 4f31916f | bellard | } |
2346 | 4f31916f | bellard | } |
2347 | 4f31916f | bellard | |
2348 | 2c0262af | bellard | /* generate a push. It depends on ss32, addseg and dflag */
|
2349 | 2c0262af | bellard | static void gen_push_T0(DisasContext *s) |
2350 | 2c0262af | bellard | { |
2351 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2352 | 14ce26e7 | bellard | if (CODE64(s)) {
|
2353 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_ESP); |
2354 | 8f091a59 | bellard | if (s->dflag) {
|
2355 | 57fec1fe | bellard | gen_op_addq_A0_im(-8);
|
2356 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_QUAD + s->mem_index); |
2357 | 8f091a59 | bellard | } else {
|
2358 | 57fec1fe | bellard | gen_op_addq_A0_im(-2);
|
2359 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2360 | 8f091a59 | bellard | } |
2361 | 57fec1fe | bellard | gen_op_mov_reg_A0(2, R_ESP);
|
2362 | 5fafdf24 | ths | } else
|
2363 | 14ce26e7 | bellard | #endif
|
2364 | 14ce26e7 | bellard | { |
2365 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2366 | 14ce26e7 | bellard | if (!s->dflag)
|
2367 | 57fec1fe | bellard | gen_op_addl_A0_im(-2);
|
2368 | 14ce26e7 | bellard | else
|
2369 | 57fec1fe | bellard | gen_op_addl_A0_im(-4);
|
2370 | 14ce26e7 | bellard | if (s->ss32) {
|
2371 | 14ce26e7 | bellard | if (s->addseg) {
|
2372 | 14ce26e7 | bellard | gen_op_movl_T1_A0(); |
2373 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2374 | 14ce26e7 | bellard | } |
2375 | 14ce26e7 | bellard | } else {
|
2376 | 14ce26e7 | bellard | gen_op_andl_A0_ffff(); |
2377 | 4f31916f | bellard | gen_op_movl_T1_A0(); |
2378 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2379 | 2c0262af | bellard | } |
2380 | 57fec1fe | bellard | gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
|
2381 | 14ce26e7 | bellard | if (s->ss32 && !s->addseg)
|
2382 | 57fec1fe | bellard | gen_op_mov_reg_A0(1, R_ESP);
|
2383 | 14ce26e7 | bellard | else
|
2384 | 57fec1fe | bellard | gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
|
2385 | 2c0262af | bellard | } |
2386 | 2c0262af | bellard | } |
2387 | 2c0262af | bellard | |
2388 | 4f31916f | bellard | /* generate a push. It depends on ss32, addseg and dflag */
|
2389 | 4f31916f | bellard | /* slower version for T1, only used for call Ev */
|
2390 | 4f31916f | bellard | static void gen_push_T1(DisasContext *s) |
2391 | 2c0262af | bellard | { |
2392 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2393 | 14ce26e7 | bellard | if (CODE64(s)) {
|
2394 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_ESP); |
2395 | 8f091a59 | bellard | if (s->dflag) {
|
2396 | 57fec1fe | bellard | gen_op_addq_A0_im(-8);
|
2397 | 57fec1fe | bellard | gen_op_st_T1_A0(OT_QUAD + s->mem_index); |
2398 | 8f091a59 | bellard | } else {
|
2399 | 57fec1fe | bellard | gen_op_addq_A0_im(-2);
|
2400 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2401 | 8f091a59 | bellard | } |
2402 | 57fec1fe | bellard | gen_op_mov_reg_A0(2, R_ESP);
|
2403 | 5fafdf24 | ths | } else
|
2404 | 14ce26e7 | bellard | #endif
|
2405 | 14ce26e7 | bellard | { |
2406 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2407 | 14ce26e7 | bellard | if (!s->dflag)
|
2408 | 57fec1fe | bellard | gen_op_addl_A0_im(-2);
|
2409 | 14ce26e7 | bellard | else
|
2410 | 57fec1fe | bellard | gen_op_addl_A0_im(-4);
|
2411 | 14ce26e7 | bellard | if (s->ss32) {
|
2412 | 14ce26e7 | bellard | if (s->addseg) {
|
2413 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2414 | 14ce26e7 | bellard | } |
2415 | 14ce26e7 | bellard | } else {
|
2416 | 14ce26e7 | bellard | gen_op_andl_A0_ffff(); |
2417 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2418 | 2c0262af | bellard | } |
2419 | 57fec1fe | bellard | gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
|
2420 | 3b46e624 | ths | |
2421 | 14ce26e7 | bellard | if (s->ss32 && !s->addseg)
|
2422 | 57fec1fe | bellard | gen_op_mov_reg_A0(1, R_ESP);
|
2423 | 14ce26e7 | bellard | else
|
2424 | 14ce26e7 | bellard | gen_stack_update(s, (-2) << s->dflag);
|
2425 | 2c0262af | bellard | } |
2426 | 2c0262af | bellard | } |
2427 | 2c0262af | bellard | |
2428 | 4f31916f | bellard | /* two step pop is necessary for precise exceptions */
|
2429 | 4f31916f | bellard | static void gen_pop_T0(DisasContext *s) |
2430 | 2c0262af | bellard | { |
2431 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2432 | 14ce26e7 | bellard | if (CODE64(s)) {
|
2433 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_ESP); |
2434 | 57fec1fe | bellard | gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index); |
2435 | 5fafdf24 | ths | } else
|
2436 | 14ce26e7 | bellard | #endif
|
2437 | 14ce26e7 | bellard | { |
2438 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2439 | 14ce26e7 | bellard | if (s->ss32) {
|
2440 | 14ce26e7 | bellard | if (s->addseg)
|
2441 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2442 | 14ce26e7 | bellard | } else {
|
2443 | 14ce26e7 | bellard | gen_op_andl_A0_ffff(); |
2444 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2445 | 14ce26e7 | bellard | } |
2446 | 57fec1fe | bellard | gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
|
2447 | 2c0262af | bellard | } |
2448 | 2c0262af | bellard | } |
2449 | 2c0262af | bellard | |
2450 | 2c0262af | bellard | static void gen_pop_update(DisasContext *s) |
2451 | 2c0262af | bellard | { |
2452 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
2453 | 8f091a59 | bellard | if (CODE64(s) && s->dflag) {
|
2454 | 14ce26e7 | bellard | gen_stack_update(s, 8);
|
2455 | 14ce26e7 | bellard | } else
|
2456 | 14ce26e7 | bellard | #endif
|
2457 | 14ce26e7 | bellard | { |
2458 | 14ce26e7 | bellard | gen_stack_update(s, 2 << s->dflag);
|
2459 | 14ce26e7 | bellard | } |
2460 | 2c0262af | bellard | } |
2461 | 2c0262af | bellard | |
2462 | 2c0262af | bellard | static void gen_stack_A0(DisasContext *s) |
2463 | 2c0262af | bellard | { |
2464 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2465 | 2c0262af | bellard | if (!s->ss32)
|
2466 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
2467 | 2c0262af | bellard | gen_op_movl_T1_A0(); |
2468 | 2c0262af | bellard | if (s->addseg)
|
2469 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2470 | 2c0262af | bellard | } |
2471 | 2c0262af | bellard | |
2472 | 2c0262af | bellard | /* NOTE: wrap around in 16 bit not fully handled */
|
2473 | 2c0262af | bellard | static void gen_pusha(DisasContext *s) |
2474 | 2c0262af | bellard | { |
2475 | 2c0262af | bellard | int i;
|
2476 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2477 | 2c0262af | bellard | gen_op_addl_A0_im(-16 << s->dflag);
|
2478 | 2c0262af | bellard | if (!s->ss32)
|
2479 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
2480 | 2c0262af | bellard | gen_op_movl_T1_A0(); |
2481 | 2c0262af | bellard | if (s->addseg)
|
2482 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2483 | 2c0262af | bellard | for(i = 0;i < 8; i++) { |
2484 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, 7 - i); |
2485 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index); |
2486 | 2c0262af | bellard | gen_op_addl_A0_im(2 << s->dflag);
|
2487 | 2c0262af | bellard | } |
2488 | 57fec1fe | bellard | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2489 | 2c0262af | bellard | } |
2490 | 2c0262af | bellard | |
2491 | 2c0262af | bellard | /* NOTE: wrap around in 16 bit not fully handled */
|
2492 | 2c0262af | bellard | static void gen_popa(DisasContext *s) |
2493 | 2c0262af | bellard | { |
2494 | 2c0262af | bellard | int i;
|
2495 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2496 | 2c0262af | bellard | if (!s->ss32)
|
2497 | 2c0262af | bellard | gen_op_andl_A0_ffff(); |
2498 | 2c0262af | bellard | gen_op_movl_T1_A0(); |
2499 | 2c0262af | bellard | gen_op_addl_T1_im(16 << s->dflag);
|
2500 | 2c0262af | bellard | if (s->addseg)
|
2501 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2502 | 2c0262af | bellard | for(i = 0;i < 8; i++) { |
2503 | 2c0262af | bellard | /* ESP is not reloaded */
|
2504 | 2c0262af | bellard | if (i != 3) { |
2505 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index); |
2506 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
|
2507 | 2c0262af | bellard | } |
2508 | 2c0262af | bellard | gen_op_addl_A0_im(2 << s->dflag);
|
2509 | 2c0262af | bellard | } |
2510 | 57fec1fe | bellard | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2511 | 2c0262af | bellard | } |
2512 | 2c0262af | bellard | |
2513 | 2c0262af | bellard | static void gen_enter(DisasContext *s, int esp_addend, int level) |
2514 | 2c0262af | bellard | { |
2515 | 61a8c4ec | bellard | int ot, opsize;
|
2516 | 2c0262af | bellard | |
2517 | 2c0262af | bellard | level &= 0x1f;
|
2518 | 8f091a59 | bellard | #ifdef TARGET_X86_64
|
2519 | 8f091a59 | bellard | if (CODE64(s)) {
|
2520 | 8f091a59 | bellard | ot = s->dflag ? OT_QUAD : OT_WORD; |
2521 | 8f091a59 | bellard | opsize = 1 << ot;
|
2522 | 3b46e624 | ths | |
2523 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2524 | 8f091a59 | bellard | gen_op_addq_A0_im(-opsize); |
2525 | 8f091a59 | bellard | gen_op_movl_T1_A0(); |
2526 | 8f091a59 | bellard | |
2527 | 8f091a59 | bellard | /* push bp */
|
2528 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
|
2529 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
2530 | 8f091a59 | bellard | if (level) {
|
2531 | b5b38f61 | bellard | /* XXX: must save state */
|
2532 | b8b6a50b | bellard | tcg_gen_helper_0_3(helper_enter64_level, |
2533 | b5b38f61 | bellard | tcg_const_i32(level), |
2534 | b8b6a50b | bellard | tcg_const_i32((ot == OT_QUAD)), |
2535 | b8b6a50b | bellard | cpu_T[1]);
|
2536 | 8f091a59 | bellard | } |
2537 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, R_EBP); |
2538 | 8f091a59 | bellard | gen_op_addl_T1_im( -esp_addend + (-opsize * level) ); |
2539 | 57fec1fe | bellard | gen_op_mov_reg_T1(OT_QUAD, R_ESP); |
2540 | 5fafdf24 | ths | } else
|
2541 | 8f091a59 | bellard | #endif
|
2542 | 8f091a59 | bellard | { |
2543 | 8f091a59 | bellard | ot = s->dflag + OT_WORD; |
2544 | 8f091a59 | bellard | opsize = 2 << s->dflag;
|
2545 | 3b46e624 | ths | |
2546 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_ESP); |
2547 | 8f091a59 | bellard | gen_op_addl_A0_im(-opsize); |
2548 | 8f091a59 | bellard | if (!s->ss32)
|
2549 | 8f091a59 | bellard | gen_op_andl_A0_ffff(); |
2550 | 8f091a59 | bellard | gen_op_movl_T1_A0(); |
2551 | 8f091a59 | bellard | if (s->addseg)
|
2552 | 57fec1fe | bellard | gen_op_addl_A0_seg(R_SS); |
2553 | 8f091a59 | bellard | /* push bp */
|
2554 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
|
2555 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
2556 | 8f091a59 | bellard | if (level) {
|
2557 | b5b38f61 | bellard | /* XXX: must save state */
|
2558 | b8b6a50b | bellard | tcg_gen_helper_0_3(helper_enter_level, |
2559 | b5b38f61 | bellard | tcg_const_i32(level), |
2560 | b8b6a50b | bellard | tcg_const_i32(s->dflag), |
2561 | b8b6a50b | bellard | cpu_T[1]);
|
2562 | 8f091a59 | bellard | } |
2563 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, R_EBP); |
2564 | 8f091a59 | bellard | gen_op_addl_T1_im( -esp_addend + (-opsize * level) ); |
2565 | 57fec1fe | bellard | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2566 | 2c0262af | bellard | } |
2567 | 2c0262af | bellard | } |
2568 | 2c0262af | bellard | |
2569 | 14ce26e7 | bellard | static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) |
2570 | 2c0262af | bellard | { |
2571 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2572 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2573 | 14ce26e7 | bellard | gen_jmp_im(cur_eip); |
2574 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_raise_exception, tcg_const_i32(trapno)); |
2575 | 2c0262af | bellard | s->is_jmp = 3;
|
2576 | 2c0262af | bellard | } |
2577 | 2c0262af | bellard | |
2578 | 2c0262af | bellard | /* an interrupt is different from an exception because of the
|
2579 | 7f75ffd3 | blueswir1 | privilege checks */
|
2580 | 5fafdf24 | ths | static void gen_interrupt(DisasContext *s, int intno, |
2581 | 14ce26e7 | bellard | target_ulong cur_eip, target_ulong next_eip) |
2582 | 2c0262af | bellard | { |
2583 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2584 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2585 | 14ce26e7 | bellard | gen_jmp_im(cur_eip); |
2586 | b5b38f61 | bellard | tcg_gen_helper_0_2(helper_raise_interrupt, |
2587 | b5b38f61 | bellard | tcg_const_i32(intno), |
2588 | b5b38f61 | bellard | tcg_const_i32(next_eip - cur_eip)); |
2589 | 2c0262af | bellard | s->is_jmp = 3;
|
2590 | 2c0262af | bellard | } |
2591 | 2c0262af | bellard | |
2592 | 14ce26e7 | bellard | static void gen_debug(DisasContext *s, target_ulong cur_eip) |
2593 | 2c0262af | bellard | { |
2594 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2595 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2596 | 14ce26e7 | bellard | gen_jmp_im(cur_eip); |
2597 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_debug); |
2598 | 2c0262af | bellard | s->is_jmp = 3;
|
2599 | 2c0262af | bellard | } |
2600 | 2c0262af | bellard | |
2601 | 2c0262af | bellard | /* generate a generic end of block. Trace exception is also generated
|
2602 | 2c0262af | bellard | if needed */
|
2603 | 2c0262af | bellard | static void gen_eob(DisasContext *s) |
2604 | 2c0262af | bellard | { |
2605 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
2606 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2607 | a2cc3b24 | bellard | if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
|
2608 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_reset_inhibit_irq); |
2609 | a2cc3b24 | bellard | } |
2610 | 34865134 | bellard | if (s->singlestep_enabled) {
|
2611 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_debug); |
2612 | 34865134 | bellard | } else if (s->tf) { |
2613 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_single_step); |
2614 | 2c0262af | bellard | } else {
|
2615 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2616 | 2c0262af | bellard | } |
2617 | 2c0262af | bellard | s->is_jmp = 3;
|
2618 | 2c0262af | bellard | } |
2619 | 2c0262af | bellard | |
2620 | 2c0262af | bellard | /* generate a jump to eip. No segment change must happen before as a
|
2621 | 2c0262af | bellard | direct call to the next block may occur */
|
2622 | 14ce26e7 | bellard | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) |
2623 | 2c0262af | bellard | { |
2624 | 2c0262af | bellard | if (s->jmp_opt) {
|
2625 | 6e256c93 | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
2626 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
2627 | 6e256c93 | bellard | s->cc_op = CC_OP_DYNAMIC; |
2628 | 6e256c93 | bellard | } |
2629 | 6e256c93 | bellard | gen_goto_tb(s, tb_num, eip); |
2630 | 2c0262af | bellard | s->is_jmp = 3;
|
2631 | 2c0262af | bellard | } else {
|
2632 | 14ce26e7 | bellard | gen_jmp_im(eip); |
2633 | 2c0262af | bellard | gen_eob(s); |
2634 | 2c0262af | bellard | } |
2635 | 2c0262af | bellard | } |
2636 | 2c0262af | bellard | |
2637 | 14ce26e7 | bellard | static void gen_jmp(DisasContext *s, target_ulong eip) |
2638 | 14ce26e7 | bellard | { |
2639 | 14ce26e7 | bellard | gen_jmp_tb(s, eip, 0);
|
2640 | 14ce26e7 | bellard | } |
2641 | 14ce26e7 | bellard | |
2642 | 8686c490 | bellard | static inline void gen_ldq_env_A0(int idx, int offset) |
2643 | 8686c490 | bellard | { |
2644 | 8686c490 | bellard | int mem_index = (idx >> 2) - 1; |
2645 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2646 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); |
2647 | 8686c490 | bellard | } |
2648 | 664e0f19 | bellard | |
2649 | 8686c490 | bellard | static inline void gen_stq_env_A0(int idx, int offset) |
2650 | 8686c490 | bellard | { |
2651 | 8686c490 | bellard | int mem_index = (idx >> 2) - 1; |
2652 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); |
2653 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); |
2654 | 8686c490 | bellard | } |
2655 | 664e0f19 | bellard | |
2656 | 8686c490 | bellard | static inline void gen_ldo_env_A0(int idx, int offset) |
2657 | 8686c490 | bellard | { |
2658 | 8686c490 | bellard | int mem_index = (idx >> 2) - 1; |
2659 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2660 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
|
2661 | 8686c490 | bellard | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
|
2662 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index); |
2663 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
|
2664 | 8686c490 | bellard | } |
2665 | 14ce26e7 | bellard | |
2666 | 8686c490 | bellard | static inline void gen_sto_env_A0(int idx, int offset) |
2667 | 8686c490 | bellard | { |
2668 | 8686c490 | bellard | int mem_index = (idx >> 2) - 1; |
2669 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
|
2670 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); |
2671 | 8686c490 | bellard | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
|
2672 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
|
2673 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index); |
2674 | 8686c490 | bellard | } |
2675 | 14ce26e7 | bellard | |
2676 | 5af45186 | bellard | static inline void gen_op_movo(int d_offset, int s_offset) |
2677 | 5af45186 | bellard | { |
2678 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2679 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); |
2680 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
|
2681 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
|
2682 | 5af45186 | bellard | } |
2683 | 5af45186 | bellard | |
2684 | 5af45186 | bellard | static inline void gen_op_movq(int d_offset, int s_offset) |
2685 | 5af45186 | bellard | { |
2686 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2687 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); |
2688 | 5af45186 | bellard | } |
2689 | 5af45186 | bellard | |
2690 | 5af45186 | bellard | static inline void gen_op_movl(int d_offset, int s_offset) |
2691 | 5af45186 | bellard | { |
2692 | b6abf97d | bellard | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); |
2693 | b6abf97d | bellard | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); |
2694 | 5af45186 | bellard | } |
2695 | 5af45186 | bellard | |
2696 | 5af45186 | bellard | static inline void gen_op_movq_env_0(int d_offset) |
2697 | 5af45186 | bellard | { |
2698 | b6abf97d | bellard | tcg_gen_movi_i64(cpu_tmp1_i64, 0);
|
2699 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); |
2700 | 5af45186 | bellard | } |
2701 | 664e0f19 | bellard | |
2702 | 5af45186 | bellard | #define SSE_SPECIAL ((void *)1) |
2703 | 5af45186 | bellard | #define SSE_DUMMY ((void *)2) |
2704 | 664e0f19 | bellard | |
2705 | 5af45186 | bellard | #define MMX_OP2(x) { helper_ ## x ## _mmx, helper_ ## x ## _xmm } |
2706 | 5af45186 | bellard | #define SSE_FOP(x) { helper_ ## x ## ps, helper_ ## x ## pd, \ |
2707 | 5af45186 | bellard | helper_ ## x ## ss, helper_ ## x ## sd, } |
2708 | 5af45186 | bellard | |
2709 | 5af45186 | bellard | static void *sse_op_table1[256][4] = { |
2710 | a35f3ec7 | aurel32 | /* 3DNow! extensions */
|
2711 | a35f3ec7 | aurel32 | [0x0e] = { SSE_DUMMY }, /* femms */ |
2712 | a35f3ec7 | aurel32 | [0x0f] = { SSE_DUMMY }, /* pf... */ |
2713 | 664e0f19 | bellard | /* pure SSE operations */
|
2714 | 664e0f19 | bellard | [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ |
2715 | 664e0f19 | bellard | [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ |
2716 | 465e9838 | bellard | [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ |
2717 | 664e0f19 | bellard | [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ |
2718 | 5af45186 | bellard | [0x14] = { helper_punpckldq_xmm, helper_punpcklqdq_xmm },
|
2719 | 5af45186 | bellard | [0x15] = { helper_punpckhdq_xmm, helper_punpckhqdq_xmm },
|
2720 | 664e0f19 | bellard | [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ |
2721 | 664e0f19 | bellard | [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ |
2722 | 664e0f19 | bellard | |
2723 | 664e0f19 | bellard | [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ |
2724 | 664e0f19 | bellard | [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ |
2725 | 664e0f19 | bellard | [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ |
2726 | 664e0f19 | bellard | [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */ |
2727 | 664e0f19 | bellard | [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ |
2728 | 664e0f19 | bellard | [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ |
2729 | 5af45186 | bellard | [0x2e] = { helper_ucomiss, helper_ucomisd },
|
2730 | 5af45186 | bellard | [0x2f] = { helper_comiss, helper_comisd },
|
2731 | 664e0f19 | bellard | [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ |
2732 | 664e0f19 | bellard | [0x51] = SSE_FOP(sqrt),
|
2733 | 5af45186 | bellard | [0x52] = { helper_rsqrtps, NULL, helper_rsqrtss, NULL }, |
2734 | 5af45186 | bellard | [0x53] = { helper_rcpps, NULL, helper_rcpss, NULL }, |
2735 | 5af45186 | bellard | [0x54] = { helper_pand_xmm, helper_pand_xmm }, /* andps, andpd */ |
2736 | 5af45186 | bellard | [0x55] = { helper_pandn_xmm, helper_pandn_xmm }, /* andnps, andnpd */ |
2737 | 5af45186 | bellard | [0x56] = { helper_por_xmm, helper_por_xmm }, /* orps, orpd */ |
2738 | 5af45186 | bellard | [0x57] = { helper_pxor_xmm, helper_pxor_xmm }, /* xorps, xorpd */ |
2739 | 664e0f19 | bellard | [0x58] = SSE_FOP(add),
|
2740 | 664e0f19 | bellard | [0x59] = SSE_FOP(mul),
|
2741 | 5af45186 | bellard | [0x5a] = { helper_cvtps2pd, helper_cvtpd2ps,
|
2742 | 5af45186 | bellard | helper_cvtss2sd, helper_cvtsd2ss }, |
2743 | 5af45186 | bellard | [0x5b] = { helper_cvtdq2ps, helper_cvtps2dq, helper_cvttps2dq },
|
2744 | 664e0f19 | bellard | [0x5c] = SSE_FOP(sub),
|
2745 | 664e0f19 | bellard | [0x5d] = SSE_FOP(min),
|
2746 | 664e0f19 | bellard | [0x5e] = SSE_FOP(div),
|
2747 | 664e0f19 | bellard | [0x5f] = SSE_FOP(max),
|
2748 | 664e0f19 | bellard | |
2749 | 664e0f19 | bellard | [0xc2] = SSE_FOP(cmpeq),
|
2750 | 5af45186 | bellard | [0xc6] = { helper_shufps, helper_shufpd },
|
2751 | 664e0f19 | bellard | |
2752 | 664e0f19 | bellard | /* MMX ops and their SSE extensions */
|
2753 | 664e0f19 | bellard | [0x60] = MMX_OP2(punpcklbw),
|
2754 | 664e0f19 | bellard | [0x61] = MMX_OP2(punpcklwd),
|
2755 | 664e0f19 | bellard | [0x62] = MMX_OP2(punpckldq),
|
2756 | 664e0f19 | bellard | [0x63] = MMX_OP2(packsswb),
|
2757 | 664e0f19 | bellard | [0x64] = MMX_OP2(pcmpgtb),
|
2758 | 664e0f19 | bellard | [0x65] = MMX_OP2(pcmpgtw),
|
2759 | 664e0f19 | bellard | [0x66] = MMX_OP2(pcmpgtl),
|
2760 | 664e0f19 | bellard | [0x67] = MMX_OP2(packuswb),
|
2761 | 664e0f19 | bellard | [0x68] = MMX_OP2(punpckhbw),
|
2762 | 664e0f19 | bellard | [0x69] = MMX_OP2(punpckhwd),
|
2763 | 664e0f19 | bellard | [0x6a] = MMX_OP2(punpckhdq),
|
2764 | 664e0f19 | bellard | [0x6b] = MMX_OP2(packssdw),
|
2765 | 5af45186 | bellard | [0x6c] = { NULL, helper_punpcklqdq_xmm }, |
2766 | 5af45186 | bellard | [0x6d] = { NULL, helper_punpckhqdq_xmm }, |
2767 | 664e0f19 | bellard | [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ |
2768 | 664e0f19 | bellard | [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ |
2769 | 5af45186 | bellard | [0x70] = { helper_pshufw_mmx,
|
2770 | 5af45186 | bellard | helper_pshufd_xmm, |
2771 | 5af45186 | bellard | helper_pshufhw_xmm, |
2772 | 5af45186 | bellard | helper_pshuflw_xmm }, |
2773 | 664e0f19 | bellard | [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ |
2774 | 664e0f19 | bellard | [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ |
2775 | 664e0f19 | bellard | [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ |
2776 | 664e0f19 | bellard | [0x74] = MMX_OP2(pcmpeqb),
|
2777 | 664e0f19 | bellard | [0x75] = MMX_OP2(pcmpeqw),
|
2778 | 664e0f19 | bellard | [0x76] = MMX_OP2(pcmpeql),
|
2779 | a35f3ec7 | aurel32 | [0x77] = { SSE_DUMMY }, /* emms */ |
2780 | 5af45186 | bellard | [0x7c] = { NULL, helper_haddpd, NULL, helper_haddps }, |
2781 | 5af45186 | bellard | [0x7d] = { NULL, helper_hsubpd, NULL, helper_hsubps }, |
2782 | 664e0f19 | bellard | [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ |
2783 | 664e0f19 | bellard | [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ |
2784 | 664e0f19 | bellard | [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ |
2785 | 664e0f19 | bellard | [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ |
2786 | 5af45186 | bellard | [0xd0] = { NULL, helper_addsubpd, NULL, helper_addsubps }, |
2787 | 664e0f19 | bellard | [0xd1] = MMX_OP2(psrlw),
|
2788 | 664e0f19 | bellard | [0xd2] = MMX_OP2(psrld),
|
2789 | 664e0f19 | bellard | [0xd3] = MMX_OP2(psrlq),
|
2790 | 664e0f19 | bellard | [0xd4] = MMX_OP2(paddq),
|
2791 | 664e0f19 | bellard | [0xd5] = MMX_OP2(pmullw),
|
2792 | 664e0f19 | bellard | [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, |
2793 | 664e0f19 | bellard | [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ |
2794 | 664e0f19 | bellard | [0xd8] = MMX_OP2(psubusb),
|
2795 | 664e0f19 | bellard | [0xd9] = MMX_OP2(psubusw),
|
2796 | 664e0f19 | bellard | [0xda] = MMX_OP2(pminub),
|
2797 | 664e0f19 | bellard | [0xdb] = MMX_OP2(pand),
|
2798 | 664e0f19 | bellard | [0xdc] = MMX_OP2(paddusb),
|
2799 | 664e0f19 | bellard | [0xdd] = MMX_OP2(paddusw),
|
2800 | 664e0f19 | bellard | [0xde] = MMX_OP2(pmaxub),
|
2801 | 664e0f19 | bellard | [0xdf] = MMX_OP2(pandn),
|
2802 | 664e0f19 | bellard | [0xe0] = MMX_OP2(pavgb),
|
2803 | 664e0f19 | bellard | [0xe1] = MMX_OP2(psraw),
|
2804 | 664e0f19 | bellard | [0xe2] = MMX_OP2(psrad),
|
2805 | 664e0f19 | bellard | [0xe3] = MMX_OP2(pavgw),
|
2806 | 664e0f19 | bellard | [0xe4] = MMX_OP2(pmulhuw),
|
2807 | 664e0f19 | bellard | [0xe5] = MMX_OP2(pmulhw),
|
2808 | 5af45186 | bellard | [0xe6] = { NULL, helper_cvttpd2dq, helper_cvtdq2pd, helper_cvtpd2dq }, |
2809 | 664e0f19 | bellard | [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ |
2810 | 664e0f19 | bellard | [0xe8] = MMX_OP2(psubsb),
|
2811 | 664e0f19 | bellard | [0xe9] = MMX_OP2(psubsw),
|
2812 | 664e0f19 | bellard | [0xea] = MMX_OP2(pminsw),
|
2813 | 664e0f19 | bellard | [0xeb] = MMX_OP2(por),
|
2814 | 664e0f19 | bellard | [0xec] = MMX_OP2(paddsb),
|
2815 | 664e0f19 | bellard | [0xed] = MMX_OP2(paddsw),
|
2816 | 664e0f19 | bellard | [0xee] = MMX_OP2(pmaxsw),
|
2817 | 664e0f19 | bellard | [0xef] = MMX_OP2(pxor),
|
2818 | 465e9838 | bellard | [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ |
2819 | 664e0f19 | bellard | [0xf1] = MMX_OP2(psllw),
|
2820 | 664e0f19 | bellard | [0xf2] = MMX_OP2(pslld),
|
2821 | 664e0f19 | bellard | [0xf3] = MMX_OP2(psllq),
|
2822 | 664e0f19 | bellard | [0xf4] = MMX_OP2(pmuludq),
|
2823 | 664e0f19 | bellard | [0xf5] = MMX_OP2(pmaddwd),
|
2824 | 664e0f19 | bellard | [0xf6] = MMX_OP2(psadbw),
|
2825 | 664e0f19 | bellard | [0xf7] = MMX_OP2(maskmov),
|
2826 | 664e0f19 | bellard | [0xf8] = MMX_OP2(psubb),
|
2827 | 664e0f19 | bellard | [0xf9] = MMX_OP2(psubw),
|
2828 | 664e0f19 | bellard | [0xfa] = MMX_OP2(psubl),
|
2829 | 664e0f19 | bellard | [0xfb] = MMX_OP2(psubq),
|
2830 | 664e0f19 | bellard | [0xfc] = MMX_OP2(paddb),
|
2831 | 664e0f19 | bellard | [0xfd] = MMX_OP2(paddw),
|
2832 | 664e0f19 | bellard | [0xfe] = MMX_OP2(paddl),
|
2833 | 664e0f19 | bellard | }; |
2834 | 664e0f19 | bellard | |
2835 | 5af45186 | bellard | static void *sse_op_table2[3 * 8][2] = { |
2836 | 664e0f19 | bellard | [0 + 2] = MMX_OP2(psrlw), |
2837 | 664e0f19 | bellard | [0 + 4] = MMX_OP2(psraw), |
2838 | 664e0f19 | bellard | [0 + 6] = MMX_OP2(psllw), |
2839 | 664e0f19 | bellard | [8 + 2] = MMX_OP2(psrld), |
2840 | 664e0f19 | bellard | [8 + 4] = MMX_OP2(psrad), |
2841 | 664e0f19 | bellard | [8 + 6] = MMX_OP2(pslld), |
2842 | 664e0f19 | bellard | [16 + 2] = MMX_OP2(psrlq), |
2843 | 5af45186 | bellard | [16 + 3] = { NULL, helper_psrldq_xmm }, |
2844 | 664e0f19 | bellard | [16 + 6] = MMX_OP2(psllq), |
2845 | 5af45186 | bellard | [16 + 7] = { NULL, helper_pslldq_xmm }, |
2846 | 664e0f19 | bellard | }; |
2847 | 664e0f19 | bellard | |
2848 | 5af45186 | bellard | static void *sse_op_table3[4 * 3] = { |
2849 | 5af45186 | bellard | helper_cvtsi2ss, |
2850 | 5af45186 | bellard | helper_cvtsi2sd, |
2851 | 5af45186 | bellard | X86_64_ONLY(helper_cvtsq2ss), |
2852 | 5af45186 | bellard | X86_64_ONLY(helper_cvtsq2sd), |
2853 | 5af45186 | bellard | |
2854 | 5af45186 | bellard | helper_cvttss2si, |
2855 | 5af45186 | bellard | helper_cvttsd2si, |
2856 | 5af45186 | bellard | X86_64_ONLY(helper_cvttss2sq), |
2857 | 5af45186 | bellard | X86_64_ONLY(helper_cvttsd2sq), |
2858 | 5af45186 | bellard | |
2859 | 5af45186 | bellard | helper_cvtss2si, |
2860 | 5af45186 | bellard | helper_cvtsd2si, |
2861 | 5af45186 | bellard | X86_64_ONLY(helper_cvtss2sq), |
2862 | 5af45186 | bellard | X86_64_ONLY(helper_cvtsd2sq), |
2863 | 664e0f19 | bellard | }; |
2864 | 3b46e624 | ths | |
2865 | 5af45186 | bellard | static void *sse_op_table4[8][4] = { |
2866 | 664e0f19 | bellard | SSE_FOP(cmpeq), |
2867 | 664e0f19 | bellard | SSE_FOP(cmplt), |
2868 | 664e0f19 | bellard | SSE_FOP(cmple), |
2869 | 664e0f19 | bellard | SSE_FOP(cmpunord), |
2870 | 664e0f19 | bellard | SSE_FOP(cmpneq), |
2871 | 664e0f19 | bellard | SSE_FOP(cmpnlt), |
2872 | 664e0f19 | bellard | SSE_FOP(cmpnle), |
2873 | 664e0f19 | bellard | SSE_FOP(cmpord), |
2874 | 664e0f19 | bellard | }; |
2875 | 3b46e624 | ths | |
2876 | 5af45186 | bellard | static void *sse_op_table5[256] = { |
2877 | 5af45186 | bellard | [0x0c] = helper_pi2fw,
|
2878 | 5af45186 | bellard | [0x0d] = helper_pi2fd,
|
2879 | 5af45186 | bellard | [0x1c] = helper_pf2iw,
|
2880 | 5af45186 | bellard | [0x1d] = helper_pf2id,
|
2881 | 5af45186 | bellard | [0x8a] = helper_pfnacc,
|
2882 | 5af45186 | bellard | [0x8e] = helper_pfpnacc,
|
2883 | 5af45186 | bellard | [0x90] = helper_pfcmpge,
|
2884 | 5af45186 | bellard | [0x94] = helper_pfmin,
|
2885 | 5af45186 | bellard | [0x96] = helper_pfrcp,
|
2886 | 5af45186 | bellard | [0x97] = helper_pfrsqrt,
|
2887 | 5af45186 | bellard | [0x9a] = helper_pfsub,
|
2888 | 5af45186 | bellard | [0x9e] = helper_pfadd,
|
2889 | 5af45186 | bellard | [0xa0] = helper_pfcmpgt,
|
2890 | 5af45186 | bellard | [0xa4] = helper_pfmax,
|
2891 | 5af45186 | bellard | [0xa6] = helper_movq, /* pfrcpit1; no need to actually increase precision */ |
2892 | 5af45186 | bellard | [0xa7] = helper_movq, /* pfrsqit1 */ |
2893 | 5af45186 | bellard | [0xaa] = helper_pfsubr,
|
2894 | 5af45186 | bellard | [0xae] = helper_pfacc,
|
2895 | 5af45186 | bellard | [0xb0] = helper_pfcmpeq,
|
2896 | 5af45186 | bellard | [0xb4] = helper_pfmul,
|
2897 | 5af45186 | bellard | [0xb6] = helper_movq, /* pfrcpit2 */ |
2898 | 5af45186 | bellard | [0xb7] = helper_pmulhrw_mmx,
|
2899 | 5af45186 | bellard | [0xbb] = helper_pswapd,
|
2900 | 5af45186 | bellard | [0xbf] = helper_pavgb_mmx /* pavgusb */ |
2901 | a35f3ec7 | aurel32 | }; |
2902 | a35f3ec7 | aurel32 | |
2903 | 664e0f19 | bellard | static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) |
2904 | 664e0f19 | bellard | { |
2905 | 664e0f19 | bellard | int b1, op1_offset, op2_offset, is_xmm, val, ot;
|
2906 | 664e0f19 | bellard | int modrm, mod, rm, reg, reg_addr, offset_addr;
|
2907 | 5af45186 | bellard | void *sse_op2;
|
2908 | 664e0f19 | bellard | |
2909 | 664e0f19 | bellard | b &= 0xff;
|
2910 | 5fafdf24 | ths | if (s->prefix & PREFIX_DATA)
|
2911 | 664e0f19 | bellard | b1 = 1;
|
2912 | 5fafdf24 | ths | else if (s->prefix & PREFIX_REPZ) |
2913 | 664e0f19 | bellard | b1 = 2;
|
2914 | 5fafdf24 | ths | else if (s->prefix & PREFIX_REPNZ) |
2915 | 664e0f19 | bellard | b1 = 3;
|
2916 | 664e0f19 | bellard | else
|
2917 | 664e0f19 | bellard | b1 = 0;
|
2918 | 664e0f19 | bellard | sse_op2 = sse_op_table1[b][b1]; |
2919 | 5fafdf24 | ths | if (!sse_op2)
|
2920 | 664e0f19 | bellard | goto illegal_op;
|
2921 | a35f3ec7 | aurel32 | if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { |
2922 | 664e0f19 | bellard | is_xmm = 1;
|
2923 | 664e0f19 | bellard | } else {
|
2924 | 664e0f19 | bellard | if (b1 == 0) { |
2925 | 664e0f19 | bellard | /* MMX case */
|
2926 | 664e0f19 | bellard | is_xmm = 0;
|
2927 | 664e0f19 | bellard | } else {
|
2928 | 664e0f19 | bellard | is_xmm = 1;
|
2929 | 664e0f19 | bellard | } |
2930 | 664e0f19 | bellard | } |
2931 | 664e0f19 | bellard | /* simple MMX/SSE operation */
|
2932 | 664e0f19 | bellard | if (s->flags & HF_TS_MASK) {
|
2933 | 664e0f19 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
2934 | 664e0f19 | bellard | return;
|
2935 | 664e0f19 | bellard | } |
2936 | 664e0f19 | bellard | if (s->flags & HF_EM_MASK) {
|
2937 | 664e0f19 | bellard | illegal_op:
|
2938 | 664e0f19 | bellard | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); |
2939 | 664e0f19 | bellard | return;
|
2940 | 664e0f19 | bellard | } |
2941 | 664e0f19 | bellard | if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
|
2942 | 664e0f19 | bellard | goto illegal_op;
|
2943 | e771edab | aurel32 | if (b == 0x0e) { |
2944 | e771edab | aurel32 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
|
2945 | e771edab | aurel32 | goto illegal_op;
|
2946 | e771edab | aurel32 | /* femms */
|
2947 | 5af45186 | bellard | tcg_gen_helper_0_0(helper_emms); |
2948 | e771edab | aurel32 | return;
|
2949 | e771edab | aurel32 | } |
2950 | e771edab | aurel32 | if (b == 0x77) { |
2951 | e771edab | aurel32 | /* emms */
|
2952 | 5af45186 | bellard | tcg_gen_helper_0_0(helper_emms); |
2953 | 664e0f19 | bellard | return;
|
2954 | 664e0f19 | bellard | } |
2955 | 664e0f19 | bellard | /* prepare MMX state (XXX: optimize by storing fptt and fptags in
|
2956 | 664e0f19 | bellard | the static cpu state) */
|
2957 | 664e0f19 | bellard | if (!is_xmm) {
|
2958 | 5af45186 | bellard | tcg_gen_helper_0_0(helper_enter_mmx); |
2959 | 664e0f19 | bellard | } |
2960 | 664e0f19 | bellard | |
2961 | 664e0f19 | bellard | modrm = ldub_code(s->pc++); |
2962 | 664e0f19 | bellard | reg = ((modrm >> 3) & 7); |
2963 | 664e0f19 | bellard | if (is_xmm)
|
2964 | 664e0f19 | bellard | reg |= rex_r; |
2965 | 664e0f19 | bellard | mod = (modrm >> 6) & 3; |
2966 | 664e0f19 | bellard | if (sse_op2 == SSE_SPECIAL) {
|
2967 | 664e0f19 | bellard | b |= (b1 << 8);
|
2968 | 664e0f19 | bellard | switch(b) {
|
2969 | 664e0f19 | bellard | case 0x0e7: /* movntq */ |
2970 | 5fafdf24 | ths | if (mod == 3) |
2971 | 664e0f19 | bellard | goto illegal_op;
|
2972 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
2973 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
2974 | 664e0f19 | bellard | break;
|
2975 | 664e0f19 | bellard | case 0x1e7: /* movntdq */ |
2976 | 664e0f19 | bellard | case 0x02b: /* movntps */ |
2977 | 664e0f19 | bellard | case 0x12b: /* movntps */ |
2978 | 465e9838 | bellard | case 0x3f0: /* lddqu */ |
2979 | 465e9838 | bellard | if (mod == 3) |
2980 | 664e0f19 | bellard | goto illegal_op;
|
2981 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
2982 | 8686c490 | bellard | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
2983 | 664e0f19 | bellard | break;
|
2984 | 664e0f19 | bellard | case 0x6e: /* movd mm, ea */ |
2985 | dabd98dd | bellard | #ifdef TARGET_X86_64
|
2986 | dabd98dd | bellard | if (s->dflag == 2) { |
2987 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
|
2988 | 5af45186 | bellard | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
|
2989 | 5fafdf24 | ths | } else
|
2990 | dabd98dd | bellard | #endif
|
2991 | dabd98dd | bellard | { |
2992 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
|
2993 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
2994 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[reg].mmx)); |
2995 | 5af45186 | bellard | tcg_gen_helper_0_2(helper_movl_mm_T0_mmx, cpu_ptr0, cpu_T[0]);
|
2996 | dabd98dd | bellard | } |
2997 | 664e0f19 | bellard | break;
|
2998 | 664e0f19 | bellard | case 0x16e: /* movd xmm, ea */ |
2999 | dabd98dd | bellard | #ifdef TARGET_X86_64
|
3000 | dabd98dd | bellard | if (s->dflag == 2) { |
3001 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
|
3002 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3003 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[reg])); |
3004 | 5af45186 | bellard | tcg_gen_helper_0_2(helper_movq_mm_T0_xmm, cpu_ptr0, cpu_T[0]);
|
3005 | 5fafdf24 | ths | } else
|
3006 | dabd98dd | bellard | #endif
|
3007 | dabd98dd | bellard | { |
3008 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
|
3009 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3010 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[reg])); |
3011 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
3012 | b6abf97d | bellard | tcg_gen_helper_0_2(helper_movl_mm_T0_xmm, cpu_ptr0, cpu_tmp2_i32); |
3013 | dabd98dd | bellard | } |
3014 | 664e0f19 | bellard | break;
|
3015 | 664e0f19 | bellard | case 0x6f: /* movq mm, ea */ |
3016 | 664e0f19 | bellard | if (mod != 3) { |
3017 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3018 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
3019 | 664e0f19 | bellard | } else {
|
3020 | 664e0f19 | bellard | rm = (modrm & 7);
|
3021 | b6abf97d | bellard | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
3022 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[rm].mmx)); |
3023 | b6abf97d | bellard | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
3024 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[reg].mmx)); |
3025 | 664e0f19 | bellard | } |
3026 | 664e0f19 | bellard | break;
|
3027 | 664e0f19 | bellard | case 0x010: /* movups */ |
3028 | 664e0f19 | bellard | case 0x110: /* movupd */ |
3029 | 664e0f19 | bellard | case 0x028: /* movaps */ |
3030 | 664e0f19 | bellard | case 0x128: /* movapd */ |
3031 | 664e0f19 | bellard | case 0x16f: /* movdqa xmm, ea */ |
3032 | 664e0f19 | bellard | case 0x26f: /* movdqu xmm, ea */ |
3033 | 664e0f19 | bellard | if (mod != 3) { |
3034 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3035 | 8686c490 | bellard | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3036 | 664e0f19 | bellard | } else {
|
3037 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3038 | 664e0f19 | bellard | gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), |
3039 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm])); |
3040 | 664e0f19 | bellard | } |
3041 | 664e0f19 | bellard | break;
|
3042 | 664e0f19 | bellard | case 0x210: /* movss xmm, ea */ |
3043 | 664e0f19 | bellard | if (mod != 3) { |
3044 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3045 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
3046 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
3047 | 664e0f19 | bellard | gen_op_movl_T0_0(); |
3048 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
|
3049 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
|
3050 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
|
3051 | 664e0f19 | bellard | } else {
|
3052 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3053 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
|
3054 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
|
3055 | 664e0f19 | bellard | } |
3056 | 664e0f19 | bellard | break;
|
3057 | 664e0f19 | bellard | case 0x310: /* movsd xmm, ea */ |
3058 | 664e0f19 | bellard | if (mod != 3) { |
3059 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3060 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3061 | 664e0f19 | bellard | gen_op_movl_T0_0(); |
3062 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
|
3063 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
|
3064 | 664e0f19 | bellard | } else {
|
3065 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3066 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
3067 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
3068 | 664e0f19 | bellard | } |
3069 | 664e0f19 | bellard | break;
|
3070 | 664e0f19 | bellard | case 0x012: /* movlps */ |
3071 | 664e0f19 | bellard | case 0x112: /* movlpd */ |
3072 | 664e0f19 | bellard | if (mod != 3) { |
3073 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3074 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3075 | 664e0f19 | bellard | } else {
|
3076 | 664e0f19 | bellard | /* movhlps */
|
3077 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3078 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
3079 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
|
3080 | 664e0f19 | bellard | } |
3081 | 664e0f19 | bellard | break;
|
3082 | 465e9838 | bellard | case 0x212: /* movsldup */ |
3083 | 465e9838 | bellard | if (mod != 3) { |
3084 | 465e9838 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3085 | 8686c490 | bellard | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3086 | 465e9838 | bellard | } else {
|
3087 | 465e9838 | bellard | rm = (modrm & 7) | REX_B(s);
|
3088 | 465e9838 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
|
3089 | 465e9838 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
|
3090 | 465e9838 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
|
3091 | 465e9838 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
|
3092 | 465e9838 | bellard | } |
3093 | 465e9838 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
|
3094 | 465e9838 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
3095 | 465e9838 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
|
3096 | 465e9838 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
|
3097 | 465e9838 | bellard | break;
|
3098 | 465e9838 | bellard | case 0x312: /* movddup */ |
3099 | 465e9838 | bellard | if (mod != 3) { |
3100 | 465e9838 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3101 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3102 | 465e9838 | bellard | } else {
|
3103 | 465e9838 | bellard | rm = (modrm & 7) | REX_B(s);
|
3104 | 465e9838 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
3105 | 465e9838 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
3106 | 465e9838 | bellard | } |
3107 | 465e9838 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
|
3108 | ba6526df | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3109 | 465e9838 | bellard | break;
|
3110 | 664e0f19 | bellard | case 0x016: /* movhps */ |
3111 | 664e0f19 | bellard | case 0x116: /* movhpd */ |
3112 | 664e0f19 | bellard | if (mod != 3) { |
3113 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3114 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
|
3115 | 664e0f19 | bellard | } else {
|
3116 | 664e0f19 | bellard | /* movlhps */
|
3117 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3118 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
|
3119 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
3120 | 664e0f19 | bellard | } |
3121 | 664e0f19 | bellard | break;
|
3122 | 664e0f19 | bellard | case 0x216: /* movshdup */ |
3123 | 664e0f19 | bellard | if (mod != 3) { |
3124 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3125 | 8686c490 | bellard | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3126 | 664e0f19 | bellard | } else {
|
3127 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3128 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
|
3129 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
|
3130 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
|
3131 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
|
3132 | 664e0f19 | bellard | } |
3133 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
|
3134 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
|
3135 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
|
3136 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
|
3137 | 664e0f19 | bellard | break;
|
3138 | 664e0f19 | bellard | case 0x7e: /* movd ea, mm */ |
3139 | dabd98dd | bellard | #ifdef TARGET_X86_64
|
3140 | dabd98dd | bellard | if (s->dflag == 2) { |
3141 | 5af45186 | bellard | tcg_gen_ld_i64(cpu_T[0], cpu_env,
|
3142 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[reg].mmx)); |
3143 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
|
3144 | 5fafdf24 | ths | } else
|
3145 | dabd98dd | bellard | #endif
|
3146 | dabd98dd | bellard | { |
3147 | 5af45186 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
|
3148 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
|
3149 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
|
3150 | dabd98dd | bellard | } |
3151 | 664e0f19 | bellard | break;
|
3152 | 664e0f19 | bellard | case 0x17e: /* movd ea, xmm */ |
3153 | dabd98dd | bellard | #ifdef TARGET_X86_64
|
3154 | dabd98dd | bellard | if (s->dflag == 2) { |
3155 | 5af45186 | bellard | tcg_gen_ld_i64(cpu_T[0], cpu_env,
|
3156 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3157 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
|
3158 | 5fafdf24 | ths | } else
|
3159 | dabd98dd | bellard | #endif
|
3160 | dabd98dd | bellard | { |
3161 | 5af45186 | bellard | tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
|
3162 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
3163 | dabd98dd | bellard | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
|
3164 | dabd98dd | bellard | } |
3165 | 664e0f19 | bellard | break;
|
3166 | 664e0f19 | bellard | case 0x27e: /* movq xmm, ea */ |
3167 | 664e0f19 | bellard | if (mod != 3) { |
3168 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3169 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3170 | 664e0f19 | bellard | } else {
|
3171 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3172 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
3173 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
3174 | 664e0f19 | bellard | } |
3175 | 664e0f19 | bellard | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
|
3176 | 664e0f19 | bellard | break;
|
3177 | 664e0f19 | bellard | case 0x7f: /* movq ea, mm */ |
3178 | 664e0f19 | bellard | if (mod != 3) { |
3179 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3180 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
3181 | 664e0f19 | bellard | } else {
|
3182 | 664e0f19 | bellard | rm = (modrm & 7);
|
3183 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), |
3184 | 664e0f19 | bellard | offsetof(CPUX86State,fpregs[reg].mmx)); |
3185 | 664e0f19 | bellard | } |
3186 | 664e0f19 | bellard | break;
|
3187 | 664e0f19 | bellard | case 0x011: /* movups */ |
3188 | 664e0f19 | bellard | case 0x111: /* movupd */ |
3189 | 664e0f19 | bellard | case 0x029: /* movaps */ |
3190 | 664e0f19 | bellard | case 0x129: /* movapd */ |
3191 | 664e0f19 | bellard | case 0x17f: /* movdqa ea, xmm */ |
3192 | 664e0f19 | bellard | case 0x27f: /* movdqu ea, xmm */ |
3193 | 664e0f19 | bellard | if (mod != 3) { |
3194 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3195 | 8686c490 | bellard | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3196 | 664e0f19 | bellard | } else {
|
3197 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3198 | 664e0f19 | bellard | gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), |
3199 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg])); |
3200 | 664e0f19 | bellard | } |
3201 | 664e0f19 | bellard | break;
|
3202 | 664e0f19 | bellard | case 0x211: /* movss ea, xmm */ |
3203 | 664e0f19 | bellard | if (mod != 3) { |
3204 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3205 | 664e0f19 | bellard | gen_op_movl_T0_env(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
3206 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
3207 | 664e0f19 | bellard | } else {
|
3208 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3209 | 664e0f19 | bellard | gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
|
3210 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
3211 | 664e0f19 | bellard | } |
3212 | 664e0f19 | bellard | break;
|
3213 | 664e0f19 | bellard | case 0x311: /* movsd ea, xmm */ |
3214 | 664e0f19 | bellard | if (mod != 3) { |
3215 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3216 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3217 | 664e0f19 | bellard | } else {
|
3218 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3219 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
|
3220 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3221 | 664e0f19 | bellard | } |
3222 | 664e0f19 | bellard | break;
|
3223 | 664e0f19 | bellard | case 0x013: /* movlps */ |
3224 | 664e0f19 | bellard | case 0x113: /* movlpd */ |
3225 | 664e0f19 | bellard | if (mod != 3) { |
3226 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3227 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3228 | 664e0f19 | bellard | } else {
|
3229 | 664e0f19 | bellard | goto illegal_op;
|
3230 | 664e0f19 | bellard | } |
3231 | 664e0f19 | bellard | break;
|
3232 | 664e0f19 | bellard | case 0x017: /* movhps */ |
3233 | 664e0f19 | bellard | case 0x117: /* movhpd */ |
3234 | 664e0f19 | bellard | if (mod != 3) { |
3235 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3236 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
|
3237 | 664e0f19 | bellard | } else {
|
3238 | 664e0f19 | bellard | goto illegal_op;
|
3239 | 664e0f19 | bellard | } |
3240 | 664e0f19 | bellard | break;
|
3241 | 664e0f19 | bellard | case 0x71: /* shift mm, im */ |
3242 | 664e0f19 | bellard | case 0x72: |
3243 | 664e0f19 | bellard | case 0x73: |
3244 | 664e0f19 | bellard | case 0x171: /* shift xmm, im */ |
3245 | 664e0f19 | bellard | case 0x172: |
3246 | 664e0f19 | bellard | case 0x173: |
3247 | 664e0f19 | bellard | val = ldub_code(s->pc++); |
3248 | 664e0f19 | bellard | if (is_xmm) {
|
3249 | 664e0f19 | bellard | gen_op_movl_T0_im(val); |
3250 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
|
3251 | 664e0f19 | bellard | gen_op_movl_T0_0(); |
3252 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(1)));
|
3253 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,xmm_t0); |
3254 | 664e0f19 | bellard | } else {
|
3255 | 664e0f19 | bellard | gen_op_movl_T0_im(val); |
3256 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(0)));
|
3257 | 664e0f19 | bellard | gen_op_movl_T0_0(); |
3258 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(1)));
|
3259 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,mmx_t0); |
3260 | 664e0f19 | bellard | } |
3261 | 664e0f19 | bellard | sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1]; |
3262 | 664e0f19 | bellard | if (!sse_op2)
|
3263 | 664e0f19 | bellard | goto illegal_op;
|
3264 | 664e0f19 | bellard | if (is_xmm) {
|
3265 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3266 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); |
3267 | 664e0f19 | bellard | } else {
|
3268 | 664e0f19 | bellard | rm = (modrm & 7);
|
3269 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); |
3270 | 664e0f19 | bellard | } |
3271 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3272 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); |
3273 | 5af45186 | bellard | tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1); |
3274 | 664e0f19 | bellard | break;
|
3275 | 664e0f19 | bellard | case 0x050: /* movmskps */ |
3276 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3277 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3278 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[rm])); |
3279 | b6abf97d | bellard | tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2_i32, cpu_ptr0); |
3280 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
3281 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, reg); |
3282 | 664e0f19 | bellard | break;
|
3283 | 664e0f19 | bellard | case 0x150: /* movmskpd */ |
3284 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3285 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3286 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[rm])); |
3287 | b6abf97d | bellard | tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2_i32, cpu_ptr0); |
3288 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
3289 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, reg); |
3290 | 664e0f19 | bellard | break;
|
3291 | 664e0f19 | bellard | case 0x02a: /* cvtpi2ps */ |
3292 | 664e0f19 | bellard | case 0x12a: /* cvtpi2pd */ |
3293 | 5af45186 | bellard | tcg_gen_helper_0_0(helper_enter_mmx); |
3294 | 664e0f19 | bellard | if (mod != 3) { |
3295 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3296 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,mmx_t0); |
3297 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, op2_offset); |
3298 | 664e0f19 | bellard | } else {
|
3299 | 664e0f19 | bellard | rm = (modrm & 7);
|
3300 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); |
3301 | 664e0f19 | bellard | } |
3302 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
3303 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3304 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3305 | 664e0f19 | bellard | switch(b >> 8) { |
3306 | 664e0f19 | bellard | case 0x0: |
3307 | 5af45186 | bellard | tcg_gen_helper_0_2(helper_cvtpi2ps, cpu_ptr0, cpu_ptr1); |
3308 | 664e0f19 | bellard | break;
|
3309 | 664e0f19 | bellard | default:
|
3310 | 664e0f19 | bellard | case 0x1: |
3311 | 5af45186 | bellard | tcg_gen_helper_0_2(helper_cvtpi2pd, cpu_ptr0, cpu_ptr1); |
3312 | 664e0f19 | bellard | break;
|
3313 | 664e0f19 | bellard | } |
3314 | 664e0f19 | bellard | break;
|
3315 | 664e0f19 | bellard | case 0x22a: /* cvtsi2ss */ |
3316 | 664e0f19 | bellard | case 0x32a: /* cvtsi2sd */ |
3317 | 664e0f19 | bellard | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
|
3318 | 664e0f19 | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
3319 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
3320 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3321 | 5af45186 | bellard | sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)]; |
3322 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
3323 | b6abf97d | bellard | tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_tmp2_i32); |
3324 | 664e0f19 | bellard | break;
|
3325 | 664e0f19 | bellard | case 0x02c: /* cvttps2pi */ |
3326 | 664e0f19 | bellard | case 0x12c: /* cvttpd2pi */ |
3327 | 664e0f19 | bellard | case 0x02d: /* cvtps2pi */ |
3328 | 664e0f19 | bellard | case 0x12d: /* cvtpd2pi */ |
3329 | 5af45186 | bellard | tcg_gen_helper_0_0(helper_enter_mmx); |
3330 | 664e0f19 | bellard | if (mod != 3) { |
3331 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3332 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,xmm_t0); |
3333 | 8686c490 | bellard | gen_ldo_env_A0(s->mem_index, op2_offset); |
3334 | 664e0f19 | bellard | } else {
|
3335 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3336 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); |
3337 | 664e0f19 | bellard | } |
3338 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
|
3339 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3340 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3341 | 664e0f19 | bellard | switch(b) {
|
3342 | 664e0f19 | bellard | case 0x02c: |
3343 | 5af45186 | bellard | tcg_gen_helper_0_2(helper_cvttps2pi, cpu_ptr0, cpu_ptr1); |
3344 | 664e0f19 | bellard | break;
|
3345 | 664e0f19 | bellard | case 0x12c: |
3346 | 5af45186 | bellard | tcg_gen_helper_0_2(helper_cvttpd2pi, cpu_ptr0, cpu_ptr1); |
3347 | 664e0f19 | bellard | break;
|
3348 | 664e0f19 | bellard | case 0x02d: |
3349 | 5af45186 | bellard | tcg_gen_helper_0_2(helper_cvtps2pi, cpu_ptr0, cpu_ptr1); |
3350 | 664e0f19 | bellard | break;
|
3351 | 664e0f19 | bellard | case 0x12d: |
3352 | 5af45186 | bellard | tcg_gen_helper_0_2(helper_cvtpd2pi, cpu_ptr0, cpu_ptr1); |
3353 | 664e0f19 | bellard | break;
|
3354 | 664e0f19 | bellard | } |
3355 | 664e0f19 | bellard | break;
|
3356 | 664e0f19 | bellard | case 0x22c: /* cvttss2si */ |
3357 | 664e0f19 | bellard | case 0x32c: /* cvttsd2si */ |
3358 | 664e0f19 | bellard | case 0x22d: /* cvtss2si */ |
3359 | 664e0f19 | bellard | case 0x32d: /* cvtsd2si */ |
3360 | 664e0f19 | bellard | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
|
3361 | 31313213 | bellard | if (mod != 3) { |
3362 | 31313213 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3363 | 31313213 | bellard | if ((b >> 8) & 1) { |
3364 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
|
3365 | 31313213 | bellard | } else {
|
3366 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
3367 | 31313213 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
|
3368 | 31313213 | bellard | } |
3369 | 31313213 | bellard | op2_offset = offsetof(CPUX86State,xmm_t0); |
3370 | 31313213 | bellard | } else {
|
3371 | 31313213 | bellard | rm = (modrm & 7) | REX_B(s);
|
3372 | 31313213 | bellard | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); |
3373 | 31313213 | bellard | } |
3374 | 5af45186 | bellard | sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 + |
3375 | 5af45186 | bellard | (b & 1) * 4]; |
3376 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3377 | 5af45186 | bellard | if (ot == OT_LONG) {
|
3378 | b6abf97d | bellard | tcg_gen_helper_1_1(sse_op2, cpu_tmp2_i32, cpu_ptr0); |
3379 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
3380 | 5af45186 | bellard | } else {
|
3381 | 5af45186 | bellard | tcg_gen_helper_1_1(sse_op2, cpu_T[0], cpu_ptr0);
|
3382 | 5af45186 | bellard | } |
3383 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
3384 | 664e0f19 | bellard | break;
|
3385 | 664e0f19 | bellard | case 0xc4: /* pinsrw */ |
3386 | 5fafdf24 | ths | case 0x1c4: |
3387 | d1e42c5c | bellard | s->rip_offset = 1;
|
3388 | 664e0f19 | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
3389 | 664e0f19 | bellard | val = ldub_code(s->pc++); |
3390 | 664e0f19 | bellard | if (b1) {
|
3391 | 664e0f19 | bellard | val &= 7;
|
3392 | 5af45186 | bellard | tcg_gen_st16_tl(cpu_T[0], cpu_env,
|
3393 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); |
3394 | 664e0f19 | bellard | } else {
|
3395 | 664e0f19 | bellard | val &= 3;
|
3396 | 5af45186 | bellard | tcg_gen_st16_tl(cpu_T[0], cpu_env,
|
3397 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); |
3398 | 664e0f19 | bellard | } |
3399 | 664e0f19 | bellard | break;
|
3400 | 664e0f19 | bellard | case 0xc5: /* pextrw */ |
3401 | 5fafdf24 | ths | case 0x1c5: |
3402 | 664e0f19 | bellard | if (mod != 3) |
3403 | 664e0f19 | bellard | goto illegal_op;
|
3404 | 664e0f19 | bellard | val = ldub_code(s->pc++); |
3405 | 664e0f19 | bellard | if (b1) {
|
3406 | 664e0f19 | bellard | val &= 7;
|
3407 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3408 | 5af45186 | bellard | tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
|
3409 | 5af45186 | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); |
3410 | 664e0f19 | bellard | } else {
|
3411 | 664e0f19 | bellard | val &= 3;
|
3412 | 664e0f19 | bellard | rm = (modrm & 7);
|
3413 | 5af45186 | bellard | tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
|
3414 | 5af45186 | bellard | offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); |
3415 | 664e0f19 | bellard | } |
3416 | 664e0f19 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
3417 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, reg); |
3418 | 664e0f19 | bellard | break;
|
3419 | 664e0f19 | bellard | case 0x1d6: /* movq ea, xmm */ |
3420 | 664e0f19 | bellard | if (mod != 3) { |
3421 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3422 | 8686c490 | bellard | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3423 | 664e0f19 | bellard | } else {
|
3424 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3425 | 664e0f19 | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
|
3426 | 664e0f19 | bellard | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
3427 | 664e0f19 | bellard | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
|
3428 | 664e0f19 | bellard | } |
3429 | 664e0f19 | bellard | break;
|
3430 | 664e0f19 | bellard | case 0x2d6: /* movq2dq */ |
3431 | 5af45186 | bellard | tcg_gen_helper_0_0(helper_enter_mmx); |
3432 | 480c1cdb | bellard | rm = (modrm & 7);
|
3433 | 480c1cdb | bellard | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
3434 | 480c1cdb | bellard | offsetof(CPUX86State,fpregs[rm].mmx)); |
3435 | 480c1cdb | bellard | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
|
3436 | 664e0f19 | bellard | break;
|
3437 | 664e0f19 | bellard | case 0x3d6: /* movdq2q */ |
3438 | 5af45186 | bellard | tcg_gen_helper_0_0(helper_enter_mmx); |
3439 | 480c1cdb | bellard | rm = (modrm & 7) | REX_B(s);
|
3440 | 480c1cdb | bellard | gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
|
3441 | 480c1cdb | bellard | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
3442 | 664e0f19 | bellard | break;
|
3443 | 664e0f19 | bellard | case 0xd7: /* pmovmskb */ |
3444 | 664e0f19 | bellard | case 0x1d7: |
3445 | 664e0f19 | bellard | if (mod != 3) |
3446 | 664e0f19 | bellard | goto illegal_op;
|
3447 | 664e0f19 | bellard | if (b1) {
|
3448 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3449 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
3450 | b6abf97d | bellard | tcg_gen_helper_1_1(helper_pmovmskb_xmm, cpu_tmp2_i32, cpu_ptr0); |
3451 | 664e0f19 | bellard | } else {
|
3452 | 664e0f19 | bellard | rm = (modrm & 7);
|
3453 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
3454 | b6abf97d | bellard | tcg_gen_helper_1_1(helper_pmovmskb_mmx, cpu_tmp2_i32, cpu_ptr0); |
3455 | 664e0f19 | bellard | } |
3456 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
3457 | 664e0f19 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
3458 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, reg); |
3459 | 664e0f19 | bellard | break;
|
3460 | 664e0f19 | bellard | default:
|
3461 | 664e0f19 | bellard | goto illegal_op;
|
3462 | 664e0f19 | bellard | } |
3463 | 664e0f19 | bellard | } else {
|
3464 | 664e0f19 | bellard | /* generic MMX or SSE operation */
|
3465 | d1e42c5c | bellard | switch(b) {
|
3466 | d1e42c5c | bellard | case 0x70: /* pshufx insn */ |
3467 | d1e42c5c | bellard | case 0xc6: /* pshufx insn */ |
3468 | d1e42c5c | bellard | case 0xc2: /* compare insns */ |
3469 | d1e42c5c | bellard | s->rip_offset = 1;
|
3470 | d1e42c5c | bellard | break;
|
3471 | d1e42c5c | bellard | default:
|
3472 | d1e42c5c | bellard | break;
|
3473 | 664e0f19 | bellard | } |
3474 | 664e0f19 | bellard | if (is_xmm) {
|
3475 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
3476 | 664e0f19 | bellard | if (mod != 3) { |
3477 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3478 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,xmm_t0); |
3479 | 480c1cdb | bellard | if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || |
3480 | 664e0f19 | bellard | b == 0xc2)) {
|
3481 | 664e0f19 | bellard | /* specific case for SSE single instructions */
|
3482 | 664e0f19 | bellard | if (b1 == 2) { |
3483 | 664e0f19 | bellard | /* 32 bit access */
|
3484 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
3485 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
|
3486 | 664e0f19 | bellard | } else {
|
3487 | 664e0f19 | bellard | /* 64 bit access */
|
3488 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
|
3489 | 664e0f19 | bellard | } |
3490 | 664e0f19 | bellard | } else {
|
3491 | 8686c490 | bellard | gen_ldo_env_A0(s->mem_index, op2_offset); |
3492 | 664e0f19 | bellard | } |
3493 | 664e0f19 | bellard | } else {
|
3494 | 664e0f19 | bellard | rm = (modrm & 7) | REX_B(s);
|
3495 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); |
3496 | 664e0f19 | bellard | } |
3497 | 664e0f19 | bellard | } else {
|
3498 | 664e0f19 | bellard | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); |
3499 | 664e0f19 | bellard | if (mod != 3) { |
3500 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3501 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,mmx_t0); |
3502 | 8686c490 | bellard | gen_ldq_env_A0(s->mem_index, op2_offset); |
3503 | 664e0f19 | bellard | } else {
|
3504 | 664e0f19 | bellard | rm = (modrm & 7);
|
3505 | 664e0f19 | bellard | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); |
3506 | 664e0f19 | bellard | } |
3507 | 664e0f19 | bellard | } |
3508 | 664e0f19 | bellard | switch(b) {
|
3509 | a35f3ec7 | aurel32 | case 0x0f: /* 3DNow! data insns */ |
3510 | e771edab | aurel32 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
|
3511 | e771edab | aurel32 | goto illegal_op;
|
3512 | a35f3ec7 | aurel32 | val = ldub_code(s->pc++); |
3513 | a35f3ec7 | aurel32 | sse_op2 = sse_op_table5[val]; |
3514 | a35f3ec7 | aurel32 | if (!sse_op2)
|
3515 | a35f3ec7 | aurel32 | goto illegal_op;
|
3516 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3517 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3518 | 5af45186 | bellard | tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1); |
3519 | a35f3ec7 | aurel32 | break;
|
3520 | 664e0f19 | bellard | case 0x70: /* pshufx insn */ |
3521 | 664e0f19 | bellard | case 0xc6: /* pshufx insn */ |
3522 | 664e0f19 | bellard | val = ldub_code(s->pc++); |
3523 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3524 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3525 | 5af45186 | bellard | tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
3526 | 664e0f19 | bellard | break;
|
3527 | 664e0f19 | bellard | case 0xc2: |
3528 | 664e0f19 | bellard | /* compare insns */
|
3529 | 664e0f19 | bellard | val = ldub_code(s->pc++); |
3530 | 664e0f19 | bellard | if (val >= 8) |
3531 | 664e0f19 | bellard | goto illegal_op;
|
3532 | 664e0f19 | bellard | sse_op2 = sse_op_table4[val][b1]; |
3533 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3534 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3535 | 5af45186 | bellard | tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1); |
3536 | 664e0f19 | bellard | break;
|
3537 | b8b6a50b | bellard | case 0xf7: |
3538 | b8b6a50b | bellard | /* maskmov : we must prepare A0 */
|
3539 | b8b6a50b | bellard | if (mod != 3) |
3540 | b8b6a50b | bellard | goto illegal_op;
|
3541 | b8b6a50b | bellard | #ifdef TARGET_X86_64
|
3542 | b8b6a50b | bellard | if (s->aflag == 2) { |
3543 | b8b6a50b | bellard | gen_op_movq_A0_reg(R_EDI); |
3544 | b8b6a50b | bellard | } else
|
3545 | b8b6a50b | bellard | #endif
|
3546 | b8b6a50b | bellard | { |
3547 | b8b6a50b | bellard | gen_op_movl_A0_reg(R_EDI); |
3548 | b8b6a50b | bellard | if (s->aflag == 0) |
3549 | b8b6a50b | bellard | gen_op_andl_A0_ffff(); |
3550 | b8b6a50b | bellard | } |
3551 | b8b6a50b | bellard | gen_add_A0_ds_seg(s); |
3552 | b8b6a50b | bellard | |
3553 | b8b6a50b | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3554 | b8b6a50b | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3555 | b8b6a50b | bellard | tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, cpu_A0); |
3556 | b8b6a50b | bellard | break;
|
3557 | 664e0f19 | bellard | default:
|
3558 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3559 | 5af45186 | bellard | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); |
3560 | 5af45186 | bellard | tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1); |
3561 | 664e0f19 | bellard | break;
|
3562 | 664e0f19 | bellard | } |
3563 | 664e0f19 | bellard | if (b == 0x2e || b == 0x2f) { |
3564 | 5af45186 | bellard | /* just to keep the EFLAGS optimization correct */
|
3565 | 5af45186 | bellard | gen_op_com_dummy(); |
3566 | 664e0f19 | bellard | s->cc_op = CC_OP_EFLAGS; |
3567 | 664e0f19 | bellard | } |
3568 | 664e0f19 | bellard | } |
3569 | 664e0f19 | bellard | } |
3570 | 664e0f19 | bellard | |
3571 | 2c0262af | bellard | /* convert one instruction. s->is_jmp is set if the translation must
|
3572 | 2c0262af | bellard | be stopped. Return the next pc value */
|
3573 | 14ce26e7 | bellard | static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
|
3574 | 2c0262af | bellard | { |
3575 | 2c0262af | bellard | int b, prefixes, aflag, dflag;
|
3576 | 2c0262af | bellard | int shift, ot;
|
3577 | 2c0262af | bellard | int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
|
3578 | 14ce26e7 | bellard | target_ulong next_eip, tval; |
3579 | 14ce26e7 | bellard | int rex_w, rex_r;
|
3580 | 2c0262af | bellard | |
3581 | 2c0262af | bellard | s->pc = pc_start; |
3582 | 2c0262af | bellard | prefixes = 0;
|
3583 | 2c0262af | bellard | aflag = s->code32; |
3584 | 2c0262af | bellard | dflag = s->code32; |
3585 | 2c0262af | bellard | s->override = -1;
|
3586 | 14ce26e7 | bellard | rex_w = -1;
|
3587 | 14ce26e7 | bellard | rex_r = 0;
|
3588 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
3589 | 14ce26e7 | bellard | s->rex_x = 0;
|
3590 | 14ce26e7 | bellard | s->rex_b = 0;
|
3591 | 5fafdf24 | ths | x86_64_hregs = 0;
|
3592 | 14ce26e7 | bellard | #endif
|
3593 | 14ce26e7 | bellard | s->rip_offset = 0; /* for relative ip address */ |
3594 | 2c0262af | bellard | next_byte:
|
3595 | 61382a50 | bellard | b = ldub_code(s->pc); |
3596 | 2c0262af | bellard | s->pc++; |
3597 | 2c0262af | bellard | /* check prefixes */
|
3598 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
3599 | 14ce26e7 | bellard | if (CODE64(s)) {
|
3600 | 14ce26e7 | bellard | switch (b) {
|
3601 | 14ce26e7 | bellard | case 0xf3: |
3602 | 14ce26e7 | bellard | prefixes |= PREFIX_REPZ; |
3603 | 14ce26e7 | bellard | goto next_byte;
|
3604 | 14ce26e7 | bellard | case 0xf2: |
3605 | 14ce26e7 | bellard | prefixes |= PREFIX_REPNZ; |
3606 | 14ce26e7 | bellard | goto next_byte;
|
3607 | 14ce26e7 | bellard | case 0xf0: |
3608 | 14ce26e7 | bellard | prefixes |= PREFIX_LOCK; |
3609 | 14ce26e7 | bellard | goto next_byte;
|
3610 | 14ce26e7 | bellard | case 0x2e: |
3611 | 14ce26e7 | bellard | s->override = R_CS; |
3612 | 14ce26e7 | bellard | goto next_byte;
|
3613 | 14ce26e7 | bellard | case 0x36: |
3614 | 14ce26e7 | bellard | s->override = R_SS; |
3615 | 14ce26e7 | bellard | goto next_byte;
|
3616 | 14ce26e7 | bellard | case 0x3e: |
3617 | 14ce26e7 | bellard | s->override = R_DS; |
3618 | 14ce26e7 | bellard | goto next_byte;
|
3619 | 14ce26e7 | bellard | case 0x26: |
3620 | 14ce26e7 | bellard | s->override = R_ES; |
3621 | 14ce26e7 | bellard | goto next_byte;
|
3622 | 14ce26e7 | bellard | case 0x64: |
3623 | 14ce26e7 | bellard | s->override = R_FS; |
3624 | 14ce26e7 | bellard | goto next_byte;
|
3625 | 14ce26e7 | bellard | case 0x65: |
3626 | 14ce26e7 | bellard | s->override = R_GS; |
3627 | 14ce26e7 | bellard | goto next_byte;
|
3628 | 14ce26e7 | bellard | case 0x66: |
3629 | 14ce26e7 | bellard | prefixes |= PREFIX_DATA; |
3630 | 14ce26e7 | bellard | goto next_byte;
|
3631 | 14ce26e7 | bellard | case 0x67: |
3632 | 14ce26e7 | bellard | prefixes |= PREFIX_ADR; |
3633 | 14ce26e7 | bellard | goto next_byte;
|
3634 | 14ce26e7 | bellard | case 0x40 ... 0x4f: |
3635 | 14ce26e7 | bellard | /* REX prefix */
|
3636 | 14ce26e7 | bellard | rex_w = (b >> 3) & 1; |
3637 | 14ce26e7 | bellard | rex_r = (b & 0x4) << 1; |
3638 | 14ce26e7 | bellard | s->rex_x = (b & 0x2) << 2; |
3639 | 14ce26e7 | bellard | REX_B(s) = (b & 0x1) << 3; |
3640 | 14ce26e7 | bellard | x86_64_hregs = 1; /* select uniform byte register addressing */ |
3641 | 14ce26e7 | bellard | goto next_byte;
|
3642 | 14ce26e7 | bellard | } |
3643 | 14ce26e7 | bellard | if (rex_w == 1) { |
3644 | 14ce26e7 | bellard | /* 0x66 is ignored if rex.w is set */
|
3645 | 14ce26e7 | bellard | dflag = 2;
|
3646 | 14ce26e7 | bellard | } else {
|
3647 | 14ce26e7 | bellard | if (prefixes & PREFIX_DATA)
|
3648 | 14ce26e7 | bellard | dflag ^= 1;
|
3649 | 14ce26e7 | bellard | } |
3650 | 14ce26e7 | bellard | if (!(prefixes & PREFIX_ADR))
|
3651 | 14ce26e7 | bellard | aflag = 2;
|
3652 | 5fafdf24 | ths | } else
|
3653 | 14ce26e7 | bellard | #endif
|
3654 | 14ce26e7 | bellard | { |
3655 | 14ce26e7 | bellard | switch (b) {
|
3656 | 14ce26e7 | bellard | case 0xf3: |
3657 | 14ce26e7 | bellard | prefixes |= PREFIX_REPZ; |
3658 | 14ce26e7 | bellard | goto next_byte;
|
3659 | 14ce26e7 | bellard | case 0xf2: |
3660 | 14ce26e7 | bellard | prefixes |= PREFIX_REPNZ; |
3661 | 14ce26e7 | bellard | goto next_byte;
|
3662 | 14ce26e7 | bellard | case 0xf0: |
3663 | 14ce26e7 | bellard | prefixes |= PREFIX_LOCK; |
3664 | 14ce26e7 | bellard | goto next_byte;
|
3665 | 14ce26e7 | bellard | case 0x2e: |
3666 | 14ce26e7 | bellard | s->override = R_CS; |
3667 | 14ce26e7 | bellard | goto next_byte;
|
3668 | 14ce26e7 | bellard | case 0x36: |
3669 | 14ce26e7 | bellard | s->override = R_SS; |
3670 | 14ce26e7 | bellard | goto next_byte;
|
3671 | 14ce26e7 | bellard | case 0x3e: |
3672 | 14ce26e7 | bellard | s->override = R_DS; |
3673 | 14ce26e7 | bellard | goto next_byte;
|
3674 | 14ce26e7 | bellard | case 0x26: |
3675 | 14ce26e7 | bellard | s->override = R_ES; |
3676 | 14ce26e7 | bellard | goto next_byte;
|
3677 | 14ce26e7 | bellard | case 0x64: |
3678 | 14ce26e7 | bellard | s->override = R_FS; |
3679 | 14ce26e7 | bellard | goto next_byte;
|
3680 | 14ce26e7 | bellard | case 0x65: |
3681 | 14ce26e7 | bellard | s->override = R_GS; |
3682 | 14ce26e7 | bellard | goto next_byte;
|
3683 | 14ce26e7 | bellard | case 0x66: |
3684 | 14ce26e7 | bellard | prefixes |= PREFIX_DATA; |
3685 | 14ce26e7 | bellard | goto next_byte;
|
3686 | 14ce26e7 | bellard | case 0x67: |
3687 | 14ce26e7 | bellard | prefixes |= PREFIX_ADR; |
3688 | 14ce26e7 | bellard | goto next_byte;
|
3689 | 14ce26e7 | bellard | } |
3690 | 14ce26e7 | bellard | if (prefixes & PREFIX_DATA)
|
3691 | 14ce26e7 | bellard | dflag ^= 1;
|
3692 | 14ce26e7 | bellard | if (prefixes & PREFIX_ADR)
|
3693 | 14ce26e7 | bellard | aflag ^= 1;
|
3694 | 2c0262af | bellard | } |
3695 | 2c0262af | bellard | |
3696 | 2c0262af | bellard | s->prefix = prefixes; |
3697 | 2c0262af | bellard | s->aflag = aflag; |
3698 | 2c0262af | bellard | s->dflag = dflag; |
3699 | 2c0262af | bellard | |
3700 | 2c0262af | bellard | /* lock generation */
|
3701 | 2c0262af | bellard | if (prefixes & PREFIX_LOCK)
|
3702 | b8b6a50b | bellard | tcg_gen_helper_0_0(helper_lock); |
3703 | 2c0262af | bellard | |
3704 | 2c0262af | bellard | /* now check op code */
|
3705 | 2c0262af | bellard | reswitch:
|
3706 | 2c0262af | bellard | switch(b) {
|
3707 | 2c0262af | bellard | case 0x0f: |
3708 | 2c0262af | bellard | /**************************/
|
3709 | 2c0262af | bellard | /* extended op code */
|
3710 | 61382a50 | bellard | b = ldub_code(s->pc++) | 0x100;
|
3711 | 2c0262af | bellard | goto reswitch;
|
3712 | 3b46e624 | ths | |
3713 | 2c0262af | bellard | /**************************/
|
3714 | 2c0262af | bellard | /* arith & logic */
|
3715 | 2c0262af | bellard | case 0x00 ... 0x05: |
3716 | 2c0262af | bellard | case 0x08 ... 0x0d: |
3717 | 2c0262af | bellard | case 0x10 ... 0x15: |
3718 | 2c0262af | bellard | case 0x18 ... 0x1d: |
3719 | 2c0262af | bellard | case 0x20 ... 0x25: |
3720 | 2c0262af | bellard | case 0x28 ... 0x2d: |
3721 | 2c0262af | bellard | case 0x30 ... 0x35: |
3722 | 2c0262af | bellard | case 0x38 ... 0x3d: |
3723 | 2c0262af | bellard | { |
3724 | 2c0262af | bellard | int op, f, val;
|
3725 | 2c0262af | bellard | op = (b >> 3) & 7; |
3726 | 2c0262af | bellard | f = (b >> 1) & 3; |
3727 | 2c0262af | bellard | |
3728 | 2c0262af | bellard | if ((b & 1) == 0) |
3729 | 2c0262af | bellard | ot = OT_BYTE; |
3730 | 2c0262af | bellard | else
|
3731 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
3732 | 3b46e624 | ths | |
3733 | 2c0262af | bellard | switch(f) {
|
3734 | 2c0262af | bellard | case 0: /* OP Ev, Gv */ |
3735 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
3736 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
3737 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
3738 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
3739 | 2c0262af | bellard | if (mod != 3) { |
3740 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3741 | 2c0262af | bellard | opreg = OR_TMP0; |
3742 | 2c0262af | bellard | } else if (op == OP_XORL && rm == reg) { |
3743 | 2c0262af | bellard | xor_zero:
|
3744 | 2c0262af | bellard | /* xor reg, reg optimisation */
|
3745 | 2c0262af | bellard | gen_op_movl_T0_0(); |
3746 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB + ot; |
3747 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
3748 | 2c0262af | bellard | gen_op_update1_cc(); |
3749 | 2c0262af | bellard | break;
|
3750 | 2c0262af | bellard | } else {
|
3751 | 2c0262af | bellard | opreg = rm; |
3752 | 2c0262af | bellard | } |
3753 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
3754 | 2c0262af | bellard | gen_op(s, op, ot, opreg); |
3755 | 2c0262af | bellard | break;
|
3756 | 2c0262af | bellard | case 1: /* OP Gv, Ev */ |
3757 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
3758 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
3759 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
3760 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
3761 | 2c0262af | bellard | if (mod != 3) { |
3762 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3763 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
3764 | 2c0262af | bellard | } else if (op == OP_XORL && rm == reg) { |
3765 | 2c0262af | bellard | goto xor_zero;
|
3766 | 2c0262af | bellard | } else {
|
3767 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, rm);
|
3768 | 2c0262af | bellard | } |
3769 | 2c0262af | bellard | gen_op(s, op, ot, reg); |
3770 | 2c0262af | bellard | break;
|
3771 | 2c0262af | bellard | case 2: /* OP A, Iv */ |
3772 | 2c0262af | bellard | val = insn_get(s, ot); |
3773 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
3774 | 2c0262af | bellard | gen_op(s, op, ot, OR_EAX); |
3775 | 2c0262af | bellard | break;
|
3776 | 2c0262af | bellard | } |
3777 | 2c0262af | bellard | } |
3778 | 2c0262af | bellard | break;
|
3779 | 2c0262af | bellard | |
3780 | 2c0262af | bellard | case 0x80: /* GRP1 */ |
3781 | 2c0262af | bellard | case 0x81: |
3782 | d64477af | bellard | case 0x82: |
3783 | 2c0262af | bellard | case 0x83: |
3784 | 2c0262af | bellard | { |
3785 | 2c0262af | bellard | int val;
|
3786 | 2c0262af | bellard | |
3787 | 2c0262af | bellard | if ((b & 1) == 0) |
3788 | 2c0262af | bellard | ot = OT_BYTE; |
3789 | 2c0262af | bellard | else
|
3790 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
3791 | 3b46e624 | ths | |
3792 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
3793 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
3794 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
3795 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
3796 | 3b46e624 | ths | |
3797 | 2c0262af | bellard | if (mod != 3) { |
3798 | 14ce26e7 | bellard | if (b == 0x83) |
3799 | 14ce26e7 | bellard | s->rip_offset = 1;
|
3800 | 14ce26e7 | bellard | else
|
3801 | 14ce26e7 | bellard | s->rip_offset = insn_const_size(ot); |
3802 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3803 | 2c0262af | bellard | opreg = OR_TMP0; |
3804 | 2c0262af | bellard | } else {
|
3805 | 14ce26e7 | bellard | opreg = rm; |
3806 | 2c0262af | bellard | } |
3807 | 2c0262af | bellard | |
3808 | 2c0262af | bellard | switch(b) {
|
3809 | 2c0262af | bellard | default:
|
3810 | 2c0262af | bellard | case 0x80: |
3811 | 2c0262af | bellard | case 0x81: |
3812 | d64477af | bellard | case 0x82: |
3813 | 2c0262af | bellard | val = insn_get(s, ot); |
3814 | 2c0262af | bellard | break;
|
3815 | 2c0262af | bellard | case 0x83: |
3816 | 2c0262af | bellard | val = (int8_t)insn_get(s, OT_BYTE); |
3817 | 2c0262af | bellard | break;
|
3818 | 2c0262af | bellard | } |
3819 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
3820 | 2c0262af | bellard | gen_op(s, op, ot, opreg); |
3821 | 2c0262af | bellard | } |
3822 | 2c0262af | bellard | break;
|
3823 | 2c0262af | bellard | |
3824 | 2c0262af | bellard | /**************************/
|
3825 | 2c0262af | bellard | /* inc, dec, and other misc arith */
|
3826 | 2c0262af | bellard | case 0x40 ... 0x47: /* inc Gv */ |
3827 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
3828 | 2c0262af | bellard | gen_inc(s, ot, OR_EAX + (b & 7), 1); |
3829 | 2c0262af | bellard | break;
|
3830 | 2c0262af | bellard | case 0x48 ... 0x4f: /* dec Gv */ |
3831 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
3832 | 2c0262af | bellard | gen_inc(s, ot, OR_EAX + (b & 7), -1); |
3833 | 2c0262af | bellard | break;
|
3834 | 2c0262af | bellard | case 0xf6: /* GRP3 */ |
3835 | 2c0262af | bellard | case 0xf7: |
3836 | 2c0262af | bellard | if ((b & 1) == 0) |
3837 | 2c0262af | bellard | ot = OT_BYTE; |
3838 | 2c0262af | bellard | else
|
3839 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
3840 | 2c0262af | bellard | |
3841 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
3842 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
3843 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
3844 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
3845 | 2c0262af | bellard | if (mod != 3) { |
3846 | 14ce26e7 | bellard | if (op == 0) |
3847 | 14ce26e7 | bellard | s->rip_offset = insn_const_size(ot); |
3848 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
3849 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
3850 | 2c0262af | bellard | } else {
|
3851 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
3852 | 2c0262af | bellard | } |
3853 | 2c0262af | bellard | |
3854 | 2c0262af | bellard | switch(op) {
|
3855 | 2c0262af | bellard | case 0: /* test */ |
3856 | 2c0262af | bellard | val = insn_get(s, ot); |
3857 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
3858 | 2c0262af | bellard | gen_op_testl_T0_T1_cc(); |
3859 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB + ot; |
3860 | 2c0262af | bellard | break;
|
3861 | 2c0262af | bellard | case 2: /* not */ |
3862 | b6abf97d | bellard | tcg_gen_not_tl(cpu_T[0], cpu_T[0]); |
3863 | 2c0262af | bellard | if (mod != 3) { |
3864 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
3865 | 2c0262af | bellard | } else {
|
3866 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
3867 | 2c0262af | bellard | } |
3868 | 2c0262af | bellard | break;
|
3869 | 2c0262af | bellard | case 3: /* neg */ |
3870 | b6abf97d | bellard | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
3871 | 2c0262af | bellard | if (mod != 3) { |
3872 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
3873 | 2c0262af | bellard | } else {
|
3874 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
3875 | 2c0262af | bellard | } |
3876 | 2c0262af | bellard | gen_op_update_neg_cc(); |
3877 | 2c0262af | bellard | s->cc_op = CC_OP_SUBB + ot; |
3878 | 2c0262af | bellard | break;
|
3879 | 2c0262af | bellard | case 4: /* mul */ |
3880 | 2c0262af | bellard | switch(ot) {
|
3881 | 2c0262af | bellard | case OT_BYTE:
|
3882 | 2c0262af | bellard | gen_op_mulb_AL_T0(); |
3883 | d36cd60e | bellard | s->cc_op = CC_OP_MULB; |
3884 | 2c0262af | bellard | break;
|
3885 | 2c0262af | bellard | case OT_WORD:
|
3886 | 2c0262af | bellard | gen_op_mulw_AX_T0(); |
3887 | d36cd60e | bellard | s->cc_op = CC_OP_MULW; |
3888 | 2c0262af | bellard | break;
|
3889 | 2c0262af | bellard | default:
|
3890 | 2c0262af | bellard | case OT_LONG:
|
3891 | 2c0262af | bellard | gen_op_mull_EAX_T0(); |
3892 | d36cd60e | bellard | s->cc_op = CC_OP_MULL; |
3893 | 2c0262af | bellard | break;
|
3894 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
3895 | 14ce26e7 | bellard | case OT_QUAD:
|
3896 | 14ce26e7 | bellard | gen_op_mulq_EAX_T0(); |
3897 | 14ce26e7 | bellard | s->cc_op = CC_OP_MULQ; |
3898 | 14ce26e7 | bellard | break;
|
3899 | 14ce26e7 | bellard | #endif
|
3900 | 2c0262af | bellard | } |
3901 | 2c0262af | bellard | break;
|
3902 | 2c0262af | bellard | case 5: /* imul */ |
3903 | 2c0262af | bellard | switch(ot) {
|
3904 | 2c0262af | bellard | case OT_BYTE:
|
3905 | 2c0262af | bellard | gen_op_imulb_AL_T0(); |
3906 | d36cd60e | bellard | s->cc_op = CC_OP_MULB; |
3907 | 2c0262af | bellard | break;
|
3908 | 2c0262af | bellard | case OT_WORD:
|
3909 | 2c0262af | bellard | gen_op_imulw_AX_T0(); |
3910 | d36cd60e | bellard | s->cc_op = CC_OP_MULW; |
3911 | 2c0262af | bellard | break;
|
3912 | 2c0262af | bellard | default:
|
3913 | 2c0262af | bellard | case OT_LONG:
|
3914 | 2c0262af | bellard | gen_op_imull_EAX_T0(); |
3915 | d36cd60e | bellard | s->cc_op = CC_OP_MULL; |
3916 | 2c0262af | bellard | break;
|
3917 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
3918 | 14ce26e7 | bellard | case OT_QUAD:
|
3919 | 14ce26e7 | bellard | gen_op_imulq_EAX_T0(); |
3920 | 14ce26e7 | bellard | s->cc_op = CC_OP_MULQ; |
3921 | 14ce26e7 | bellard | break;
|
3922 | 14ce26e7 | bellard | #endif
|
3923 | 2c0262af | bellard | } |
3924 | 2c0262af | bellard | break;
|
3925 | 2c0262af | bellard | case 6: /* div */ |
3926 | 2c0262af | bellard | switch(ot) {
|
3927 | 2c0262af | bellard | case OT_BYTE:
|
3928 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
3929 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_divb_AL, cpu_T[0]);
|
3930 | 2c0262af | bellard | break;
|
3931 | 2c0262af | bellard | case OT_WORD:
|
3932 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
3933 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_divw_AX, cpu_T[0]);
|
3934 | 2c0262af | bellard | break;
|
3935 | 2c0262af | bellard | default:
|
3936 | 2c0262af | bellard | case OT_LONG:
|
3937 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
3938 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_divl_EAX, cpu_T[0]);
|
3939 | 14ce26e7 | bellard | break;
|
3940 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
3941 | 14ce26e7 | bellard | case OT_QUAD:
|
3942 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
3943 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_divq_EAX, cpu_T[0]);
|
3944 | 2c0262af | bellard | break;
|
3945 | 14ce26e7 | bellard | #endif
|
3946 | 2c0262af | bellard | } |
3947 | 2c0262af | bellard | break;
|
3948 | 2c0262af | bellard | case 7: /* idiv */ |
3949 | 2c0262af | bellard | switch(ot) {
|
3950 | 2c0262af | bellard | case OT_BYTE:
|
3951 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
3952 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_idivb_AL, cpu_T[0]);
|
3953 | 2c0262af | bellard | break;
|
3954 | 2c0262af | bellard | case OT_WORD:
|
3955 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
3956 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_idivw_AX, cpu_T[0]);
|
3957 | 2c0262af | bellard | break;
|
3958 | 2c0262af | bellard | default:
|
3959 | 2c0262af | bellard | case OT_LONG:
|
3960 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
3961 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_idivl_EAX, cpu_T[0]);
|
3962 | 14ce26e7 | bellard | break;
|
3963 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
3964 | 14ce26e7 | bellard | case OT_QUAD:
|
3965 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
3966 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_idivq_EAX, cpu_T[0]);
|
3967 | 2c0262af | bellard | break;
|
3968 | 14ce26e7 | bellard | #endif
|
3969 | 2c0262af | bellard | } |
3970 | 2c0262af | bellard | break;
|
3971 | 2c0262af | bellard | default:
|
3972 | 2c0262af | bellard | goto illegal_op;
|
3973 | 2c0262af | bellard | } |
3974 | 2c0262af | bellard | break;
|
3975 | 2c0262af | bellard | |
3976 | 2c0262af | bellard | case 0xfe: /* GRP4 */ |
3977 | 2c0262af | bellard | case 0xff: /* GRP5 */ |
3978 | 2c0262af | bellard | if ((b & 1) == 0) |
3979 | 2c0262af | bellard | ot = OT_BYTE; |
3980 | 2c0262af | bellard | else
|
3981 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
3982 | 2c0262af | bellard | |
3983 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
3984 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
3985 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
3986 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
3987 | 2c0262af | bellard | if (op >= 2 && b == 0xfe) { |
3988 | 2c0262af | bellard | goto illegal_op;
|
3989 | 2c0262af | bellard | } |
3990 | 14ce26e7 | bellard | if (CODE64(s)) {
|
3991 | aba9d61e | bellard | if (op == 2 || op == 4) { |
3992 | 14ce26e7 | bellard | /* operand size for jumps is 64 bit */
|
3993 | 14ce26e7 | bellard | ot = OT_QUAD; |
3994 | aba9d61e | bellard | } else if (op == 3 || op == 5) { |
3995 | aba9d61e | bellard | /* for call calls, the operand is 16 or 32 bit, even
|
3996 | aba9d61e | bellard | in long mode */
|
3997 | aba9d61e | bellard | ot = dflag ? OT_LONG : OT_WORD; |
3998 | 14ce26e7 | bellard | } else if (op == 6) { |
3999 | 14ce26e7 | bellard | /* default push size is 64 bit */
|
4000 | 14ce26e7 | bellard | ot = dflag ? OT_QUAD : OT_WORD; |
4001 | 14ce26e7 | bellard | } |
4002 | 14ce26e7 | bellard | } |
4003 | 2c0262af | bellard | if (mod != 3) { |
4004 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4005 | 2c0262af | bellard | if (op >= 2 && op != 3 && op != 5) |
4006 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
4007 | 2c0262af | bellard | } else {
|
4008 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
4009 | 2c0262af | bellard | } |
4010 | 2c0262af | bellard | |
4011 | 2c0262af | bellard | switch(op) {
|
4012 | 2c0262af | bellard | case 0: /* inc Ev */ |
4013 | 2c0262af | bellard | if (mod != 3) |
4014 | 2c0262af | bellard | opreg = OR_TMP0; |
4015 | 2c0262af | bellard | else
|
4016 | 2c0262af | bellard | opreg = rm; |
4017 | 2c0262af | bellard | gen_inc(s, ot, opreg, 1);
|
4018 | 2c0262af | bellard | break;
|
4019 | 2c0262af | bellard | case 1: /* dec Ev */ |
4020 | 2c0262af | bellard | if (mod != 3) |
4021 | 2c0262af | bellard | opreg = OR_TMP0; |
4022 | 2c0262af | bellard | else
|
4023 | 2c0262af | bellard | opreg = rm; |
4024 | 2c0262af | bellard | gen_inc(s, ot, opreg, -1);
|
4025 | 2c0262af | bellard | break;
|
4026 | 2c0262af | bellard | case 2: /* call Ev */ |
4027 | 4f31916f | bellard | /* XXX: optimize if memory (no 'and' is necessary) */
|
4028 | 2c0262af | bellard | if (s->dflag == 0) |
4029 | 2c0262af | bellard | gen_op_andl_T0_ffff(); |
4030 | 2c0262af | bellard | next_eip = s->pc - s->cs_base; |
4031 | 1ef38687 | bellard | gen_movtl_T1_im(next_eip); |
4032 | 4f31916f | bellard | gen_push_T1(s); |
4033 | 4f31916f | bellard | gen_op_jmp_T0(); |
4034 | 2c0262af | bellard | gen_eob(s); |
4035 | 2c0262af | bellard | break;
|
4036 | 61382a50 | bellard | case 3: /* lcall Ev */ |
4037 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
4038 | aba9d61e | bellard | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
4039 | 57fec1fe | bellard | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
4040 | 2c0262af | bellard | do_lcall:
|
4041 | 2c0262af | bellard | if (s->pe && !s->vm86) {
|
4042 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4043 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
4044 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4045 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4046 | b8b6a50b | bellard | tcg_gen_helper_0_4(helper_lcall_protected, |
4047 | b6abf97d | bellard | cpu_tmp2_i32, cpu_T[1],
|
4048 | b8b6a50b | bellard | tcg_const_i32(dflag), |
4049 | b8b6a50b | bellard | tcg_const_i32(s->pc - pc_start)); |
4050 | 2c0262af | bellard | } else {
|
4051 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4052 | b8b6a50b | bellard | tcg_gen_helper_0_4(helper_lcall_real, |
4053 | b6abf97d | bellard | cpu_tmp2_i32, cpu_T[1],
|
4054 | b8b6a50b | bellard | tcg_const_i32(dflag), |
4055 | b8b6a50b | bellard | tcg_const_i32(s->pc - s->cs_base)); |
4056 | 2c0262af | bellard | } |
4057 | 2c0262af | bellard | gen_eob(s); |
4058 | 2c0262af | bellard | break;
|
4059 | 2c0262af | bellard | case 4: /* jmp Ev */ |
4060 | 2c0262af | bellard | if (s->dflag == 0) |
4061 | 2c0262af | bellard | gen_op_andl_T0_ffff(); |
4062 | 2c0262af | bellard | gen_op_jmp_T0(); |
4063 | 2c0262af | bellard | gen_eob(s); |
4064 | 2c0262af | bellard | break;
|
4065 | 2c0262af | bellard | case 5: /* ljmp Ev */ |
4066 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
4067 | aba9d61e | bellard | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
4068 | 57fec1fe | bellard | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
4069 | 2c0262af | bellard | do_ljmp:
|
4070 | 2c0262af | bellard | if (s->pe && !s->vm86) {
|
4071 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4072 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
4073 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4074 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4075 | b8b6a50b | bellard | tcg_gen_helper_0_3(helper_ljmp_protected, |
4076 | b6abf97d | bellard | cpu_tmp2_i32, |
4077 | b8b6a50b | bellard | cpu_T[1],
|
4078 | b8b6a50b | bellard | tcg_const_i32(s->pc - pc_start)); |
4079 | 2c0262af | bellard | } else {
|
4080 | 2c0262af | bellard | gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS])); |
4081 | 2c0262af | bellard | gen_op_movl_T0_T1(); |
4082 | 2c0262af | bellard | gen_op_jmp_T0(); |
4083 | 2c0262af | bellard | } |
4084 | 2c0262af | bellard | gen_eob(s); |
4085 | 2c0262af | bellard | break;
|
4086 | 2c0262af | bellard | case 6: /* push Ev */ |
4087 | 2c0262af | bellard | gen_push_T0(s); |
4088 | 2c0262af | bellard | break;
|
4089 | 2c0262af | bellard | default:
|
4090 | 2c0262af | bellard | goto illegal_op;
|
4091 | 2c0262af | bellard | } |
4092 | 2c0262af | bellard | break;
|
4093 | 2c0262af | bellard | |
4094 | 2c0262af | bellard | case 0x84: /* test Ev, Gv */ |
4095 | 5fafdf24 | ths | case 0x85: |
4096 | 2c0262af | bellard | if ((b & 1) == 0) |
4097 | 2c0262af | bellard | ot = OT_BYTE; |
4098 | 2c0262af | bellard | else
|
4099 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4100 | 2c0262af | bellard | |
4101 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4102 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4103 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4104 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4105 | 3b46e624 | ths | |
4106 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
4107 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
4108 | 2c0262af | bellard | gen_op_testl_T0_T1_cc(); |
4109 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB + ot; |
4110 | 2c0262af | bellard | break;
|
4111 | 3b46e624 | ths | |
4112 | 2c0262af | bellard | case 0xa8: /* test eAX, Iv */ |
4113 | 2c0262af | bellard | case 0xa9: |
4114 | 2c0262af | bellard | if ((b & 1) == 0) |
4115 | 2c0262af | bellard | ot = OT_BYTE; |
4116 | 2c0262af | bellard | else
|
4117 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4118 | 2c0262af | bellard | val = insn_get(s, ot); |
4119 | 2c0262af | bellard | |
4120 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, OR_EAX);
|
4121 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
4122 | 2c0262af | bellard | gen_op_testl_T0_T1_cc(); |
4123 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB + ot; |
4124 | 2c0262af | bellard | break;
|
4125 | 3b46e624 | ths | |
4126 | 2c0262af | bellard | case 0x98: /* CWDE/CBW */ |
4127 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4128 | 14ce26e7 | bellard | if (dflag == 2) { |
4129 | 14ce26e7 | bellard | gen_op_movslq_RAX_EAX(); |
4130 | 14ce26e7 | bellard | } else
|
4131 | 14ce26e7 | bellard | #endif
|
4132 | 14ce26e7 | bellard | if (dflag == 1) |
4133 | 2c0262af | bellard | gen_op_movswl_EAX_AX(); |
4134 | 2c0262af | bellard | else
|
4135 | 2c0262af | bellard | gen_op_movsbw_AX_AL(); |
4136 | 2c0262af | bellard | break;
|
4137 | 2c0262af | bellard | case 0x99: /* CDQ/CWD */ |
4138 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4139 | 14ce26e7 | bellard | if (dflag == 2) { |
4140 | 14ce26e7 | bellard | gen_op_movsqo_RDX_RAX(); |
4141 | 14ce26e7 | bellard | } else
|
4142 | 14ce26e7 | bellard | #endif
|
4143 | 14ce26e7 | bellard | if (dflag == 1) |
4144 | 2c0262af | bellard | gen_op_movslq_EDX_EAX(); |
4145 | 2c0262af | bellard | else
|
4146 | 2c0262af | bellard | gen_op_movswl_DX_AX(); |
4147 | 2c0262af | bellard | break;
|
4148 | 2c0262af | bellard | case 0x1af: /* imul Gv, Ev */ |
4149 | 2c0262af | bellard | case 0x69: /* imul Gv, Ev, I */ |
4150 | 2c0262af | bellard | case 0x6b: |
4151 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4152 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4153 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4154 | 14ce26e7 | bellard | if (b == 0x69) |
4155 | 14ce26e7 | bellard | s->rip_offset = insn_const_size(ot); |
4156 | 14ce26e7 | bellard | else if (b == 0x6b) |
4157 | 14ce26e7 | bellard | s->rip_offset = 1;
|
4158 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
4159 | 2c0262af | bellard | if (b == 0x69) { |
4160 | 2c0262af | bellard | val = insn_get(s, ot); |
4161 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
4162 | 2c0262af | bellard | } else if (b == 0x6b) { |
4163 | d64477af | bellard | val = (int8_t)insn_get(s, OT_BYTE); |
4164 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
4165 | 2c0262af | bellard | } else {
|
4166 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
4167 | 2c0262af | bellard | } |
4168 | 2c0262af | bellard | |
4169 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4170 | 14ce26e7 | bellard | if (ot == OT_QUAD) {
|
4171 | 14ce26e7 | bellard | gen_op_imulq_T0_T1(); |
4172 | 14ce26e7 | bellard | } else
|
4173 | 14ce26e7 | bellard | #endif
|
4174 | 2c0262af | bellard | if (ot == OT_LONG) {
|
4175 | 2c0262af | bellard | gen_op_imull_T0_T1(); |
4176 | 2c0262af | bellard | } else {
|
4177 | 2c0262af | bellard | gen_op_imulw_T0_T1(); |
4178 | 2c0262af | bellard | } |
4179 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
4180 | d36cd60e | bellard | s->cc_op = CC_OP_MULB + ot; |
4181 | 2c0262af | bellard | break;
|
4182 | 2c0262af | bellard | case 0x1c0: |
4183 | 2c0262af | bellard | case 0x1c1: /* xadd Ev, Gv */ |
4184 | 2c0262af | bellard | if ((b & 1) == 0) |
4185 | 2c0262af | bellard | ot = OT_BYTE; |
4186 | 2c0262af | bellard | else
|
4187 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4188 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4189 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4190 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4191 | 2c0262af | bellard | if (mod == 3) { |
4192 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4193 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
4194 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, rm);
|
4195 | 2c0262af | bellard | gen_op_addl_T0_T1(); |
4196 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
4197 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
4198 | 2c0262af | bellard | } else {
|
4199 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4200 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
4201 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
4202 | 2c0262af | bellard | gen_op_addl_T0_T1(); |
4203 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
4204 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
4205 | 2c0262af | bellard | } |
4206 | 2c0262af | bellard | gen_op_update2_cc(); |
4207 | 2c0262af | bellard | s->cc_op = CC_OP_ADDB + ot; |
4208 | 2c0262af | bellard | break;
|
4209 | 2c0262af | bellard | case 0x1b0: |
4210 | 2c0262af | bellard | case 0x1b1: /* cmpxchg Ev, Gv */ |
4211 | cad3a37d | bellard | { |
4212 | cad3a37d | bellard | int label1;
|
4213 | cad3a37d | bellard | |
4214 | cad3a37d | bellard | if ((b & 1) == 0) |
4215 | cad3a37d | bellard | ot = OT_BYTE; |
4216 | cad3a37d | bellard | else
|
4217 | cad3a37d | bellard | ot = dflag + OT_WORD; |
4218 | cad3a37d | bellard | modrm = ldub_code(s->pc++); |
4219 | cad3a37d | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4220 | cad3a37d | bellard | mod = (modrm >> 6) & 3; |
4221 | cad3a37d | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
4222 | cad3a37d | bellard | if (mod == 3) { |
4223 | cad3a37d | bellard | rm = (modrm & 7) | REX_B(s);
|
4224 | cad3a37d | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
4225 | cad3a37d | bellard | } else {
|
4226 | cad3a37d | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4227 | cad3a37d | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
4228 | cad3a37d | bellard | rm = 0; /* avoid warning */ |
4229 | cad3a37d | bellard | } |
4230 | cad3a37d | bellard | label1 = gen_new_label(); |
4231 | cad3a37d | bellard | tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_EAX])); |
4232 | cad3a37d | bellard | tcg_gen_sub_tl(cpu_T3, cpu_T3, cpu_T[0]);
|
4233 | cad3a37d | bellard | gen_extu(ot, cpu_T3); |
4234 | cad3a37d | bellard | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1);
|
4235 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
4236 | cad3a37d | bellard | gen_op_mov_reg_T0(ot, R_EAX); |
4237 | cad3a37d | bellard | gen_set_label(label1); |
4238 | cad3a37d | bellard | if (mod == 3) { |
4239 | cad3a37d | bellard | gen_op_mov_reg_T1(ot, rm); |
4240 | cad3a37d | bellard | } else {
|
4241 | cad3a37d | bellard | gen_op_st_T1_A0(ot + s->mem_index); |
4242 | cad3a37d | bellard | } |
4243 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
4244 | cad3a37d | bellard | tcg_gen_mov_tl(cpu_cc_dst, cpu_T3); |
4245 | cad3a37d | bellard | s->cc_op = CC_OP_SUBB + ot; |
4246 | 2c0262af | bellard | } |
4247 | 2c0262af | bellard | break;
|
4248 | 2c0262af | bellard | case 0x1c7: /* cmpxchg8b */ |
4249 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4250 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4251 | 71c3558e | balrog | if ((mod == 3) || ((modrm & 0x38) != 0x8)) |
4252 | 2c0262af | bellard | goto illegal_op;
|
4253 | 2f6ecc62 | ths | gen_jmp_im(pc_start - s->cs_base); |
4254 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4255 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
4256 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4257 | 2c0262af | bellard | gen_op_cmpxchg8b(); |
4258 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
4259 | 2c0262af | bellard | break;
|
4260 | 3b46e624 | ths | |
4261 | 2c0262af | bellard | /**************************/
|
4262 | 2c0262af | bellard | /* push/pop */
|
4263 | 2c0262af | bellard | case 0x50 ... 0x57: /* push */ |
4264 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s)); |
4265 | 2c0262af | bellard | gen_push_T0(s); |
4266 | 2c0262af | bellard | break;
|
4267 | 2c0262af | bellard | case 0x58 ... 0x5f: /* pop */ |
4268 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4269 | 14ce26e7 | bellard | ot = dflag ? OT_QUAD : OT_WORD; |
4270 | 14ce26e7 | bellard | } else {
|
4271 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4272 | 14ce26e7 | bellard | } |
4273 | 2c0262af | bellard | gen_pop_T0(s); |
4274 | 77729c24 | bellard | /* NOTE: order is important for pop %sp */
|
4275 | 2c0262af | bellard | gen_pop_update(s); |
4276 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
|
4277 | 2c0262af | bellard | break;
|
4278 | 2c0262af | bellard | case 0x60: /* pusha */ |
4279 | 14ce26e7 | bellard | if (CODE64(s))
|
4280 | 14ce26e7 | bellard | goto illegal_op;
|
4281 | 2c0262af | bellard | gen_pusha(s); |
4282 | 2c0262af | bellard | break;
|
4283 | 2c0262af | bellard | case 0x61: /* popa */ |
4284 | 14ce26e7 | bellard | if (CODE64(s))
|
4285 | 14ce26e7 | bellard | goto illegal_op;
|
4286 | 2c0262af | bellard | gen_popa(s); |
4287 | 2c0262af | bellard | break;
|
4288 | 2c0262af | bellard | case 0x68: /* push Iv */ |
4289 | 2c0262af | bellard | case 0x6a: |
4290 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4291 | 14ce26e7 | bellard | ot = dflag ? OT_QUAD : OT_WORD; |
4292 | 14ce26e7 | bellard | } else {
|
4293 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4294 | 14ce26e7 | bellard | } |
4295 | 2c0262af | bellard | if (b == 0x68) |
4296 | 2c0262af | bellard | val = insn_get(s, ot); |
4297 | 2c0262af | bellard | else
|
4298 | 2c0262af | bellard | val = (int8_t)insn_get(s, OT_BYTE); |
4299 | 2c0262af | bellard | gen_op_movl_T0_im(val); |
4300 | 2c0262af | bellard | gen_push_T0(s); |
4301 | 2c0262af | bellard | break;
|
4302 | 2c0262af | bellard | case 0x8f: /* pop Ev */ |
4303 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4304 | 14ce26e7 | bellard | ot = dflag ? OT_QUAD : OT_WORD; |
4305 | 14ce26e7 | bellard | } else {
|
4306 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4307 | 14ce26e7 | bellard | } |
4308 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4309 | 77729c24 | bellard | mod = (modrm >> 6) & 3; |
4310 | 2c0262af | bellard | gen_pop_T0(s); |
4311 | 77729c24 | bellard | if (mod == 3) { |
4312 | 77729c24 | bellard | /* NOTE: order is important for pop %sp */
|
4313 | 77729c24 | bellard | gen_pop_update(s); |
4314 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4315 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
4316 | 77729c24 | bellard | } else {
|
4317 | 77729c24 | bellard | /* NOTE: order is important too for MMU exceptions */
|
4318 | 14ce26e7 | bellard | s->popl_esp_hack = 1 << ot;
|
4319 | 77729c24 | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
|
4320 | 77729c24 | bellard | s->popl_esp_hack = 0;
|
4321 | 77729c24 | bellard | gen_pop_update(s); |
4322 | 77729c24 | bellard | } |
4323 | 2c0262af | bellard | break;
|
4324 | 2c0262af | bellard | case 0xc8: /* enter */ |
4325 | 2c0262af | bellard | { |
4326 | 2c0262af | bellard | int level;
|
4327 | 61382a50 | bellard | val = lduw_code(s->pc); |
4328 | 2c0262af | bellard | s->pc += 2;
|
4329 | 61382a50 | bellard | level = ldub_code(s->pc++); |
4330 | 2c0262af | bellard | gen_enter(s, val, level); |
4331 | 2c0262af | bellard | } |
4332 | 2c0262af | bellard | break;
|
4333 | 2c0262af | bellard | case 0xc9: /* leave */ |
4334 | 2c0262af | bellard | /* XXX: exception not precise (ESP is updated before potential exception) */
|
4335 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4336 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
|
4337 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_QUAD, R_ESP); |
4338 | 14ce26e7 | bellard | } else if (s->ss32) { |
4339 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
|
4340 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, R_ESP); |
4341 | 2c0262af | bellard | } else {
|
4342 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
|
4343 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_WORD, R_ESP); |
4344 | 2c0262af | bellard | } |
4345 | 2c0262af | bellard | gen_pop_T0(s); |
4346 | 14ce26e7 | bellard | if (CODE64(s)) {
|
4347 | 14ce26e7 | bellard | ot = dflag ? OT_QUAD : OT_WORD; |
4348 | 14ce26e7 | bellard | } else {
|
4349 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4350 | 14ce26e7 | bellard | } |
4351 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, R_EBP); |
4352 | 2c0262af | bellard | gen_pop_update(s); |
4353 | 2c0262af | bellard | break;
|
4354 | 2c0262af | bellard | case 0x06: /* push es */ |
4355 | 2c0262af | bellard | case 0x0e: /* push cs */ |
4356 | 2c0262af | bellard | case 0x16: /* push ss */ |
4357 | 2c0262af | bellard | case 0x1e: /* push ds */ |
4358 | 14ce26e7 | bellard | if (CODE64(s))
|
4359 | 14ce26e7 | bellard | goto illegal_op;
|
4360 | 2c0262af | bellard | gen_op_movl_T0_seg(b >> 3);
|
4361 | 2c0262af | bellard | gen_push_T0(s); |
4362 | 2c0262af | bellard | break;
|
4363 | 2c0262af | bellard | case 0x1a0: /* push fs */ |
4364 | 2c0262af | bellard | case 0x1a8: /* push gs */ |
4365 | 2c0262af | bellard | gen_op_movl_T0_seg((b >> 3) & 7); |
4366 | 2c0262af | bellard | gen_push_T0(s); |
4367 | 2c0262af | bellard | break;
|
4368 | 2c0262af | bellard | case 0x07: /* pop es */ |
4369 | 2c0262af | bellard | case 0x17: /* pop ss */ |
4370 | 2c0262af | bellard | case 0x1f: /* pop ds */ |
4371 | 14ce26e7 | bellard | if (CODE64(s))
|
4372 | 14ce26e7 | bellard | goto illegal_op;
|
4373 | 2c0262af | bellard | reg = b >> 3;
|
4374 | 2c0262af | bellard | gen_pop_T0(s); |
4375 | 2c0262af | bellard | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
4376 | 2c0262af | bellard | gen_pop_update(s); |
4377 | 2c0262af | bellard | if (reg == R_SS) {
|
4378 | a2cc3b24 | bellard | /* if reg == SS, inhibit interrupts/trace. */
|
4379 | a2cc3b24 | bellard | /* If several instructions disable interrupts, only the
|
4380 | a2cc3b24 | bellard | _first_ does it */
|
4381 | a2cc3b24 | bellard | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
|
4382 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_set_inhibit_irq); |
4383 | 2c0262af | bellard | s->tf = 0;
|
4384 | 2c0262af | bellard | } |
4385 | 2c0262af | bellard | if (s->is_jmp) {
|
4386 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
4387 | 2c0262af | bellard | gen_eob(s); |
4388 | 2c0262af | bellard | } |
4389 | 2c0262af | bellard | break;
|
4390 | 2c0262af | bellard | case 0x1a1: /* pop fs */ |
4391 | 2c0262af | bellard | case 0x1a9: /* pop gs */ |
4392 | 2c0262af | bellard | gen_pop_T0(s); |
4393 | 2c0262af | bellard | gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base); |
4394 | 2c0262af | bellard | gen_pop_update(s); |
4395 | 2c0262af | bellard | if (s->is_jmp) {
|
4396 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
4397 | 2c0262af | bellard | gen_eob(s); |
4398 | 2c0262af | bellard | } |
4399 | 2c0262af | bellard | break;
|
4400 | 2c0262af | bellard | |
4401 | 2c0262af | bellard | /**************************/
|
4402 | 2c0262af | bellard | /* mov */
|
4403 | 2c0262af | bellard | case 0x88: |
4404 | 2c0262af | bellard | case 0x89: /* mov Gv, Ev */ |
4405 | 2c0262af | bellard | if ((b & 1) == 0) |
4406 | 2c0262af | bellard | ot = OT_BYTE; |
4407 | 2c0262af | bellard | else
|
4408 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4409 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4410 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4411 | 3b46e624 | ths | |
4412 | 2c0262af | bellard | /* generate a generic store */
|
4413 | 14ce26e7 | bellard | gen_ldst_modrm(s, modrm, ot, reg, 1);
|
4414 | 2c0262af | bellard | break;
|
4415 | 2c0262af | bellard | case 0xc6: |
4416 | 2c0262af | bellard | case 0xc7: /* mov Ev, Iv */ |
4417 | 2c0262af | bellard | if ((b & 1) == 0) |
4418 | 2c0262af | bellard | ot = OT_BYTE; |
4419 | 2c0262af | bellard | else
|
4420 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4421 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4422 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4423 | 14ce26e7 | bellard | if (mod != 3) { |
4424 | 14ce26e7 | bellard | s->rip_offset = insn_const_size(ot); |
4425 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4426 | 14ce26e7 | bellard | } |
4427 | 2c0262af | bellard | val = insn_get(s, ot); |
4428 | 2c0262af | bellard | gen_op_movl_T0_im(val); |
4429 | 2c0262af | bellard | if (mod != 3) |
4430 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
4431 | 2c0262af | bellard | else
|
4432 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
|
4433 | 2c0262af | bellard | break;
|
4434 | 2c0262af | bellard | case 0x8a: |
4435 | 2c0262af | bellard | case 0x8b: /* mov Ev, Gv */ |
4436 | 2c0262af | bellard | if ((b & 1) == 0) |
4437 | 2c0262af | bellard | ot = OT_BYTE; |
4438 | 2c0262af | bellard | else
|
4439 | 14ce26e7 | bellard | ot = OT_WORD + dflag; |
4440 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4441 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4442 | 3b46e624 | ths | |
4443 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
4444 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
4445 | 2c0262af | bellard | break;
|
4446 | 2c0262af | bellard | case 0x8e: /* mov seg, Gv */ |
4447 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4448 | 2c0262af | bellard | reg = (modrm >> 3) & 7; |
4449 | 2c0262af | bellard | if (reg >= 6 || reg == R_CS) |
4450 | 2c0262af | bellard | goto illegal_op;
|
4451 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
4452 | 2c0262af | bellard | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
4453 | 2c0262af | bellard | if (reg == R_SS) {
|
4454 | 2c0262af | bellard | /* if reg == SS, inhibit interrupts/trace */
|
4455 | a2cc3b24 | bellard | /* If several instructions disable interrupts, only the
|
4456 | a2cc3b24 | bellard | _first_ does it */
|
4457 | a2cc3b24 | bellard | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
|
4458 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_set_inhibit_irq); |
4459 | 2c0262af | bellard | s->tf = 0;
|
4460 | 2c0262af | bellard | } |
4461 | 2c0262af | bellard | if (s->is_jmp) {
|
4462 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
4463 | 2c0262af | bellard | gen_eob(s); |
4464 | 2c0262af | bellard | } |
4465 | 2c0262af | bellard | break;
|
4466 | 2c0262af | bellard | case 0x8c: /* mov Gv, seg */ |
4467 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4468 | 2c0262af | bellard | reg = (modrm >> 3) & 7; |
4469 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4470 | 2c0262af | bellard | if (reg >= 6) |
4471 | 2c0262af | bellard | goto illegal_op;
|
4472 | 2c0262af | bellard | gen_op_movl_T0_seg(reg); |
4473 | 14ce26e7 | bellard | if (mod == 3) |
4474 | 14ce26e7 | bellard | ot = OT_WORD + dflag; |
4475 | 14ce26e7 | bellard | else
|
4476 | 14ce26e7 | bellard | ot = OT_WORD; |
4477 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
|
4478 | 2c0262af | bellard | break;
|
4479 | 2c0262af | bellard | |
4480 | 2c0262af | bellard | case 0x1b6: /* movzbS Gv, Eb */ |
4481 | 2c0262af | bellard | case 0x1b7: /* movzwS Gv, Eb */ |
4482 | 2c0262af | bellard | case 0x1be: /* movsbS Gv, Eb */ |
4483 | 2c0262af | bellard | case 0x1bf: /* movswS Gv, Eb */ |
4484 | 2c0262af | bellard | { |
4485 | 2c0262af | bellard | int d_ot;
|
4486 | 2c0262af | bellard | /* d_ot is the size of destination */
|
4487 | 2c0262af | bellard | d_ot = dflag + OT_WORD; |
4488 | 2c0262af | bellard | /* ot is the size of source */
|
4489 | 2c0262af | bellard | ot = (b & 1) + OT_BYTE;
|
4490 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4491 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4492 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4493 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4494 | 3b46e624 | ths | |
4495 | 2c0262af | bellard | if (mod == 3) { |
4496 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
4497 | 2c0262af | bellard | switch(ot | (b & 8)) { |
4498 | 2c0262af | bellard | case OT_BYTE:
|
4499 | 2c0262af | bellard | gen_op_movzbl_T0_T0(); |
4500 | 2c0262af | bellard | break;
|
4501 | 2c0262af | bellard | case OT_BYTE | 8: |
4502 | 2c0262af | bellard | gen_op_movsbl_T0_T0(); |
4503 | 2c0262af | bellard | break;
|
4504 | 2c0262af | bellard | case OT_WORD:
|
4505 | 2c0262af | bellard | gen_op_movzwl_T0_T0(); |
4506 | 2c0262af | bellard | break;
|
4507 | 2c0262af | bellard | default:
|
4508 | 2c0262af | bellard | case OT_WORD | 8: |
4509 | 2c0262af | bellard | gen_op_movswl_T0_T0(); |
4510 | 2c0262af | bellard | break;
|
4511 | 2c0262af | bellard | } |
4512 | 57fec1fe | bellard | gen_op_mov_reg_T0(d_ot, reg); |
4513 | 2c0262af | bellard | } else {
|
4514 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4515 | 2c0262af | bellard | if (b & 8) { |
4516 | 57fec1fe | bellard | gen_op_lds_T0_A0(ot + s->mem_index); |
4517 | 2c0262af | bellard | } else {
|
4518 | 57fec1fe | bellard | gen_op_ldu_T0_A0(ot + s->mem_index); |
4519 | 2c0262af | bellard | } |
4520 | 57fec1fe | bellard | gen_op_mov_reg_T0(d_ot, reg); |
4521 | 2c0262af | bellard | } |
4522 | 2c0262af | bellard | } |
4523 | 2c0262af | bellard | break;
|
4524 | 2c0262af | bellard | |
4525 | 2c0262af | bellard | case 0x8d: /* lea */ |
4526 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4527 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4528 | 3a1d9b8b | bellard | mod = (modrm >> 6) & 3; |
4529 | 3a1d9b8b | bellard | if (mod == 3) |
4530 | 3a1d9b8b | bellard | goto illegal_op;
|
4531 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4532 | 2c0262af | bellard | /* we must ensure that no segment is added */
|
4533 | 2c0262af | bellard | s->override = -1;
|
4534 | 2c0262af | bellard | val = s->addseg; |
4535 | 2c0262af | bellard | s->addseg = 0;
|
4536 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4537 | 2c0262af | bellard | s->addseg = val; |
4538 | 57fec1fe | bellard | gen_op_mov_reg_A0(ot - OT_WORD, reg); |
4539 | 2c0262af | bellard | break;
|
4540 | 3b46e624 | ths | |
4541 | 2c0262af | bellard | case 0xa0: /* mov EAX, Ov */ |
4542 | 2c0262af | bellard | case 0xa1: |
4543 | 2c0262af | bellard | case 0xa2: /* mov Ov, EAX */ |
4544 | 2c0262af | bellard | case 0xa3: |
4545 | 2c0262af | bellard | { |
4546 | 14ce26e7 | bellard | target_ulong offset_addr; |
4547 | 14ce26e7 | bellard | |
4548 | 14ce26e7 | bellard | if ((b & 1) == 0) |
4549 | 14ce26e7 | bellard | ot = OT_BYTE; |
4550 | 14ce26e7 | bellard | else
|
4551 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4552 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4553 | 8f091a59 | bellard | if (s->aflag == 2) { |
4554 | 14ce26e7 | bellard | offset_addr = ldq_code(s->pc); |
4555 | 14ce26e7 | bellard | s->pc += 8;
|
4556 | 57fec1fe | bellard | gen_op_movq_A0_im(offset_addr); |
4557 | 5fafdf24 | ths | } else
|
4558 | 14ce26e7 | bellard | #endif
|
4559 | 14ce26e7 | bellard | { |
4560 | 14ce26e7 | bellard | if (s->aflag) {
|
4561 | 14ce26e7 | bellard | offset_addr = insn_get(s, OT_LONG); |
4562 | 14ce26e7 | bellard | } else {
|
4563 | 14ce26e7 | bellard | offset_addr = insn_get(s, OT_WORD); |
4564 | 14ce26e7 | bellard | } |
4565 | 14ce26e7 | bellard | gen_op_movl_A0_im(offset_addr); |
4566 | 14ce26e7 | bellard | } |
4567 | 664e0f19 | bellard | gen_add_A0_ds_seg(s); |
4568 | 14ce26e7 | bellard | if ((b & 2) == 0) { |
4569 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
4570 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, R_EAX); |
4571 | 14ce26e7 | bellard | } else {
|
4572 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, R_EAX);
|
4573 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
4574 | 2c0262af | bellard | } |
4575 | 2c0262af | bellard | } |
4576 | 2c0262af | bellard | break;
|
4577 | 2c0262af | bellard | case 0xd7: /* xlat */ |
4578 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4579 | 8f091a59 | bellard | if (s->aflag == 2) { |
4580 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_EBX); |
4581 | 14ce26e7 | bellard | gen_op_addq_A0_AL(); |
4582 | 5fafdf24 | ths | } else
|
4583 | 14ce26e7 | bellard | #endif
|
4584 | 14ce26e7 | bellard | { |
4585 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBX); |
4586 | 14ce26e7 | bellard | gen_op_addl_A0_AL(); |
4587 | 14ce26e7 | bellard | if (s->aflag == 0) |
4588 | 14ce26e7 | bellard | gen_op_andl_A0_ffff(); |
4589 | 14ce26e7 | bellard | } |
4590 | 664e0f19 | bellard | gen_add_A0_ds_seg(s); |
4591 | 57fec1fe | bellard | gen_op_ldu_T0_A0(OT_BYTE + s->mem_index); |
4592 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_BYTE, R_EAX); |
4593 | 2c0262af | bellard | break;
|
4594 | 2c0262af | bellard | case 0xb0 ... 0xb7: /* mov R, Ib */ |
4595 | 2c0262af | bellard | val = insn_get(s, OT_BYTE); |
4596 | 2c0262af | bellard | gen_op_movl_T0_im(val); |
4597 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
|
4598 | 2c0262af | bellard | break;
|
4599 | 2c0262af | bellard | case 0xb8 ... 0xbf: /* mov R, Iv */ |
4600 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
4601 | 14ce26e7 | bellard | if (dflag == 2) { |
4602 | 14ce26e7 | bellard | uint64_t tmp; |
4603 | 14ce26e7 | bellard | /* 64 bit case */
|
4604 | 14ce26e7 | bellard | tmp = ldq_code(s->pc); |
4605 | 14ce26e7 | bellard | s->pc += 8;
|
4606 | 14ce26e7 | bellard | reg = (b & 7) | REX_B(s);
|
4607 | 14ce26e7 | bellard | gen_movtl_T0_im(tmp); |
4608 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_QUAD, reg); |
4609 | 5fafdf24 | ths | } else
|
4610 | 14ce26e7 | bellard | #endif
|
4611 | 14ce26e7 | bellard | { |
4612 | 14ce26e7 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
4613 | 14ce26e7 | bellard | val = insn_get(s, ot); |
4614 | 14ce26e7 | bellard | reg = (b & 7) | REX_B(s);
|
4615 | 14ce26e7 | bellard | gen_op_movl_T0_im(val); |
4616 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, reg); |
4617 | 14ce26e7 | bellard | } |
4618 | 2c0262af | bellard | break;
|
4619 | 2c0262af | bellard | |
4620 | 2c0262af | bellard | case 0x91 ... 0x97: /* xchg R, EAX */ |
4621 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4622 | 14ce26e7 | bellard | reg = (b & 7) | REX_B(s);
|
4623 | 2c0262af | bellard | rm = R_EAX; |
4624 | 2c0262af | bellard | goto do_xchg_reg;
|
4625 | 2c0262af | bellard | case 0x86: |
4626 | 2c0262af | bellard | case 0x87: /* xchg Ev, Gv */ |
4627 | 2c0262af | bellard | if ((b & 1) == 0) |
4628 | 2c0262af | bellard | ot = OT_BYTE; |
4629 | 2c0262af | bellard | else
|
4630 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4631 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4632 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4633 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4634 | 2c0262af | bellard | if (mod == 3) { |
4635 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4636 | 2c0262af | bellard | do_xchg_reg:
|
4637 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
4638 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, rm);
|
4639 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
4640 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
4641 | 2c0262af | bellard | } else {
|
4642 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4643 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
4644 | 2c0262af | bellard | /* for xchg, lock is implicit */
|
4645 | 2c0262af | bellard | if (!(prefixes & PREFIX_LOCK))
|
4646 | b8b6a50b | bellard | tcg_gen_helper_0_0(helper_lock); |
4647 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
4648 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
4649 | 2c0262af | bellard | if (!(prefixes & PREFIX_LOCK))
|
4650 | b8b6a50b | bellard | tcg_gen_helper_0_0(helper_unlock); |
4651 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
4652 | 2c0262af | bellard | } |
4653 | 2c0262af | bellard | break;
|
4654 | 2c0262af | bellard | case 0xc4: /* les Gv */ |
4655 | 14ce26e7 | bellard | if (CODE64(s))
|
4656 | 14ce26e7 | bellard | goto illegal_op;
|
4657 | 2c0262af | bellard | op = R_ES; |
4658 | 2c0262af | bellard | goto do_lxx;
|
4659 | 2c0262af | bellard | case 0xc5: /* lds Gv */ |
4660 | 14ce26e7 | bellard | if (CODE64(s))
|
4661 | 14ce26e7 | bellard | goto illegal_op;
|
4662 | 2c0262af | bellard | op = R_DS; |
4663 | 2c0262af | bellard | goto do_lxx;
|
4664 | 2c0262af | bellard | case 0x1b2: /* lss Gv */ |
4665 | 2c0262af | bellard | op = R_SS; |
4666 | 2c0262af | bellard | goto do_lxx;
|
4667 | 2c0262af | bellard | case 0x1b4: /* lfs Gv */ |
4668 | 2c0262af | bellard | op = R_FS; |
4669 | 2c0262af | bellard | goto do_lxx;
|
4670 | 2c0262af | bellard | case 0x1b5: /* lgs Gv */ |
4671 | 2c0262af | bellard | op = R_GS; |
4672 | 2c0262af | bellard | do_lxx:
|
4673 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
4674 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4675 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4676 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4677 | 2c0262af | bellard | if (mod == 3) |
4678 | 2c0262af | bellard | goto illegal_op;
|
4679 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4680 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
4681 | aba9d61e | bellard | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
4682 | 2c0262af | bellard | /* load the segment first to handle exceptions properly */
|
4683 | 57fec1fe | bellard | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
4684 | 2c0262af | bellard | gen_movl_seg_T0(s, op, pc_start - s->cs_base); |
4685 | 2c0262af | bellard | /* then put the data */
|
4686 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
4687 | 2c0262af | bellard | if (s->is_jmp) {
|
4688 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
4689 | 2c0262af | bellard | gen_eob(s); |
4690 | 2c0262af | bellard | } |
4691 | 2c0262af | bellard | break;
|
4692 | 3b46e624 | ths | |
4693 | 2c0262af | bellard | /************************/
|
4694 | 2c0262af | bellard | /* shifts */
|
4695 | 2c0262af | bellard | case 0xc0: |
4696 | 2c0262af | bellard | case 0xc1: |
4697 | 2c0262af | bellard | /* shift Ev,Ib */
|
4698 | 2c0262af | bellard | shift = 2;
|
4699 | 2c0262af | bellard | grp2:
|
4700 | 2c0262af | bellard | { |
4701 | 2c0262af | bellard | if ((b & 1) == 0) |
4702 | 2c0262af | bellard | ot = OT_BYTE; |
4703 | 2c0262af | bellard | else
|
4704 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4705 | 3b46e624 | ths | |
4706 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4707 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4708 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
4709 | 3b46e624 | ths | |
4710 | 2c0262af | bellard | if (mod != 3) { |
4711 | 14ce26e7 | bellard | if (shift == 2) { |
4712 | 14ce26e7 | bellard | s->rip_offset = 1;
|
4713 | 14ce26e7 | bellard | } |
4714 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4715 | 2c0262af | bellard | opreg = OR_TMP0; |
4716 | 2c0262af | bellard | } else {
|
4717 | 14ce26e7 | bellard | opreg = (modrm & 7) | REX_B(s);
|
4718 | 2c0262af | bellard | } |
4719 | 2c0262af | bellard | |
4720 | 2c0262af | bellard | /* simpler op */
|
4721 | 2c0262af | bellard | if (shift == 0) { |
4722 | 2c0262af | bellard | gen_shift(s, op, ot, opreg, OR_ECX); |
4723 | 2c0262af | bellard | } else {
|
4724 | 2c0262af | bellard | if (shift == 2) { |
4725 | 61382a50 | bellard | shift = ldub_code(s->pc++); |
4726 | 2c0262af | bellard | } |
4727 | 2c0262af | bellard | gen_shifti(s, op, ot, opreg, shift); |
4728 | 2c0262af | bellard | } |
4729 | 2c0262af | bellard | } |
4730 | 2c0262af | bellard | break;
|
4731 | 2c0262af | bellard | case 0xd0: |
4732 | 2c0262af | bellard | case 0xd1: |
4733 | 2c0262af | bellard | /* shift Ev,1 */
|
4734 | 2c0262af | bellard | shift = 1;
|
4735 | 2c0262af | bellard | goto grp2;
|
4736 | 2c0262af | bellard | case 0xd2: |
4737 | 2c0262af | bellard | case 0xd3: |
4738 | 2c0262af | bellard | /* shift Ev,cl */
|
4739 | 2c0262af | bellard | shift = 0;
|
4740 | 2c0262af | bellard | goto grp2;
|
4741 | 2c0262af | bellard | |
4742 | 2c0262af | bellard | case 0x1a4: /* shld imm */ |
4743 | 2c0262af | bellard | op = 0;
|
4744 | 2c0262af | bellard | shift = 1;
|
4745 | 2c0262af | bellard | goto do_shiftd;
|
4746 | 2c0262af | bellard | case 0x1a5: /* shld cl */ |
4747 | 2c0262af | bellard | op = 0;
|
4748 | 2c0262af | bellard | shift = 0;
|
4749 | 2c0262af | bellard | goto do_shiftd;
|
4750 | 2c0262af | bellard | case 0x1ac: /* shrd imm */ |
4751 | 2c0262af | bellard | op = 1;
|
4752 | 2c0262af | bellard | shift = 1;
|
4753 | 2c0262af | bellard | goto do_shiftd;
|
4754 | 2c0262af | bellard | case 0x1ad: /* shrd cl */ |
4755 | 2c0262af | bellard | op = 1;
|
4756 | 2c0262af | bellard | shift = 0;
|
4757 | 2c0262af | bellard | do_shiftd:
|
4758 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
4759 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4760 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4761 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
4762 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
4763 | 2c0262af | bellard | if (mod != 3) { |
4764 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4765 | b6abf97d | bellard | opreg = OR_TMP0; |
4766 | 2c0262af | bellard | } else {
|
4767 | b6abf97d | bellard | opreg = rm; |
4768 | 2c0262af | bellard | } |
4769 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
4770 | 3b46e624 | ths | |
4771 | 2c0262af | bellard | if (shift) {
|
4772 | 61382a50 | bellard | val = ldub_code(s->pc++); |
4773 | b6abf97d | bellard | tcg_gen_movi_tl(cpu_T3, val); |
4774 | 2c0262af | bellard | } else {
|
4775 | b6abf97d | bellard | tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX])); |
4776 | 2c0262af | bellard | } |
4777 | b6abf97d | bellard | gen_shiftd_rm_T1_T3(s, ot, opreg, op); |
4778 | 2c0262af | bellard | break;
|
4779 | 2c0262af | bellard | |
4780 | 2c0262af | bellard | /************************/
|
4781 | 2c0262af | bellard | /* floats */
|
4782 | 5fafdf24 | ths | case 0xd8 ... 0xdf: |
4783 | 7eee2a50 | bellard | if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
|
4784 | 7eee2a50 | bellard | /* if CR0.EM or CR0.TS are set, generate an FPU exception */
|
4785 | 7eee2a50 | bellard | /* XXX: what to do if illegal op ? */
|
4786 | 7eee2a50 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
4787 | 7eee2a50 | bellard | break;
|
4788 | 7eee2a50 | bellard | } |
4789 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
4790 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
4791 | 2c0262af | bellard | rm = modrm & 7;
|
4792 | 2c0262af | bellard | op = ((b & 7) << 3) | ((modrm >> 3) & 7); |
4793 | 2c0262af | bellard | if (mod != 3) { |
4794 | 2c0262af | bellard | /* memory op */
|
4795 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4796 | 2c0262af | bellard | switch(op) {
|
4797 | 2c0262af | bellard | case 0x00 ... 0x07: /* fxxxs */ |
4798 | 2c0262af | bellard | case 0x10 ... 0x17: /* fixxxl */ |
4799 | 2c0262af | bellard | case 0x20 ... 0x27: /* fxxxl */ |
4800 | 2c0262af | bellard | case 0x30 ... 0x37: /* fixxx */ |
4801 | 2c0262af | bellard | { |
4802 | 2c0262af | bellard | int op1;
|
4803 | 2c0262af | bellard | op1 = op & 7;
|
4804 | 2c0262af | bellard | |
4805 | 2c0262af | bellard | switch(op >> 4) { |
4806 | 2c0262af | bellard | case 0: |
4807 | ba7cd150 | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
4808 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4809 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2_i32); |
4810 | 2c0262af | bellard | break;
|
4811 | 2c0262af | bellard | case 1: |
4812 | ba7cd150 | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
4813 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4814 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32); |
4815 | 2c0262af | bellard | break;
|
4816 | 2c0262af | bellard | case 2: |
4817 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
4818 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
4819 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1_i64); |
4820 | 2c0262af | bellard | break;
|
4821 | 2c0262af | bellard | case 3: |
4822 | 2c0262af | bellard | default:
|
4823 | ba7cd150 | bellard | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
4824 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4825 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32); |
4826 | 2c0262af | bellard | break;
|
4827 | 2c0262af | bellard | } |
4828 | 3b46e624 | ths | |
4829 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]); |
4830 | 2c0262af | bellard | if (op1 == 3) { |
4831 | 2c0262af | bellard | /* fcomp needs pop */
|
4832 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
4833 | 2c0262af | bellard | } |
4834 | 2c0262af | bellard | } |
4835 | 2c0262af | bellard | break;
|
4836 | 2c0262af | bellard | case 0x08: /* flds */ |
4837 | 2c0262af | bellard | case 0x0a: /* fsts */ |
4838 | 2c0262af | bellard | case 0x0b: /* fstps */ |
4839 | 465e9838 | bellard | case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ |
4840 | 465e9838 | bellard | case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ |
4841 | 465e9838 | bellard | case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ |
4842 | 2c0262af | bellard | switch(op & 7) { |
4843 | 2c0262af | bellard | case 0: |
4844 | 2c0262af | bellard | switch(op >> 4) { |
4845 | 2c0262af | bellard | case 0: |
4846 | ba7cd150 | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
4847 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4848 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2_i32); |
4849 | 2c0262af | bellard | break;
|
4850 | 2c0262af | bellard | case 1: |
4851 | ba7cd150 | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
4852 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4853 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32); |
4854 | 2c0262af | bellard | break;
|
4855 | 2c0262af | bellard | case 2: |
4856 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
4857 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
4858 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1_i64); |
4859 | 2c0262af | bellard | break;
|
4860 | 2c0262af | bellard | case 3: |
4861 | 2c0262af | bellard | default:
|
4862 | ba7cd150 | bellard | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
4863 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4864 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32); |
4865 | 2c0262af | bellard | break;
|
4866 | 2c0262af | bellard | } |
4867 | 2c0262af | bellard | break;
|
4868 | 465e9838 | bellard | case 1: |
4869 | 19e6c4b8 | bellard | /* XXX: the corresponding CPUID bit must be tested ! */
|
4870 | 465e9838 | bellard | switch(op >> 4) { |
4871 | 465e9838 | bellard | case 1: |
4872 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2_i32); |
4873 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
4874 | ba7cd150 | bellard | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
4875 | 465e9838 | bellard | break;
|
4876 | 465e9838 | bellard | case 2: |
4877 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1_i64); |
4878 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
4879 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
4880 | 465e9838 | bellard | break;
|
4881 | 465e9838 | bellard | case 3: |
4882 | 465e9838 | bellard | default:
|
4883 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2_i32); |
4884 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
4885 | ba7cd150 | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
4886 | 19e6c4b8 | bellard | break;
|
4887 | 465e9838 | bellard | } |
4888 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
4889 | 465e9838 | bellard | break;
|
4890 | 2c0262af | bellard | default:
|
4891 | 2c0262af | bellard | switch(op >> 4) { |
4892 | 2c0262af | bellard | case 0: |
4893 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2_i32); |
4894 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
4895 | ba7cd150 | bellard | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
4896 | 2c0262af | bellard | break;
|
4897 | 2c0262af | bellard | case 1: |
4898 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2_i32); |
4899 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
4900 | ba7cd150 | bellard | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
4901 | 2c0262af | bellard | break;
|
4902 | 2c0262af | bellard | case 2: |
4903 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1_i64); |
4904 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
4905 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
4906 | 2c0262af | bellard | break;
|
4907 | 2c0262af | bellard | case 3: |
4908 | 2c0262af | bellard | default:
|
4909 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2_i32); |
4910 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
4911 | ba7cd150 | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
4912 | 2c0262af | bellard | break;
|
4913 | 2c0262af | bellard | } |
4914 | 2c0262af | bellard | if ((op & 7) == 3) |
4915 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
4916 | 2c0262af | bellard | break;
|
4917 | 2c0262af | bellard | } |
4918 | 2c0262af | bellard | break;
|
4919 | 2c0262af | bellard | case 0x0c: /* fldenv mem */ |
4920 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4921 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
4922 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4923 | 19e6c4b8 | bellard | tcg_gen_helper_0_2(helper_fldenv, |
4924 | 19e6c4b8 | bellard | cpu_A0, tcg_const_i32(s->dflag)); |
4925 | 2c0262af | bellard | break;
|
4926 | 2c0262af | bellard | case 0x0d: /* fldcw mem */ |
4927 | 19e6c4b8 | bellard | gen_op_ld_T0_A0(OT_WORD + s->mem_index); |
4928 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
4929 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2_i32); |
4930 | 2c0262af | bellard | break;
|
4931 | 2c0262af | bellard | case 0x0e: /* fnstenv mem */ |
4932 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4933 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
4934 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4935 | 19e6c4b8 | bellard | tcg_gen_helper_0_2(helper_fstenv, |
4936 | 19e6c4b8 | bellard | cpu_A0, tcg_const_i32(s->dflag)); |
4937 | 2c0262af | bellard | break;
|
4938 | 2c0262af | bellard | case 0x0f: /* fnstcw mem */ |
4939 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2_i32); |
4940 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
4941 | 19e6c4b8 | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
4942 | 2c0262af | bellard | break;
|
4943 | 2c0262af | bellard | case 0x1d: /* fldt mem */ |
4944 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4945 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
4946 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4947 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fldt_ST0, cpu_A0); |
4948 | 2c0262af | bellard | break;
|
4949 | 2c0262af | bellard | case 0x1f: /* fstpt mem */ |
4950 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4951 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
4952 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4953 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fstt_ST0, cpu_A0); |
4954 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
4955 | 2c0262af | bellard | break;
|
4956 | 2c0262af | bellard | case 0x2c: /* frstor mem */ |
4957 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4958 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
4959 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4960 | 19e6c4b8 | bellard | tcg_gen_helper_0_2(helper_frstor, |
4961 | 19e6c4b8 | bellard | cpu_A0, tcg_const_i32(s->dflag)); |
4962 | 2c0262af | bellard | break;
|
4963 | 2c0262af | bellard | case 0x2e: /* fnsave mem */ |
4964 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4965 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
4966 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4967 | 19e6c4b8 | bellard | tcg_gen_helper_0_2(helper_fsave, |
4968 | 19e6c4b8 | bellard | cpu_A0, tcg_const_i32(s->dflag)); |
4969 | 2c0262af | bellard | break;
|
4970 | 2c0262af | bellard | case 0x2f: /* fnstsw mem */ |
4971 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32); |
4972 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
4973 | 19e6c4b8 | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
4974 | 2c0262af | bellard | break;
|
4975 | 2c0262af | bellard | case 0x3c: /* fbld */ |
4976 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4977 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
4978 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4979 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fbld_ST0, cpu_A0); |
4980 | 2c0262af | bellard | break;
|
4981 | 2c0262af | bellard | case 0x3e: /* fbstp */ |
4982 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
4983 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
4984 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
4985 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fbst_ST0, cpu_A0); |
4986 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
4987 | 2c0262af | bellard | break;
|
4988 | 2c0262af | bellard | case 0x3d: /* fildll */ |
4989 | b6abf97d | bellard | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
4990 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
4991 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1_i64); |
4992 | 2c0262af | bellard | break;
|
4993 | 2c0262af | bellard | case 0x3f: /* fistpll */ |
4994 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1_i64); |
4995 | b6abf97d | bellard | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
4996 | 19e6c4b8 | bellard | (s->mem_index >> 2) - 1); |
4997 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
4998 | 2c0262af | bellard | break;
|
4999 | 2c0262af | bellard | default:
|
5000 | 2c0262af | bellard | goto illegal_op;
|
5001 | 2c0262af | bellard | } |
5002 | 2c0262af | bellard | } else {
|
5003 | 2c0262af | bellard | /* register float ops */
|
5004 | 2c0262af | bellard | opreg = rm; |
5005 | 2c0262af | bellard | |
5006 | 2c0262af | bellard | switch(op) {
|
5007 | 2c0262af | bellard | case 0x08: /* fld sti */ |
5008 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpush); |
5009 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32((opreg + 1) & 7)); |
5010 | 2c0262af | bellard | break;
|
5011 | 2c0262af | bellard | case 0x09: /* fxchg sti */ |
5012 | c169c906 | bellard | case 0x29: /* fxchg4 sti, undocumented op */ |
5013 | c169c906 | bellard | case 0x39: /* fxchg7 sti, undocumented op */ |
5014 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fxchg_ST0_STN, tcg_const_i32(opreg)); |
5015 | 2c0262af | bellard | break;
|
5016 | 2c0262af | bellard | case 0x0a: /* grp d9/2 */ |
5017 | 2c0262af | bellard | switch(rm) {
|
5018 | 2c0262af | bellard | case 0: /* fnop */ |
5019 | 023fe10d | bellard | /* check exceptions (FreeBSD FPU probe) */
|
5020 | 023fe10d | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5021 | 023fe10d | bellard | gen_op_set_cc_op(s->cc_op); |
5022 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5023 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fwait); |
5024 | 2c0262af | bellard | break;
|
5025 | 2c0262af | bellard | default:
|
5026 | 2c0262af | bellard | goto illegal_op;
|
5027 | 2c0262af | bellard | } |
5028 | 2c0262af | bellard | break;
|
5029 | 2c0262af | bellard | case 0x0c: /* grp d9/4 */ |
5030 | 2c0262af | bellard | switch(rm) {
|
5031 | 2c0262af | bellard | case 0: /* fchs */ |
5032 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fchs_ST0); |
5033 | 2c0262af | bellard | break;
|
5034 | 2c0262af | bellard | case 1: /* fabs */ |
5035 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fabs_ST0); |
5036 | 2c0262af | bellard | break;
|
5037 | 2c0262af | bellard | case 4: /* ftst */ |
5038 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fldz_FT0); |
5039 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fcom_ST0_FT0); |
5040 | 2c0262af | bellard | break;
|
5041 | 2c0262af | bellard | case 5: /* fxam */ |
5042 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fxam_ST0); |
5043 | 2c0262af | bellard | break;
|
5044 | 2c0262af | bellard | default:
|
5045 | 2c0262af | bellard | goto illegal_op;
|
5046 | 2c0262af | bellard | } |
5047 | 2c0262af | bellard | break;
|
5048 | 2c0262af | bellard | case 0x0d: /* grp d9/5 */ |
5049 | 2c0262af | bellard | { |
5050 | 2c0262af | bellard | switch(rm) {
|
5051 | 2c0262af | bellard | case 0: |
5052 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpush); |
5053 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fld1_ST0); |
5054 | 2c0262af | bellard | break;
|
5055 | 2c0262af | bellard | case 1: |
5056 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpush); |
5057 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fldl2t_ST0); |
5058 | 2c0262af | bellard | break;
|
5059 | 2c0262af | bellard | case 2: |
5060 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpush); |
5061 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fldl2e_ST0); |
5062 | 2c0262af | bellard | break;
|
5063 | 2c0262af | bellard | case 3: |
5064 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpush); |
5065 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fldpi_ST0); |
5066 | 2c0262af | bellard | break;
|
5067 | 2c0262af | bellard | case 4: |
5068 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpush); |
5069 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fldlg2_ST0); |
5070 | 2c0262af | bellard | break;
|
5071 | 2c0262af | bellard | case 5: |
5072 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpush); |
5073 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fldln2_ST0); |
5074 | 2c0262af | bellard | break;
|
5075 | 2c0262af | bellard | case 6: |
5076 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpush); |
5077 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fldz_ST0); |
5078 | 2c0262af | bellard | break;
|
5079 | 2c0262af | bellard | default:
|
5080 | 2c0262af | bellard | goto illegal_op;
|
5081 | 2c0262af | bellard | } |
5082 | 2c0262af | bellard | } |
5083 | 2c0262af | bellard | break;
|
5084 | 2c0262af | bellard | case 0x0e: /* grp d9/6 */ |
5085 | 2c0262af | bellard | switch(rm) {
|
5086 | 2c0262af | bellard | case 0: /* f2xm1 */ |
5087 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_f2xm1); |
5088 | 2c0262af | bellard | break;
|
5089 | 2c0262af | bellard | case 1: /* fyl2x */ |
5090 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fyl2x); |
5091 | 2c0262af | bellard | break;
|
5092 | 2c0262af | bellard | case 2: /* fptan */ |
5093 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fptan); |
5094 | 2c0262af | bellard | break;
|
5095 | 2c0262af | bellard | case 3: /* fpatan */ |
5096 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpatan); |
5097 | 2c0262af | bellard | break;
|
5098 | 2c0262af | bellard | case 4: /* fxtract */ |
5099 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fxtract); |
5100 | 2c0262af | bellard | break;
|
5101 | 2c0262af | bellard | case 5: /* fprem1 */ |
5102 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fprem1); |
5103 | 2c0262af | bellard | break;
|
5104 | 2c0262af | bellard | case 6: /* fdecstp */ |
5105 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fdecstp); |
5106 | 2c0262af | bellard | break;
|
5107 | 2c0262af | bellard | default:
|
5108 | 2c0262af | bellard | case 7: /* fincstp */ |
5109 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fincstp); |
5110 | 2c0262af | bellard | break;
|
5111 | 2c0262af | bellard | } |
5112 | 2c0262af | bellard | break;
|
5113 | 2c0262af | bellard | case 0x0f: /* grp d9/7 */ |
5114 | 2c0262af | bellard | switch(rm) {
|
5115 | 2c0262af | bellard | case 0: /* fprem */ |
5116 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fprem); |
5117 | 2c0262af | bellard | break;
|
5118 | 2c0262af | bellard | case 1: /* fyl2xp1 */ |
5119 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fyl2xp1); |
5120 | 2c0262af | bellard | break;
|
5121 | 2c0262af | bellard | case 2: /* fsqrt */ |
5122 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fsqrt); |
5123 | 2c0262af | bellard | break;
|
5124 | 2c0262af | bellard | case 3: /* fsincos */ |
5125 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fsincos); |
5126 | 2c0262af | bellard | break;
|
5127 | 2c0262af | bellard | case 5: /* fscale */ |
5128 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fscale); |
5129 | 2c0262af | bellard | break;
|
5130 | 2c0262af | bellard | case 4: /* frndint */ |
5131 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_frndint); |
5132 | 2c0262af | bellard | break;
|
5133 | 2c0262af | bellard | case 6: /* fsin */ |
5134 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fsin); |
5135 | 2c0262af | bellard | break;
|
5136 | 2c0262af | bellard | default:
|
5137 | 2c0262af | bellard | case 7: /* fcos */ |
5138 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fcos); |
5139 | 2c0262af | bellard | break;
|
5140 | 2c0262af | bellard | } |
5141 | 2c0262af | bellard | break;
|
5142 | 2c0262af | bellard | case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ |
5143 | 2c0262af | bellard | case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ |
5144 | 2c0262af | bellard | case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ |
5145 | 2c0262af | bellard | { |
5146 | 2c0262af | bellard | int op1;
|
5147 | 3b46e624 | ths | |
5148 | 2c0262af | bellard | op1 = op & 7;
|
5149 | 2c0262af | bellard | if (op >= 0x20) { |
5150 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fp_arith_STN_ST0[op1], tcg_const_i32(opreg)); |
5151 | 2c0262af | bellard | if (op >= 0x30) |
5152 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5153 | 2c0262af | bellard | } else {
|
5154 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
5155 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]); |
5156 | 2c0262af | bellard | } |
5157 | 2c0262af | bellard | } |
5158 | 2c0262af | bellard | break;
|
5159 | 2c0262af | bellard | case 0x02: /* fcom */ |
5160 | c169c906 | bellard | case 0x22: /* fcom2, undocumented op */ |
5161 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
5162 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fcom_ST0_FT0); |
5163 | 2c0262af | bellard | break;
|
5164 | 2c0262af | bellard | case 0x03: /* fcomp */ |
5165 | c169c906 | bellard | case 0x23: /* fcomp3, undocumented op */ |
5166 | c169c906 | bellard | case 0x32: /* fcomp5, undocumented op */ |
5167 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
5168 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fcom_ST0_FT0); |
5169 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5170 | 2c0262af | bellard | break;
|
5171 | 2c0262af | bellard | case 0x15: /* da/5 */ |
5172 | 2c0262af | bellard | switch(rm) {
|
5173 | 2c0262af | bellard | case 1: /* fucompp */ |
5174 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
|
5175 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fucom_ST0_FT0); |
5176 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5177 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5178 | 2c0262af | bellard | break;
|
5179 | 2c0262af | bellard | default:
|
5180 | 2c0262af | bellard | goto illegal_op;
|
5181 | 2c0262af | bellard | } |
5182 | 2c0262af | bellard | break;
|
5183 | 2c0262af | bellard | case 0x1c: |
5184 | 2c0262af | bellard | switch(rm) {
|
5185 | 2c0262af | bellard | case 0: /* feni (287 only, just do nop here) */ |
5186 | 2c0262af | bellard | break;
|
5187 | 2c0262af | bellard | case 1: /* fdisi (287 only, just do nop here) */ |
5188 | 2c0262af | bellard | break;
|
5189 | 2c0262af | bellard | case 2: /* fclex */ |
5190 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fclex); |
5191 | 2c0262af | bellard | break;
|
5192 | 2c0262af | bellard | case 3: /* fninit */ |
5193 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fninit); |
5194 | 2c0262af | bellard | break;
|
5195 | 2c0262af | bellard | case 4: /* fsetpm (287 only, just do nop here) */ |
5196 | 2c0262af | bellard | break;
|
5197 | 2c0262af | bellard | default:
|
5198 | 2c0262af | bellard | goto illegal_op;
|
5199 | 2c0262af | bellard | } |
5200 | 2c0262af | bellard | break;
|
5201 | 2c0262af | bellard | case 0x1d: /* fucomi */ |
5202 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5203 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5204 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
5205 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fucomi_ST0_FT0); |
5206 | 19e6c4b8 | bellard | gen_op_fcomi_dummy(); |
5207 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5208 | 2c0262af | bellard | break;
|
5209 | 2c0262af | bellard | case 0x1e: /* fcomi */ |
5210 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5211 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5212 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
5213 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fcomi_ST0_FT0); |
5214 | 19e6c4b8 | bellard | gen_op_fcomi_dummy(); |
5215 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5216 | 2c0262af | bellard | break;
|
5217 | 658c8bda | bellard | case 0x28: /* ffree sti */ |
5218 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg)); |
5219 | 5fafdf24 | ths | break;
|
5220 | 2c0262af | bellard | case 0x2a: /* fst sti */ |
5221 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg)); |
5222 | 2c0262af | bellard | break;
|
5223 | 2c0262af | bellard | case 0x2b: /* fstp sti */ |
5224 | c169c906 | bellard | case 0x0b: /* fstp1 sti, undocumented op */ |
5225 | c169c906 | bellard | case 0x3a: /* fstp8 sti, undocumented op */ |
5226 | c169c906 | bellard | case 0x3b: /* fstp9 sti, undocumented op */ |
5227 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg)); |
5228 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5229 | 2c0262af | bellard | break;
|
5230 | 2c0262af | bellard | case 0x2c: /* fucom st(i) */ |
5231 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
5232 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fucom_ST0_FT0); |
5233 | 2c0262af | bellard | break;
|
5234 | 2c0262af | bellard | case 0x2d: /* fucomp st(i) */ |
5235 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
5236 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fucom_ST0_FT0); |
5237 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5238 | 2c0262af | bellard | break;
|
5239 | 2c0262af | bellard | case 0x33: /* de/3 */ |
5240 | 2c0262af | bellard | switch(rm) {
|
5241 | 2c0262af | bellard | case 1: /* fcompp */ |
5242 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
|
5243 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fcom_ST0_FT0); |
5244 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5245 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5246 | 2c0262af | bellard | break;
|
5247 | 2c0262af | bellard | default:
|
5248 | 2c0262af | bellard | goto illegal_op;
|
5249 | 2c0262af | bellard | } |
5250 | 2c0262af | bellard | break;
|
5251 | c169c906 | bellard | case 0x38: /* ffreep sti, undocumented op */ |
5252 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg)); |
5253 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5254 | c169c906 | bellard | break;
|
5255 | 2c0262af | bellard | case 0x3c: /* df/4 */ |
5256 | 2c0262af | bellard | switch(rm) {
|
5257 | 2c0262af | bellard | case 0: |
5258 | b6abf97d | bellard | tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32); |
5259 | b6abf97d | bellard | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
5260 | 19e6c4b8 | bellard | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
5261 | 2c0262af | bellard | break;
|
5262 | 2c0262af | bellard | default:
|
5263 | 2c0262af | bellard | goto illegal_op;
|
5264 | 2c0262af | bellard | } |
5265 | 2c0262af | bellard | break;
|
5266 | 2c0262af | bellard | case 0x3d: /* fucomip */ |
5267 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5268 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5269 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
5270 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fucomi_ST0_FT0); |
5271 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5272 | 19e6c4b8 | bellard | gen_op_fcomi_dummy(); |
5273 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5274 | 2c0262af | bellard | break;
|
5275 | 2c0262af | bellard | case 0x3e: /* fcomip */ |
5276 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5277 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5278 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); |
5279 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fcomi_ST0_FT0); |
5280 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fpop); |
5281 | 19e6c4b8 | bellard | gen_op_fcomi_dummy(); |
5282 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5283 | 2c0262af | bellard | break;
|
5284 | a2cc3b24 | bellard | case 0x10 ... 0x13: /* fcmovxx */ |
5285 | a2cc3b24 | bellard | case 0x18 ... 0x1b: |
5286 | a2cc3b24 | bellard | { |
5287 | 19e6c4b8 | bellard | int op1, l1;
|
5288 | a2cc3b24 | bellard | const static uint8_t fcmov_cc[8] = { |
5289 | a2cc3b24 | bellard | (JCC_B << 1),
|
5290 | a2cc3b24 | bellard | (JCC_Z << 1),
|
5291 | a2cc3b24 | bellard | (JCC_BE << 1),
|
5292 | a2cc3b24 | bellard | (JCC_P << 1),
|
5293 | a2cc3b24 | bellard | }; |
5294 | a2cc3b24 | bellard | op1 = fcmov_cc[op & 3] | ((op >> 3) & 1); |
5295 | a2cc3b24 | bellard | gen_setcc(s, op1); |
5296 | 19e6c4b8 | bellard | l1 = gen_new_label(); |
5297 | 19e6c4b8 | bellard | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1); |
5298 | 19e6c4b8 | bellard | tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32(opreg)); |
5299 | 19e6c4b8 | bellard | gen_set_label(l1); |
5300 | a2cc3b24 | bellard | } |
5301 | a2cc3b24 | bellard | break;
|
5302 | 2c0262af | bellard | default:
|
5303 | 2c0262af | bellard | goto illegal_op;
|
5304 | 2c0262af | bellard | } |
5305 | 2c0262af | bellard | } |
5306 | 2c0262af | bellard | break;
|
5307 | 2c0262af | bellard | /************************/
|
5308 | 2c0262af | bellard | /* string ops */
|
5309 | 2c0262af | bellard | |
5310 | 2c0262af | bellard | case 0xa4: /* movsS */ |
5311 | 2c0262af | bellard | case 0xa5: |
5312 | 2c0262af | bellard | if ((b & 1) == 0) |
5313 | 2c0262af | bellard | ot = OT_BYTE; |
5314 | 2c0262af | bellard | else
|
5315 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5316 | 2c0262af | bellard | |
5317 | 2c0262af | bellard | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
5318 | 2c0262af | bellard | gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); |
5319 | 2c0262af | bellard | } else {
|
5320 | 2c0262af | bellard | gen_movs(s, ot); |
5321 | 2c0262af | bellard | } |
5322 | 2c0262af | bellard | break;
|
5323 | 3b46e624 | ths | |
5324 | 2c0262af | bellard | case 0xaa: /* stosS */ |
5325 | 2c0262af | bellard | case 0xab: |
5326 | 2c0262af | bellard | if ((b & 1) == 0) |
5327 | 2c0262af | bellard | ot = OT_BYTE; |
5328 | 2c0262af | bellard | else
|
5329 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5330 | 2c0262af | bellard | |
5331 | 2c0262af | bellard | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
5332 | 2c0262af | bellard | gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); |
5333 | 2c0262af | bellard | } else {
|
5334 | 2c0262af | bellard | gen_stos(s, ot); |
5335 | 2c0262af | bellard | } |
5336 | 2c0262af | bellard | break;
|
5337 | 2c0262af | bellard | case 0xac: /* lodsS */ |
5338 | 2c0262af | bellard | case 0xad: |
5339 | 2c0262af | bellard | if ((b & 1) == 0) |
5340 | 2c0262af | bellard | ot = OT_BYTE; |
5341 | 2c0262af | bellard | else
|
5342 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5343 | 2c0262af | bellard | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
5344 | 2c0262af | bellard | gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); |
5345 | 2c0262af | bellard | } else {
|
5346 | 2c0262af | bellard | gen_lods(s, ot); |
5347 | 2c0262af | bellard | } |
5348 | 2c0262af | bellard | break;
|
5349 | 2c0262af | bellard | case 0xae: /* scasS */ |
5350 | 2c0262af | bellard | case 0xaf: |
5351 | 2c0262af | bellard | if ((b & 1) == 0) |
5352 | 2c0262af | bellard | ot = OT_BYTE; |
5353 | 2c0262af | bellard | else
|
5354 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5355 | 2c0262af | bellard | if (prefixes & PREFIX_REPNZ) {
|
5356 | 2c0262af | bellard | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
|
5357 | 2c0262af | bellard | } else if (prefixes & PREFIX_REPZ) { |
5358 | 2c0262af | bellard | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
|
5359 | 2c0262af | bellard | } else {
|
5360 | 2c0262af | bellard | gen_scas(s, ot); |
5361 | 2c0262af | bellard | s->cc_op = CC_OP_SUBB + ot; |
5362 | 2c0262af | bellard | } |
5363 | 2c0262af | bellard | break;
|
5364 | 2c0262af | bellard | |
5365 | 2c0262af | bellard | case 0xa6: /* cmpsS */ |
5366 | 2c0262af | bellard | case 0xa7: |
5367 | 2c0262af | bellard | if ((b & 1) == 0) |
5368 | 2c0262af | bellard | ot = OT_BYTE; |
5369 | 2c0262af | bellard | else
|
5370 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5371 | 2c0262af | bellard | if (prefixes & PREFIX_REPNZ) {
|
5372 | 2c0262af | bellard | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
|
5373 | 2c0262af | bellard | } else if (prefixes & PREFIX_REPZ) { |
5374 | 2c0262af | bellard | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
|
5375 | 2c0262af | bellard | } else {
|
5376 | 2c0262af | bellard | gen_cmps(s, ot); |
5377 | 2c0262af | bellard | s->cc_op = CC_OP_SUBB + ot; |
5378 | 2c0262af | bellard | } |
5379 | 2c0262af | bellard | break;
|
5380 | 2c0262af | bellard | case 0x6c: /* insS */ |
5381 | 2c0262af | bellard | case 0x6d: |
5382 | f115e911 | bellard | if ((b & 1) == 0) |
5383 | f115e911 | bellard | ot = OT_BYTE; |
5384 | f115e911 | bellard | else
|
5385 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
5386 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
|
5387 | 0573fbfc | ths | gen_op_andl_T0_ffff(); |
5388 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
5389 | b8b6a50b | bellard | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
|
5390 | f115e911 | bellard | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
5391 | f115e911 | bellard | gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); |
5392 | 2c0262af | bellard | } else {
|
5393 | f115e911 | bellard | gen_ins(s, ot); |
5394 | 2c0262af | bellard | } |
5395 | 2c0262af | bellard | break;
|
5396 | 2c0262af | bellard | case 0x6e: /* outsS */ |
5397 | 2c0262af | bellard | case 0x6f: |
5398 | f115e911 | bellard | if ((b & 1) == 0) |
5399 | f115e911 | bellard | ot = OT_BYTE; |
5400 | f115e911 | bellard | else
|
5401 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
5402 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
|
5403 | 0573fbfc | ths | gen_op_andl_T0_ffff(); |
5404 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
5405 | b8b6a50b | bellard | svm_is_rep(prefixes) | 4);
|
5406 | f115e911 | bellard | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
5407 | f115e911 | bellard | gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); |
5408 | 2c0262af | bellard | } else {
|
5409 | f115e911 | bellard | gen_outs(s, ot); |
5410 | 2c0262af | bellard | } |
5411 | 2c0262af | bellard | break;
|
5412 | 2c0262af | bellard | |
5413 | 2c0262af | bellard | /************************/
|
5414 | 2c0262af | bellard | /* port I/O */
|
5415 | 0573fbfc | ths | |
5416 | 2c0262af | bellard | case 0xe4: |
5417 | 2c0262af | bellard | case 0xe5: |
5418 | f115e911 | bellard | if ((b & 1) == 0) |
5419 | f115e911 | bellard | ot = OT_BYTE; |
5420 | f115e911 | bellard | else
|
5421 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
5422 | f115e911 | bellard | val = ldub_code(s->pc++); |
5423 | f115e911 | bellard | gen_op_movl_T0_im(val); |
5424 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
5425 | b8b6a50b | bellard | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); |
5426 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5427 | b6abf97d | bellard | tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
|
5428 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, R_EAX); |
5429 | 2c0262af | bellard | break;
|
5430 | 2c0262af | bellard | case 0xe6: |
5431 | 2c0262af | bellard | case 0xe7: |
5432 | f115e911 | bellard | if ((b & 1) == 0) |
5433 | f115e911 | bellard | ot = OT_BYTE; |
5434 | f115e911 | bellard | else
|
5435 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
5436 | f115e911 | bellard | val = ldub_code(s->pc++); |
5437 | f115e911 | bellard | gen_op_movl_T0_im(val); |
5438 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
5439 | b8b6a50b | bellard | svm_is_rep(prefixes)); |
5440 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, R_EAX);
|
5441 | b8b6a50b | bellard | |
5442 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5443 | b6abf97d | bellard | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
5444 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
|
5445 | b6abf97d | bellard | tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32); |
5446 | 2c0262af | bellard | break;
|
5447 | 2c0262af | bellard | case 0xec: |
5448 | 2c0262af | bellard | case 0xed: |
5449 | f115e911 | bellard | if ((b & 1) == 0) |
5450 | f115e911 | bellard | ot = OT_BYTE; |
5451 | f115e911 | bellard | else
|
5452 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
5453 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
|
5454 | 4f31916f | bellard | gen_op_andl_T0_ffff(); |
5455 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
5456 | b8b6a50b | bellard | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); |
5457 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5458 | b6abf97d | bellard | tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
|
5459 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, R_EAX); |
5460 | 2c0262af | bellard | break;
|
5461 | 2c0262af | bellard | case 0xee: |
5462 | 2c0262af | bellard | case 0xef: |
5463 | f115e911 | bellard | if ((b & 1) == 0) |
5464 | f115e911 | bellard | ot = OT_BYTE; |
5465 | f115e911 | bellard | else
|
5466 | f115e911 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
5467 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
|
5468 | 4f31916f | bellard | gen_op_andl_T0_ffff(); |
5469 | b8b6a50b | bellard | gen_check_io(s, ot, pc_start - s->cs_base, |
5470 | b8b6a50b | bellard | svm_is_rep(prefixes)); |
5471 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, R_EAX);
|
5472 | b8b6a50b | bellard | |
5473 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
5474 | b6abf97d | bellard | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
5475 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
|
5476 | b6abf97d | bellard | tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32); |
5477 | 2c0262af | bellard | break;
|
5478 | 2c0262af | bellard | |
5479 | 2c0262af | bellard | /************************/
|
5480 | 2c0262af | bellard | /* control */
|
5481 | 2c0262af | bellard | case 0xc2: /* ret im */ |
5482 | 61382a50 | bellard | val = ldsw_code(s->pc); |
5483 | 2c0262af | bellard | s->pc += 2;
|
5484 | 2c0262af | bellard | gen_pop_T0(s); |
5485 | 8f091a59 | bellard | if (CODE64(s) && s->dflag)
|
5486 | 8f091a59 | bellard | s->dflag = 2;
|
5487 | 2c0262af | bellard | gen_stack_update(s, val + (2 << s->dflag));
|
5488 | 2c0262af | bellard | if (s->dflag == 0) |
5489 | 2c0262af | bellard | gen_op_andl_T0_ffff(); |
5490 | 2c0262af | bellard | gen_op_jmp_T0(); |
5491 | 2c0262af | bellard | gen_eob(s); |
5492 | 2c0262af | bellard | break;
|
5493 | 2c0262af | bellard | case 0xc3: /* ret */ |
5494 | 2c0262af | bellard | gen_pop_T0(s); |
5495 | 2c0262af | bellard | gen_pop_update(s); |
5496 | 2c0262af | bellard | if (s->dflag == 0) |
5497 | 2c0262af | bellard | gen_op_andl_T0_ffff(); |
5498 | 2c0262af | bellard | gen_op_jmp_T0(); |
5499 | 2c0262af | bellard | gen_eob(s); |
5500 | 2c0262af | bellard | break;
|
5501 | 2c0262af | bellard | case 0xca: /* lret im */ |
5502 | 61382a50 | bellard | val = ldsw_code(s->pc); |
5503 | 2c0262af | bellard | s->pc += 2;
|
5504 | 2c0262af | bellard | do_lret:
|
5505 | 2c0262af | bellard | if (s->pe && !s->vm86) {
|
5506 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5507 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5508 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5509 | b8b6a50b | bellard | tcg_gen_helper_0_2(helper_lret_protected, |
5510 | b8b6a50b | bellard | tcg_const_i32(s->dflag), |
5511 | b8b6a50b | bellard | tcg_const_i32(val)); |
5512 | 2c0262af | bellard | } else {
|
5513 | 2c0262af | bellard | gen_stack_A0(s); |
5514 | 2c0262af | bellard | /* pop offset */
|
5515 | 57fec1fe | bellard | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
|
5516 | 2c0262af | bellard | if (s->dflag == 0) |
5517 | 2c0262af | bellard | gen_op_andl_T0_ffff(); |
5518 | 2c0262af | bellard | /* NOTE: keeping EIP updated is not a problem in case of
|
5519 | 2c0262af | bellard | exception */
|
5520 | 2c0262af | bellard | gen_op_jmp_T0(); |
5521 | 2c0262af | bellard | /* pop selector */
|
5522 | 2c0262af | bellard | gen_op_addl_A0_im(2 << s->dflag);
|
5523 | 57fec1fe | bellard | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
|
5524 | 2c0262af | bellard | gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS])); |
5525 | 2c0262af | bellard | /* add stack offset */
|
5526 | 2c0262af | bellard | gen_stack_update(s, val + (4 << s->dflag));
|
5527 | 2c0262af | bellard | } |
5528 | 2c0262af | bellard | gen_eob(s); |
5529 | 2c0262af | bellard | break;
|
5530 | 2c0262af | bellard | case 0xcb: /* lret */ |
5531 | 2c0262af | bellard | val = 0;
|
5532 | 2c0262af | bellard | goto do_lret;
|
5533 | 2c0262af | bellard | case 0xcf: /* iret */ |
5534 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET))
|
5535 | 0573fbfc | ths | break;
|
5536 | 2c0262af | bellard | if (!s->pe) {
|
5537 | 2c0262af | bellard | /* real mode */
|
5538 | b8b6a50b | bellard | tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag)); |
5539 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5540 | f115e911 | bellard | } else if (s->vm86) { |
5541 | f115e911 | bellard | if (s->iopl != 3) { |
5542 | f115e911 | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
5543 | f115e911 | bellard | } else {
|
5544 | b8b6a50b | bellard | tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag)); |
5545 | f115e911 | bellard | s->cc_op = CC_OP_EFLAGS; |
5546 | f115e911 | bellard | } |
5547 | 2c0262af | bellard | } else {
|
5548 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5549 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5550 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5551 | b8b6a50b | bellard | tcg_gen_helper_0_2(helper_iret_protected, |
5552 | b8b6a50b | bellard | tcg_const_i32(s->dflag), |
5553 | b8b6a50b | bellard | tcg_const_i32(s->pc - s->cs_base)); |
5554 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5555 | 2c0262af | bellard | } |
5556 | 2c0262af | bellard | gen_eob(s); |
5557 | 2c0262af | bellard | break;
|
5558 | 2c0262af | bellard | case 0xe8: /* call im */ |
5559 | 2c0262af | bellard | { |
5560 | 14ce26e7 | bellard | if (dflag)
|
5561 | 14ce26e7 | bellard | tval = (int32_t)insn_get(s, OT_LONG); |
5562 | 14ce26e7 | bellard | else
|
5563 | 14ce26e7 | bellard | tval = (int16_t)insn_get(s, OT_WORD); |
5564 | 2c0262af | bellard | next_eip = s->pc - s->cs_base; |
5565 | 14ce26e7 | bellard | tval += next_eip; |
5566 | 2c0262af | bellard | if (s->dflag == 0) |
5567 | 14ce26e7 | bellard | tval &= 0xffff;
|
5568 | 14ce26e7 | bellard | gen_movtl_T0_im(next_eip); |
5569 | 2c0262af | bellard | gen_push_T0(s); |
5570 | 14ce26e7 | bellard | gen_jmp(s, tval); |
5571 | 2c0262af | bellard | } |
5572 | 2c0262af | bellard | break;
|
5573 | 2c0262af | bellard | case 0x9a: /* lcall im */ |
5574 | 2c0262af | bellard | { |
5575 | 2c0262af | bellard | unsigned int selector, offset; |
5576 | 3b46e624 | ths | |
5577 | 14ce26e7 | bellard | if (CODE64(s))
|
5578 | 14ce26e7 | bellard | goto illegal_op;
|
5579 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
5580 | 2c0262af | bellard | offset = insn_get(s, ot); |
5581 | 2c0262af | bellard | selector = insn_get(s, OT_WORD); |
5582 | 3b46e624 | ths | |
5583 | 2c0262af | bellard | gen_op_movl_T0_im(selector); |
5584 | 14ce26e7 | bellard | gen_op_movl_T1_imu(offset); |
5585 | 2c0262af | bellard | } |
5586 | 2c0262af | bellard | goto do_lcall;
|
5587 | ecada8a2 | bellard | case 0xe9: /* jmp im */ |
5588 | 14ce26e7 | bellard | if (dflag)
|
5589 | 14ce26e7 | bellard | tval = (int32_t)insn_get(s, OT_LONG); |
5590 | 14ce26e7 | bellard | else
|
5591 | 14ce26e7 | bellard | tval = (int16_t)insn_get(s, OT_WORD); |
5592 | 14ce26e7 | bellard | tval += s->pc - s->cs_base; |
5593 | 2c0262af | bellard | if (s->dflag == 0) |
5594 | 14ce26e7 | bellard | tval &= 0xffff;
|
5595 | 14ce26e7 | bellard | gen_jmp(s, tval); |
5596 | 2c0262af | bellard | break;
|
5597 | 2c0262af | bellard | case 0xea: /* ljmp im */ |
5598 | 2c0262af | bellard | { |
5599 | 2c0262af | bellard | unsigned int selector, offset; |
5600 | 2c0262af | bellard | |
5601 | 14ce26e7 | bellard | if (CODE64(s))
|
5602 | 14ce26e7 | bellard | goto illegal_op;
|
5603 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
5604 | 2c0262af | bellard | offset = insn_get(s, ot); |
5605 | 2c0262af | bellard | selector = insn_get(s, OT_WORD); |
5606 | 3b46e624 | ths | |
5607 | 2c0262af | bellard | gen_op_movl_T0_im(selector); |
5608 | 14ce26e7 | bellard | gen_op_movl_T1_imu(offset); |
5609 | 2c0262af | bellard | } |
5610 | 2c0262af | bellard | goto do_ljmp;
|
5611 | 2c0262af | bellard | case 0xeb: /* jmp Jb */ |
5612 | 14ce26e7 | bellard | tval = (int8_t)insn_get(s, OT_BYTE); |
5613 | 14ce26e7 | bellard | tval += s->pc - s->cs_base; |
5614 | 2c0262af | bellard | if (s->dflag == 0) |
5615 | 14ce26e7 | bellard | tval &= 0xffff;
|
5616 | 14ce26e7 | bellard | gen_jmp(s, tval); |
5617 | 2c0262af | bellard | break;
|
5618 | 2c0262af | bellard | case 0x70 ... 0x7f: /* jcc Jb */ |
5619 | 14ce26e7 | bellard | tval = (int8_t)insn_get(s, OT_BYTE); |
5620 | 2c0262af | bellard | goto do_jcc;
|
5621 | 2c0262af | bellard | case 0x180 ... 0x18f: /* jcc Jv */ |
5622 | 2c0262af | bellard | if (dflag) {
|
5623 | 14ce26e7 | bellard | tval = (int32_t)insn_get(s, OT_LONG); |
5624 | 2c0262af | bellard | } else {
|
5625 | 5fafdf24 | ths | tval = (int16_t)insn_get(s, OT_WORD); |
5626 | 2c0262af | bellard | } |
5627 | 2c0262af | bellard | do_jcc:
|
5628 | 2c0262af | bellard | next_eip = s->pc - s->cs_base; |
5629 | 14ce26e7 | bellard | tval += next_eip; |
5630 | 2c0262af | bellard | if (s->dflag == 0) |
5631 | 14ce26e7 | bellard | tval &= 0xffff;
|
5632 | 14ce26e7 | bellard | gen_jcc(s, b, tval, next_eip); |
5633 | 2c0262af | bellard | break;
|
5634 | 2c0262af | bellard | |
5635 | 2c0262af | bellard | case 0x190 ... 0x19f: /* setcc Gv */ |
5636 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5637 | 2c0262af | bellard | gen_setcc(s, b); |
5638 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
|
5639 | 2c0262af | bellard | break;
|
5640 | 2c0262af | bellard | case 0x140 ... 0x14f: /* cmov Gv, Ev */ |
5641 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5642 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5643 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
5644 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5645 | 2c0262af | bellard | gen_setcc(s, b); |
5646 | 2c0262af | bellard | if (mod != 3) { |
5647 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5648 | 57fec1fe | bellard | gen_op_ld_T1_A0(ot + s->mem_index); |
5649 | 2c0262af | bellard | } else {
|
5650 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
5651 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, rm);
|
5652 | 2c0262af | bellard | } |
5653 | 2c0262af | bellard | gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg](); |
5654 | 2c0262af | bellard | break;
|
5655 | 3b46e624 | ths | |
5656 | 2c0262af | bellard | /************************/
|
5657 | 2c0262af | bellard | /* flags */
|
5658 | 2c0262af | bellard | case 0x9c: /* pushf */ |
5659 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF))
|
5660 | 0573fbfc | ths | break;
|
5661 | 2c0262af | bellard | if (s->vm86 && s->iopl != 3) { |
5662 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
5663 | 2c0262af | bellard | } else {
|
5664 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5665 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5666 | 2c0262af | bellard | gen_op_movl_T0_eflags(); |
5667 | 2c0262af | bellard | gen_push_T0(s); |
5668 | 2c0262af | bellard | } |
5669 | 2c0262af | bellard | break;
|
5670 | 2c0262af | bellard | case 0x9d: /* popf */ |
5671 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF))
|
5672 | 0573fbfc | ths | break;
|
5673 | 2c0262af | bellard | if (s->vm86 && s->iopl != 3) { |
5674 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
5675 | 2c0262af | bellard | } else {
|
5676 | 2c0262af | bellard | gen_pop_T0(s); |
5677 | 2c0262af | bellard | if (s->cpl == 0) { |
5678 | 2c0262af | bellard | if (s->dflag) {
|
5679 | 2c0262af | bellard | gen_op_movl_eflags_T0_cpl0(); |
5680 | 2c0262af | bellard | } else {
|
5681 | 2c0262af | bellard | gen_op_movw_eflags_T0_cpl0(); |
5682 | 2c0262af | bellard | } |
5683 | 2c0262af | bellard | } else {
|
5684 | 4136f33c | bellard | if (s->cpl <= s->iopl) {
|
5685 | 4136f33c | bellard | if (s->dflag) {
|
5686 | 4136f33c | bellard | gen_op_movl_eflags_T0_io(); |
5687 | 4136f33c | bellard | } else {
|
5688 | 4136f33c | bellard | gen_op_movw_eflags_T0_io(); |
5689 | 4136f33c | bellard | } |
5690 | 2c0262af | bellard | } else {
|
5691 | 4136f33c | bellard | if (s->dflag) {
|
5692 | 4136f33c | bellard | gen_op_movl_eflags_T0(); |
5693 | 4136f33c | bellard | } else {
|
5694 | 4136f33c | bellard | gen_op_movw_eflags_T0(); |
5695 | 4136f33c | bellard | } |
5696 | 2c0262af | bellard | } |
5697 | 2c0262af | bellard | } |
5698 | 2c0262af | bellard | gen_pop_update(s); |
5699 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5700 | 2c0262af | bellard | /* abort translation because TF flag may change */
|
5701 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
5702 | 2c0262af | bellard | gen_eob(s); |
5703 | 2c0262af | bellard | } |
5704 | 2c0262af | bellard | break;
|
5705 | 2c0262af | bellard | case 0x9e: /* sahf */ |
5706 | 14ce26e7 | bellard | if (CODE64(s))
|
5707 | 14ce26e7 | bellard | goto illegal_op;
|
5708 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
|
5709 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5710 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5711 | 2c0262af | bellard | gen_op_movb_eflags_T0(); |
5712 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5713 | 2c0262af | bellard | break;
|
5714 | 2c0262af | bellard | case 0x9f: /* lahf */ |
5715 | 14ce26e7 | bellard | if (CODE64(s))
|
5716 | 14ce26e7 | bellard | goto illegal_op;
|
5717 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5718 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5719 | 2c0262af | bellard | gen_op_movl_T0_eflags(); |
5720 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_BYTE, R_AH); |
5721 | 2c0262af | bellard | break;
|
5722 | 2c0262af | bellard | case 0xf5: /* cmc */ |
5723 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5724 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5725 | 2c0262af | bellard | gen_op_cmc(); |
5726 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5727 | 2c0262af | bellard | break;
|
5728 | 2c0262af | bellard | case 0xf8: /* clc */ |
5729 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5730 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5731 | 2c0262af | bellard | gen_op_clc(); |
5732 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5733 | 2c0262af | bellard | break;
|
5734 | 2c0262af | bellard | case 0xf9: /* stc */ |
5735 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5736 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5737 | 2c0262af | bellard | gen_op_stc(); |
5738 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5739 | 2c0262af | bellard | break;
|
5740 | 2c0262af | bellard | case 0xfc: /* cld */ |
5741 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_tmp2_i32, 1);
|
5742 | b6abf97d | bellard | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); |
5743 | 2c0262af | bellard | break;
|
5744 | 2c0262af | bellard | case 0xfd: /* std */ |
5745 | b6abf97d | bellard | tcg_gen_movi_i32(cpu_tmp2_i32, -1);
|
5746 | b6abf97d | bellard | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); |
5747 | 2c0262af | bellard | break;
|
5748 | 2c0262af | bellard | |
5749 | 2c0262af | bellard | /************************/
|
5750 | 2c0262af | bellard | /* bit operations */
|
5751 | 2c0262af | bellard | case 0x1ba: /* bt/bts/btr/btc Gv, im */ |
5752 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5753 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5754 | 33698e5f | bellard | op = (modrm >> 3) & 7; |
5755 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5756 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
5757 | 2c0262af | bellard | if (mod != 3) { |
5758 | 14ce26e7 | bellard | s->rip_offset = 1;
|
5759 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5760 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
5761 | 2c0262af | bellard | } else {
|
5762 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
5763 | 2c0262af | bellard | } |
5764 | 2c0262af | bellard | /* load shift */
|
5765 | 61382a50 | bellard | val = ldub_code(s->pc++); |
5766 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
5767 | 2c0262af | bellard | if (op < 4) |
5768 | 2c0262af | bellard | goto illegal_op;
|
5769 | 2c0262af | bellard | op -= 4;
|
5770 | f484d386 | bellard | goto bt_op;
|
5771 | 2c0262af | bellard | case 0x1a3: /* bt Gv, Ev */ |
5772 | 2c0262af | bellard | op = 0;
|
5773 | 2c0262af | bellard | goto do_btx;
|
5774 | 2c0262af | bellard | case 0x1ab: /* bts */ |
5775 | 2c0262af | bellard | op = 1;
|
5776 | 2c0262af | bellard | goto do_btx;
|
5777 | 2c0262af | bellard | case 0x1b3: /* btr */ |
5778 | 2c0262af | bellard | op = 2;
|
5779 | 2c0262af | bellard | goto do_btx;
|
5780 | 2c0262af | bellard | case 0x1bb: /* btc */ |
5781 | 2c0262af | bellard | op = 3;
|
5782 | 2c0262af | bellard | do_btx:
|
5783 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5784 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5785 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
5786 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
5787 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
5788 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 1, reg);
|
5789 | 2c0262af | bellard | if (mod != 3) { |
5790 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5791 | 2c0262af | bellard | /* specific case: we need to add a displacement */
|
5792 | f484d386 | bellard | gen_exts(ot, cpu_T[1]);
|
5793 | f484d386 | bellard | tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); |
5794 | f484d386 | bellard | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); |
5795 | f484d386 | bellard | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
5796 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
5797 | 2c0262af | bellard | } else {
|
5798 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
5799 | 2c0262af | bellard | } |
5800 | f484d386 | bellard | bt_op:
|
5801 | f484d386 | bellard | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); |
5802 | f484d386 | bellard | switch(op) {
|
5803 | f484d386 | bellard | case 0: |
5804 | f484d386 | bellard | tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); |
5805 | f484d386 | bellard | tcg_gen_movi_tl(cpu_cc_dst, 0);
|
5806 | f484d386 | bellard | break;
|
5807 | f484d386 | bellard | case 1: |
5808 | f484d386 | bellard | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); |
5809 | f484d386 | bellard | tcg_gen_movi_tl(cpu_tmp0, 1);
|
5810 | f484d386 | bellard | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
|
5811 | f484d386 | bellard | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
5812 | f484d386 | bellard | break;
|
5813 | f484d386 | bellard | case 2: |
5814 | f484d386 | bellard | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); |
5815 | f484d386 | bellard | tcg_gen_movi_tl(cpu_tmp0, 1);
|
5816 | f484d386 | bellard | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
|
5817 | f484d386 | bellard | tcg_gen_not_tl(cpu_tmp0, cpu_tmp0); |
5818 | f484d386 | bellard | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
5819 | f484d386 | bellard | break;
|
5820 | f484d386 | bellard | default:
|
5821 | f484d386 | bellard | case 3: |
5822 | f484d386 | bellard | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); |
5823 | f484d386 | bellard | tcg_gen_movi_tl(cpu_tmp0, 1);
|
5824 | f484d386 | bellard | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
|
5825 | f484d386 | bellard | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
5826 | f484d386 | bellard | break;
|
5827 | f484d386 | bellard | } |
5828 | 2c0262af | bellard | s->cc_op = CC_OP_SARB + ot; |
5829 | 2c0262af | bellard | if (op != 0) { |
5830 | 2c0262af | bellard | if (mod != 3) |
5831 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
5832 | 2c0262af | bellard | else
|
5833 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
5834 | f484d386 | bellard | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
5835 | f484d386 | bellard | tcg_gen_movi_tl(cpu_cc_dst, 0);
|
5836 | 2c0262af | bellard | } |
5837 | 2c0262af | bellard | break;
|
5838 | 2c0262af | bellard | case 0x1bc: /* bsf */ |
5839 | 2c0262af | bellard | case 0x1bd: /* bsr */ |
5840 | 14ce26e7 | bellard | ot = dflag + OT_WORD; |
5841 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
5842 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
5843 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
5844 | 686f3f26 | bellard | /* NOTE: in order to handle the 0 case, we must load the
|
5845 | 686f3f26 | bellard | result. It could be optimized with a generated jump */
|
5846 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
5847 | 2c0262af | bellard | gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
|
5848 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
5849 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB + ot; |
5850 | 2c0262af | bellard | break;
|
5851 | 2c0262af | bellard | /************************/
|
5852 | 2c0262af | bellard | /* bcd */
|
5853 | 2c0262af | bellard | case 0x27: /* daa */ |
5854 | 14ce26e7 | bellard | if (CODE64(s))
|
5855 | 14ce26e7 | bellard | goto illegal_op;
|
5856 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5857 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5858 | 2c0262af | bellard | gen_op_daa(); |
5859 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5860 | 2c0262af | bellard | break;
|
5861 | 2c0262af | bellard | case 0x2f: /* das */ |
5862 | 14ce26e7 | bellard | if (CODE64(s))
|
5863 | 14ce26e7 | bellard | goto illegal_op;
|
5864 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5865 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5866 | 2c0262af | bellard | gen_op_das(); |
5867 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5868 | 2c0262af | bellard | break;
|
5869 | 2c0262af | bellard | case 0x37: /* aaa */ |
5870 | 14ce26e7 | bellard | if (CODE64(s))
|
5871 | 14ce26e7 | bellard | goto illegal_op;
|
5872 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5873 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5874 | 2c0262af | bellard | gen_op_aaa(); |
5875 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5876 | 2c0262af | bellard | break;
|
5877 | 2c0262af | bellard | case 0x3f: /* aas */ |
5878 | 14ce26e7 | bellard | if (CODE64(s))
|
5879 | 14ce26e7 | bellard | goto illegal_op;
|
5880 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5881 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5882 | 2c0262af | bellard | gen_op_aas(); |
5883 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
5884 | 2c0262af | bellard | break;
|
5885 | 2c0262af | bellard | case 0xd4: /* aam */ |
5886 | 14ce26e7 | bellard | if (CODE64(s))
|
5887 | 14ce26e7 | bellard | goto illegal_op;
|
5888 | 61382a50 | bellard | val = ldub_code(s->pc++); |
5889 | b6d7c3db | ths | if (val == 0) { |
5890 | b6d7c3db | ths | gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); |
5891 | b6d7c3db | ths | } else {
|
5892 | b6d7c3db | ths | gen_op_aam(val); |
5893 | b6d7c3db | ths | s->cc_op = CC_OP_LOGICB; |
5894 | b6d7c3db | ths | } |
5895 | 2c0262af | bellard | break;
|
5896 | 2c0262af | bellard | case 0xd5: /* aad */ |
5897 | 14ce26e7 | bellard | if (CODE64(s))
|
5898 | 14ce26e7 | bellard | goto illegal_op;
|
5899 | 61382a50 | bellard | val = ldub_code(s->pc++); |
5900 | 2c0262af | bellard | gen_op_aad(val); |
5901 | 2c0262af | bellard | s->cc_op = CC_OP_LOGICB; |
5902 | 2c0262af | bellard | break;
|
5903 | 2c0262af | bellard | /************************/
|
5904 | 2c0262af | bellard | /* misc */
|
5905 | 2c0262af | bellard | case 0x90: /* nop */ |
5906 | 14ce26e7 | bellard | /* XXX: xchg + rex handling */
|
5907 | ab1f142b | bellard | /* XXX: correct lock test for all insn */
|
5908 | ab1f142b | bellard | if (prefixes & PREFIX_LOCK)
|
5909 | ab1f142b | bellard | goto illegal_op;
|
5910 | 0573fbfc | ths | if (prefixes & PREFIX_REPZ) {
|
5911 | 0573fbfc | ths | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE); |
5912 | 0573fbfc | ths | } |
5913 | 2c0262af | bellard | break;
|
5914 | 2c0262af | bellard | case 0x9b: /* fwait */ |
5915 | 5fafdf24 | ths | if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
|
5916 | 7eee2a50 | bellard | (HF_MP_MASK | HF_TS_MASK)) { |
5917 | 7eee2a50 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
5918 | 2ee73ac3 | bellard | } else {
|
5919 | 2ee73ac3 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5920 | 2ee73ac3 | bellard | gen_op_set_cc_op(s->cc_op); |
5921 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
5922 | 19e6c4b8 | bellard | tcg_gen_helper_0_0(helper_fwait); |
5923 | 7eee2a50 | bellard | } |
5924 | 2c0262af | bellard | break;
|
5925 | 2c0262af | bellard | case 0xcc: /* int3 */ |
5926 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
|
5927 | 0573fbfc | ths | break;
|
5928 | 2c0262af | bellard | gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); |
5929 | 2c0262af | bellard | break;
|
5930 | 2c0262af | bellard | case 0xcd: /* int N */ |
5931 | 61382a50 | bellard | val = ldub_code(s->pc++); |
5932 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
|
5933 | 0573fbfc | ths | break;
|
5934 | f115e911 | bellard | if (s->vm86 && s->iopl != 3) { |
5935 | 5fafdf24 | ths | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
5936 | f115e911 | bellard | } else {
|
5937 | f115e911 | bellard | gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); |
5938 | f115e911 | bellard | } |
5939 | 2c0262af | bellard | break;
|
5940 | 2c0262af | bellard | case 0xce: /* into */ |
5941 | 14ce26e7 | bellard | if (CODE64(s))
|
5942 | 14ce26e7 | bellard | goto illegal_op;
|
5943 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
|
5944 | 0573fbfc | ths | break;
|
5945 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
5946 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
5947 | a8ede8ba | bellard | gen_jmp_im(pc_start - s->cs_base); |
5948 | a8ede8ba | bellard | gen_op_into(s->pc - pc_start); |
5949 | 2c0262af | bellard | break;
|
5950 | 2c0262af | bellard | case 0xf1: /* icebp (undocumented, exits to external debugger) */ |
5951 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP))
|
5952 | 0573fbfc | ths | break;
|
5953 | aba9d61e | bellard | #if 1 |
5954 | 2c0262af | bellard | gen_debug(s, pc_start - s->cs_base); |
5955 | aba9d61e | bellard | #else
|
5956 | aba9d61e | bellard | /* start debug */
|
5957 | aba9d61e | bellard | tb_flush(cpu_single_env); |
5958 | aba9d61e | bellard | cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); |
5959 | aba9d61e | bellard | #endif
|
5960 | 2c0262af | bellard | break;
|
5961 | 2c0262af | bellard | case 0xfa: /* cli */ |
5962 | 2c0262af | bellard | if (!s->vm86) {
|
5963 | 2c0262af | bellard | if (s->cpl <= s->iopl) {
|
5964 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_cli); |
5965 | 2c0262af | bellard | } else {
|
5966 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
5967 | 2c0262af | bellard | } |
5968 | 2c0262af | bellard | } else {
|
5969 | 2c0262af | bellard | if (s->iopl == 3) { |
5970 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_cli); |
5971 | 2c0262af | bellard | } else {
|
5972 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
5973 | 2c0262af | bellard | } |
5974 | 2c0262af | bellard | } |
5975 | 2c0262af | bellard | break;
|
5976 | 2c0262af | bellard | case 0xfb: /* sti */ |
5977 | 2c0262af | bellard | if (!s->vm86) {
|
5978 | 2c0262af | bellard | if (s->cpl <= s->iopl) {
|
5979 | 2c0262af | bellard | gen_sti:
|
5980 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_sti); |
5981 | 2c0262af | bellard | /* interruptions are enabled only the first insn after sti */
|
5982 | a2cc3b24 | bellard | /* If several instructions disable interrupts, only the
|
5983 | a2cc3b24 | bellard | _first_ does it */
|
5984 | a2cc3b24 | bellard | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
|
5985 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_set_inhibit_irq); |
5986 | 2c0262af | bellard | /* give a chance to handle pending irqs */
|
5987 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
5988 | 2c0262af | bellard | gen_eob(s); |
5989 | 2c0262af | bellard | } else {
|
5990 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
5991 | 2c0262af | bellard | } |
5992 | 2c0262af | bellard | } else {
|
5993 | 2c0262af | bellard | if (s->iopl == 3) { |
5994 | 2c0262af | bellard | goto gen_sti;
|
5995 | 2c0262af | bellard | } else {
|
5996 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
5997 | 2c0262af | bellard | } |
5998 | 2c0262af | bellard | } |
5999 | 2c0262af | bellard | break;
|
6000 | 2c0262af | bellard | case 0x62: /* bound */ |
6001 | 14ce26e7 | bellard | if (CODE64(s))
|
6002 | 14ce26e7 | bellard | goto illegal_op;
|
6003 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6004 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6005 | 2c0262af | bellard | reg = (modrm >> 3) & 7; |
6006 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
6007 | 2c0262af | bellard | if (mod == 3) |
6008 | 2c0262af | bellard | goto illegal_op;
|
6009 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, reg);
|
6010 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6011 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6012 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
6013 | 2c0262af | bellard | if (ot == OT_WORD)
|
6014 | b6abf97d | bellard | tcg_gen_helper_0_2(helper_boundw, cpu_A0, cpu_tmp2_i32); |
6015 | 2c0262af | bellard | else
|
6016 | b6abf97d | bellard | tcg_gen_helper_0_2(helper_boundl, cpu_A0, cpu_tmp2_i32); |
6017 | 2c0262af | bellard | break;
|
6018 | 2c0262af | bellard | case 0x1c8 ... 0x1cf: /* bswap reg */ |
6019 | 14ce26e7 | bellard | reg = (b & 7) | REX_B(s);
|
6020 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
6021 | 14ce26e7 | bellard | if (dflag == 2) { |
6022 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_QUAD, 0, reg);
|
6023 | 57fec1fe | bellard | tcg_gen_bswap_i64(cpu_T[0], cpu_T[0]); |
6024 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_QUAD, reg); |
6025 | 5fafdf24 | ths | } else
|
6026 | 14ce26e7 | bellard | { |
6027 | ac56dd48 | pbrook | TCGv tmp0; |
6028 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, reg);
|
6029 | 57fec1fe | bellard | |
6030 | 57fec1fe | bellard | tmp0 = tcg_temp_new(TCG_TYPE_I32); |
6031 | 57fec1fe | bellard | tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]);
|
6032 | 57fec1fe | bellard | tcg_gen_bswap_i32(tmp0, tmp0); |
6033 | 57fec1fe | bellard | tcg_gen_extu_i32_i64(cpu_T[0], tmp0);
|
6034 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, reg); |
6035 | 57fec1fe | bellard | } |
6036 | 57fec1fe | bellard | #else
|
6037 | 57fec1fe | bellard | { |
6038 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, reg);
|
6039 | 57fec1fe | bellard | tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); |
6040 | 57fec1fe | bellard | gen_op_mov_reg_T0(OT_LONG, reg); |
6041 | 14ce26e7 | bellard | } |
6042 | 57fec1fe | bellard | #endif
|
6043 | 2c0262af | bellard | break;
|
6044 | 2c0262af | bellard | case 0xd6: /* salc */ |
6045 | 14ce26e7 | bellard | if (CODE64(s))
|
6046 | 14ce26e7 | bellard | goto illegal_op;
|
6047 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6048 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6049 | 2c0262af | bellard | gen_op_salc(); |
6050 | 2c0262af | bellard | break;
|
6051 | 2c0262af | bellard | case 0xe0: /* loopnz */ |
6052 | 2c0262af | bellard | case 0xe1: /* loopz */ |
6053 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6054 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6055 | 2c0262af | bellard | /* FALL THRU */
|
6056 | 2c0262af | bellard | case 0xe2: /* loop */ |
6057 | 2c0262af | bellard | case 0xe3: /* jecxz */ |
6058 | 14ce26e7 | bellard | { |
6059 | 14ce26e7 | bellard | int l1, l2;
|
6060 | 14ce26e7 | bellard | |
6061 | 14ce26e7 | bellard | tval = (int8_t)insn_get(s, OT_BYTE); |
6062 | 14ce26e7 | bellard | next_eip = s->pc - s->cs_base; |
6063 | 14ce26e7 | bellard | tval += next_eip; |
6064 | 14ce26e7 | bellard | if (s->dflag == 0) |
6065 | 14ce26e7 | bellard | tval &= 0xffff;
|
6066 | 3b46e624 | ths | |
6067 | 14ce26e7 | bellard | l1 = gen_new_label(); |
6068 | 14ce26e7 | bellard | l2 = gen_new_label(); |
6069 | 14ce26e7 | bellard | b &= 3;
|
6070 | 14ce26e7 | bellard | if (b == 3) { |
6071 | 14ce26e7 | bellard | gen_op_jz_ecx[s->aflag](l1); |
6072 | 14ce26e7 | bellard | } else {
|
6073 | 14ce26e7 | bellard | gen_op_dec_ECX[s->aflag](); |
6074 | 0b9dc5e4 | bellard | if (b <= 1) |
6075 | 0b9dc5e4 | bellard | gen_op_mov_T0_cc(); |
6076 | 14ce26e7 | bellard | gen_op_loop[s->aflag][b](l1); |
6077 | 14ce26e7 | bellard | } |
6078 | 14ce26e7 | bellard | |
6079 | 14ce26e7 | bellard | gen_jmp_im(next_eip); |
6080 | 14ce26e7 | bellard | gen_op_jmp_label(l2); |
6081 | 14ce26e7 | bellard | gen_set_label(l1); |
6082 | 14ce26e7 | bellard | gen_jmp_im(tval); |
6083 | 14ce26e7 | bellard | gen_set_label(l2); |
6084 | 14ce26e7 | bellard | gen_eob(s); |
6085 | 14ce26e7 | bellard | } |
6086 | 2c0262af | bellard | break;
|
6087 | 2c0262af | bellard | case 0x130: /* wrmsr */ |
6088 | 2c0262af | bellard | case 0x132: /* rdmsr */ |
6089 | 2c0262af | bellard | if (s->cpl != 0) { |
6090 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6091 | 2c0262af | bellard | } else {
|
6092 | 0573fbfc | ths | int retval = 0; |
6093 | 0573fbfc | ths | if (b & 2) { |
6094 | 0573fbfc | ths | retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 0);
|
6095 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_rdmsr); |
6096 | 0573fbfc | ths | } else {
|
6097 | 0573fbfc | ths | retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 1);
|
6098 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_wrmsr); |
6099 | 0573fbfc | ths | } |
6100 | 0573fbfc | ths | if(retval)
|
6101 | 0573fbfc | ths | gen_eob(s); |
6102 | 2c0262af | bellard | } |
6103 | 2c0262af | bellard | break;
|
6104 | 2c0262af | bellard | case 0x131: /* rdtsc */ |
6105 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RDTSC))
|
6106 | 0573fbfc | ths | break;
|
6107 | ecada8a2 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6108 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_rdtsc); |
6109 | 2c0262af | bellard | break;
|
6110 | df01e0fc | balrog | case 0x133: /* rdpmc */ |
6111 | df01e0fc | balrog | gen_jmp_im(pc_start - s->cs_base); |
6112 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_rdpmc); |
6113 | df01e0fc | balrog | break;
|
6114 | 023fe10d | bellard | case 0x134: /* sysenter */ |
6115 | 14ce26e7 | bellard | if (CODE64(s))
|
6116 | 14ce26e7 | bellard | goto illegal_op;
|
6117 | 023fe10d | bellard | if (!s->pe) {
|
6118 | 023fe10d | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6119 | 023fe10d | bellard | } else {
|
6120 | 023fe10d | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
6121 | 023fe10d | bellard | gen_op_set_cc_op(s->cc_op); |
6122 | 023fe10d | bellard | s->cc_op = CC_OP_DYNAMIC; |
6123 | 023fe10d | bellard | } |
6124 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6125 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_sysenter); |
6126 | 023fe10d | bellard | gen_eob(s); |
6127 | 023fe10d | bellard | } |
6128 | 023fe10d | bellard | break;
|
6129 | 023fe10d | bellard | case 0x135: /* sysexit */ |
6130 | 14ce26e7 | bellard | if (CODE64(s))
|
6131 | 14ce26e7 | bellard | goto illegal_op;
|
6132 | 023fe10d | bellard | if (!s->pe) {
|
6133 | 023fe10d | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6134 | 023fe10d | bellard | } else {
|
6135 | 023fe10d | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
6136 | 023fe10d | bellard | gen_op_set_cc_op(s->cc_op); |
6137 | 023fe10d | bellard | s->cc_op = CC_OP_DYNAMIC; |
6138 | 023fe10d | bellard | } |
6139 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6140 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_sysexit); |
6141 | 023fe10d | bellard | gen_eob(s); |
6142 | 023fe10d | bellard | } |
6143 | 023fe10d | bellard | break;
|
6144 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
6145 | 14ce26e7 | bellard | case 0x105: /* syscall */ |
6146 | 14ce26e7 | bellard | /* XXX: is it usable in real mode ? */
|
6147 | 14ce26e7 | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
6148 | 14ce26e7 | bellard | gen_op_set_cc_op(s->cc_op); |
6149 | 14ce26e7 | bellard | s->cc_op = CC_OP_DYNAMIC; |
6150 | 14ce26e7 | bellard | } |
6151 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6152 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_syscall, tcg_const_i32(s->pc - pc_start)); |
6153 | 14ce26e7 | bellard | gen_eob(s); |
6154 | 14ce26e7 | bellard | break;
|
6155 | 14ce26e7 | bellard | case 0x107: /* sysret */ |
6156 | 14ce26e7 | bellard | if (!s->pe) {
|
6157 | 14ce26e7 | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6158 | 14ce26e7 | bellard | } else {
|
6159 | 14ce26e7 | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
6160 | 14ce26e7 | bellard | gen_op_set_cc_op(s->cc_op); |
6161 | 14ce26e7 | bellard | s->cc_op = CC_OP_DYNAMIC; |
6162 | 14ce26e7 | bellard | } |
6163 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6164 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_sysret, tcg_const_i32(s->dflag)); |
6165 | aba9d61e | bellard | /* condition codes are modified only in long mode */
|
6166 | aba9d61e | bellard | if (s->lma)
|
6167 | aba9d61e | bellard | s->cc_op = CC_OP_EFLAGS; |
6168 | 14ce26e7 | bellard | gen_eob(s); |
6169 | 14ce26e7 | bellard | } |
6170 | 14ce26e7 | bellard | break;
|
6171 | 14ce26e7 | bellard | #endif
|
6172 | 2c0262af | bellard | case 0x1a2: /* cpuid */ |
6173 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CPUID))
|
6174 | 0573fbfc | ths | break;
|
6175 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_cpuid); |
6176 | 2c0262af | bellard | break;
|
6177 | 2c0262af | bellard | case 0xf4: /* hlt */ |
6178 | 2c0262af | bellard | if (s->cpl != 0) { |
6179 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6180 | 2c0262af | bellard | } else {
|
6181 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_HLT))
|
6182 | 0573fbfc | ths | break;
|
6183 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6184 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6185 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
6186 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_hlt); |
6187 | 2c0262af | bellard | s->is_jmp = 3;
|
6188 | 2c0262af | bellard | } |
6189 | 2c0262af | bellard | break;
|
6190 | 2c0262af | bellard | case 0x100: |
6191 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6192 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
6193 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
6194 | 2c0262af | bellard | switch(op) {
|
6195 | 2c0262af | bellard | case 0: /* sldt */ |
6196 | f115e911 | bellard | if (!s->pe || s->vm86)
|
6197 | f115e911 | bellard | goto illegal_op;
|
6198 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ))
|
6199 | 0573fbfc | ths | break;
|
6200 | 2c0262af | bellard | gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector)); |
6201 | 2c0262af | bellard | ot = OT_WORD; |
6202 | 2c0262af | bellard | if (mod == 3) |
6203 | 2c0262af | bellard | ot += s->dflag; |
6204 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
|
6205 | 2c0262af | bellard | break;
|
6206 | 2c0262af | bellard | case 2: /* lldt */ |
6207 | f115e911 | bellard | if (!s->pe || s->vm86)
|
6208 | f115e911 | bellard | goto illegal_op;
|
6209 | 2c0262af | bellard | if (s->cpl != 0) { |
6210 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6211 | 2c0262af | bellard | } else {
|
6212 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE))
|
6213 | 0573fbfc | ths | break;
|
6214 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
6215 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6216 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
6217 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_lldt, cpu_tmp2_i32); |
6218 | 2c0262af | bellard | } |
6219 | 2c0262af | bellard | break;
|
6220 | 2c0262af | bellard | case 1: /* str */ |
6221 | f115e911 | bellard | if (!s->pe || s->vm86)
|
6222 | f115e911 | bellard | goto illegal_op;
|
6223 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ))
|
6224 | 0573fbfc | ths | break;
|
6225 | 2c0262af | bellard | gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector)); |
6226 | 2c0262af | bellard | ot = OT_WORD; |
6227 | 2c0262af | bellard | if (mod == 3) |
6228 | 2c0262af | bellard | ot += s->dflag; |
6229 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
|
6230 | 2c0262af | bellard | break;
|
6231 | 2c0262af | bellard | case 3: /* ltr */ |
6232 | f115e911 | bellard | if (!s->pe || s->vm86)
|
6233 | f115e911 | bellard | goto illegal_op;
|
6234 | 2c0262af | bellard | if (s->cpl != 0) { |
6235 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6236 | 2c0262af | bellard | } else {
|
6237 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE))
|
6238 | 0573fbfc | ths | break;
|
6239 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
6240 | 14ce26e7 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6241 | b6abf97d | bellard | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
6242 | b6abf97d | bellard | tcg_gen_helper_0_1(helper_ltr, cpu_tmp2_i32); |
6243 | 2c0262af | bellard | } |
6244 | 2c0262af | bellard | break;
|
6245 | 2c0262af | bellard | case 4: /* verr */ |
6246 | 2c0262af | bellard | case 5: /* verw */ |
6247 | f115e911 | bellard | if (!s->pe || s->vm86)
|
6248 | f115e911 | bellard | goto illegal_op;
|
6249 | f115e911 | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
6250 | f115e911 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6251 | f115e911 | bellard | gen_op_set_cc_op(s->cc_op); |
6252 | f115e911 | bellard | if (op == 4) |
6253 | f115e911 | bellard | gen_op_verr(); |
6254 | f115e911 | bellard | else
|
6255 | f115e911 | bellard | gen_op_verw(); |
6256 | f115e911 | bellard | s->cc_op = CC_OP_EFLAGS; |
6257 | f115e911 | bellard | break;
|
6258 | 2c0262af | bellard | default:
|
6259 | 2c0262af | bellard | goto illegal_op;
|
6260 | 2c0262af | bellard | } |
6261 | 2c0262af | bellard | break;
|
6262 | 2c0262af | bellard | case 0x101: |
6263 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6264 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
6265 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
6266 | 3d7374c5 | bellard | rm = modrm & 7;
|
6267 | 2c0262af | bellard | switch(op) {
|
6268 | 2c0262af | bellard | case 0: /* sgdt */ |
6269 | 2c0262af | bellard | if (mod == 3) |
6270 | 2c0262af | bellard | goto illegal_op;
|
6271 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ))
|
6272 | 0573fbfc | ths | break;
|
6273 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6274 | 3d7374c5 | bellard | gen_op_movl_T0_env(offsetof(CPUX86State, gdt.limit)); |
6275 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
6276 | aba9d61e | bellard | gen_add_A0_im(s, 2);
|
6277 | 3d7374c5 | bellard | gen_op_movtl_T0_env(offsetof(CPUX86State, gdt.base)); |
6278 | 2c0262af | bellard | if (!s->dflag)
|
6279 | 2c0262af | bellard | gen_op_andl_T0_im(0xffffff);
|
6280 | 57fec1fe | bellard | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
6281 | 2c0262af | bellard | break;
|
6282 | 3d7374c5 | bellard | case 1: |
6283 | 3d7374c5 | bellard | if (mod == 3) { |
6284 | 3d7374c5 | bellard | switch (rm) {
|
6285 | 3d7374c5 | bellard | case 0: /* monitor */ |
6286 | 3d7374c5 | bellard | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
|
6287 | 3d7374c5 | bellard | s->cpl != 0)
|
6288 | 3d7374c5 | bellard | goto illegal_op;
|
6289 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MONITOR))
|
6290 | 0573fbfc | ths | break;
|
6291 | 3d7374c5 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6292 | 3d7374c5 | bellard | #ifdef TARGET_X86_64
|
6293 | 3d7374c5 | bellard | if (s->aflag == 2) { |
6294 | 57fec1fe | bellard | gen_op_movq_A0_reg(R_EBX); |
6295 | 3d7374c5 | bellard | gen_op_addq_A0_AL(); |
6296 | 5fafdf24 | ths | } else
|
6297 | 3d7374c5 | bellard | #endif
|
6298 | 3d7374c5 | bellard | { |
6299 | 57fec1fe | bellard | gen_op_movl_A0_reg(R_EBX); |
6300 | 3d7374c5 | bellard | gen_op_addl_A0_AL(); |
6301 | 3d7374c5 | bellard | if (s->aflag == 0) |
6302 | 3d7374c5 | bellard | gen_op_andl_A0_ffff(); |
6303 | 3d7374c5 | bellard | } |
6304 | 3d7374c5 | bellard | gen_add_A0_ds_seg(s); |
6305 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_monitor, cpu_A0); |
6306 | 3d7374c5 | bellard | break;
|
6307 | 3d7374c5 | bellard | case 1: /* mwait */ |
6308 | 3d7374c5 | bellard | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
|
6309 | 3d7374c5 | bellard | s->cpl != 0)
|
6310 | 3d7374c5 | bellard | goto illegal_op;
|
6311 | 3d7374c5 | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
6312 | 3d7374c5 | bellard | gen_op_set_cc_op(s->cc_op); |
6313 | 3d7374c5 | bellard | s->cc_op = CC_OP_DYNAMIC; |
6314 | 3d7374c5 | bellard | } |
6315 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MWAIT))
|
6316 | 0573fbfc | ths | break;
|
6317 | 3d7374c5 | bellard | gen_jmp_im(s->pc - s->cs_base); |
6318 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_mwait); |
6319 | 3d7374c5 | bellard | gen_eob(s); |
6320 | 3d7374c5 | bellard | break;
|
6321 | 3d7374c5 | bellard | default:
|
6322 | 3d7374c5 | bellard | goto illegal_op;
|
6323 | 3d7374c5 | bellard | } |
6324 | 3d7374c5 | bellard | } else { /* sidt */ |
6325 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ))
|
6326 | 0573fbfc | ths | break;
|
6327 | 3d7374c5 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6328 | 3d7374c5 | bellard | gen_op_movl_T0_env(offsetof(CPUX86State, idt.limit)); |
6329 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
6330 | 3d7374c5 | bellard | gen_add_A0_im(s, 2);
|
6331 | 3d7374c5 | bellard | gen_op_movtl_T0_env(offsetof(CPUX86State, idt.base)); |
6332 | 3d7374c5 | bellard | if (!s->dflag)
|
6333 | 3d7374c5 | bellard | gen_op_andl_T0_im(0xffffff);
|
6334 | 57fec1fe | bellard | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
6335 | 3d7374c5 | bellard | } |
6336 | 3d7374c5 | bellard | break;
|
6337 | 2c0262af | bellard | case 2: /* lgdt */ |
6338 | 2c0262af | bellard | case 3: /* lidt */ |
6339 | 0573fbfc | ths | if (mod == 3) { |
6340 | 0573fbfc | ths | switch(rm) {
|
6341 | 0573fbfc | ths | case 0: /* VMRUN */ |
6342 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMRUN))
|
6343 | 0573fbfc | ths | break;
|
6344 | 0573fbfc | ths | if (s->cc_op != CC_OP_DYNAMIC)
|
6345 | 0573fbfc | ths | gen_op_set_cc_op(s->cc_op); |
6346 | 0573fbfc | ths | gen_jmp_im(s->pc - s->cs_base); |
6347 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_vmrun); |
6348 | 0573fbfc | ths | s->cc_op = CC_OP_EFLAGS; |
6349 | 0573fbfc | ths | gen_eob(s); |
6350 | 0573fbfc | ths | break;
|
6351 | 0573fbfc | ths | case 1: /* VMMCALL */ |
6352 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMMCALL))
|
6353 | 0573fbfc | ths | break;
|
6354 | 0573fbfc | ths | /* FIXME: cause #UD if hflags & SVM */
|
6355 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_vmmcall); |
6356 | 0573fbfc | ths | break;
|
6357 | 0573fbfc | ths | case 2: /* VMLOAD */ |
6358 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMLOAD))
|
6359 | 0573fbfc | ths | break;
|
6360 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_vmload); |
6361 | 0573fbfc | ths | break;
|
6362 | 0573fbfc | ths | case 3: /* VMSAVE */ |
6363 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMSAVE))
|
6364 | 0573fbfc | ths | break;
|
6365 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_vmsave); |
6366 | 0573fbfc | ths | break;
|
6367 | 0573fbfc | ths | case 4: /* STGI */ |
6368 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_STGI))
|
6369 | 0573fbfc | ths | break;
|
6370 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_stgi); |
6371 | 0573fbfc | ths | break;
|
6372 | 0573fbfc | ths | case 5: /* CLGI */ |
6373 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CLGI))
|
6374 | 0573fbfc | ths | break;
|
6375 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_clgi); |
6376 | 0573fbfc | ths | break;
|
6377 | 0573fbfc | ths | case 6: /* SKINIT */ |
6378 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SKINIT))
|
6379 | 0573fbfc | ths | break;
|
6380 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_skinit); |
6381 | 0573fbfc | ths | break;
|
6382 | 0573fbfc | ths | case 7: /* INVLPGA */ |
6383 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPGA))
|
6384 | 0573fbfc | ths | break;
|
6385 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_invlpga); |
6386 | 0573fbfc | ths | break;
|
6387 | 0573fbfc | ths | default:
|
6388 | 0573fbfc | ths | goto illegal_op;
|
6389 | 0573fbfc | ths | } |
6390 | 0573fbfc | ths | } else if (s->cpl != 0) { |
6391 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6392 | 2c0262af | bellard | } else {
|
6393 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start,
|
6394 | 0573fbfc | ths | op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE))
|
6395 | 0573fbfc | ths | break;
|
6396 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6397 | 57fec1fe | bellard | gen_op_ld_T1_A0(OT_WORD + s->mem_index); |
6398 | aba9d61e | bellard | gen_add_A0_im(s, 2);
|
6399 | 57fec1fe | bellard | gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
6400 | 2c0262af | bellard | if (!s->dflag)
|
6401 | 2c0262af | bellard | gen_op_andl_T0_im(0xffffff);
|
6402 | 2c0262af | bellard | if (op == 2) { |
6403 | 14ce26e7 | bellard | gen_op_movtl_env_T0(offsetof(CPUX86State,gdt.base)); |
6404 | 2c0262af | bellard | gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit)); |
6405 | 2c0262af | bellard | } else {
|
6406 | 14ce26e7 | bellard | gen_op_movtl_env_T0(offsetof(CPUX86State,idt.base)); |
6407 | 2c0262af | bellard | gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit)); |
6408 | 2c0262af | bellard | } |
6409 | 2c0262af | bellard | } |
6410 | 2c0262af | bellard | break;
|
6411 | 2c0262af | bellard | case 4: /* smsw */ |
6412 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0))
|
6413 | 0573fbfc | ths | break;
|
6414 | 2c0262af | bellard | gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
|
6415 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
|
6416 | 2c0262af | bellard | break;
|
6417 | 2c0262af | bellard | case 6: /* lmsw */ |
6418 | 2c0262af | bellard | if (s->cpl != 0) { |
6419 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6420 | 2c0262af | bellard | } else {
|
6421 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0))
|
6422 | 0573fbfc | ths | break;
|
6423 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
|
6424 | b8b6a50b | bellard | tcg_gen_helper_0_1(helper_lmsw, cpu_T[0]);
|
6425 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
6426 | d71b9a8b | bellard | gen_eob(s); |
6427 | 2c0262af | bellard | } |
6428 | 2c0262af | bellard | break;
|
6429 | 2c0262af | bellard | case 7: /* invlpg */ |
6430 | 2c0262af | bellard | if (s->cpl != 0) { |
6431 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6432 | 2c0262af | bellard | } else {
|
6433 | 14ce26e7 | bellard | if (mod == 3) { |
6434 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
6435 | 3d7374c5 | bellard | if (CODE64(s) && rm == 0) { |
6436 | 14ce26e7 | bellard | /* swapgs */
|
6437 | 14ce26e7 | bellard | gen_op_movtl_T0_env(offsetof(CPUX86State,segs[R_GS].base)); |
6438 | 14ce26e7 | bellard | gen_op_movtl_T1_env(offsetof(CPUX86State,kernelgsbase)); |
6439 | 14ce26e7 | bellard | gen_op_movtl_env_T1(offsetof(CPUX86State,segs[R_GS].base)); |
6440 | 14ce26e7 | bellard | gen_op_movtl_env_T0(offsetof(CPUX86State,kernelgsbase)); |
6441 | 5fafdf24 | ths | } else
|
6442 | 14ce26e7 | bellard | #endif
|
6443 | 14ce26e7 | bellard | { |
6444 | 14ce26e7 | bellard | goto illegal_op;
|
6445 | 14ce26e7 | bellard | } |
6446 | 14ce26e7 | bellard | } else {
|
6447 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPG))
|
6448 | 0573fbfc | ths | break;
|
6449 | 14ce26e7 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6450 | b5b38f61 | bellard | tcg_gen_helper_0_1(helper_invlpg, cpu_A0); |
6451 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
6452 | 14ce26e7 | bellard | gen_eob(s); |
6453 | 14ce26e7 | bellard | } |
6454 | 2c0262af | bellard | } |
6455 | 2c0262af | bellard | break;
|
6456 | 2c0262af | bellard | default:
|
6457 | 2c0262af | bellard | goto illegal_op;
|
6458 | 2c0262af | bellard | } |
6459 | 2c0262af | bellard | break;
|
6460 | 3415a4dd | bellard | case 0x108: /* invd */ |
6461 | 3415a4dd | bellard | case 0x109: /* wbinvd */ |
6462 | 3415a4dd | bellard | if (s->cpl != 0) { |
6463 | 3415a4dd | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6464 | 3415a4dd | bellard | } else {
|
6465 | ad848875 | balrog | if (gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD)) |
6466 | 0573fbfc | ths | break;
|
6467 | 3415a4dd | bellard | /* nothing to do */
|
6468 | 3415a4dd | bellard | } |
6469 | 3415a4dd | bellard | break;
|
6470 | 14ce26e7 | bellard | case 0x63: /* arpl or movslS (x86_64) */ |
6471 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
6472 | 14ce26e7 | bellard | if (CODE64(s)) {
|
6473 | 14ce26e7 | bellard | int d_ot;
|
6474 | 14ce26e7 | bellard | /* d_ot is the size of destination */
|
6475 | 14ce26e7 | bellard | d_ot = dflag + OT_WORD; |
6476 | 14ce26e7 | bellard | |
6477 | 14ce26e7 | bellard | modrm = ldub_code(s->pc++); |
6478 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
6479 | 14ce26e7 | bellard | mod = (modrm >> 6) & 3; |
6480 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
6481 | 3b46e624 | ths | |
6482 | 14ce26e7 | bellard | if (mod == 3) { |
6483 | 57fec1fe | bellard | gen_op_mov_TN_reg(OT_LONG, 0, rm);
|
6484 | 14ce26e7 | bellard | /* sign extend */
|
6485 | 14ce26e7 | bellard | if (d_ot == OT_QUAD)
|
6486 | 14ce26e7 | bellard | gen_op_movslq_T0_T0(); |
6487 | 57fec1fe | bellard | gen_op_mov_reg_T0(d_ot, reg); |
6488 | 14ce26e7 | bellard | } else {
|
6489 | 14ce26e7 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6490 | 14ce26e7 | bellard | if (d_ot == OT_QUAD) {
|
6491 | 57fec1fe | bellard | gen_op_lds_T0_A0(OT_LONG + s->mem_index); |
6492 | 14ce26e7 | bellard | } else {
|
6493 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
6494 | 14ce26e7 | bellard | } |
6495 | 57fec1fe | bellard | gen_op_mov_reg_T0(d_ot, reg); |
6496 | 14ce26e7 | bellard | } |
6497 | 5fafdf24 | ths | } else
|
6498 | 14ce26e7 | bellard | #endif
|
6499 | 14ce26e7 | bellard | { |
6500 | 14ce26e7 | bellard | if (!s->pe || s->vm86)
|
6501 | 14ce26e7 | bellard | goto illegal_op;
|
6502 | 14ce26e7 | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6503 | 14ce26e7 | bellard | modrm = ldub_code(s->pc++); |
6504 | 14ce26e7 | bellard | reg = (modrm >> 3) & 7; |
6505 | 14ce26e7 | bellard | mod = (modrm >> 6) & 3; |
6506 | 14ce26e7 | bellard | rm = modrm & 7;
|
6507 | 14ce26e7 | bellard | if (mod != 3) { |
6508 | 14ce26e7 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6509 | 57fec1fe | bellard | gen_op_ld_T0_A0(ot + s->mem_index); |
6510 | 14ce26e7 | bellard | } else {
|
6511 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
6512 | 14ce26e7 | bellard | } |
6513 | b8b6a50b | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
6514 | 14ce26e7 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6515 | 14ce26e7 | bellard | gen_op_set_cc_op(s->cc_op); |
6516 | 14ce26e7 | bellard | gen_op_arpl(); |
6517 | 14ce26e7 | bellard | s->cc_op = CC_OP_EFLAGS; |
6518 | 14ce26e7 | bellard | if (mod != 3) { |
6519 | 57fec1fe | bellard | gen_op_st_T0_A0(ot + s->mem_index); |
6520 | 14ce26e7 | bellard | } else {
|
6521 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
6522 | 14ce26e7 | bellard | } |
6523 | 14ce26e7 | bellard | gen_op_arpl_update(); |
6524 | f115e911 | bellard | } |
6525 | f115e911 | bellard | break;
|
6526 | 2c0262af | bellard | case 0x102: /* lar */ |
6527 | 2c0262af | bellard | case 0x103: /* lsl */ |
6528 | 2c0262af | bellard | if (!s->pe || s->vm86)
|
6529 | 2c0262af | bellard | goto illegal_op;
|
6530 | 2c0262af | bellard | ot = dflag ? OT_LONG : OT_WORD; |
6531 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6532 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
6533 | 2c0262af | bellard | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
|
6534 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 1, reg);
|
6535 | 2c0262af | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6536 | 2c0262af | bellard | gen_op_set_cc_op(s->cc_op); |
6537 | 2c0262af | bellard | if (b == 0x102) |
6538 | 2c0262af | bellard | gen_op_lar(); |
6539 | 2c0262af | bellard | else
|
6540 | 2c0262af | bellard | gen_op_lsl(); |
6541 | 2c0262af | bellard | s->cc_op = CC_OP_EFLAGS; |
6542 | 57fec1fe | bellard | gen_op_mov_reg_T1(ot, reg); |
6543 | 2c0262af | bellard | break;
|
6544 | 2c0262af | bellard | case 0x118: |
6545 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6546 | 2c0262af | bellard | mod = (modrm >> 6) & 3; |
6547 | 2c0262af | bellard | op = (modrm >> 3) & 7; |
6548 | 2c0262af | bellard | switch(op) {
|
6549 | 2c0262af | bellard | case 0: /* prefetchnta */ |
6550 | 2c0262af | bellard | case 1: /* prefetchnt0 */ |
6551 | 2c0262af | bellard | case 2: /* prefetchnt0 */ |
6552 | 2c0262af | bellard | case 3: /* prefetchnt0 */ |
6553 | 2c0262af | bellard | if (mod == 3) |
6554 | 2c0262af | bellard | goto illegal_op;
|
6555 | 2c0262af | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6556 | 2c0262af | bellard | /* nothing more to do */
|
6557 | 2c0262af | bellard | break;
|
6558 | e17a36ce | bellard | default: /* nop (multi byte) */ |
6559 | e17a36ce | bellard | gen_nop_modrm(s, modrm); |
6560 | e17a36ce | bellard | break;
|
6561 | 2c0262af | bellard | } |
6562 | 2c0262af | bellard | break;
|
6563 | e17a36ce | bellard | case 0x119 ... 0x11f: /* nop (multi byte) */ |
6564 | e17a36ce | bellard | modrm = ldub_code(s->pc++); |
6565 | e17a36ce | bellard | gen_nop_modrm(s, modrm); |
6566 | e17a36ce | bellard | break;
|
6567 | 2c0262af | bellard | case 0x120: /* mov reg, crN */ |
6568 | 2c0262af | bellard | case 0x122: /* mov crN, reg */ |
6569 | 2c0262af | bellard | if (s->cpl != 0) { |
6570 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6571 | 2c0262af | bellard | } else {
|
6572 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6573 | 2c0262af | bellard | if ((modrm & 0xc0) != 0xc0) |
6574 | 2c0262af | bellard | goto illegal_op;
|
6575 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
6576 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
6577 | 14ce26e7 | bellard | if (CODE64(s))
|
6578 | 14ce26e7 | bellard | ot = OT_QUAD; |
6579 | 14ce26e7 | bellard | else
|
6580 | 14ce26e7 | bellard | ot = OT_LONG; |
6581 | 2c0262af | bellard | switch(reg) {
|
6582 | 2c0262af | bellard | case 0: |
6583 | 2c0262af | bellard | case 2: |
6584 | 2c0262af | bellard | case 3: |
6585 | 2c0262af | bellard | case 4: |
6586 | 9230e66e | bellard | case 8: |
6587 | 2c0262af | bellard | if (b & 2) { |
6588 | 0573fbfc | ths | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0 + reg); |
6589 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
6590 | b8b6a50b | bellard | tcg_gen_helper_0_2(helper_movl_crN_T0, |
6591 | b8b6a50b | bellard | tcg_const_i32(reg), cpu_T[0]);
|
6592 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
6593 | 2c0262af | bellard | gen_eob(s); |
6594 | 2c0262af | bellard | } else {
|
6595 | 0573fbfc | ths | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0 + reg); |
6596 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
6597 | 9230e66e | bellard | if (reg == 8) |
6598 | b8b6a50b | bellard | tcg_gen_helper_1_0(helper_movtl_T0_cr8, cpu_T[0]);
|
6599 | 9230e66e | bellard | else
|
6600 | 82e41634 | bellard | #endif
|
6601 | 9230e66e | bellard | gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg])); |
6602 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
6603 | 2c0262af | bellard | } |
6604 | 2c0262af | bellard | break;
|
6605 | 2c0262af | bellard | default:
|
6606 | 2c0262af | bellard | goto illegal_op;
|
6607 | 2c0262af | bellard | } |
6608 | 2c0262af | bellard | } |
6609 | 2c0262af | bellard | break;
|
6610 | 2c0262af | bellard | case 0x121: /* mov reg, drN */ |
6611 | 2c0262af | bellard | case 0x123: /* mov drN, reg */ |
6612 | 2c0262af | bellard | if (s->cpl != 0) { |
6613 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6614 | 2c0262af | bellard | } else {
|
6615 | 61382a50 | bellard | modrm = ldub_code(s->pc++); |
6616 | 2c0262af | bellard | if ((modrm & 0xc0) != 0xc0) |
6617 | 2c0262af | bellard | goto illegal_op;
|
6618 | 14ce26e7 | bellard | rm = (modrm & 7) | REX_B(s);
|
6619 | 14ce26e7 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
6620 | 14ce26e7 | bellard | if (CODE64(s))
|
6621 | 14ce26e7 | bellard | ot = OT_QUAD; |
6622 | 14ce26e7 | bellard | else
|
6623 | 14ce26e7 | bellard | ot = OT_LONG; |
6624 | 2c0262af | bellard | /* XXX: do it dynamically with CR4.DE bit */
|
6625 | 14ce26e7 | bellard | if (reg == 4 || reg == 5 || reg >= 8) |
6626 | 2c0262af | bellard | goto illegal_op;
|
6627 | 2c0262af | bellard | if (b & 2) { |
6628 | 0573fbfc | ths | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); |
6629 | 57fec1fe | bellard | gen_op_mov_TN_reg(ot, 0, rm);
|
6630 | b8b6a50b | bellard | tcg_gen_helper_0_2(helper_movl_drN_T0, |
6631 | b8b6a50b | bellard | tcg_const_i32(reg), cpu_T[0]);
|
6632 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
6633 | 2c0262af | bellard | gen_eob(s); |
6634 | 2c0262af | bellard | } else {
|
6635 | 0573fbfc | ths | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); |
6636 | 14ce26e7 | bellard | gen_op_movtl_T0_env(offsetof(CPUX86State,dr[reg])); |
6637 | 57fec1fe | bellard | gen_op_mov_reg_T0(ot, rm); |
6638 | 2c0262af | bellard | } |
6639 | 2c0262af | bellard | } |
6640 | 2c0262af | bellard | break;
|
6641 | 2c0262af | bellard | case 0x106: /* clts */ |
6642 | 2c0262af | bellard | if (s->cpl != 0) { |
6643 | 2c0262af | bellard | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
6644 | 2c0262af | bellard | } else {
|
6645 | 0573fbfc | ths | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
6646 | b8b6a50b | bellard | tcg_gen_helper_0_0(helper_clts); |
6647 | 7eee2a50 | bellard | /* abort block because static cpu state changed */
|
6648 | 14ce26e7 | bellard | gen_jmp_im(s->pc - s->cs_base); |
6649 | 7eee2a50 | bellard | gen_eob(s); |
6650 | 2c0262af | bellard | } |
6651 | 2c0262af | bellard | break;
|
6652 | a35f3ec7 | aurel32 | /* MMX/3DNow!/SSE/SSE2/SSE3 support */
|
6653 | 664e0f19 | bellard | case 0x1c3: /* MOVNTI reg, mem */ |
6654 | 664e0f19 | bellard | if (!(s->cpuid_features & CPUID_SSE2))
|
6655 | 14ce26e7 | bellard | goto illegal_op;
|
6656 | 664e0f19 | bellard | ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
|
6657 | 664e0f19 | bellard | modrm = ldub_code(s->pc++); |
6658 | 664e0f19 | bellard | mod = (modrm >> 6) & 3; |
6659 | 664e0f19 | bellard | if (mod == 3) |
6660 | 664e0f19 | bellard | goto illegal_op;
|
6661 | 664e0f19 | bellard | reg = ((modrm >> 3) & 7) | rex_r; |
6662 | 664e0f19 | bellard | /* generate a generic store */
|
6663 | 664e0f19 | bellard | gen_ldst_modrm(s, modrm, ot, reg, 1);
|
6664 | 14ce26e7 | bellard | break;
|
6665 | 664e0f19 | bellard | case 0x1ae: |
6666 | 664e0f19 | bellard | modrm = ldub_code(s->pc++); |
6667 | 664e0f19 | bellard | mod = (modrm >> 6) & 3; |
6668 | 664e0f19 | bellard | op = (modrm >> 3) & 7; |
6669 | 664e0f19 | bellard | switch(op) {
|
6670 | 664e0f19 | bellard | case 0: /* fxsave */ |
6671 | 5fafdf24 | ths | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
6672 | 0fd14b72 | bellard | (s->flags & HF_EM_MASK)) |
6673 | 14ce26e7 | bellard | goto illegal_op;
|
6674 | 0fd14b72 | bellard | if (s->flags & HF_TS_MASK) {
|
6675 | 0fd14b72 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
6676 | 0fd14b72 | bellard | break;
|
6677 | 0fd14b72 | bellard | } |
6678 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6679 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6680 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
6681 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6682 | 19e6c4b8 | bellard | tcg_gen_helper_0_2(helper_fxsave, |
6683 | 19e6c4b8 | bellard | cpu_A0, tcg_const_i32((s->dflag == 2)));
|
6684 | 664e0f19 | bellard | break;
|
6685 | 664e0f19 | bellard | case 1: /* fxrstor */ |
6686 | 5fafdf24 | ths | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
6687 | 0fd14b72 | bellard | (s->flags & HF_EM_MASK)) |
6688 | 14ce26e7 | bellard | goto illegal_op;
|
6689 | 0fd14b72 | bellard | if (s->flags & HF_TS_MASK) {
|
6690 | 0fd14b72 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
6691 | 0fd14b72 | bellard | break;
|
6692 | 0fd14b72 | bellard | } |
6693 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6694 | 19e6c4b8 | bellard | if (s->cc_op != CC_OP_DYNAMIC)
|
6695 | 19e6c4b8 | bellard | gen_op_set_cc_op(s->cc_op); |
6696 | 19e6c4b8 | bellard | gen_jmp_im(pc_start - s->cs_base); |
6697 | 19e6c4b8 | bellard | tcg_gen_helper_0_2(helper_fxrstor, |
6698 | 19e6c4b8 | bellard | cpu_A0, tcg_const_i32((s->dflag == 2)));
|
6699 | 664e0f19 | bellard | break;
|
6700 | 664e0f19 | bellard | case 2: /* ldmxcsr */ |
6701 | 664e0f19 | bellard | case 3: /* stmxcsr */ |
6702 | 664e0f19 | bellard | if (s->flags & HF_TS_MASK) {
|
6703 | 664e0f19 | bellard | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
6704 | 664e0f19 | bellard | break;
|
6705 | 14ce26e7 | bellard | } |
6706 | 664e0f19 | bellard | if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
|
6707 | 664e0f19 | bellard | mod == 3)
|
6708 | 14ce26e7 | bellard | goto illegal_op;
|
6709 | 664e0f19 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6710 | 664e0f19 | bellard | if (op == 2) { |
6711 | 57fec1fe | bellard | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
6712 | 664e0f19 | bellard | gen_op_movl_env_T0(offsetof(CPUX86State, mxcsr)); |
6713 | 14ce26e7 | bellard | } else {
|
6714 | 664e0f19 | bellard | gen_op_movl_T0_env(offsetof(CPUX86State, mxcsr)); |
6715 | 57fec1fe | bellard | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
6716 | 14ce26e7 | bellard | } |
6717 | 664e0f19 | bellard | break;
|
6718 | 664e0f19 | bellard | case 5: /* lfence */ |
6719 | 664e0f19 | bellard | case 6: /* mfence */ |
6720 | 664e0f19 | bellard | if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE)) |
6721 | 664e0f19 | bellard | goto illegal_op;
|
6722 | 664e0f19 | bellard | break;
|
6723 | 8f091a59 | bellard | case 7: /* sfence / clflush */ |
6724 | 8f091a59 | bellard | if ((modrm & 0xc7) == 0xc0) { |
6725 | 8f091a59 | bellard | /* sfence */
|
6726 | a35f3ec7 | aurel32 | /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
|
6727 | 8f091a59 | bellard | if (!(s->cpuid_features & CPUID_SSE))
|
6728 | 8f091a59 | bellard | goto illegal_op;
|
6729 | 8f091a59 | bellard | } else {
|
6730 | 8f091a59 | bellard | /* clflush */
|
6731 | 8f091a59 | bellard | if (!(s->cpuid_features & CPUID_CLFLUSH))
|
6732 | 8f091a59 | bellard | goto illegal_op;
|
6733 | 8f091a59 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6734 | 8f091a59 | bellard | } |
6735 | 8f091a59 | bellard | break;
|
6736 | 664e0f19 | bellard | default:
|
6737 | 14ce26e7 | bellard | goto illegal_op;
|
6738 | 14ce26e7 | bellard | } |
6739 | 14ce26e7 | bellard | break;
|
6740 | a35f3ec7 | aurel32 | case 0x10d: /* 3DNow! prefetch(w) */ |
6741 | 8f091a59 | bellard | modrm = ldub_code(s->pc++); |
6742 | a35f3ec7 | aurel32 | mod = (modrm >> 6) & 3; |
6743 | a35f3ec7 | aurel32 | if (mod == 3) |
6744 | a35f3ec7 | aurel32 | goto illegal_op;
|
6745 | 8f091a59 | bellard | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
6746 | 8f091a59 | bellard | /* ignore for now */
|
6747 | 8f091a59 | bellard | break;
|
6748 | 3b21e03e | bellard | case 0x1aa: /* rsm */ |
6749 | 0573fbfc | ths | if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM))
|
6750 | 0573fbfc | ths | break;
|
6751 | 3b21e03e | bellard | if (!(s->flags & HF_SMM_MASK))
|
6752 | 3b21e03e | bellard | goto illegal_op;
|
6753 | 3b21e03e | bellard | if (s->cc_op != CC_OP_DYNAMIC) {
|
6754 | 3b21e03e | bellard | gen_op_set_cc_op(s->cc_op); |
6755 | 3b21e03e | bellard | s->cc_op = CC_OP_DYNAMIC; |
6756 | 3b21e03e | bellard | } |
6757 | 3b21e03e | bellard | gen_jmp_im(s->pc - s->cs_base); |
6758 | b5b38f61 | bellard | tcg_gen_helper_0_0(helper_rsm); |
6759 | 3b21e03e | bellard | gen_eob(s); |
6760 | 3b21e03e | bellard | break;
|
6761 | a35f3ec7 | aurel32 | case 0x10e ... 0x10f: |
6762 | a35f3ec7 | aurel32 | /* 3DNow! instructions, ignore prefixes */
|
6763 | a35f3ec7 | aurel32 | s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); |
6764 | 664e0f19 | bellard | case 0x110 ... 0x117: |
6765 | 664e0f19 | bellard | case 0x128 ... 0x12f: |
6766 | 664e0f19 | bellard | case 0x150 ... 0x177: |
6767 | 664e0f19 | bellard | case 0x17c ... 0x17f: |
6768 | 664e0f19 | bellard | case 0x1c2: |
6769 | 664e0f19 | bellard | case 0x1c4 ... 0x1c6: |
6770 | 664e0f19 | bellard | case 0x1d0 ... 0x1fe: |
6771 | 664e0f19 | bellard | gen_sse(s, b, pc_start, rex_r); |
6772 | 664e0f19 | bellard | break;
|
6773 | 2c0262af | bellard | default:
|
6774 | 2c0262af | bellard | goto illegal_op;
|
6775 | 2c0262af | bellard | } |
6776 | 2c0262af | bellard | /* lock generation */
|
6777 | 2c0262af | bellard | if (s->prefix & PREFIX_LOCK)
|
6778 | b8b6a50b | bellard | tcg_gen_helper_0_0(helper_unlock); |
6779 | 2c0262af | bellard | return s->pc;
|
6780 | 2c0262af | bellard | illegal_op:
|
6781 | ab1f142b | bellard | if (s->prefix & PREFIX_LOCK)
|
6782 | b8b6a50b | bellard | tcg_gen_helper_0_0(helper_unlock); |
6783 | 2c0262af | bellard | /* XXX: ensure that no lock was generated */
|
6784 | 2c0262af | bellard | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); |
6785 | 2c0262af | bellard | return s->pc;
|
6786 | 2c0262af | bellard | } |
6787 | 2c0262af | bellard | |
6788 | 57fec1fe | bellard | static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args) |
6789 | 57fec1fe | bellard | { |
6790 | 57fec1fe | bellard | switch(macro_id) {
|
6791 | 57fec1fe | bellard | #ifdef MACRO_TEST
|
6792 | 57fec1fe | bellard | case MACRO_TEST:
|
6793 | 57fec1fe | bellard | tcg_gen_helper_0_1(helper_divl_EAX_T0, cpu_T[0]);
|
6794 | 57fec1fe | bellard | break;
|
6795 | 57fec1fe | bellard | #endif
|
6796 | 57fec1fe | bellard | } |
6797 | 57fec1fe | bellard | } |
6798 | 57fec1fe | bellard | |
6799 | 2c0262af | bellard | void optimize_flags_init(void) |
6800 | 2c0262af | bellard | { |
6801 | b6abf97d | bellard | #if TCG_TARGET_REG_BITS == 32 |
6802 | b6abf97d | bellard | assert(sizeof(CCTable) == (1 << 3)); |
6803 | b6abf97d | bellard | #else
|
6804 | b6abf97d | bellard | assert(sizeof(CCTable) == (1 << 4)); |
6805 | b6abf97d | bellard | #endif
|
6806 | 57fec1fe | bellard | tcg_set_macro_func(&tcg_ctx, tcg_macro_func); |
6807 | 57fec1fe | bellard | |
6808 | 57fec1fe | bellard | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
|
6809 | 57fec1fe | bellard | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
6810 | 57fec1fe | bellard | cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
|
6811 | 57fec1fe | bellard | TCG_AREG0, offsetof(CPUState, t0), "T0");
|
6812 | 57fec1fe | bellard | cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
|
6813 | 57fec1fe | bellard | TCG_AREG0, offsetof(CPUState, t1), "T1");
|
6814 | 57fec1fe | bellard | cpu_A0 = tcg_global_mem_new(TCG_TYPE_TL, |
6815 | 57fec1fe | bellard | TCG_AREG0, offsetof(CPUState, t2), "A0");
|
6816 | 57fec1fe | bellard | #else
|
6817 | 57fec1fe | bellard | cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); |
6818 | 57fec1fe | bellard | cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); |
6819 | 57fec1fe | bellard | cpu_A0 = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "A0");
|
6820 | 3bd8c5e4 | bellard | #endif
|
6821 | b6abf97d | bellard | cpu_T3 = tcg_global_mem_new(TCG_TYPE_TL, |
6822 | b6abf97d | bellard | TCG_AREG0, offsetof(CPUState, t3), "T3");
|
6823 | b8b6a50b | bellard | #if defined(__i386__) && (TARGET_LONG_BITS <= HOST_LONG_BITS)
|
6824 | b8b6a50b | bellard | /* XXX: must be suppressed once there are less fixed registers */
|
6825 | b6abf97d | bellard | cpu_tmp1_i64 = tcg_global_reg2_new_hack(TCG_TYPE_I64, TCG_AREG1, TCG_AREG2, "tmp1");
|
6826 | 57fec1fe | bellard | #endif
|
6827 | b6abf97d | bellard | cpu_cc_op = tcg_global_mem_new(TCG_TYPE_I32, |
6828 | b6abf97d | bellard | TCG_AREG0, offsetof(CPUState, cc_op), "cc_op");
|
6829 | b6abf97d | bellard | cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
6830 | b6abf97d | bellard | TCG_AREG0, offsetof(CPUState, cc_src), "cc_src");
|
6831 | b6abf97d | bellard | cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, |
6832 | b6abf97d | bellard | TCG_AREG0, offsetof(CPUState, cc_dst), "cc_dst");
|
6833 | 2c0262af | bellard | } |
6834 | 2c0262af | bellard | |
6835 | 2c0262af | bellard | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
|
6836 | 2c0262af | bellard | basic block 'tb'. If search_pc is TRUE, also generate PC
|
6837 | 2c0262af | bellard | information for each intermediate instruction. */
|
6838 | 2c0262af | bellard | static inline int gen_intermediate_code_internal(CPUState *env, |
6839 | 5fafdf24 | ths | TranslationBlock *tb, |
6840 | 2c0262af | bellard | int search_pc)
|
6841 | 2c0262af | bellard | { |
6842 | 2c0262af | bellard | DisasContext dc1, *dc = &dc1; |
6843 | 14ce26e7 | bellard | target_ulong pc_ptr; |
6844 | 2c0262af | bellard | uint16_t *gen_opc_end; |
6845 | c068688b | j_mayer | int j, lj, cflags;
|
6846 | c068688b | j_mayer | uint64_t flags; |
6847 | 14ce26e7 | bellard | target_ulong pc_start; |
6848 | 14ce26e7 | bellard | target_ulong cs_base; |
6849 | 3b46e624 | ths | |
6850 | 2c0262af | bellard | /* generate intermediate code */
|
6851 | 14ce26e7 | bellard | pc_start = tb->pc; |
6852 | 14ce26e7 | bellard | cs_base = tb->cs_base; |
6853 | 2c0262af | bellard | flags = tb->flags; |
6854 | d720b93d | bellard | cflags = tb->cflags; |
6855 | 3a1d9b8b | bellard | |
6856 | 4f31916f | bellard | dc->pe = (flags >> HF_PE_SHIFT) & 1;
|
6857 | 2c0262af | bellard | dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
|
6858 | 2c0262af | bellard | dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
|
6859 | 2c0262af | bellard | dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
|
6860 | 2c0262af | bellard | dc->f_st = 0;
|
6861 | 2c0262af | bellard | dc->vm86 = (flags >> VM_SHIFT) & 1;
|
6862 | 2c0262af | bellard | dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
|
6863 | 2c0262af | bellard | dc->iopl = (flags >> IOPL_SHIFT) & 3;
|
6864 | 2c0262af | bellard | dc->tf = (flags >> TF_SHIFT) & 1;
|
6865 | 34865134 | bellard | dc->singlestep_enabled = env->singlestep_enabled; |
6866 | 2c0262af | bellard | dc->cc_op = CC_OP_DYNAMIC; |
6867 | 2c0262af | bellard | dc->cs_base = cs_base; |
6868 | 2c0262af | bellard | dc->tb = tb; |
6869 | 2c0262af | bellard | dc->popl_esp_hack = 0;
|
6870 | 2c0262af | bellard | /* select memory access functions */
|
6871 | 2c0262af | bellard | dc->mem_index = 0;
|
6872 | 2c0262af | bellard | if (flags & HF_SOFTMMU_MASK) {
|
6873 | 2c0262af | bellard | if (dc->cpl == 3) |
6874 | 14ce26e7 | bellard | dc->mem_index = 2 * 4; |
6875 | 2c0262af | bellard | else
|
6876 | 14ce26e7 | bellard | dc->mem_index = 1 * 4; |
6877 | 2c0262af | bellard | } |
6878 | 14ce26e7 | bellard | dc->cpuid_features = env->cpuid_features; |
6879 | 3d7374c5 | bellard | dc->cpuid_ext_features = env->cpuid_ext_features; |
6880 | e771edab | aurel32 | dc->cpuid_ext2_features = env->cpuid_ext2_features; |
6881 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
6882 | 14ce26e7 | bellard | dc->lma = (flags >> HF_LMA_SHIFT) & 1;
|
6883 | 14ce26e7 | bellard | dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
|
6884 | 14ce26e7 | bellard | #endif
|
6885 | 7eee2a50 | bellard | dc->flags = flags; |
6886 | a2cc3b24 | bellard | dc->jmp_opt = !(dc->tf || env->singlestep_enabled || |
6887 | a2cc3b24 | bellard | (flags & HF_INHIBIT_IRQ_MASK) |
6888 | 415fa2ea | bellard | #ifndef CONFIG_SOFTMMU
|
6889 | 2c0262af | bellard | || (flags & HF_SOFTMMU_MASK) |
6890 | 2c0262af | bellard | #endif
|
6891 | 2c0262af | bellard | ); |
6892 | 4f31916f | bellard | #if 0
|
6893 | 4f31916f | bellard | /* check addseg logic */
|
6894 | dc196a57 | bellard | if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
|
6895 | 4f31916f | bellard | printf("ERROR addseg\n");
|
6896 | 4f31916f | bellard | #endif
|
6897 | 4f31916f | bellard | |
6898 | 57fec1fe | bellard | cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
6899 | b8b6a50b | bellard | #if !(defined(__i386__) && (TARGET_LONG_BITS <= HOST_LONG_BITS))
|
6900 | b6abf97d | bellard | cpu_tmp1_i64 = tcg_temp_new(TCG_TYPE_I64); |
6901 | 8686c490 | bellard | #endif
|
6902 | b6abf97d | bellard | cpu_tmp2_i32 = tcg_temp_new(TCG_TYPE_I32); |
6903 | b6abf97d | bellard | cpu_tmp3_i32 = tcg_temp_new(TCG_TYPE_I32); |
6904 | b6abf97d | bellard | cpu_tmp4 = tcg_temp_new(TCG_TYPE_TL); |
6905 | b6abf97d | bellard | cpu_tmp5 = tcg_temp_new(TCG_TYPE_TL); |
6906 | b6abf97d | bellard | cpu_tmp6 = tcg_temp_new(TCG_TYPE_TL); |
6907 | 5af45186 | bellard | cpu_ptr0 = tcg_temp_new(TCG_TYPE_PTR); |
6908 | 5af45186 | bellard | cpu_ptr1 = tcg_temp_new(TCG_TYPE_PTR); |
6909 | 57fec1fe | bellard | |
6910 | 2c0262af | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
6911 | 2c0262af | bellard | |
6912 | 2c0262af | bellard | dc->is_jmp = DISAS_NEXT; |
6913 | 2c0262af | bellard | pc_ptr = pc_start; |
6914 | 2c0262af | bellard | lj = -1;
|
6915 | 2c0262af | bellard | |
6916 | 2c0262af | bellard | for(;;) {
|
6917 | 2c0262af | bellard | if (env->nb_breakpoints > 0) { |
6918 | 2c0262af | bellard | for(j = 0; j < env->nb_breakpoints; j++) { |
6919 | 14ce26e7 | bellard | if (env->breakpoints[j] == pc_ptr) {
|
6920 | 2c0262af | bellard | gen_debug(dc, pc_ptr - dc->cs_base); |
6921 | 2c0262af | bellard | break;
|
6922 | 2c0262af | bellard | } |
6923 | 2c0262af | bellard | } |
6924 | 2c0262af | bellard | } |
6925 | 2c0262af | bellard | if (search_pc) {
|
6926 | 2c0262af | bellard | j = gen_opc_ptr - gen_opc_buf; |
6927 | 2c0262af | bellard | if (lj < j) {
|
6928 | 2c0262af | bellard | lj++; |
6929 | 2c0262af | bellard | while (lj < j)
|
6930 | 2c0262af | bellard | gen_opc_instr_start[lj++] = 0;
|
6931 | 2c0262af | bellard | } |
6932 | 14ce26e7 | bellard | gen_opc_pc[lj] = pc_ptr; |
6933 | 2c0262af | bellard | gen_opc_cc_op[lj] = dc->cc_op; |
6934 | 2c0262af | bellard | gen_opc_instr_start[lj] = 1;
|
6935 | 2c0262af | bellard | } |
6936 | 2c0262af | bellard | pc_ptr = disas_insn(dc, pc_ptr); |
6937 | 2c0262af | bellard | /* stop translation if indicated */
|
6938 | 2c0262af | bellard | if (dc->is_jmp)
|
6939 | 2c0262af | bellard | break;
|
6940 | 2c0262af | bellard | /* if single step mode, we generate only one instruction and
|
6941 | 2c0262af | bellard | generate an exception */
|
6942 | a2cc3b24 | bellard | /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
|
6943 | a2cc3b24 | bellard | the flag and abort the translation to give the irqs a
|
6944 | a2cc3b24 | bellard | change to be happen */
|
6945 | 5fafdf24 | ths | if (dc->tf || dc->singlestep_enabled ||
|
6946 | d720b93d | bellard | (flags & HF_INHIBIT_IRQ_MASK) || |
6947 | d720b93d | bellard | (cflags & CF_SINGLE_INSN)) { |
6948 | 14ce26e7 | bellard | gen_jmp_im(pc_ptr - dc->cs_base); |
6949 | 2c0262af | bellard | gen_eob(dc); |
6950 | 2c0262af | bellard | break;
|
6951 | 2c0262af | bellard | } |
6952 | 2c0262af | bellard | /* if too long translation, stop generation too */
|
6953 | 2c0262af | bellard | if (gen_opc_ptr >= gen_opc_end ||
|
6954 | 2c0262af | bellard | (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
|
6955 | 14ce26e7 | bellard | gen_jmp_im(pc_ptr - dc->cs_base); |
6956 | 2c0262af | bellard | gen_eob(dc); |
6957 | 2c0262af | bellard | break;
|
6958 | 2c0262af | bellard | } |
6959 | 2c0262af | bellard | } |
6960 | 2c0262af | bellard | *gen_opc_ptr = INDEX_op_end; |
6961 | 2c0262af | bellard | /* we don't forget to fill the last values */
|
6962 | 2c0262af | bellard | if (search_pc) {
|
6963 | 2c0262af | bellard | j = gen_opc_ptr - gen_opc_buf; |
6964 | 2c0262af | bellard | lj++; |
6965 | 2c0262af | bellard | while (lj <= j)
|
6966 | 2c0262af | bellard | gen_opc_instr_start[lj++] = 0;
|
6967 | 2c0262af | bellard | } |
6968 | 3b46e624 | ths | |
6969 | 2c0262af | bellard | #ifdef DEBUG_DISAS
|
6970 | 658c8bda | bellard | if (loglevel & CPU_LOG_TB_CPU) {
|
6971 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
6972 | 658c8bda | bellard | } |
6973 | e19e89a5 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
6974 | 14ce26e7 | bellard | int disas_flags;
|
6975 | 2c0262af | bellard | fprintf(logfile, "----------------\n");
|
6976 | 2c0262af | bellard | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
6977 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
6978 | 14ce26e7 | bellard | if (dc->code64)
|
6979 | 14ce26e7 | bellard | disas_flags = 2;
|
6980 | 14ce26e7 | bellard | else
|
6981 | 14ce26e7 | bellard | #endif
|
6982 | 14ce26e7 | bellard | disas_flags = !dc->code32; |
6983 | 14ce26e7 | bellard | target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags); |
6984 | 2c0262af | bellard | fprintf(logfile, "\n");
|
6985 | 57fec1fe | bellard | if (loglevel & CPU_LOG_TB_OP_OPT) {
|
6986 | 57fec1fe | bellard | fprintf(logfile, "OP before opt:\n");
|
6987 | 57fec1fe | bellard | tcg_dump_ops(&tcg_ctx, logfile); |
6988 | e19e89a5 | bellard | fprintf(logfile, "\n");
|
6989 | e19e89a5 | bellard | } |
6990 | 2c0262af | bellard | } |
6991 | 2c0262af | bellard | #endif
|
6992 | 2c0262af | bellard | |
6993 | 2c0262af | bellard | if (!search_pc)
|
6994 | 2c0262af | bellard | tb->size = pc_ptr - pc_start; |
6995 | 2c0262af | bellard | return 0; |
6996 | 2c0262af | bellard | } |
6997 | 2c0262af | bellard | |
6998 | 2c0262af | bellard | int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
|
6999 | 2c0262af | bellard | { |
7000 | 2c0262af | bellard | return gen_intermediate_code_internal(env, tb, 0); |
7001 | 2c0262af | bellard | } |
7002 | 2c0262af | bellard | |
7003 | 2c0262af | bellard | int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
|
7004 | 2c0262af | bellard | { |
7005 | 2c0262af | bellard | return gen_intermediate_code_internal(env, tb, 1); |
7006 | 2c0262af | bellard | } |
7007 | 2c0262af | bellard | |
7008 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
7009 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
7010 | d2856f1a | aurel32 | { |
7011 | d2856f1a | aurel32 | int cc_op;
|
7012 | d2856f1a | aurel32 | #ifdef DEBUG_DISAS
|
7013 | d2856f1a | aurel32 | if (loglevel & CPU_LOG_TB_OP) {
|
7014 | d2856f1a | aurel32 | int i;
|
7015 | d2856f1a | aurel32 | fprintf(logfile, "RESTORE:\n");
|
7016 | d2856f1a | aurel32 | for(i = 0;i <= pc_pos; i++) { |
7017 | d2856f1a | aurel32 | if (gen_opc_instr_start[i]) {
|
7018 | d2856f1a | aurel32 | fprintf(logfile, "0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]); |
7019 | d2856f1a | aurel32 | } |
7020 | d2856f1a | aurel32 | } |
7021 | d2856f1a | aurel32 | fprintf(logfile, "spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", |
7022 | d2856f1a | aurel32 | searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base, |
7023 | d2856f1a | aurel32 | (uint32_t)tb->cs_base); |
7024 | d2856f1a | aurel32 | } |
7025 | d2856f1a | aurel32 | #endif
|
7026 | d2856f1a | aurel32 | env->eip = gen_opc_pc[pc_pos] - tb->cs_base; |
7027 | d2856f1a | aurel32 | cc_op = gen_opc_cc_op[pc_pos]; |
7028 | d2856f1a | aurel32 | if (cc_op != CC_OP_DYNAMIC)
|
7029 | d2856f1a | aurel32 | env->cc_op = cc_op; |
7030 | d2856f1a | aurel32 | } |